From: Vijay Kumar Tumati <vijay.tumati@oss.qualcomm.com>
To: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Cc: Bryan O'Donoghue <bryan.odonoghue@linaro.org>,
Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Neil Armstrong <neil.armstrong@linaro.org>,
Bryan O'Donoghue <bod@kernel.org>,
Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>,
linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org,
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 1/2] dt-bindings: phy: qcom: Add CSI2 C-PHY/DPHY schema
Date: Tue, 3 Mar 2026 15:24:16 -0800 [thread overview]
Message-ID: <f83f616d-9114-426d-bc9b-42ddc839686f@oss.qualcomm.com> (raw)
In-Reply-To: <yhatx2iuoofvsqpu5da7ohpyvzhc2y7uq3bhuhfuv6pkfpqrnz@75xei3bawzza>
On 3/3/2026 2:31 PM, Dmitry Baryshkov wrote:
> On Mon, Mar 02, 2026 at 05:51:24PM -0800, Vijay Kumar Tumati wrote:
>> Hi Bryan,
>>
>> On 2/26/2026 4:34 AM, Bryan O'Donoghue wrote:
>>> + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
>> As we are cleaning up the PHY device nodes, we should consider fixing the
>> power domains as well. Although TOP GDSC is defined as a power domain, it is
>> not the power source for the PHY devices. Rather, it is the MMCX, MXC and
>> optionally MXA based on the architecture (Refer to 'Voltage rail' column for
>> PHY clocks in IPCAT). There is no
>> parent-child relationship between the TOP GDSC and these in the clock driver
>> and it was just working as the required power rails are getting enabled
>> by/for other MM devices.
>
> Which domains are required to access CSI PHY registers?
PHY register access requires the PHY core clock, cam_top_ahb clock. So
in my understanding, we need to trace these clocks in the topology
backwards up until at least the RCG, and all the voltage rails powering
these clocks will be the required power domains. Having said that, just
register access works even if the voltage rails are configured to the
min level, which camcc does already.
>
>>> +
>>> + vdda-0p8-supply = <&vreg_l2c_0p8>;
>>> + vdda-1p2-supply = <&vreg_l1c_1p2>;
>>> + };
>>> +
>
Thanks,
Vijay.
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next prev parent reply other threads:[~2026-03-03 23:24 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-26 12:34 [PATCH v3 0/2] phy: qcom-mipi-csi2: Add a CSI2 MIPI DPHY driver Bryan O'Donoghue
2026-02-26 12:34 ` [PATCH v3 1/2] dt-bindings: phy: qcom: Add CSI2 C-PHY/DPHY schema Bryan O'Donoghue
2026-02-27 9:41 ` Krzysztof Kozlowski
2026-02-27 9:47 ` Bryan O'Donoghue
2026-03-03 1:51 ` Vijay Kumar Tumati
2026-03-03 9:27 ` Bryan O'Donoghue
2026-03-03 18:08 ` Vijay Kumar Tumati
2026-03-03 18:58 ` Vijay Kumar Tumati
2026-03-03 22:53 ` Bryan O'Donoghue
2026-03-03 23:17 ` Vijay Kumar Tumati
2026-03-03 23:26 ` Bryan O'Donoghue
2026-03-03 23:50 ` Vijay Kumar Tumati
2026-03-04 0:02 ` Bryan O'Donoghue
2026-03-04 0:15 ` Vijay Kumar Tumati
2026-03-03 9:30 ` Bryan O'Donoghue
2026-03-03 12:34 ` Konrad Dybcio
2026-03-03 14:56 ` Bryan O'Donoghue
2026-03-04 10:32 ` Konrad Dybcio
2026-03-03 18:03 ` Vijay Kumar Tumati
2026-03-03 22:31 ` Dmitry Baryshkov
2026-03-03 23:24 ` Vijay Kumar Tumati [this message]
2026-03-03 23:49 ` Dmitry Baryshkov
2026-03-03 23:51 ` Vijay Kumar Tumati
2026-02-26 12:34 ` [PATCH v3 2/2] phy: qcom-mipi-csi2: Add a CSI2 MIPI DPHY driver Bryan O'Donoghue
2026-02-27 1:40 ` Dmitry Baryshkov
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