From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: Abel Vesa <abel.vesa@linaro.org>,
Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Cc: Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Dmitry Baryshkov <lumag@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Neil Armstrong <neil.armstrong@linaro.org>,
Johan Hovold <johan@kernel.org>,
linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 3/3] phy: qcom: edp: Add Glymur platform support
Date: Thu, 11 Sep 2025 11:18:53 +0200 [thread overview]
Message-ID: <fff688c9-af7d-43fd-a3f1-00209842bcc9@oss.qualcomm.com> (raw)
In-Reply-To: <wetzewmbraeawwintmxqntjhvennq5iu2jeegel3glk7y6rsnf@4vwscm5bwezr>
On 9/11/25 10:52 AM, Abel Vesa wrote:
> On 25-09-09 14:12:46, Dmitry Baryshkov wrote:
>> On Tue, Sep 09, 2025 at 01:07:28PM +0300, Abel Vesa wrote:
>>> The Qualcomm Glymur platform has the new v8 version
>>> of the eDP/DP PHY. So rework the driver to support this
>>> new version and add the platform specific configuration data.
>>>
>>> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
>>> ---
>>> drivers/phy/qualcomm/phy-qcom-edp.c | 242 ++++++++++++++++++++++++++++++++++--
>>> 1 file changed, 235 insertions(+), 7 deletions(-)
>>>
>>> diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy-qcom-edp.c
>>> index ca9bb9d70e29e1a132bd499fb9f74b5837acf45b..b670cda0fa066d3ff45c66b73cc67e165e55b79a 100644
>>> --- a/drivers/phy/qualcomm/phy-qcom-edp.c
>>> +++ b/drivers/phy/qualcomm/phy-qcom-edp.c
>>> @@ -26,13 +26,15 @@
>>> #include "phy-qcom-qmp-qserdes-com-v4.h"
>>> #include "phy-qcom-qmp-qserdes-com-v6.h"
>>>
>>> +#include "phy-qcom-qmp-dp-qserdes-com-v8.h"
>>> +
>>> /* EDP_PHY registers */
>>> #define DP_PHY_CFG 0x0010
>>> #define DP_PHY_CFG_1 0x0014
>>> #define DP_PHY_PD_CTL 0x001c
>>> #define DP_PHY_MODE 0x0020
>>>
>>> -#define DP_AUX_CFG_SIZE 10
>>> +#define DP_AUX_CFG_SIZE 13
>>
>> If it differs from platform to platform, do we need to continue defining
>> it?
>>
>> Also, if the AUX CFG size has increased, didn't it cause other registers
>> to shift too?
>
> AFAICT, all platforms have AUX_CFG0 through AUX_CFG12, we just didn't
> need to write anything to the last two so far.
I checked 7180/7280/8180/8280/x1e/Glymur and they all do
It would make sense to perhaps spell this out explicitly in a separate
patch
Konrad
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next prev parent reply other threads:[~2025-09-11 9:19 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-09 10:07 [PATCH v2 0/3] phy: qcom: edp: Add support for Glymur platform Abel Vesa
2025-09-09 10:07 ` [PATCH v2 1/3] dt-bindings: phy: Add DP PHY compatible for Glymur Abel Vesa
2025-09-10 11:32 ` Krzysztof Kozlowski
2025-09-11 9:02 ` Abel Vesa
2025-09-09 10:07 ` [PATCH v2 2/3] phy: qcom-qmp: qserdes-com: Add v8 DP-specific qserdes register offsets Abel Vesa
2025-09-09 11:19 ` Dmitry Baryshkov
2025-09-09 11:24 ` Konrad Dybcio
2025-09-09 11:40 ` Dmitry Baryshkov
2025-09-09 10:07 ` [PATCH v2 3/3] phy: qcom: edp: Add Glymur platform support Abel Vesa
2025-09-09 11:12 ` Dmitry Baryshkov
2025-09-11 8:52 ` Abel Vesa
2025-09-11 9:18 ` Konrad Dybcio [this message]
2025-09-11 12:33 ` Abel Vesa
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