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Thu, 01 Oct 2026 10:40:08 -0700 (PDT) Received: from strix.localnet ([197.250.96.176]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48b0690d284sm7098316f8f.17.2026.10.01.10.40.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Oct 2026 10:40:07 -0700 (PDT) From: Stefan =?UTF-8?B?RMO2c2luZ2Vy?= To: linux-clk@vger.kernel.org Cc: Brian Masney , Conor Dooley , devicetree@vger.kernel.org, Jerome Brunet , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Manivannan Sadhasivam , Neil Armstrong , Philipp Zabel , Rob Herring , Stephen Boyd , Vinod Koul , mturquette@baylibre.com Subject: [GIT PULL] clk: zte: zx297520v3 clock bindings and driver (v2) Date: Thu, 01 Oct 2026 20:39:27 +0300 Message-ID: MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261001_104011_020872_10A1062A X-CRM114-Status: GOOD ( 13.56 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============4185650771328732059==" Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org --===============4185650771328732059== Content-Type: multipart/signed; boundary="nextPartts1z5F9iR2ap04uw5rhYqQ"; micalg="pgp-sha256"; protocol="application/pgp-signature" --nextPartts1z5F9iR2ap04uw5rhYqQ Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8"; protected-headers="v1" From: Stefan =?UTF-8?B?RMO2c2luZ2Vy?= To: linux-clk@vger.kernel.org Subject: [GIT PULL] clk: zte: zx297520v3 clock bindings and driver (v2) Date: Thu, 01 Oct 2026 20:39:27 +0300 Message-ID: MIME-Version: 1.0 Hi, This pull request contains the device tree bindings and clock driver for ZTE zx297520v3 boards. It contains the next step in adding support for zx297520v3 boards: Documenting clock and reset manager hardware and adding drivers for its PLLs and clock tree. This is v2 of the pull request, based on v7.3-rc1 rather than clk-next. The patches have been reviewed and carry appropriate R-B tags by Krzysztof Kozlowski (bindings) and Brian Masney (clk driver). The PR does not contain the MFD, reset and device tree patches. They will be submitted to the MFD, reset and soc trees respectively. The clock driver compiles without them, but won't be instantiated without the MFD parent. The following changes since commit cee9395acd8043be0644b25c34bfa86623f2b935: Linux 7.3-rc1 (2026-08-30 13:34:40 -0700) are available in the Git repository at: https://gitlab.com/stefandoesinger/zx297520-kernel.git tags/v2-zx29-clk-f= or-7.4 for you to fetch changes up to 75e4151c9e157d84c8c6c365893ecf33d221bca5: clk: zte: Introduce a driver for zx297520v3 LSP clocks (2026-10-01 20:20:= 43 +0300) =2D--------------------------------------------------------------- clk: zte: Add clock drivers for zx297520v3 SoC This tag contains the device tree bindings and clock driver for ZTE zx297520v3 boards. It contains the next step in adding support for zx297520v3 boards: Documenting clock and reset manager hardware and adding drivers for its PLLs and clock tree. The PR does not contain the MFD, reset and device tree patches. They will be submitted to the MFD, reset and soc trees respectively. The clock driver compiles without them, but won't be instantiated without the MFD parent. =2D--------------------------------------------------------------- Stefan D=C3=B6singer (9): dt-bindings: clk: zte: Add zx297520v3 top clock and reset controller dt-bindings: clk: zte: Add zx297520v3 matrix clock and reset controll= er dt-bindings: clk: zte: Add zx297520v3 LSP clock and reset controller clk: zte: Add Clock registration infrastructure clk: zte: Add regmap-based clocks clk: zte: Add zx PLL support infrastructure clk: zte: Introduce a driver for zx297520v3 top clocks clk: zte: Introduce a driver for zx297520v3 matrix clocks clk: zte: Introduce a driver for zx297520v3 LSP clocks .../bindings/clock/zte,zx297520v3-lspcrm.yaml | 101 ++ .../bindings/clock/zte,zx297520v3-matrixcrm.yaml | 98 ++ .../bindings/clock/zte,zx297520v3-topcrm.yaml | 122 ++ MAINTAINERS | 7 + drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/zte/Kconfig | 28 + drivers/clk/zte/Makefile | 6 + drivers/clk/zte/clk-regmap.c | 237 +++ drivers/clk/zte/clk-zx.c | 192 +++ drivers/clk/zte/clk-zx.h | 137 ++ drivers/clk/zte/clk-zx297520v3.c | 1657 ++++++++++++++++= ++++ drivers/clk/zte/pll-zx.c | 576 +++++++ include/dt-bindings/clock/zte,zx297520v3-clk.h | 154 ++ include/dt-bindings/phy/zte,zx297520v3-topcrm.h | 12 + include/dt-bindings/reset/zte,zx297520v3-reset.h | 62 + 16 files changed, 3391 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/zte,zx297520v3-= lspcrm.yaml create mode 100644 Documentation/devicetree/bindings/clock/zte,zx297520v3-= matrixcrm.yaml create mode 100644 Documentation/devicetree/bindings/clock/zte,zx297520v3-= topcrm.yaml create mode 100644 drivers/clk/zte/Kconfig create mode 100644 drivers/clk/zte/Makefile create mode 100644 drivers/clk/zte/clk-regmap.c create mode 100644 drivers/clk/zte/clk-zx.c create mode 100644 drivers/clk/zte/clk-zx.h create mode 100644 drivers/clk/zte/clk-zx297520v3.c create mode 100644 drivers/clk/zte/pll-zx.c create mode 100644 include/dt-bindings/clock/zte,zx297520v3-clk.h create mode 100644 include/dt-bindings/phy/zte,zx297520v3-topcrm.h create mode 100644 include/dt-bindings/reset/zte,zx297520v3-reset.h --nextPartts1z5F9iR2ap04uw5rhYqQ Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part. 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