* [PATCH net-next v2 0/2] net: phy: Use is_phy_driver() and is_phy_device()
From: Yajun Deng @ 2024-01-03 2:53 UTC (permalink / raw)
To: davem, edumazet, kuba, pabeni
Cc: andrew, olteanv, hkallweit1, linux, przemyslaw.kitszel,
rmk+kernel, kabel, netdev, linux-kernel, linux-phy, Yajun Deng
There is only one flag that can be set in struct mdio_driver_common and
mdio_device. We can compare the probe of the driver or the type of the
device to implement it. Hence, these flags in struct mdio_driver_common
and mdio_device can be removed.
Introduce is_phy_driver() and is_phy_device(). Use them test the driver
or device.
v1 -> v2:
remove redundant parens and the exported.
Yajun Deng (2):
net: phy: Cleanup struct mdio_driver_common and introduce
is_phy_driver()
net: phy: Introduce is_phy_device()
drivers/net/dsa/b53/b53_mdio.c | 2 +-
drivers/net/dsa/dsa_loop.c | 2 +-
drivers/net/dsa/lan9303_mdio.c | 2 +-
drivers/net/dsa/microchip/ksz8863_smi.c | 2 +-
drivers/net/dsa/mt7530-mdio.c | 2 +-
drivers/net/dsa/mv88e6060.c | 2 +-
drivers/net/dsa/mv88e6xxx/chip.c | 2 +-
drivers/net/dsa/qca/ar9331.c | 2 +-
drivers/net/dsa/qca/qca8k-8xxx.c | 2 +-
drivers/net/dsa/realtek/realtek-mdio.c | 2 +-
drivers/net/dsa/xrs700x/xrs700x_mdio.c | 2 +-
drivers/net/phy/mdio_bus.c | 7 ++--
drivers/net/phy/mdio_device.c | 21 +++++-------
drivers/net/phy/phy_device.c | 44 ++++++++++++++-----------
drivers/net/phy/xilinx_gmii2rgmii.c | 2 +-
drivers/phy/broadcom/phy-bcm-ns-usb3.c | 8 ++---
drivers/phy/broadcom/phy-bcm-ns2-pcie.c | 8 ++---
include/linux/mdio.h | 19 ++---------
include/linux/phy.h | 10 +++---
19 files changed, 62 insertions(+), 79 deletions(-)
--
2.25.1
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^ permalink raw reply
* Re: [PATCH net-next] net: phy: Cleanup struct mdio_driver_common
From: Yajun Deng @ 2024-01-03 2:03 UTC (permalink / raw)
To: Russell King (Oracle)
Cc: davem, edumazet, kuba, pabeni, andrew, olteanv, hkallweit1, kabel,
netdev, linux-kernel, linux-phy
In-Reply-To: <ZZRJLg6U0G5CNRQ0@shell.armlinux.org.uk>
On 2024/1/3 01:34, Russell King (Oracle) wrote:
> On Thu, Dec 28, 2023 at 03:23:50PM +0800, Yajun Deng wrote:
>> The struct mdio_driver_common is a wrapper for driver-model structure,
>> it contains device_driver and flags. There are only struct phy_driver
>> and mdio_driver that use it. The flags is used to distinguish between
>> struct phy_driver and mdio_driver.
>>
>> We can test that if probe of device_driver is equal to phy_probe. This
>> way, the struct mdio_driver_common is no longer needed, and struct
>> phy_driver and usb_mdio_driver will be consistent with other driver
>> structs.
> usb_mdio_driver?
This is a mistake. It should be 'mdio_driver'.
>
> I'm not sure why this consistency is even desired, the commit message
> doesn't properly say _why_ this change is being proposed.
Most drivers use device_driver directly. This should be added to the commit.
Like this:
struct sdio_driver {
... ...
struct device_driver drv;
};
struct pcie_port_service_driver {
... ...
struct device_driver driver;
};
and so on ...
>
>> +bool is_phy_driver(struct device_driver *driver)
>> +{
>> + return driver->probe == phy_probe;
>> +}
>> +EXPORT_SYMBOL_GPL(is_phy_driver);
> Do we really need this exported? It doesn't seem like something anything
> other than core MDIO/phylib code should know about, and all that becomes
> a single module when building it in a modular way - phylib can't be a
> separate module from mdio stuff.
I think this exported can be removed.
--
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^ permalink raw reply
* Re: [PATCH net-next] net: phy: Cleanup struct mdio_driver_common
From: Russell King (Oracle) @ 2024-01-02 17:34 UTC (permalink / raw)
To: Yajun Deng
Cc: davem, edumazet, kuba, pabeni, andrew, olteanv, hkallweit1, kabel,
netdev, linux-kernel, linux-phy
In-Reply-To: <20231228072350.1294425-1-yajun.deng@linux.dev>
On Thu, Dec 28, 2023 at 03:23:50PM +0800, Yajun Deng wrote:
> The struct mdio_driver_common is a wrapper for driver-model structure,
> it contains device_driver and flags. There are only struct phy_driver
> and mdio_driver that use it. The flags is used to distinguish between
> struct phy_driver and mdio_driver.
>
> We can test that if probe of device_driver is equal to phy_probe. This
> way, the struct mdio_driver_common is no longer needed, and struct
> phy_driver and usb_mdio_driver will be consistent with other driver
> structs.
usb_mdio_driver?
I'm not sure why this consistency is even desired, the commit message
doesn't properly say _why_ this change is being proposed.
> +bool is_phy_driver(struct device_driver *driver)
> +{
> + return driver->probe == phy_probe;
> +}
> +EXPORT_SYMBOL_GPL(is_phy_driver);
Do we really need this exported? It doesn't seem like something anything
other than core MDIO/phylib code should know about, and all that becomes
a single module when building it in a modular way - phylib can't be a
separate module from mdio stuff.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
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^ permalink raw reply
* Re: [PATCH net-next] net: phy: Cleanup struct mdio_driver_common
From: Yajun Deng @ 2023-12-28 8:37 UTC (permalink / raw)
To: Przemek Kitszel
Cc: andrew, olteanv, hkallweit1, linux, rmk+kernel, kabel, netdev,
linux-kernel, linux-phy, davem, edumazet, kuba, pabeni
In-Reply-To: <95b7ee65-5661-6529-07d3-ce13968a3c25@intel.com>
On 2023/12/28 16:24, Przemek Kitszel wrote:
> On 12/28/23 08:23, Yajun Deng wrote:
>> The struct mdio_driver_common is a wrapper for driver-model structure,
>> it contains device_driver and flags. There are only struct phy_driver
>> and mdio_driver that use it. The flags is used to distinguish between
>> struct phy_driver and mdio_driver.
>>
>> We can test that if probe of device_driver is equal to phy_probe. This
>> way, the struct mdio_driver_common is no longer needed, and struct
>> phy_driver and usb_mdio_driver will be consistent with other driver
>> structs.
>>
>> Cleanup struct mdio_driver_common and introduce is_phy_driver(). Use
>> is_phy_driver() test that if the driver is a phy or not.
>>
>> Signed-off-by: Yajun Deng <yajun.deng@linux.dev>
>> ---
>> drivers/net/dsa/b53/b53_mdio.c | 2 +-
>> drivers/net/dsa/dsa_loop.c | 2 +-
>> drivers/net/dsa/lan9303_mdio.c | 2 +-
>> drivers/net/dsa/microchip/ksz8863_smi.c | 2 +-
>> drivers/net/dsa/mt7530-mdio.c | 2 +-
>> drivers/net/dsa/mv88e6060.c | 2 +-
>> drivers/net/dsa/mv88e6xxx/chip.c | 2 +-
>> drivers/net/dsa/qca/ar9331.c | 2 +-
>> drivers/net/dsa/qca/qca8k-8xxx.c | 2 +-
>> drivers/net/dsa/realtek/realtek-mdio.c | 2 +-
>> drivers/net/dsa/xrs700x/xrs700x_mdio.c | 2 +-
>> drivers/net/phy/mdio_bus.c | 2 +-
>> drivers/net/phy/mdio_device.c | 21 +++++++--------
>> drivers/net/phy/phy_device.c | 35 ++++++++++++++-----------
>> drivers/net/phy/xilinx_gmii2rgmii.c | 2 +-
>> drivers/phy/broadcom/phy-bcm-ns-usb3.c | 8 +++---
>> drivers/phy/broadcom/phy-bcm-ns2-pcie.c | 8 +++---
>> include/linux/mdio.h | 16 ++---------
>> include/linux/phy.h | 9 +++----
>> 19 files changed, 54 insertions(+), 69 deletions(-)
>>
>
> some nitpicks from me,
> otherwise looks fine:
> Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com>
>
> BTW, please send v2 after winter break:
> https://patchwork.hopto.org/net-next.html
>
Ok, thanks.
>
>> diff --git a/drivers/net/dsa/b53/b53_mdio.c
>> b/drivers/net/dsa/b53/b53_mdio.c
>> index 897e5e8b3d69..1ececa4d44e4 100644
>> --- a/drivers/net/dsa/b53/b53_mdio.c
>> +++ b/drivers/net/dsa/b53/b53_mdio.c
>> @@ -392,7 +392,7 @@ static struct mdio_driver b53_mdio_driver = {
>> .probe = b53_mdio_probe,
>> .remove = b53_mdio_remove,
>> .shutdown = b53_mdio_shutdown,
>> - .mdiodrv.driver = {
>> + .driver = {
>> .name = "bcm53xx",
>> .of_match_table = b53_of_match,
>> },
>> diff --git a/drivers/net/dsa/dsa_loop.c b/drivers/net/dsa/dsa_loop.c
>> index c70ed67cc188..3f885878be3a 100644
>> --- a/drivers/net/dsa/dsa_loop.c
>> +++ b/drivers/net/dsa/dsa_loop.c
>> @@ -375,7 +375,7 @@ static void dsa_loop_drv_shutdown(struct
>> mdio_device *mdiodev)
>> }
>> static struct mdio_driver dsa_loop_drv = {
>> - .mdiodrv.driver = {
>> + .driver = {
>> .name = "dsa-loop",
>> },
>> .probe = dsa_loop_drv_probe,
>> diff --git a/drivers/net/dsa/lan9303_mdio.c
>> b/drivers/net/dsa/lan9303_mdio.c
>> index 167a86f39f27..7cb7e2b1478a 100644
>> --- a/drivers/net/dsa/lan9303_mdio.c
>> +++ b/drivers/net/dsa/lan9303_mdio.c
>> @@ -162,7 +162,7 @@ static const struct of_device_id
>> lan9303_mdio_of_match[] = {
>> MODULE_DEVICE_TABLE(of, lan9303_mdio_of_match);
>> static struct mdio_driver lan9303_mdio_driver = {
>> - .mdiodrv.driver = {
>> + .driver = {
>> .name = "LAN9303_MDIO",
>> .of_match_table = lan9303_mdio_of_match,
>> },
>> diff --git a/drivers/net/dsa/microchip/ksz8863_smi.c
>> b/drivers/net/dsa/microchip/ksz8863_smi.c
>> index 5711a59e2ac9..c788cadd7595 100644
>> --- a/drivers/net/dsa/microchip/ksz8863_smi.c
>> +++ b/drivers/net/dsa/microchip/ksz8863_smi.c
>> @@ -213,7 +213,7 @@ static struct mdio_driver ksz8863_driver = {
>> .probe = ksz8863_smi_probe,
>> .remove = ksz8863_smi_remove,
>> .shutdown = ksz8863_smi_shutdown,
>> - .mdiodrv.driver = {
>> + .driver = {
>> .name = "ksz8863-switch",
>> .of_match_table = ksz8863_dt_ids,
>> },
>> diff --git a/drivers/net/dsa/mt7530-mdio.c
>> b/drivers/net/dsa/mt7530-mdio.c
>> index 088533663b83..7315654a6757 100644
>> --- a/drivers/net/dsa/mt7530-mdio.c
>> +++ b/drivers/net/dsa/mt7530-mdio.c
>> @@ -258,7 +258,7 @@ static struct mdio_driver mt7530_mdio_driver = {
>> .probe = mt7530_probe,
>> .remove = mt7530_remove,
>> .shutdown = mt7530_shutdown,
>> - .mdiodrv.driver = {
>> + .driver = {
>> .name = "mt7530-mdio",
>> .of_match_table = mt7530_of_match,
>> },
>> diff --git a/drivers/net/dsa/mv88e6060.c b/drivers/net/dsa/mv88e6060.c
>> index 294312b58e4f..5925f23e7ab3 100644
>> --- a/drivers/net/dsa/mv88e6060.c
>> +++ b/drivers/net/dsa/mv88e6060.c
>> @@ -367,7 +367,7 @@ static struct mdio_driver mv88e6060_driver = {
>> .probe = mv88e6060_probe,
>> .remove = mv88e6060_remove,
>> .shutdown = mv88e6060_shutdown,
>> - .mdiodrv.driver = {
>> + .driver = {
>> .name = "mv88e6060",
>> .of_match_table = mv88e6060_of_match,
>> },
>> diff --git a/drivers/net/dsa/mv88e6xxx/chip.c
>> b/drivers/net/dsa/mv88e6xxx/chip.c
>> index 383b3c4d6f59..4f24699264d1 100644
>> --- a/drivers/net/dsa/mv88e6xxx/chip.c
>> +++ b/drivers/net/dsa/mv88e6xxx/chip.c
>> @@ -7258,7 +7258,7 @@ static struct mdio_driver mv88e6xxx_driver = {
>> .probe = mv88e6xxx_probe,
>> .remove = mv88e6xxx_remove,
>> .shutdown = mv88e6xxx_shutdown,
>> - .mdiodrv.driver = {
>> + .driver = {
>> .name = "mv88e6085",
>> .of_match_table = mv88e6xxx_of_match,
>> .pm = &mv88e6xxx_pm_ops,
>> diff --git a/drivers/net/dsa/qca/ar9331.c b/drivers/net/dsa/qca/ar9331.c
>> index 8d9d271ac3af..da392d60c9e7 100644
>> --- a/drivers/net/dsa/qca/ar9331.c
>> +++ b/drivers/net/dsa/qca/ar9331.c
>> @@ -1122,7 +1122,7 @@ static struct mdio_driver ar9331_sw_mdio_driver
>> = {
>> .probe = ar9331_sw_probe,
>> .remove = ar9331_sw_remove,
>> .shutdown = ar9331_sw_shutdown,
>> - .mdiodrv.driver = {
>> + .driver = {
>> .name = AR9331_SW_NAME,
>> .of_match_table = ar9331_sw_of_match,
>> },
>> diff --git a/drivers/net/dsa/qca/qca8k-8xxx.c
>> b/drivers/net/dsa/qca/qca8k-8xxx.c
>> index ec57d9d52072..fe396397f405 100644
>> --- a/drivers/net/dsa/qca/qca8k-8xxx.c
>> +++ b/drivers/net/dsa/qca/qca8k-8xxx.c
>> @@ -2187,7 +2187,7 @@ static struct mdio_driver qca8kmdio_driver = {
>> .probe = qca8k_sw_probe,
>> .remove = qca8k_sw_remove,
>> .shutdown = qca8k_sw_shutdown,
>> - .mdiodrv.driver = {
>> + .driver = {
>> .name = "qca8k",
>> .of_match_table = qca8k_of_match,
>> .pm = &qca8k_pm_ops,
>> diff --git a/drivers/net/dsa/realtek/realtek-mdio.c
>> b/drivers/net/dsa/realtek/realtek-mdio.c
>> index 292e6d087e8b..8e6a951b391c 100644
>> --- a/drivers/net/dsa/realtek/realtek-mdio.c
>> +++ b/drivers/net/dsa/realtek/realtek-mdio.c
>> @@ -274,7 +274,7 @@ static const struct of_device_id
>> realtek_mdio_of_match[] = {
>> MODULE_DEVICE_TABLE(of, realtek_mdio_of_match);
>> static struct mdio_driver realtek_mdio_driver = {
>> - .mdiodrv.driver = {
>> + .driver = {
>> .name = "realtek-mdio",
>> .of_match_table = realtek_mdio_of_match,
>> },
>> diff --git a/drivers/net/dsa/xrs700x/xrs700x_mdio.c
>> b/drivers/net/dsa/xrs700x/xrs700x_mdio.c
>> index 5f7d344b5d73..1a76d9d49f13 100644
>> --- a/drivers/net/dsa/xrs700x/xrs700x_mdio.c
>> +++ b/drivers/net/dsa/xrs700x/xrs700x_mdio.c
>> @@ -164,7 +164,7 @@ static const struct of_device_id __maybe_unused
>> xrs700x_mdio_dt_ids[] = {
>> MODULE_DEVICE_TABLE(of, xrs700x_mdio_dt_ids);
>> static struct mdio_driver xrs700x_mdio_driver = {
>> - .mdiodrv.driver = {
>> + .driver = {
>> .name = "xrs700x-mdio",
>> .of_match_table = of_match_ptr(xrs700x_mdio_dt_ids),
>> },
>> diff --git a/drivers/net/phy/mdio_bus.c b/drivers/net/phy/mdio_bus.c
>> index 6cf73c15635b..a1092c641d14 100644
>> --- a/drivers/net/phy/mdio_bus.c
>> +++ b/drivers/net/phy/mdio_bus.c
>> @@ -1342,7 +1342,7 @@ static int mdio_bus_match(struct device *dev,
>> struct device_driver *drv)
>> struct mdio_device *mdio = to_mdio_device(dev);
>> /* Both the driver and device must type-match */
>> - if (!(mdiodrv->mdiodrv.flags & MDIO_DEVICE_IS_PHY) !=
>> + if (!(is_phy_driver(&mdiodrv->driver)) !=
>> !(mdio->flags & MDIO_DEVICE_FLAG_PHY))
>
> you could remove one pair of parens, and even change condition to:
> if (is_phy_driver(&mdiodrv->driver) == !(mdio->flags &
> MDIO_DEVICE_FLAG_PHY))
>
>
>> return 0;
>> diff --git a/drivers/net/phy/mdio_device.c
>> b/drivers/net/phy/mdio_device.c
>> index 73f6539b9e50..16232e7a1255 100644
>> --- a/drivers/net/phy/mdio_device.c
>> +++ b/drivers/net/phy/mdio_device.c
>> @@ -40,7 +40,7 @@ int mdio_device_bus_match(struct device *dev,
>> struct device_driver *drv)
>> struct mdio_device *mdiodev = to_mdio_device(dev);
>> struct mdio_driver *mdiodrv = to_mdio_driver(drv);
>> - if (mdiodrv->mdiodrv.flags & MDIO_DEVICE_IS_PHY)
>> + if (is_phy_driver(&mdiodrv->driver))
>> return 0;
>> return strcmp(mdiodev->modalias, drv->name) == 0;
>> @@ -203,20 +203,19 @@ static void mdio_shutdown(struct device *dev)
>> */
>> int mdio_driver_register(struct mdio_driver *drv)
>> {
>> - struct mdio_driver_common *mdiodrv = &drv->mdiodrv;
>> int retval;
>> - pr_debug("%s: %s\n", __func__, mdiodrv->driver.name);
>> + pr_debug("%s: %s\n", __func__, drv->driver.name);
>> - mdiodrv->driver.bus = &mdio_bus_type;
>> - mdiodrv->driver.probe = mdio_probe;
>> - mdiodrv->driver.remove = mdio_remove;
>> - mdiodrv->driver.shutdown = mdio_shutdown;
>> + drv->driver.bus = &mdio_bus_type;
>> + drv->driver.probe = mdio_probe;
>> + drv->driver.remove = mdio_remove;
>> + drv->driver.shutdown = mdio_shutdown;
>> - retval = driver_register(&mdiodrv->driver);
>> + retval = driver_register(&drv->driver);
>> if (retval) {
>> pr_err("%s: Error %d in registering driver\n",
>> - mdiodrv->driver.name, retval);
>> + drv->driver.name, retval);
>> return retval;
>> }
>> @@ -227,8 +226,6 @@ EXPORT_SYMBOL(mdio_driver_register);
>> void mdio_driver_unregister(struct mdio_driver *drv)
>> {
>> - struct mdio_driver_common *mdiodrv = &drv->mdiodrv;
>> -
>> - driver_unregister(&mdiodrv->driver);
>> + driver_unregister(&drv->driver);
>> }
>> EXPORT_SYMBOL(mdio_driver_unregister);
>> diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c
>> index 3611ea64875e..55494a345bd4 100644
>> --- a/drivers/net/phy/phy_device.c
>> +++ b/drivers/net/phy/phy_device.c
>> @@ -529,7 +529,7 @@ static int phy_bus_match(struct device *dev,
>> struct device_driver *drv)
>> const int num_ids = ARRAY_SIZE(phydev->c45_ids.device_ids);
>> int i;
>> - if (!(phydrv->mdiodrv.flags & MDIO_DEVICE_IS_PHY))
>> + if (!(is_phy_driver(&phydrv->driver)))
>
> here parens are redundant too
>
>> return 0;
>> if (phydrv->match_phy_device)
>> @@ -1456,9 +1456,9 @@ int phy_attach_direct(struct net_device *dev,
>> struct phy_device *phydev,
>> */
>> if (!d->driver) {
>> if (phydev->is_c45)
>> - d->driver = &genphy_c45_driver.mdiodrv.driver;
>> + d->driver = &genphy_c45_driver.driver;
>> else
>> - d->driver = &genphy_driver.mdiodrv.driver;
>> + d->driver = &genphy_driver.driver;
>> using_genphy = true;
>> }
>> @@ -1638,14 +1638,14 @@ static bool phy_driver_is_genphy_kind(struct
>> phy_device *phydev,
>> bool phy_driver_is_genphy(struct phy_device *phydev)
>> {
>> return phy_driver_is_genphy_kind(phydev,
>> - &genphy_driver.mdiodrv.driver);
>> + &genphy_driver.driver);
>> }
>> EXPORT_SYMBOL_GPL(phy_driver_is_genphy);
>> bool phy_driver_is_genphy_10g(struct phy_device *phydev)
>> {
>> return phy_driver_is_genphy_kind(phydev,
>> - &genphy_c45_driver.mdiodrv.driver);
>> + &genphy_c45_driver.driver);
>
> now it fits into one line (same for phy_driver_is_genphy())
>
>> }
>> EXPORT_SYMBOL_GPL(phy_driver_is_genphy_10g);
>
> [snip]
>
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^ permalink raw reply
* Re: [PATCH net-next] net: phy: Cleanup struct mdio_driver_common
From: Przemek Kitszel @ 2023-12-28 8:24 UTC (permalink / raw)
To: Yajun Deng
Cc: andrew, olteanv, hkallweit1, linux, rmk+kernel, kabel, netdev,
linux-kernel, linux-phy, davem, edumazet, kuba, pabeni
In-Reply-To: <20231228072350.1294425-1-yajun.deng@linux.dev>
On 12/28/23 08:23, Yajun Deng wrote:
> The struct mdio_driver_common is a wrapper for driver-model structure,
> it contains device_driver and flags. There are only struct phy_driver
> and mdio_driver that use it. The flags is used to distinguish between
> struct phy_driver and mdio_driver.
>
> We can test that if probe of device_driver is equal to phy_probe. This
> way, the struct mdio_driver_common is no longer needed, and struct
> phy_driver and usb_mdio_driver will be consistent with other driver
> structs.
>
> Cleanup struct mdio_driver_common and introduce is_phy_driver(). Use
> is_phy_driver() test that if the driver is a phy or not.
>
> Signed-off-by: Yajun Deng <yajun.deng@linux.dev>
> ---
> drivers/net/dsa/b53/b53_mdio.c | 2 +-
> drivers/net/dsa/dsa_loop.c | 2 +-
> drivers/net/dsa/lan9303_mdio.c | 2 +-
> drivers/net/dsa/microchip/ksz8863_smi.c | 2 +-
> drivers/net/dsa/mt7530-mdio.c | 2 +-
> drivers/net/dsa/mv88e6060.c | 2 +-
> drivers/net/dsa/mv88e6xxx/chip.c | 2 +-
> drivers/net/dsa/qca/ar9331.c | 2 +-
> drivers/net/dsa/qca/qca8k-8xxx.c | 2 +-
> drivers/net/dsa/realtek/realtek-mdio.c | 2 +-
> drivers/net/dsa/xrs700x/xrs700x_mdio.c | 2 +-
> drivers/net/phy/mdio_bus.c | 2 +-
> drivers/net/phy/mdio_device.c | 21 +++++++--------
> drivers/net/phy/phy_device.c | 35 ++++++++++++++-----------
> drivers/net/phy/xilinx_gmii2rgmii.c | 2 +-
> drivers/phy/broadcom/phy-bcm-ns-usb3.c | 8 +++---
> drivers/phy/broadcom/phy-bcm-ns2-pcie.c | 8 +++---
> include/linux/mdio.h | 16 ++---------
> include/linux/phy.h | 9 +++----
> 19 files changed, 54 insertions(+), 69 deletions(-)
>
some nitpicks from me,
otherwise looks fine:
Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com>
BTW, please send v2 after winter break:
https://patchwork.hopto.org/net-next.html
> diff --git a/drivers/net/dsa/b53/b53_mdio.c b/drivers/net/dsa/b53/b53_mdio.c
> index 897e5e8b3d69..1ececa4d44e4 100644
> --- a/drivers/net/dsa/b53/b53_mdio.c
> +++ b/drivers/net/dsa/b53/b53_mdio.c
> @@ -392,7 +392,7 @@ static struct mdio_driver b53_mdio_driver = {
> .probe = b53_mdio_probe,
> .remove = b53_mdio_remove,
> .shutdown = b53_mdio_shutdown,
> - .mdiodrv.driver = {
> + .driver = {
> .name = "bcm53xx",
> .of_match_table = b53_of_match,
> },
> diff --git a/drivers/net/dsa/dsa_loop.c b/drivers/net/dsa/dsa_loop.c
> index c70ed67cc188..3f885878be3a 100644
> --- a/drivers/net/dsa/dsa_loop.c
> +++ b/drivers/net/dsa/dsa_loop.c
> @@ -375,7 +375,7 @@ static void dsa_loop_drv_shutdown(struct mdio_device *mdiodev)
> }
>
> static struct mdio_driver dsa_loop_drv = {
> - .mdiodrv.driver = {
> + .driver = {
> .name = "dsa-loop",
> },
> .probe = dsa_loop_drv_probe,
> diff --git a/drivers/net/dsa/lan9303_mdio.c b/drivers/net/dsa/lan9303_mdio.c
> index 167a86f39f27..7cb7e2b1478a 100644
> --- a/drivers/net/dsa/lan9303_mdio.c
> +++ b/drivers/net/dsa/lan9303_mdio.c
> @@ -162,7 +162,7 @@ static const struct of_device_id lan9303_mdio_of_match[] = {
> MODULE_DEVICE_TABLE(of, lan9303_mdio_of_match);
>
> static struct mdio_driver lan9303_mdio_driver = {
> - .mdiodrv.driver = {
> + .driver = {
> .name = "LAN9303_MDIO",
> .of_match_table = lan9303_mdio_of_match,
> },
> diff --git a/drivers/net/dsa/microchip/ksz8863_smi.c b/drivers/net/dsa/microchip/ksz8863_smi.c
> index 5711a59e2ac9..c788cadd7595 100644
> --- a/drivers/net/dsa/microchip/ksz8863_smi.c
> +++ b/drivers/net/dsa/microchip/ksz8863_smi.c
> @@ -213,7 +213,7 @@ static struct mdio_driver ksz8863_driver = {
> .probe = ksz8863_smi_probe,
> .remove = ksz8863_smi_remove,
> .shutdown = ksz8863_smi_shutdown,
> - .mdiodrv.driver = {
> + .driver = {
> .name = "ksz8863-switch",
> .of_match_table = ksz8863_dt_ids,
> },
> diff --git a/drivers/net/dsa/mt7530-mdio.c b/drivers/net/dsa/mt7530-mdio.c
> index 088533663b83..7315654a6757 100644
> --- a/drivers/net/dsa/mt7530-mdio.c
> +++ b/drivers/net/dsa/mt7530-mdio.c
> @@ -258,7 +258,7 @@ static struct mdio_driver mt7530_mdio_driver = {
> .probe = mt7530_probe,
> .remove = mt7530_remove,
> .shutdown = mt7530_shutdown,
> - .mdiodrv.driver = {
> + .driver = {
> .name = "mt7530-mdio",
> .of_match_table = mt7530_of_match,
> },
> diff --git a/drivers/net/dsa/mv88e6060.c b/drivers/net/dsa/mv88e6060.c
> index 294312b58e4f..5925f23e7ab3 100644
> --- a/drivers/net/dsa/mv88e6060.c
> +++ b/drivers/net/dsa/mv88e6060.c
> @@ -367,7 +367,7 @@ static struct mdio_driver mv88e6060_driver = {
> .probe = mv88e6060_probe,
> .remove = mv88e6060_remove,
> .shutdown = mv88e6060_shutdown,
> - .mdiodrv.driver = {
> + .driver = {
> .name = "mv88e6060",
> .of_match_table = mv88e6060_of_match,
> },
> diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
> index 383b3c4d6f59..4f24699264d1 100644
> --- a/drivers/net/dsa/mv88e6xxx/chip.c
> +++ b/drivers/net/dsa/mv88e6xxx/chip.c
> @@ -7258,7 +7258,7 @@ static struct mdio_driver mv88e6xxx_driver = {
> .probe = mv88e6xxx_probe,
> .remove = mv88e6xxx_remove,
> .shutdown = mv88e6xxx_shutdown,
> - .mdiodrv.driver = {
> + .driver = {
> .name = "mv88e6085",
> .of_match_table = mv88e6xxx_of_match,
> .pm = &mv88e6xxx_pm_ops,
> diff --git a/drivers/net/dsa/qca/ar9331.c b/drivers/net/dsa/qca/ar9331.c
> index 8d9d271ac3af..da392d60c9e7 100644
> --- a/drivers/net/dsa/qca/ar9331.c
> +++ b/drivers/net/dsa/qca/ar9331.c
> @@ -1122,7 +1122,7 @@ static struct mdio_driver ar9331_sw_mdio_driver = {
> .probe = ar9331_sw_probe,
> .remove = ar9331_sw_remove,
> .shutdown = ar9331_sw_shutdown,
> - .mdiodrv.driver = {
> + .driver = {
> .name = AR9331_SW_NAME,
> .of_match_table = ar9331_sw_of_match,
> },
> diff --git a/drivers/net/dsa/qca/qca8k-8xxx.c b/drivers/net/dsa/qca/qca8k-8xxx.c
> index ec57d9d52072..fe396397f405 100644
> --- a/drivers/net/dsa/qca/qca8k-8xxx.c
> +++ b/drivers/net/dsa/qca/qca8k-8xxx.c
> @@ -2187,7 +2187,7 @@ static struct mdio_driver qca8kmdio_driver = {
> .probe = qca8k_sw_probe,
> .remove = qca8k_sw_remove,
> .shutdown = qca8k_sw_shutdown,
> - .mdiodrv.driver = {
> + .driver = {
> .name = "qca8k",
> .of_match_table = qca8k_of_match,
> .pm = &qca8k_pm_ops,
> diff --git a/drivers/net/dsa/realtek/realtek-mdio.c b/drivers/net/dsa/realtek/realtek-mdio.c
> index 292e6d087e8b..8e6a951b391c 100644
> --- a/drivers/net/dsa/realtek/realtek-mdio.c
> +++ b/drivers/net/dsa/realtek/realtek-mdio.c
> @@ -274,7 +274,7 @@ static const struct of_device_id realtek_mdio_of_match[] = {
> MODULE_DEVICE_TABLE(of, realtek_mdio_of_match);
>
> static struct mdio_driver realtek_mdio_driver = {
> - .mdiodrv.driver = {
> + .driver = {
> .name = "realtek-mdio",
> .of_match_table = realtek_mdio_of_match,
> },
> diff --git a/drivers/net/dsa/xrs700x/xrs700x_mdio.c b/drivers/net/dsa/xrs700x/xrs700x_mdio.c
> index 5f7d344b5d73..1a76d9d49f13 100644
> --- a/drivers/net/dsa/xrs700x/xrs700x_mdio.c
> +++ b/drivers/net/dsa/xrs700x/xrs700x_mdio.c
> @@ -164,7 +164,7 @@ static const struct of_device_id __maybe_unused xrs700x_mdio_dt_ids[] = {
> MODULE_DEVICE_TABLE(of, xrs700x_mdio_dt_ids);
>
> static struct mdio_driver xrs700x_mdio_driver = {
> - .mdiodrv.driver = {
> + .driver = {
> .name = "xrs700x-mdio",
> .of_match_table = of_match_ptr(xrs700x_mdio_dt_ids),
> },
> diff --git a/drivers/net/phy/mdio_bus.c b/drivers/net/phy/mdio_bus.c
> index 6cf73c15635b..a1092c641d14 100644
> --- a/drivers/net/phy/mdio_bus.c
> +++ b/drivers/net/phy/mdio_bus.c
> @@ -1342,7 +1342,7 @@ static int mdio_bus_match(struct device *dev, struct device_driver *drv)
> struct mdio_device *mdio = to_mdio_device(dev);
>
> /* Both the driver and device must type-match */
> - if (!(mdiodrv->mdiodrv.flags & MDIO_DEVICE_IS_PHY) !=
> + if (!(is_phy_driver(&mdiodrv->driver)) !=
> !(mdio->flags & MDIO_DEVICE_FLAG_PHY))
you could remove one pair of parens, and even change condition to:
if (is_phy_driver(&mdiodrv->driver) == !(mdio->flags &
MDIO_DEVICE_FLAG_PHY))
> return 0;
>
> diff --git a/drivers/net/phy/mdio_device.c b/drivers/net/phy/mdio_device.c
> index 73f6539b9e50..16232e7a1255 100644
> --- a/drivers/net/phy/mdio_device.c
> +++ b/drivers/net/phy/mdio_device.c
> @@ -40,7 +40,7 @@ int mdio_device_bus_match(struct device *dev, struct device_driver *drv)
> struct mdio_device *mdiodev = to_mdio_device(dev);
> struct mdio_driver *mdiodrv = to_mdio_driver(drv);
>
> - if (mdiodrv->mdiodrv.flags & MDIO_DEVICE_IS_PHY)
> + if (is_phy_driver(&mdiodrv->driver))
> return 0;
>
> return strcmp(mdiodev->modalias, drv->name) == 0;
> @@ -203,20 +203,19 @@ static void mdio_shutdown(struct device *dev)
> */
> int mdio_driver_register(struct mdio_driver *drv)
> {
> - struct mdio_driver_common *mdiodrv = &drv->mdiodrv;
> int retval;
>
> - pr_debug("%s: %s\n", __func__, mdiodrv->driver.name);
> + pr_debug("%s: %s\n", __func__, drv->driver.name);
>
> - mdiodrv->driver.bus = &mdio_bus_type;
> - mdiodrv->driver.probe = mdio_probe;
> - mdiodrv->driver.remove = mdio_remove;
> - mdiodrv->driver.shutdown = mdio_shutdown;
> + drv->driver.bus = &mdio_bus_type;
> + drv->driver.probe = mdio_probe;
> + drv->driver.remove = mdio_remove;
> + drv->driver.shutdown = mdio_shutdown;
>
> - retval = driver_register(&mdiodrv->driver);
> + retval = driver_register(&drv->driver);
> if (retval) {
> pr_err("%s: Error %d in registering driver\n",
> - mdiodrv->driver.name, retval);
> + drv->driver.name, retval);
>
> return retval;
> }
> @@ -227,8 +226,6 @@ EXPORT_SYMBOL(mdio_driver_register);
>
> void mdio_driver_unregister(struct mdio_driver *drv)
> {
> - struct mdio_driver_common *mdiodrv = &drv->mdiodrv;
> -
> - driver_unregister(&mdiodrv->driver);
> + driver_unregister(&drv->driver);
> }
> EXPORT_SYMBOL(mdio_driver_unregister);
> diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c
> index 3611ea64875e..55494a345bd4 100644
> --- a/drivers/net/phy/phy_device.c
> +++ b/drivers/net/phy/phy_device.c
> @@ -529,7 +529,7 @@ static int phy_bus_match(struct device *dev, struct device_driver *drv)
> const int num_ids = ARRAY_SIZE(phydev->c45_ids.device_ids);
> int i;
>
> - if (!(phydrv->mdiodrv.flags & MDIO_DEVICE_IS_PHY))
> + if (!(is_phy_driver(&phydrv->driver)))
here parens are redundant too
> return 0;
>
> if (phydrv->match_phy_device)
> @@ -1456,9 +1456,9 @@ int phy_attach_direct(struct net_device *dev, struct phy_device *phydev,
> */
> if (!d->driver) {
> if (phydev->is_c45)
> - d->driver = &genphy_c45_driver.mdiodrv.driver;
> + d->driver = &genphy_c45_driver.driver;
> else
> - d->driver = &genphy_driver.mdiodrv.driver;
> + d->driver = &genphy_driver.driver;
>
> using_genphy = true;
> }
> @@ -1638,14 +1638,14 @@ static bool phy_driver_is_genphy_kind(struct phy_device *phydev,
> bool phy_driver_is_genphy(struct phy_device *phydev)
> {
> return phy_driver_is_genphy_kind(phydev,
> - &genphy_driver.mdiodrv.driver);
> + &genphy_driver.driver);
> }
> EXPORT_SYMBOL_GPL(phy_driver_is_genphy);
>
> bool phy_driver_is_genphy_10g(struct phy_device *phydev)
> {
> return phy_driver_is_genphy_kind(phydev,
> - &genphy_c45_driver.mdiodrv.driver);
> + &genphy_c45_driver.driver);
now it fits into one line (same for phy_driver_is_genphy())
> }
> EXPORT_SYMBOL_GPL(phy_driver_is_genphy_10g);
[snip]
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply
* [PATCH net-next] net: phy: Cleanup struct mdio_driver_common
From: Yajun Deng @ 2023-12-28 7:23 UTC (permalink / raw)
To: davem, edumazet, kuba, pabeni
Cc: andrew, olteanv, hkallweit1, linux, rmk+kernel, kabel, netdev,
linux-kernel, linux-phy, Yajun Deng
The struct mdio_driver_common is a wrapper for driver-model structure,
it contains device_driver and flags. There are only struct phy_driver
and mdio_driver that use it. The flags is used to distinguish between
struct phy_driver and mdio_driver.
We can test that if probe of device_driver is equal to phy_probe. This
way, the struct mdio_driver_common is no longer needed, and struct
phy_driver and usb_mdio_driver will be consistent with other driver
structs.
Cleanup struct mdio_driver_common and introduce is_phy_driver(). Use
is_phy_driver() test that if the driver is a phy or not.
Signed-off-by: Yajun Deng <yajun.deng@linux.dev>
---
drivers/net/dsa/b53/b53_mdio.c | 2 +-
drivers/net/dsa/dsa_loop.c | 2 +-
drivers/net/dsa/lan9303_mdio.c | 2 +-
drivers/net/dsa/microchip/ksz8863_smi.c | 2 +-
drivers/net/dsa/mt7530-mdio.c | 2 +-
drivers/net/dsa/mv88e6060.c | 2 +-
drivers/net/dsa/mv88e6xxx/chip.c | 2 +-
drivers/net/dsa/qca/ar9331.c | 2 +-
drivers/net/dsa/qca/qca8k-8xxx.c | 2 +-
drivers/net/dsa/realtek/realtek-mdio.c | 2 +-
drivers/net/dsa/xrs700x/xrs700x_mdio.c | 2 +-
drivers/net/phy/mdio_bus.c | 2 +-
drivers/net/phy/mdio_device.c | 21 +++++++--------
drivers/net/phy/phy_device.c | 35 ++++++++++++++-----------
drivers/net/phy/xilinx_gmii2rgmii.c | 2 +-
drivers/phy/broadcom/phy-bcm-ns-usb3.c | 8 +++---
drivers/phy/broadcom/phy-bcm-ns2-pcie.c | 8 +++---
include/linux/mdio.h | 16 ++---------
include/linux/phy.h | 9 +++----
19 files changed, 54 insertions(+), 69 deletions(-)
diff --git a/drivers/net/dsa/b53/b53_mdio.c b/drivers/net/dsa/b53/b53_mdio.c
index 897e5e8b3d69..1ececa4d44e4 100644
--- a/drivers/net/dsa/b53/b53_mdio.c
+++ b/drivers/net/dsa/b53/b53_mdio.c
@@ -392,7 +392,7 @@ static struct mdio_driver b53_mdio_driver = {
.probe = b53_mdio_probe,
.remove = b53_mdio_remove,
.shutdown = b53_mdio_shutdown,
- .mdiodrv.driver = {
+ .driver = {
.name = "bcm53xx",
.of_match_table = b53_of_match,
},
diff --git a/drivers/net/dsa/dsa_loop.c b/drivers/net/dsa/dsa_loop.c
index c70ed67cc188..3f885878be3a 100644
--- a/drivers/net/dsa/dsa_loop.c
+++ b/drivers/net/dsa/dsa_loop.c
@@ -375,7 +375,7 @@ static void dsa_loop_drv_shutdown(struct mdio_device *mdiodev)
}
static struct mdio_driver dsa_loop_drv = {
- .mdiodrv.driver = {
+ .driver = {
.name = "dsa-loop",
},
.probe = dsa_loop_drv_probe,
diff --git a/drivers/net/dsa/lan9303_mdio.c b/drivers/net/dsa/lan9303_mdio.c
index 167a86f39f27..7cb7e2b1478a 100644
--- a/drivers/net/dsa/lan9303_mdio.c
+++ b/drivers/net/dsa/lan9303_mdio.c
@@ -162,7 +162,7 @@ static const struct of_device_id lan9303_mdio_of_match[] = {
MODULE_DEVICE_TABLE(of, lan9303_mdio_of_match);
static struct mdio_driver lan9303_mdio_driver = {
- .mdiodrv.driver = {
+ .driver = {
.name = "LAN9303_MDIO",
.of_match_table = lan9303_mdio_of_match,
},
diff --git a/drivers/net/dsa/microchip/ksz8863_smi.c b/drivers/net/dsa/microchip/ksz8863_smi.c
index 5711a59e2ac9..c788cadd7595 100644
--- a/drivers/net/dsa/microchip/ksz8863_smi.c
+++ b/drivers/net/dsa/microchip/ksz8863_smi.c
@@ -213,7 +213,7 @@ static struct mdio_driver ksz8863_driver = {
.probe = ksz8863_smi_probe,
.remove = ksz8863_smi_remove,
.shutdown = ksz8863_smi_shutdown,
- .mdiodrv.driver = {
+ .driver = {
.name = "ksz8863-switch",
.of_match_table = ksz8863_dt_ids,
},
diff --git a/drivers/net/dsa/mt7530-mdio.c b/drivers/net/dsa/mt7530-mdio.c
index 088533663b83..7315654a6757 100644
--- a/drivers/net/dsa/mt7530-mdio.c
+++ b/drivers/net/dsa/mt7530-mdio.c
@@ -258,7 +258,7 @@ static struct mdio_driver mt7530_mdio_driver = {
.probe = mt7530_probe,
.remove = mt7530_remove,
.shutdown = mt7530_shutdown,
- .mdiodrv.driver = {
+ .driver = {
.name = "mt7530-mdio",
.of_match_table = mt7530_of_match,
},
diff --git a/drivers/net/dsa/mv88e6060.c b/drivers/net/dsa/mv88e6060.c
index 294312b58e4f..5925f23e7ab3 100644
--- a/drivers/net/dsa/mv88e6060.c
+++ b/drivers/net/dsa/mv88e6060.c
@@ -367,7 +367,7 @@ static struct mdio_driver mv88e6060_driver = {
.probe = mv88e6060_probe,
.remove = mv88e6060_remove,
.shutdown = mv88e6060_shutdown,
- .mdiodrv.driver = {
+ .driver = {
.name = "mv88e6060",
.of_match_table = mv88e6060_of_match,
},
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index 383b3c4d6f59..4f24699264d1 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -7258,7 +7258,7 @@ static struct mdio_driver mv88e6xxx_driver = {
.probe = mv88e6xxx_probe,
.remove = mv88e6xxx_remove,
.shutdown = mv88e6xxx_shutdown,
- .mdiodrv.driver = {
+ .driver = {
.name = "mv88e6085",
.of_match_table = mv88e6xxx_of_match,
.pm = &mv88e6xxx_pm_ops,
diff --git a/drivers/net/dsa/qca/ar9331.c b/drivers/net/dsa/qca/ar9331.c
index 8d9d271ac3af..da392d60c9e7 100644
--- a/drivers/net/dsa/qca/ar9331.c
+++ b/drivers/net/dsa/qca/ar9331.c
@@ -1122,7 +1122,7 @@ static struct mdio_driver ar9331_sw_mdio_driver = {
.probe = ar9331_sw_probe,
.remove = ar9331_sw_remove,
.shutdown = ar9331_sw_shutdown,
- .mdiodrv.driver = {
+ .driver = {
.name = AR9331_SW_NAME,
.of_match_table = ar9331_sw_of_match,
},
diff --git a/drivers/net/dsa/qca/qca8k-8xxx.c b/drivers/net/dsa/qca/qca8k-8xxx.c
index ec57d9d52072..fe396397f405 100644
--- a/drivers/net/dsa/qca/qca8k-8xxx.c
+++ b/drivers/net/dsa/qca/qca8k-8xxx.c
@@ -2187,7 +2187,7 @@ static struct mdio_driver qca8kmdio_driver = {
.probe = qca8k_sw_probe,
.remove = qca8k_sw_remove,
.shutdown = qca8k_sw_shutdown,
- .mdiodrv.driver = {
+ .driver = {
.name = "qca8k",
.of_match_table = qca8k_of_match,
.pm = &qca8k_pm_ops,
diff --git a/drivers/net/dsa/realtek/realtek-mdio.c b/drivers/net/dsa/realtek/realtek-mdio.c
index 292e6d087e8b..8e6a951b391c 100644
--- a/drivers/net/dsa/realtek/realtek-mdio.c
+++ b/drivers/net/dsa/realtek/realtek-mdio.c
@@ -274,7 +274,7 @@ static const struct of_device_id realtek_mdio_of_match[] = {
MODULE_DEVICE_TABLE(of, realtek_mdio_of_match);
static struct mdio_driver realtek_mdio_driver = {
- .mdiodrv.driver = {
+ .driver = {
.name = "realtek-mdio",
.of_match_table = realtek_mdio_of_match,
},
diff --git a/drivers/net/dsa/xrs700x/xrs700x_mdio.c b/drivers/net/dsa/xrs700x/xrs700x_mdio.c
index 5f7d344b5d73..1a76d9d49f13 100644
--- a/drivers/net/dsa/xrs700x/xrs700x_mdio.c
+++ b/drivers/net/dsa/xrs700x/xrs700x_mdio.c
@@ -164,7 +164,7 @@ static const struct of_device_id __maybe_unused xrs700x_mdio_dt_ids[] = {
MODULE_DEVICE_TABLE(of, xrs700x_mdio_dt_ids);
static struct mdio_driver xrs700x_mdio_driver = {
- .mdiodrv.driver = {
+ .driver = {
.name = "xrs700x-mdio",
.of_match_table = of_match_ptr(xrs700x_mdio_dt_ids),
},
diff --git a/drivers/net/phy/mdio_bus.c b/drivers/net/phy/mdio_bus.c
index 6cf73c15635b..a1092c641d14 100644
--- a/drivers/net/phy/mdio_bus.c
+++ b/drivers/net/phy/mdio_bus.c
@@ -1342,7 +1342,7 @@ static int mdio_bus_match(struct device *dev, struct device_driver *drv)
struct mdio_device *mdio = to_mdio_device(dev);
/* Both the driver and device must type-match */
- if (!(mdiodrv->mdiodrv.flags & MDIO_DEVICE_IS_PHY) !=
+ if (!(is_phy_driver(&mdiodrv->driver)) !=
!(mdio->flags & MDIO_DEVICE_FLAG_PHY))
return 0;
diff --git a/drivers/net/phy/mdio_device.c b/drivers/net/phy/mdio_device.c
index 73f6539b9e50..16232e7a1255 100644
--- a/drivers/net/phy/mdio_device.c
+++ b/drivers/net/phy/mdio_device.c
@@ -40,7 +40,7 @@ int mdio_device_bus_match(struct device *dev, struct device_driver *drv)
struct mdio_device *mdiodev = to_mdio_device(dev);
struct mdio_driver *mdiodrv = to_mdio_driver(drv);
- if (mdiodrv->mdiodrv.flags & MDIO_DEVICE_IS_PHY)
+ if (is_phy_driver(&mdiodrv->driver))
return 0;
return strcmp(mdiodev->modalias, drv->name) == 0;
@@ -203,20 +203,19 @@ static void mdio_shutdown(struct device *dev)
*/
int mdio_driver_register(struct mdio_driver *drv)
{
- struct mdio_driver_common *mdiodrv = &drv->mdiodrv;
int retval;
- pr_debug("%s: %s\n", __func__, mdiodrv->driver.name);
+ pr_debug("%s: %s\n", __func__, drv->driver.name);
- mdiodrv->driver.bus = &mdio_bus_type;
- mdiodrv->driver.probe = mdio_probe;
- mdiodrv->driver.remove = mdio_remove;
- mdiodrv->driver.shutdown = mdio_shutdown;
+ drv->driver.bus = &mdio_bus_type;
+ drv->driver.probe = mdio_probe;
+ drv->driver.remove = mdio_remove;
+ drv->driver.shutdown = mdio_shutdown;
- retval = driver_register(&mdiodrv->driver);
+ retval = driver_register(&drv->driver);
if (retval) {
pr_err("%s: Error %d in registering driver\n",
- mdiodrv->driver.name, retval);
+ drv->driver.name, retval);
return retval;
}
@@ -227,8 +226,6 @@ EXPORT_SYMBOL(mdio_driver_register);
void mdio_driver_unregister(struct mdio_driver *drv)
{
- struct mdio_driver_common *mdiodrv = &drv->mdiodrv;
-
- driver_unregister(&mdiodrv->driver);
+ driver_unregister(&drv->driver);
}
EXPORT_SYMBOL(mdio_driver_unregister);
diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c
index 3611ea64875e..55494a345bd4 100644
--- a/drivers/net/phy/phy_device.c
+++ b/drivers/net/phy/phy_device.c
@@ -529,7 +529,7 @@ static int phy_bus_match(struct device *dev, struct device_driver *drv)
const int num_ids = ARRAY_SIZE(phydev->c45_ids.device_ids);
int i;
- if (!(phydrv->mdiodrv.flags & MDIO_DEVICE_IS_PHY))
+ if (!(is_phy_driver(&phydrv->driver)))
return 0;
if (phydrv->match_phy_device)
@@ -1456,9 +1456,9 @@ int phy_attach_direct(struct net_device *dev, struct phy_device *phydev,
*/
if (!d->driver) {
if (phydev->is_c45)
- d->driver = &genphy_c45_driver.mdiodrv.driver;
+ d->driver = &genphy_c45_driver.driver;
else
- d->driver = &genphy_driver.mdiodrv.driver;
+ d->driver = &genphy_driver.driver;
using_genphy = true;
}
@@ -1638,14 +1638,14 @@ static bool phy_driver_is_genphy_kind(struct phy_device *phydev,
bool phy_driver_is_genphy(struct phy_device *phydev)
{
return phy_driver_is_genphy_kind(phydev,
- &genphy_driver.mdiodrv.driver);
+ &genphy_driver.driver);
}
EXPORT_SYMBOL_GPL(phy_driver_is_genphy);
bool phy_driver_is_genphy_10g(struct phy_device *phydev)
{
return phy_driver_is_genphy_kind(phydev,
- &genphy_c45_driver.mdiodrv.driver);
+ &genphy_c45_driver.driver);
}
EXPORT_SYMBOL_GPL(phy_driver_is_genphy_10g);
@@ -3410,6 +3410,12 @@ static int phy_remove(struct device *dev)
return 0;
}
+bool is_phy_driver(struct device_driver *driver)
+{
+ return driver->probe == phy_probe;
+}
+EXPORT_SYMBOL_GPL(is_phy_driver);
+
/**
* phy_driver_register - register a phy_driver with the PHY layer
* @new_driver: new phy_driver to register
@@ -3433,20 +3439,19 @@ int phy_driver_register(struct phy_driver *new_driver, struct module *owner)
* is backed by a struct phy_device. If such a case happens, we will
* make out-of-bounds accesses and lockup in phydev->lock.
*/
- if (WARN(new_driver->mdiodrv.driver.of_match_table,
+ if (WARN(new_driver->driver.of_match_table,
"%s: driver must not provide a DT match table\n",
new_driver->name))
return -EINVAL;
- new_driver->mdiodrv.flags |= MDIO_DEVICE_IS_PHY;
- new_driver->mdiodrv.driver.name = new_driver->name;
- new_driver->mdiodrv.driver.bus = &mdio_bus_type;
- new_driver->mdiodrv.driver.probe = phy_probe;
- new_driver->mdiodrv.driver.remove = phy_remove;
- new_driver->mdiodrv.driver.owner = owner;
- new_driver->mdiodrv.driver.probe_type = PROBE_FORCE_SYNCHRONOUS;
+ new_driver->driver.name = new_driver->name;
+ new_driver->driver.bus = &mdio_bus_type;
+ new_driver->driver.probe = phy_probe;
+ new_driver->driver.remove = phy_remove;
+ new_driver->driver.owner = owner;
+ new_driver->driver.probe_type = PROBE_FORCE_SYNCHRONOUS;
- retval = driver_register(&new_driver->mdiodrv.driver);
+ retval = driver_register(&new_driver->driver);
if (retval) {
pr_err("%s: Error %d in registering driver\n",
new_driver->name, retval);
@@ -3479,7 +3484,7 @@ EXPORT_SYMBOL(phy_drivers_register);
void phy_driver_unregister(struct phy_driver *drv)
{
- driver_unregister(&drv->mdiodrv.driver);
+ driver_unregister(&drv->driver);
}
EXPORT_SYMBOL(phy_driver_unregister);
diff --git a/drivers/net/phy/xilinx_gmii2rgmii.c b/drivers/net/phy/xilinx_gmii2rgmii.c
index 7fd9fe6a602b..94ba87dc1975 100644
--- a/drivers/net/phy/xilinx_gmii2rgmii.c
+++ b/drivers/net/phy/xilinx_gmii2rgmii.c
@@ -129,7 +129,7 @@ MODULE_DEVICE_TABLE(of, xgmiitorgmii_of_match);
static struct mdio_driver xgmiitorgmii_driver = {
.probe = xgmiitorgmii_probe,
- .mdiodrv.driver = {
+ .driver = {
.name = "xgmiitorgmii",
.of_match_table = xgmiitorgmii_of_match,
},
diff --git a/drivers/phy/broadcom/phy-bcm-ns-usb3.c b/drivers/phy/broadcom/phy-bcm-ns-usb3.c
index 2c8b1b7dda5b..cb6e54e9a37e 100644
--- a/drivers/phy/broadcom/phy-bcm-ns-usb3.c
+++ b/drivers/phy/broadcom/phy-bcm-ns-usb3.c
@@ -229,11 +229,9 @@ static int bcm_ns_usb3_mdio_probe(struct mdio_device *mdiodev)
}
static struct mdio_driver bcm_ns_usb3_mdio_driver = {
- .mdiodrv = {
- .driver = {
- .name = "bcm_ns_mdio_usb3",
- .of_match_table = bcm_ns_usb3_id_table,
- },
+ .driver = {
+ .name = "bcm_ns_mdio_usb3",
+ .of_match_table = bcm_ns_usb3_id_table,
},
.probe = bcm_ns_usb3_mdio_probe,
};
diff --git a/drivers/phy/broadcom/phy-bcm-ns2-pcie.c b/drivers/phy/broadcom/phy-bcm-ns2-pcie.c
index 2eaa41f8fc70..d23e19527379 100644
--- a/drivers/phy/broadcom/phy-bcm-ns2-pcie.c
+++ b/drivers/phy/broadcom/phy-bcm-ns2-pcie.c
@@ -73,11 +73,9 @@ static const struct of_device_id ns2_pci_phy_of_match[] = {
MODULE_DEVICE_TABLE(of, ns2_pci_phy_of_match);
static struct mdio_driver ns2_pci_phy_driver = {
- .mdiodrv = {
- .driver = {
- .name = "phy-bcm-ns2-pci",
- .of_match_table = ns2_pci_phy_of_match,
- },
+ .driver = {
+ .name = "phy-bcm-ns2-pci",
+ .of_match_table = ns2_pci_phy_of_match,
},
.probe = ns2_pci_phy_probe,
};
diff --git a/include/linux/mdio.h b/include/linux/mdio.h
index 79ceee3c8673..852f838f52f5 100644
--- a/include/linux/mdio.h
+++ b/include/linux/mdio.h
@@ -50,22 +50,11 @@ static inline struct mdio_device *to_mdio_device(const struct device *dev)
return container_of(dev, struct mdio_device, dev);
}
-/* struct mdio_driver_common: Common to all MDIO drivers */
-struct mdio_driver_common {
- struct device_driver driver;
- int flags;
-};
#define MDIO_DEVICE_FLAG_PHY 1
-static inline struct mdio_driver_common *
-to_mdio_common_driver(const struct device_driver *driver)
-{
- return container_of(driver, struct mdio_driver_common, driver);
-}
-
/* struct mdio_driver: Generic MDIO driver */
struct mdio_driver {
- struct mdio_driver_common mdiodrv;
+ struct device_driver driver;
/*
* Called during discovery. Used to set
@@ -83,8 +72,7 @@ struct mdio_driver {
static inline struct mdio_driver *
to_mdio_driver(const struct device_driver *driver)
{
- return container_of(to_mdio_common_driver(driver), struct mdio_driver,
- mdiodrv);
+ return container_of(driver, struct mdio_driver, driver);
}
/* device driver data */
diff --git a/include/linux/phy.h b/include/linux/phy.h
index e9e85d347587..458bceb4a832 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -87,7 +87,6 @@ extern const int phy_10gbit_features_array[1];
#define PHY_RST_AFTER_CLK_EN 0x00000002
#define PHY_POLL_CABLE_TEST 0x00000004
#define PHY_ALWAYS_CALL_SUSPEND 0x00000008
-#define MDIO_DEVICE_IS_PHY 0x80000000
/**
* enum phy_interface_t - Interface Mode definitions
@@ -873,7 +872,7 @@ struct phy_led {
/**
* struct phy_driver - Driver structure for a particular PHY type
*
- * @mdiodrv: Data common to all MDIO devices
+ * @driver: The driver-model core driver structure.
* @phy_id: The result of reading the UID registers of this PHY
* type, and ANDing them with the phy_id_mask. This driver
* only works for PHYs with IDs which match this field
@@ -894,7 +893,7 @@ struct phy_led {
* though it is not currently supported in the driver).
*/
struct phy_driver {
- struct mdio_driver_common mdiodrv;
+ struct device_driver driver;
u32 phy_id;
char *name;
u32 phy_id_mask;
@@ -1147,8 +1146,7 @@ struct phy_driver {
unsigned long *rules);
};
-#define to_phy_driver(d) container_of(to_mdio_common_driver(d), \
- struct phy_driver, mdiodrv)
+#define to_phy_driver(d) container_of(d, struct phy_driver, driver)
#define PHY_ANY_ID "MATCH ANY PHY"
#define PHY_ANY_UID 0xffffffff
@@ -2148,5 +2146,6 @@ module_exit(phy_module_exit)
bool phy_driver_is_genphy(struct phy_device *phydev);
bool phy_driver_is_genphy_10g(struct phy_device *phydev);
+bool is_phy_driver(struct device_driver *driver);
#endif /* __PHY_H */
--
2.25.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH 1/2] phy: qcom: qmp-pcie: Update PCIe1 PHY settings for SM8550
From: Qiang Yu @ 2023-12-28 5:42 UTC (permalink / raw)
To: agross, andersson, konrad.dybcio, vkoul, kishon
Cc: linux-arm-msm, linux-phy, linux-kernel, quic_cang, quic_mrana,
quic_qianyu
In-Reply-To: <1703742157-69840-1-git-send-email-quic_qianyu@quicinc.com>
From: Can Guo <quic_cang@quicinc.com>
Align PCIe1 PHY settings with SM8550 latest PCIe PHY Hardware Programming
Guide.
Signed-off-by: Can Guo <quic_cang@quicinc.com>
Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 16 +++++++++++-----
drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h | 2 ++
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h | 1 +
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h | 2 ++
4 files changed, 16 insertions(+), 5 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index 2af7115..5f87ebc 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -1823,10 +1823,9 @@ static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_serdes_tbl[] = {
static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_ln_shrd_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01),
- QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_Q_EN_RATES, 0xe),
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x00),
- QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x00),
- QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x1f),
+ QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x0d),
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0x12),
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12),
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb),
@@ -1843,6 +1842,7 @@ static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_ln_shrd_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
+ QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE, 0x5b),
};
static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_tx_tbl[] = {
@@ -1855,13 +1855,15 @@ static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_tx_tbl[] = {
};
static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_rx_tbl[] = {
- QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0c),
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2, 0x04),
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16),
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00),
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x80),
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET, 0x7c),
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x05),
+ QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_TX_ADPT_CTRL, 0x10),
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a),
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d),
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
@@ -1883,11 +1885,13 @@ static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_rx_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x78),
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76),
QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff),
+ QMP_PHY_INIT_CFG(QSERDES_V6_20_VGA_CAL_CNTRL1, 0x00),
};
static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_pcs_tbl[] = {
+ QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G12S1_TXDEEMPH_M6DB, 0x17),
QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G3S2_PRE_GAIN, 0x2e),
- QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_COM_ELECIDLE_DLY_SEL, 0x25),
+ QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_RX_SIGDET_LVL, 0xcc),
QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG4, 0x00),
QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG5, 0x22),
QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG1, 0x04),
@@ -1898,6 +1902,8 @@ static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1),
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS, 0x00),
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG1, 0x16),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_RXEQEVAL_TIME, 0x27),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_RXEQEVAL_TIME, 0x27),
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG5, 0x02),
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN, 0x2e),
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1, 0x03),
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h
index e3eb087..dfcecf3 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h
@@ -12,6 +12,8 @@
#define QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE 0x01c
#define QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS 0x090
#define QPHY_PCIE_V6_20_PCS_EQ_CONFIG1 0x0a0
+#define QPHY_PCIE_V6_20_PCS_G3_RXEQEVAL_TIME 0x0f0
+#define QPHY_PCIE_V6_20_PCS_G4_RXEQEVAL_TIME 0x0f4
#define QPHY_PCIE_V6_20_PCS_EQ_CONFIG5 0x108
#define QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN 0x15c
#define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1 0x17c
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h
index 9c3f1e4..4d9615c 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h
@@ -7,6 +7,7 @@
#define QCOM_PHY_QMP_PCS_V6_20_H_
/* Only for QMP V6_20 PHY - USB/PCIe PCS registers */
+#define QPHY_V6_20_PCS_G12S1_TXDEEMPH_M6DB 0x170
#define QPHY_V6_20_PCS_G3S2_PRE_GAIN 0x178
#define QPHY_V6_20_PCS_RX_SIGDET_LVL 0x190
#define QPHY_V6_20_PCS_COM_ELECIDLE_DLY_SEL 0x1b8
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h
index 6ed5339..7bac5d5 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h
@@ -23,6 +23,8 @@
#define QSERDES_V6_20_RX_DFE_1 0xac
#define QSERDES_V6_20_RX_DFE_2 0xb0
#define QSERDES_V6_20_RX_DFE_3 0xb4
+#define QSERDES_V6_20_RX_TX_ADPT_CTRL 0xd4
+#define QSERDES_V6_20_VGA_CAL_CNTRL1 0xe0
#define QSERDES_V6_20_RX_VGA_CAL_MAN_VAL 0xe8
#define QSERDES_V6_20_RX_GM_CAL 0x10c
#define QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4 0x120
--
2.7.4
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH 2/2] phy: qcom: qmp-pcie: Update PCIe0 PHY settings for SM8550
From: Qiang Yu @ 2023-12-28 5:42 UTC (permalink / raw)
To: agross, andersson, konrad.dybcio, vkoul, kishon
Cc: linux-arm-msm, linux-phy, linux-kernel, quic_cang, quic_mrana,
quic_qianyu
In-Reply-To: <1703742157-69840-1-git-send-email-quic_qianyu@quicinc.com>
Align PCIe0 PHY settings with SM8550 latest PCIe PHY Hardware Programming
Guide.
Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 4 +++-
drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h | 2 ++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index 5f87ebc..857581d 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -1747,7 +1747,7 @@ static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_rx_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH2, 0x5b),
QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH3, 0x1a),
QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH4, 0x89),
- QMP_PHY_INIT_CFG(QSERDES_V6_RX_TX_ADAPT_POST_THRESH, 0xf0),
+ QMP_PHY_INIT_CFG(QSERDES_V6_RX_TX_ADAPT_POST_THRESH, 0x00),
QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x09),
QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x05),
QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08),
@@ -1767,6 +1767,8 @@ static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_pcs_tbl[] = {
};
static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_EQ_CONFIG1, 0x1e),
+ QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_RXEQEVAL_TIME, 0x27),
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d),
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h
index 91e7000..0ca7933 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h
@@ -7,6 +7,8 @@
#define QCOM_PHY_QMP_PCS_PCIE_V6_H_
/* Only for QMP V6 PHY - PCIE have different offsets than V5 */
+#define QPHY_PCIE_V6_PCS_PCIE_EQ_CONFIG1 0xa4
+#define QPHY_PCIE_V6_PCS_PCIE_RXEQEVAL_TIME 0xf4
#define QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2 0x0c
#define QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4 0x14
#define QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20
--
2.7.4
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH 0/2] phy: qcom: qmp-pcie: Update PCIe PHY settings for SM8550
From: Qiang Yu @ 2023-12-28 5:42 UTC (permalink / raw)
To: agross, andersson, konrad.dybcio, vkoul, kishon
Cc: linux-arm-msm, linux-phy, linux-kernel, quic_cang, quic_mrana,
quic_qianyu
Align PCIe0/PCIe1 PHY settings with SM8550 latest PCIe PHY Hardware
Programming Guide.
Can Guo (1):
phy: qcom: qmp-pcie: Update PCIe1 PHY settings for SM8550
Qiang Yu (1):
phy: qcom: qmp-pcie: Update PCIe0 PHY settings for SM8550
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 20 ++++++++++++++------
drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h | 2 ++
drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h | 2 ++
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h | 1 +
.../phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h | 2 ++
5 files changed, 21 insertions(+), 6 deletions(-)
--
2.7.4
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply
* [PATCH v10] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
From: Can Guo @ 2023-12-26 2:31 UTC (permalink / raw)
To: quic_cang, bvanassche, mani, vkoul, abel.vesa, dmitry.baryshkov,
neil.armstrong
Cc: linux-phy, linux-arm-msm, linux-kernel, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Kishon Vijay Abraham I
On SM8550, two sets of UFS PHY settings are provided, one set is to support
HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
settings are programming different values to different registers, mixing
the two sets and/or overwriting one set with another set is definitely not
blessed by UFS PHY designers.
To add HS-G5 support for SM8550, split the two sets of PHY settings into
their dedicated overlay tables, only the common parts of the two sets of
PHY settings are left in the .tbls.
Consider we are going to add even higher gear support in future, to avoid
adding more tables with different names, rename the .tbls_hs_g4 and make it
an array, a size of 2 is enough as of now.
In this case, .tbls alone is not a complete set of PHY settings, so either
tbls_hs_overlay[0] or tbls_hs_overlay[1] must be applied on top of the
.tbls to become a complete set of PHY settings.
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Can Guo <quic_cang@quicinc.com>
---
This change is from the series "Enable HS-G5 support on SM8550". This change
is the only remaining one to be picked up from that series, hence sending it separately.
v9 -> v10:
Somehow patch "phy: qualcomm: phy-qcom-qmp-ufs: Rectify SM8550 UFS HS-G4 PHY Settings" has been merged in phy/next, rebased this change again on phy/next.
---
drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
.../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 8 +
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 169 ++++++++++++++++++---
4 files changed, 159 insertions(+), 22 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
index fe6c450..970cc06 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
@@ -19,6 +19,7 @@
#define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
#define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
#define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
+#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
#define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
#define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
#define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
@@ -28,5 +29,6 @@
#define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
#define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
#define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
+#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
index ec72914..328c6c0 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
@@ -60,6 +60,8 @@
#define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
#define QSERDES_V6_COM_PLL_IVCO 0xf4
#define QSERDES_V6_COM_PLL_IVCO_MODE1 0xf8
+#define QSERDES_V6_COM_CMN_IETRIM 0xfc
+#define QSERDES_V6_COM_CMN_IPTRIM 0x100
#define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
#define QSERDES_V6_COM_RESETSM_CNTRL 0x118
#define QSERDES_V6_COM_LOCK_CMP_EN 0x120
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
index 35d497f..d9a87bd 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
@@ -15,13 +15,19 @@
#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
+#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
#define QSERDES_UFS_V6_RX_UCDR_SO_SATURATION 0x28
+#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
#define QSERDES_UFS_V6_RX_UCDR_PI_CTRL1 0x58
#define QSERDES_UFS_V6_RX_RX_TERM_BW_CTRL0 0xc4
#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
+#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
+#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
#define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
+#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
#define QSERDES_UFS_V6_RX_INTERFACE_MODE 0x1e0
+#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
@@ -33,6 +39,8 @@
#define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
#define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
#define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
+#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
#define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
+#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index 3c2e625..11cea34 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -41,6 +41,8 @@
#define PHY_INIT_COMPLETE_TIMEOUT 10000
+#define NUM_OVERLAY 2
+
struct qmp_phy_init_tbl {
unsigned int offset;
unsigned int val;
@@ -754,15 +756,22 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
- QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
- QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
- QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
+};
+
+static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
+};
+
+static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
@@ -771,19 +780,24 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
};
-static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
- QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
+static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_serdes[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1f),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x1b),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x1c),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
};
static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = {
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05),
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
+};
+
+static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_tx[] = {
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0x4c),
};
static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c),
- QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2),
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2),
@@ -799,16 +813,45 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02),
};
+static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_rx[] = {
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
+};
+
+static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_rx[] = {
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0c),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B3, 0xb9),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B4, 0x4f),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B6, 0xff),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL, 0x30),
+};
+
static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = {
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69),
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
- QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
+};
+
+static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_pcs[] = {
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
};
+static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_pcs[] = {
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33),
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4f),
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),
+};
+
static const struct qmp_phy_init_tbl sm8650_ufsphy_serdes[] = {
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
@@ -889,6 +932,8 @@ struct qmp_phy_cfg_tbls {
int rx_num;
const struct qmp_phy_init_tbl *pcs;
int pcs_num;
+ /* Maximum supported Gear of this tbls */
+ u32 max_gear;
};
/* struct qmp_phy_cfg - per-PHY initialization config */
@@ -896,13 +941,15 @@ struct qmp_phy_cfg {
int lanes;
const struct qmp_ufs_offsets *offsets;
+ /* Maximum supported Gear of this config */
+ u32 max_supported_gear;
/* Main init sequence for PHY blocks - serdes, tx, rx, pcs */
const struct qmp_phy_cfg_tbls tbls;
/* Additional sequence for HS Series B */
const struct qmp_phy_cfg_tbls tbls_hs_b;
- /* Additional sequence for HS G4 */
- const struct qmp_phy_cfg_tbls tbls_hs_g4;
+ /* Additional sequence for different HS Gears */
+ const struct qmp_phy_cfg_tbls tbls_hs_overlay[NUM_OVERLAY];
/* clock ids to be requested */
const char * const *clk_list;
@@ -1005,6 +1052,7 @@ static const struct qmp_phy_cfg msm8996_ufsphy_cfg = {
.lanes = 1,
.offsets = &qmp_ufs_offsets,
+ .max_supported_gear = UFS_HS_G3,
.tbls = {
.serdes = msm8996_ufsphy_serdes,
@@ -1030,6 +1078,7 @@ static const struct qmp_phy_cfg sa8775p_ufsphy_cfg = {
.lanes = 2,
.offsets = &qmp_ufs_offsets,
+ .max_supported_gear = UFS_HS_G4,
.tbls = {
.serdes = sm8350_ufsphy_serdes,
@@ -1045,13 +1094,14 @@ static const struct qmp_phy_cfg sa8775p_ufsphy_cfg = {
.serdes = sm8350_ufsphy_hs_b_serdes,
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
},
- .tbls_hs_g4 = {
+ .tbls_hs_overlay[0] = {
.tx = sm8350_ufsphy_g4_tx,
.tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
.rx = sm8350_ufsphy_g4_rx,
.rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
.pcs = sm8350_ufsphy_g4_pcs,
.pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
+ .max_gear = UFS_HS_G4,
},
.clk_list = sm8450_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
@@ -1064,6 +1114,7 @@ static const struct qmp_phy_cfg sc7280_ufsphy_cfg = {
.lanes = 2,
.offsets = &qmp_ufs_offsets,
+ .max_supported_gear = UFS_HS_G4,
.tbls = {
.serdes = sm8150_ufsphy_serdes,
@@ -1079,13 +1130,14 @@ static const struct qmp_phy_cfg sc7280_ufsphy_cfg = {
.serdes = sm8150_ufsphy_hs_b_serdes,
.serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
},
- .tbls_hs_g4 = {
+ .tbls_hs_overlay[0] = {
.tx = sm8250_ufsphy_hs_g4_tx,
.tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx),
.rx = sc7280_ufsphy_hs_g4_rx,
.rx_num = ARRAY_SIZE(sc7280_ufsphy_hs_g4_rx),
.pcs = sm8150_ufsphy_hs_g4_pcs,
.pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
+ .max_gear = UFS_HS_G4,
},
.clk_list = sm8450_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
@@ -1098,6 +1150,7 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
.lanes = 2,
.offsets = &qmp_ufs_offsets,
+ .max_supported_gear = UFS_HS_G4,
.tbls = {
.serdes = sm8350_ufsphy_serdes,
@@ -1113,13 +1166,14 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
.serdes = sm8350_ufsphy_hs_b_serdes,
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
},
- .tbls_hs_g4 = {
+ .tbls_hs_overlay[0] = {
.tx = sm8350_ufsphy_g4_tx,
.tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
.rx = sm8350_ufsphy_g4_rx,
.rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
.pcs = sm8350_ufsphy_g4_pcs,
.pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
+ .max_gear = UFS_HS_G4,
},
.clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
@@ -1132,6 +1186,7 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
.lanes = 2,
.offsets = &qmp_ufs_offsets,
+ .max_supported_gear = UFS_HS_G3,
.tbls = {
.serdes = sdm845_ufsphy_serdes,
@@ -1160,6 +1215,7 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
.lanes = 1,
.offsets = &qmp_ufs_offsets,
+ .max_supported_gear = UFS_HS_G3,
.tbls = {
.serdes = sm6115_ufsphy_serdes,
@@ -1188,6 +1244,7 @@ static const struct qmp_phy_cfg sm7150_ufsphy_cfg = {
.lanes = 1,
.offsets = &qmp_ufs_offsets,
+ .max_supported_gear = UFS_HS_G3,
.tbls = {
.serdes = sdm845_ufsphy_serdes,
@@ -1216,6 +1273,7 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
.lanes = 2,
.offsets = &qmp_ufs_offsets,
+ .max_supported_gear = UFS_HS_G4,
.tbls = {
.serdes = sm8150_ufsphy_serdes,
@@ -1231,13 +1289,14 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
.serdes = sm8150_ufsphy_hs_b_serdes,
.serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
},
- .tbls_hs_g4 = {
+ .tbls_hs_overlay[0] = {
.tx = sm8150_ufsphy_hs_g4_tx,
.tx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_tx),
.rx = sm8150_ufsphy_hs_g4_rx,
.rx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_rx),
.pcs = sm8150_ufsphy_hs_g4_pcs,
.pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
+ .max_gear = UFS_HS_G4,
},
.clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
@@ -1250,6 +1309,7 @@ static const struct qmp_phy_cfg sm8250_ufsphy_cfg = {
.lanes = 2,
.offsets = &qmp_ufs_offsets,
+ .max_supported_gear = UFS_HS_G4,
.tbls = {
.serdes = sm8150_ufsphy_serdes,
@@ -1265,13 +1325,14 @@ static const struct qmp_phy_cfg sm8250_ufsphy_cfg = {
.serdes = sm8150_ufsphy_hs_b_serdes,
.serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
},
- .tbls_hs_g4 = {
+ .tbls_hs_overlay[0] = {
.tx = sm8250_ufsphy_hs_g4_tx,
.tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx),
.rx = sm8250_ufsphy_hs_g4_rx,
.rx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_rx),
.pcs = sm8150_ufsphy_hs_g4_pcs,
.pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
+ .max_gear = UFS_HS_G4,
},
.clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
@@ -1284,6 +1345,7 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
.lanes = 2,
.offsets = &qmp_ufs_offsets,
+ .max_supported_gear = UFS_HS_G4,
.tbls = {
.serdes = sm8350_ufsphy_serdes,
@@ -1299,13 +1361,14 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
.serdes = sm8350_ufsphy_hs_b_serdes,
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
},
- .tbls_hs_g4 = {
+ .tbls_hs_overlay[0] = {
.tx = sm8350_ufsphy_g4_tx,
.tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
.rx = sm8350_ufsphy_g4_rx,
.rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
.pcs = sm8350_ufsphy_g4_pcs,
.pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
+ .max_gear = UFS_HS_G4,
},
.clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
@@ -1318,6 +1381,7 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
.lanes = 2,
.offsets = &qmp_ufs_offsets,
+ .max_supported_gear = UFS_HS_G4,
.tbls = {
.serdes = sm8350_ufsphy_serdes,
@@ -1333,13 +1397,14 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
.serdes = sm8350_ufsphy_hs_b_serdes,
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
},
- .tbls_hs_g4 = {
+ .tbls_hs_overlay[0] = {
.tx = sm8350_ufsphy_g4_tx,
.tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
.rx = sm8350_ufsphy_g4_rx,
.rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
.pcs = sm8350_ufsphy_g4_pcs,
.pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
+ .max_gear = UFS_HS_G4,
},
.clk_list = sm8450_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
@@ -1352,6 +1417,7 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {
.lanes = 2,
.offsets = &qmp_ufs_offsets_v6,
+ .max_supported_gear = UFS_HS_G5,
.tbls = {
.serdes = sm8550_ufsphy_serdes,
@@ -1367,6 +1433,26 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {
.serdes = sm8550_ufsphy_hs_b_serdes,
.serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes),
},
+ .tbls_hs_overlay[0] = {
+ .serdes = sm8550_ufsphy_g4_serdes,
+ .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g4_serdes),
+ .tx = sm8550_ufsphy_g4_tx,
+ .tx_num = ARRAY_SIZE(sm8550_ufsphy_g4_tx),
+ .rx = sm8550_ufsphy_g4_rx,
+ .rx_num = ARRAY_SIZE(sm8550_ufsphy_g4_rx),
+ .pcs = sm8550_ufsphy_g4_pcs,
+ .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g4_pcs),
+ .max_gear = UFS_HS_G4,
+ },
+ .tbls_hs_overlay[1] = {
+ .serdes = sm8550_ufsphy_g5_serdes,
+ .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g5_serdes),
+ .rx = sm8550_ufsphy_g5_rx,
+ .rx_num = ARRAY_SIZE(sm8550_ufsphy_g5_rx),
+ .pcs = sm8550_ufsphy_g5_pcs,
+ .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g5_pcs),
+ .max_gear = UFS_HS_G5,
+ },
.clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
.vreg_list = qmp_phy_vreg_l,
@@ -1378,6 +1464,7 @@ static const struct qmp_phy_cfg sm8650_ufsphy_cfg = {
.lanes = 2,
.offsets = &qmp_ufs_offsets_v6,
+ .max_supported_gear = UFS_HS_G5,
.tbls = {
.serdes = sm8650_ufsphy_serdes,
@@ -1451,17 +1538,49 @@ static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls
qmp_ufs_configure(pcs, tbls->pcs, tbls->pcs_num);
}
+static int qmp_ufs_get_gear_overlay(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
+{
+ u32 max_gear, floor_max_gear = cfg->max_supported_gear;
+ int idx, ret = -EINVAL;
+
+ for (idx = NUM_OVERLAY - 1; idx >= 0; idx--) {
+ max_gear = cfg->tbls_hs_overlay[idx].max_gear;
+
+ /* Skip if the table is not available */
+ if (max_gear == 0)
+ continue;
+
+ /* Direct matching, bail */
+ if (qmp->submode == max_gear)
+ return idx;
+
+ /* If no direct matching, the lowest gear is the best matching */
+ if (max_gear < floor_max_gear) {
+ ret = idx;
+ floor_max_gear = max_gear;
+ }
+ }
+
+ return ret;
+}
+
static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
{
+ int i;
+
qmp_ufs_serdes_init(qmp, &cfg->tbls);
- if (qmp->mode == PHY_MODE_UFS_HS_B)
- qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b);
qmp_ufs_lanes_init(qmp, &cfg->tbls);
- if (qmp->submode == UFS_HS_G4)
- qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_g4);
qmp_ufs_pcs_init(qmp, &cfg->tbls);
- if (qmp->submode == UFS_HS_G4)
- qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_g4);
+
+ i = qmp_ufs_get_gear_overlay(qmp, cfg);
+ if (i >= 0) {
+ qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_overlay[i]);
+ qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_overlay[i]);
+ qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_overlay[i]);
+ }
+
+ if (qmp->mode == PHY_MODE_UFS_HS_B)
+ qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b);
}
static int qmp_ufs_com_init(struct qmp_ufs *qmp)
@@ -1633,6 +1752,12 @@ static int qmp_ufs_disable(struct phy *phy)
static int qmp_ufs_set_mode(struct phy *phy, enum phy_mode mode, int submode)
{
struct qmp_ufs *qmp = phy_get_drvdata(phy);
+ const struct qmp_phy_cfg *cfg = qmp->cfg;
+
+ if (submode > cfg->max_supported_gear || submode == 0) {
+ dev_err(qmp->dev, "Invalid PHY submode %d\n", submode);
+ return -EINVAL;
+ }
qmp->mode = mode;
qmp->submode = submode;
--
2.7.4
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* Re: [PATCH v9 2/2] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
From: kernel test robot @ 2023-12-25 22:19 UTC (permalink / raw)
To: Can Guo, bvanassche, mani, vkoul, abel.vesa, dmitry.baryshkov,
neil.armstrong
Cc: oe-kbuild-all, Andy Gross, Bjorn Andersson, Konrad Dybcio,
Kishon Vijay Abraham I, linux-phy, linux-kernel
In-Reply-To: <1703472701-34197-3-git-send-email-quic_cang@quicinc.com>
Hi Can,
kernel test robot noticed the following build errors:
[auto build test ERROR on linus/master]
[also build test ERROR on v6.7-rc7]
[cannot apply to next-20231222]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Can-Guo/phy-qualcomm-phy-qcom-qmp-ufs-Add-High-Speed-Gear-5-support-for-SM8550/20231225-154853
base: linus/master
patch link: https://lore.kernel.org/r/1703472701-34197-3-git-send-email-quic_cang%40quicinc.com
patch subject: [PATCH v9 2/2] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
config: arc-randconfig-001-20231225 (https://download.01.org/0day-ci/archive/20231226/202312260623.FFykk4qF-lkp@intel.com/config)
compiler: arc-elf-gcc (GCC) 13.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20231226/202312260623.FFykk4qF-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202312260623.FFykk4qF-lkp@intel.com/
All error/warnings (new ones prefixed by >>):
>> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c:1071:10: error: 'const struct qmp_phy_cfg' has no member named 'tbls_hs_g4'; did you mean 'tbls_hs_b'?
1071 | .tbls_hs_g4 = {
| ^~~~~~~~~~
| tbls_hs_b
>> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c:1072:17: error: field name not in record or union initializer
1072 | .tx = sm8250_ufsphy_hs_g4_tx,
| ^
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c:1072:17: note: (near initialization for 'sc7280_ufsphy_cfg.tbls_hs_overlay')
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c:1073:17: error: field name not in record or union initializer
1073 | .tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx),
| ^
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c:1073:17: note: (near initialization for 'sc7280_ufsphy_cfg.tbls_hs_overlay')
In file included from include/linux/kernel.h:16,
from include/linux/clk.h:13,
from drivers/phy/qualcomm/phy-qcom-qmp-ufs.c:6:
>> include/linux/array_size.h:11:25: warning: initialization of 'const struct qmp_phy_init_tbl *' from 'unsigned int' makes pointer from integer without a cast [-Wint-conversion]
11 | #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]) + __must_be_array(arr))
| ^
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c:1073:35: note: in expansion of macro 'ARRAY_SIZE'
1073 | .tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx),
| ^~~~~~~~~~
include/linux/array_size.h:11:25: note: (near initialization for 'sc7280_ufsphy_cfg.tbls_hs_overlay[1].serdes')
11 | #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]) + __must_be_array(arr))
| ^
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c:1073:35: note: in expansion of macro 'ARRAY_SIZE'
1073 | .tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx),
| ^~~~~~~~~~
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c:1074:17: error: field name not in record or union initializer
1074 | .rx = sc7280_ufsphy_hs_g4_rx,
| ^
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c:1074:17: note: (near initialization for 'sc7280_ufsphy_cfg.tbls_hs_overlay')
>> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c:1075:17: warning: excess elements in array initializer
1075 | .rx_num = ARRAY_SIZE(sc7280_ufsphy_hs_g4_rx),
| ^
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c:1075:17: note: (near initialization for 'sc7280_ufsphy_cfg.tbls_hs_overlay')
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c:1075:17: error: field name not in record or union initializer
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c:1075:17: note: (near initialization for 'sc7280_ufsphy_cfg.tbls_hs_overlay')
>> include/linux/array_size.h:11:25: warning: initialization of 'const struct qmp_phy_init_tbl *' from 'unsigned int' makes pointer from integer without a cast [-Wint-conversion]
11 | #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]) + __must_be_array(arr))
| ^
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c:1075:35: note: in expansion of macro 'ARRAY_SIZE'
1075 | .rx_num = ARRAY_SIZE(sc7280_ufsphy_hs_g4_rx),
| ^~~~~~~~~~
include/linux/array_size.h:11:25: note: (near initialization for 'sc7280_ufsphy_cfg.tbls_hs_overlay[2].serdes')
11 | #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]) + __must_be_array(arr))
| ^
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c:1075:35: note: in expansion of macro 'ARRAY_SIZE'
1075 | .rx_num = ARRAY_SIZE(sc7280_ufsphy_hs_g4_rx),
| ^~~~~~~~~~
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c:1076:17: warning: excess elements in array initializer
1076 | .pcs = sm8150_ufsphy_hs_g4_pcs,
| ^
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c:1076:17: note: (near initialization for 'sc7280_ufsphy_cfg.tbls_hs_overlay')
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c:1076:17: error: field name not in record or union initializer
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c:1076:17: note: (near initialization for 'sc7280_ufsphy_cfg.tbls_hs_overlay')
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c:1077:17: warning: excess elements in array initializer
1077 | .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
| ^
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c:1077:17: note: (near initialization for 'sc7280_ufsphy_cfg.tbls_hs_overlay')
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c:1077:17: error: field name not in record or union initializer
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c:1077:17: note: (near initialization for 'sc7280_ufsphy_cfg.tbls_hs_overlay')
>> include/linux/array_size.h:11:25: warning: initialization of 'const struct qmp_phy_init_tbl *' from 'unsigned int' makes pointer from integer without a cast [-Wint-conversion]
11 | #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]) + __must_be_array(arr))
| ^
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c:1077:35: note: in expansion of macro 'ARRAY_SIZE'
1077 | .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
| ^~~~~~~~~~
include/linux/array_size.h:11:25: note: (near initialization for 'sc7280_ufsphy_cfg.tbls_hs_overlay[2].serdes')
11 | #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]) + __must_be_array(arr))
| ^
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c:1077:35: note: in expansion of macro 'ARRAY_SIZE'
1077 | .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
| ^~~~~~~~~~
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c:1078:9: warning: excess elements in array initializer
1078 | },
| ^
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c:1078:9: note: (near initialization for 'sc7280_ufsphy_cfg.tbls_hs_overlay')
>> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c:1052:53: warning: missing braces around initializer [-Wmissing-braces]
1052 | static const struct qmp_phy_cfg sc7280_ufsphy_cfg = {
| ^
>> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c:1052:53: warning: missing braces around initializer [-Wmissing-braces]
vim +1071 drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
607c101fe9f2f6 Bartosz Golaszewski 2023-04-11 1051
8abe9792d1ff7e Nitin Rawat 2023-09-19 @1052 static const struct qmp_phy_cfg sc7280_ufsphy_cfg = {
8abe9792d1ff7e Nitin Rawat 2023-09-19 1053 .lanes = 2,
8abe9792d1ff7e Nitin Rawat 2023-09-19 1054
8abe9792d1ff7e Nitin Rawat 2023-09-19 1055 .offsets = &qmp_ufs_offsets,
8abe9792d1ff7e Nitin Rawat 2023-09-19 1056
8abe9792d1ff7e Nitin Rawat 2023-09-19 1057 .tbls = {
8abe9792d1ff7e Nitin Rawat 2023-09-19 1058 .serdes = sm8150_ufsphy_serdes,
8abe9792d1ff7e Nitin Rawat 2023-09-19 1059 .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes),
8abe9792d1ff7e Nitin Rawat 2023-09-19 1060 .tx = sc7280_ufsphy_tx,
8abe9792d1ff7e Nitin Rawat 2023-09-19 1061 .tx_num = ARRAY_SIZE(sc7280_ufsphy_tx),
8abe9792d1ff7e Nitin Rawat 2023-09-19 1062 .rx = sc7280_ufsphy_rx,
8abe9792d1ff7e Nitin Rawat 2023-09-19 1063 .rx_num = ARRAY_SIZE(sc7280_ufsphy_rx),
8abe9792d1ff7e Nitin Rawat 2023-09-19 1064 .pcs = sc7280_ufsphy_pcs,
8abe9792d1ff7e Nitin Rawat 2023-09-19 1065 .pcs_num = ARRAY_SIZE(sc7280_ufsphy_pcs),
8abe9792d1ff7e Nitin Rawat 2023-09-19 1066 },
8abe9792d1ff7e Nitin Rawat 2023-09-19 1067 .tbls_hs_b = {
8abe9792d1ff7e Nitin Rawat 2023-09-19 1068 .serdes = sm8150_ufsphy_hs_b_serdes,
8abe9792d1ff7e Nitin Rawat 2023-09-19 1069 .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
8abe9792d1ff7e Nitin Rawat 2023-09-19 1070 },
8abe9792d1ff7e Nitin Rawat 2023-09-19 @1071 .tbls_hs_g4 = {
8abe9792d1ff7e Nitin Rawat 2023-09-19 @1072 .tx = sm8250_ufsphy_hs_g4_tx,
8abe9792d1ff7e Nitin Rawat 2023-09-19 @1073 .tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx),
8abe9792d1ff7e Nitin Rawat 2023-09-19 1074 .rx = sc7280_ufsphy_hs_g4_rx,
8abe9792d1ff7e Nitin Rawat 2023-09-19 @1075 .rx_num = ARRAY_SIZE(sc7280_ufsphy_hs_g4_rx),
8abe9792d1ff7e Nitin Rawat 2023-09-19 1076 .pcs = sm8150_ufsphy_hs_g4_pcs,
8abe9792d1ff7e Nitin Rawat 2023-09-19 @1077 .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
8abe9792d1ff7e Nitin Rawat 2023-09-19 1078 },
8abe9792d1ff7e Nitin Rawat 2023-09-19 1079 .clk_list = sm8450_ufs_phy_clk_l,
8abe9792d1ff7e Nitin Rawat 2023-09-19 1080 .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
8abe9792d1ff7e Nitin Rawat 2023-09-19 1081 .vreg_list = qmp_phy_vreg_l,
8abe9792d1ff7e Nitin Rawat 2023-09-19 1082 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
8abe9792d1ff7e Nitin Rawat 2023-09-19 1083 .regs = ufsphy_v4_regs_layout,
8abe9792d1ff7e Nitin Rawat 2023-09-19 1084 };
8abe9792d1ff7e Nitin Rawat 2023-09-19 1085
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
--
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^ permalink raw reply
* Re: [PATCH v3 5/8] phy: qcom: qmp-ufs: Add SC7180 support
From: Dmitry Baryshkov @ 2023-12-25 18:36 UTC (permalink / raw)
To: David Wronek
Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Herbert Xu, David S . Miller,
Vinod Koul, Kishon Vijay Abraham I, Manivannan Sadhasivam,
Alim Akhtar, Avri Altman, Bart Van Assche, Joe Mason, hexdump0815,
cros-qcom-dts-watchers, linux-arm-msm, devicetree, linux-kernel,
linux-crypto, linux-phy, linux-scsi, ~postmarketos/upstreaming,
phone-devel
In-Reply-To: <20231225120327.166160-6-davidwronek@gmail.com>
On Mon, 25 Dec 2023 at 14:05, David Wronek <davidwronek@gmail.com> wrote:
>
> The SC7180 UFS PHY is identical to the one found on SM7150. Add a
> compatible for it.
>
> Signed-off-by: David Wronek <davidwronek@gmail.com>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 3 +++
> 1 file changed, 3 insertions(+)
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
--
With best wishes
Dmitry
--
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^ permalink raw reply
* [PATCH v3 8/8] arm64: dts: qcom: Add support for Xiaomi Redmi Note 9S
From: David Wronek @ 2023-12-25 12:00 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Herbert Xu, David S . Miller,
Vinod Koul, Kishon Vijay Abraham I, Manivannan Sadhasivam,
Alim Akhtar, Avri Altman, Bart Van Assche, Joe Mason, hexdump0815
Cc: cros-qcom-dts-watchers, linux-arm-msm, devicetree, linux-kernel,
linux-crypto, linux-phy, linux-scsi, ~postmarketos/upstreaming,
phone-devel, David Wronek
In-Reply-To: <20231225120327.166160-1-davidwronek@gmail.com>
From: Joe Mason <buddyjojo06@outlook.com>
Add a device tree for the Xiaomi Redmi Note 9S (curtana) phone, based on
sm7125-xiaomi-common.dtsi.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Joe Mason <buddyjojo06@outlook.com>
Signed-off-by: David Wronek <davidwronek@gmail.com>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
.../boot/dts/qcom/sm7125-xiaomi-curtana.dts | 16 ++++++++++++++++
2 files changed, 17 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/sm7125-xiaomi-curtana.dts
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 39889d5f8e12..2e6984bbbb83 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -210,6 +210,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm6125-xiaomi-laurel-sprout.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm6350-sony-xperia-lena-pdx213.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm6375-sony-xperia-murray-pdx225.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sm7125-xiaomi-curtana.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm7125-xiaomi-joyeuse.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm7225-fairphone-fp4.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8150-hdk.dtb
diff --git a/arch/arm64/boot/dts/qcom/sm7125-xiaomi-curtana.dts b/arch/arm64/boot/dts/qcom/sm7125-xiaomi-curtana.dts
new file mode 100644
index 000000000000..12f517a8492c
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm7125-xiaomi-curtana.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023, Joe Mason <buddyjojo06@outlook.com>
+ */
+
+/dts-v1/;
+
+#include "sm7125-xiaomi-common.dtsi"
+
+/ {
+ model = "Xiaomi Redmi Note 9S";
+ compatible = "xiaomi,curtana", "qcom,sm7125";
+
+ /* required for bootloader to select correct board */
+ qcom,board-id = <0x20022 1>;
+};
--
2.43.0
--
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^ permalink raw reply related
* [PATCH v3 7/8] arm64: dts: qcom: sm7125-xiaomi-common: Add UFS nodes
From: David Wronek @ 2023-12-25 12:00 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Herbert Xu, David S . Miller,
Vinod Koul, Kishon Vijay Abraham I, Manivannan Sadhasivam,
Alim Akhtar, Avri Altman, Bart Van Assche, Joe Mason, hexdump0815
Cc: cros-qcom-dts-watchers, linux-arm-msm, devicetree, linux-kernel,
linux-crypto, linux-phy, linux-scsi, ~postmarketos/upstreaming,
phone-devel, David Wronek
In-Reply-To: <20231225120327.166160-1-davidwronek@gmail.com>
Enable the UFS found on the SM7125 Xiaomi smartphones.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: David Wronek <davidwronek@gmail.com>
---
.../boot/dts/qcom/sm7125-xiaomi-common.dtsi | 28 +++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm7125-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/sm7125-xiaomi-common.dtsi
index e55cd83c19b8..0dfd1e3730e9 100644
--- a/arch/arm64/boot/dts/qcom/sm7125-xiaomi-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm7125-xiaomi-common.dtsi
@@ -152,6 +152,9 @@ vreg_l4a_0p88: ldo4 {
regulator-min-microvolt = <824000>;
regulator-max-microvolt = <928000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
};
vreg_l5a_2p7: ldo5 {
@@ -188,6 +191,9 @@ vreg_l12a_1p8: ldo12 {
regulator-min-microvolt = <1696000>;
regulator-max-microvolt = <1952000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
};
vreg_l13a_1p8: ldo13 {
@@ -230,6 +236,9 @@ vreg_l19a_3p0: ldo19 {
regulator-min-microvolt = <2696000>;
regulator-max-microvolt = <3304000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
};
};
@@ -258,6 +267,9 @@ vreg_l3c_1p23: ldo3 {
regulator-min-microvolt = <1144000>;
regulator-max-microvolt = <1304000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ regulator-allow-set-load;
+ regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+ RPMH_REGULATOR_MODE_HPM>;
};
vreg_l4c_1p8: ldo4 {
@@ -398,6 +410,22 @@ sd-cd-pins {
};
};
+&ufs_mem_hc {
+ vcc-supply = <&vreg_l19a_3p0>;
+ vcc-max-microamp = <600000>;
+ vccq2-supply = <&vreg_l12a_1p8>;
+ vccq2-max-microamp = <600000>;
+ status = "okay";
+};
+
+&ufs_mem_phy {
+ vdda-phy-supply = <&vreg_l4a_0p88>;
+ vdda-pll-supply = <&vreg_l3c_1p23>;
+ vdda-phy-max-microamp = <62900>;
+ vdda-pll-max-microamp = <18300>;
+ status = "okay";
+};
+
&usb_1 {
qcom,select-utmi-as-pipe-clk;
status = "okay";
--
2.43.0
--
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^ permalink raw reply related
* [PATCH v3 6/8] arm64: dts: qcom: sc7180: Add UFS nodes
From: David Wronek @ 2023-12-25 11:59 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Herbert Xu, David S . Miller,
Vinod Koul, Kishon Vijay Abraham I, Manivannan Sadhasivam,
Alim Akhtar, Avri Altman, Bart Van Assche, Joe Mason, hexdump0815
Cc: cros-qcom-dts-watchers, linux-arm-msm, devicetree, linux-kernel,
linux-crypto, linux-phy, linux-scsi, ~postmarketos/upstreaming,
phone-devel, David Wronek
In-Reply-To: <20231225120327.166160-1-davidwronek@gmail.com>
Add the UFS, QMP PHY and ICE nodes for the Qualcomm SC7180 SoC.
Signed-off-by: David Wronek <davidwronek@gmail.com>
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 70 ++++++++++++++++++++++++++++
1 file changed, 70 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 4dcaa15caef2..93c867cac755 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -1532,6 +1532,76 @@ mmss_noc: interconnect@1740000 {
qcom,bcm-voters = <&apps_bcm_voter>;
};
+ ufs_mem_hc: ufshc@1d84000 {
+ compatible = "qcom,sc7180-ufshc", "qcom,ufshc",
+ "jedec,ufs-2.0";
+ reg = <0 0x01d84000 0 0x3000>;
+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&ufs_mem_phy>;
+ phy-names = "ufsphy";
+ lanes-per-direction = <1>;
+ #reset-cells = <1>;
+ resets = <&gcc GCC_UFS_PHY_BCR>;
+ reset-names = "rst";
+
+ power-domains = <&gcc UFS_PHY_GDSC>;
+
+ iommus = <&apps_smmu 0xa0 0x0>;
+
+ clock-names = "core_clk",
+ "bus_aggr_clk",
+ "iface_clk",
+ "core_clk_unipro",
+ "ref_clk",
+ "tx_lane0_sync_clk",
+ "rx_lane0_sync_clk";
+ clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_UFS_PHY_AHB_CLK>,
+ <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>;
+ freq-table-hz = <50000000 200000000>,
+ <0 0>,
+ <0 0>,
+ <37500000 150000000>,
+ <0 0>,
+ <0 0>,
+ <0 0>;
+
+ interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "ufs-ddr", "cpu-ufs";
+
+ qcom,ice = <&ice>;
+
+ status = "disabled";
+ };
+
+ ufs_mem_phy: phy@1d87000 {
+ compatible = "qcom,sc7180-qmp-ufs-phy",
+ "qcom,sm7150-qmp-ufs-phy";
+ reg = <0 0x01d87000 0 0x1000>;
+ clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
+ <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
+ clock-names = "ref", "ref_aux";
+ power-domains = <&gcc UFS_PHY_GDSC>;
+ resets = <&ufs_mem_hc 0>;
+ reset-names = "ufsphy";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ ice: crypto@1d90000 {
+ compatible = "qcom,sc7180-inline-crypto-engine",
+ "qcom,inline-crypto-engine";
+ reg = <0 0x01d90000 0 0x8000>;
+ clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+ };
+
ipa: ipa@1e40000 {
compatible = "qcom,sc7180-ipa";
--
2.43.0
--
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^ permalink raw reply related
* [PATCH v3 5/8] phy: qcom: qmp-ufs: Add SC7180 support
From: David Wronek @ 2023-12-25 11:59 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Herbert Xu, David S . Miller,
Vinod Koul, Kishon Vijay Abraham I, Manivannan Sadhasivam,
Alim Akhtar, Avri Altman, Bart Van Assche, Joe Mason, hexdump0815
Cc: cros-qcom-dts-watchers, linux-arm-msm, devicetree, linux-kernel,
linux-crypto, linux-phy, linux-scsi, ~postmarketos/upstreaming,
phone-devel, David Wronek
In-Reply-To: <20231225120327.166160-1-davidwronek@gmail.com>
The SC7180 UFS PHY is identical to the one found on SM7150. Add a
compatible for it.
Signed-off-by: David Wronek <davidwronek@gmail.com>
---
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index 3c2e6255e26f..0276de802d78 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -1880,6 +1880,9 @@ static const struct of_device_id qmp_ufs_of_match_table[] = {
}, {
.compatible = "qcom,sa8775p-qmp-ufs-phy",
.data = &sa8775p_ufsphy_cfg,
+ }, {
+ .compatible = "qcom,sc7180-qmp-ufs-phy",
+ .data = &sm7150_ufsphy_cfg,
}, {
.compatible = "qcom,sc7280-qmp-ufs-phy",
.data = &sc7280_ufsphy_cfg,
--
2.43.0
--
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^ permalink raw reply related
* [PATCH v3 4/8] dt-bindings: arm: qcom: Add Xiaomi Redmi Note 9S
From: David Wronek @ 2023-12-25 11:59 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Herbert Xu, David S . Miller,
Vinod Koul, Kishon Vijay Abraham I, Manivannan Sadhasivam,
Alim Akhtar, Avri Altman, Bart Van Assche, Joe Mason, hexdump0815
Cc: cros-qcom-dts-watchers, linux-arm-msm, devicetree, linux-kernel,
linux-crypto, linux-phy, linux-scsi, ~postmarketos/upstreaming,
phone-devel, David Wronek, Krzysztof Kozlowski
In-Reply-To: <20231225120327.166160-1-davidwronek@gmail.com>
Document the Xiaomi Redmi Note 9S (curtana) smartphone, which is based
on the Qualcomm SM7125 SoC.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: David Wronek <davidwronek@gmail.com>
---
Documentation/devicetree/bindings/arm/qcom.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 1a5fb889a444..59430524dac6 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -988,6 +988,7 @@ properties:
- items:
- enum:
+ - xiaomi,curtana
- xiaomi,joyeuse
- const: qcom,sm7125
--
2.43.0
--
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^ permalink raw reply related
* [PATCH v3 2/8] dt-bindings: ufs: qcom: Add SC7180 compatible string
From: David Wronek @ 2023-12-25 11:59 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Herbert Xu, David S . Miller,
Vinod Koul, Kishon Vijay Abraham I, Manivannan Sadhasivam,
Alim Akhtar, Avri Altman, Bart Van Assche, Joe Mason, hexdump0815
Cc: cros-qcom-dts-watchers, linux-arm-msm, devicetree, linux-kernel,
linux-crypto, linux-phy, linux-scsi, ~postmarketos/upstreaming,
phone-devel, David Wronek, Krzysztof Kozlowski
In-Reply-To: <20231225120327.166160-1-davidwronek@gmail.com>
Document the compatible for the UFS found on SC7180.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: David Wronek <davidwronek@gmail.com>
---
Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
index 10c146424baa..9a4f2b43e155 100644
--- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
+++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
@@ -27,6 +27,7 @@ properties:
- qcom,msm8996-ufshc
- qcom,msm8998-ufshc
- qcom,sa8775p-ufshc
+ - qcom,sc7180-ufshc
- qcom,sc7280-ufshc
- qcom,sc8280xp-ufshc
- qcom,sdm845-ufshc
@@ -214,6 +215,7 @@ allOf:
compatible:
contains:
enum:
+ - qcom,sc7180-ufshc
- qcom,sm6115-ufshc
then:
properties:
--
2.43.0
--
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^ permalink raw reply related
* [PATCH v3 3/8] dt-bindings: phy: Add QMP UFS PHY compatible for SC7180
From: David Wronek @ 2023-12-25 11:59 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Herbert Xu, David S . Miller,
Vinod Koul, Kishon Vijay Abraham I, Manivannan Sadhasivam,
Alim Akhtar, Avri Altman, Bart Van Assche, Joe Mason, hexdump0815
Cc: cros-qcom-dts-watchers, linux-arm-msm, devicetree, linux-kernel,
linux-crypto, linux-phy, linux-scsi, ~postmarketos/upstreaming,
phone-devel, David Wronek, Rob Herring
In-Reply-To: <20231225120327.166160-1-davidwronek@gmail.com>
Document the QMP UFS PHY compatible for SC7180
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: David Wronek <davidwronek@gmail.com>
---
.../devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
index 8474eef8d0ff..5faa1cb3a12e 100644
--- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
@@ -19,6 +19,7 @@ properties:
- qcom,msm8996-qmp-ufs-phy
- qcom,msm8998-qmp-ufs-phy
- qcom,sa8775p-qmp-ufs-phy
+ - qcom,sc7180-qmp-ufs-phy
- qcom,sc7280-qmp-ufs-phy
- qcom,sc8180x-qmp-ufs-phy
- qcom,sc8280xp-qmp-ufs-phy
@@ -102,6 +103,7 @@ allOf:
contains:
enum:
- qcom,msm8998-qmp-ufs-phy
+ - qcom,sc7180-qmp-ufs-phy
- qcom,sc8180x-qmp-ufs-phy
- qcom,sc8280xp-qmp-ufs-phy
- qcom,sdm845-qmp-ufs-phy
--
2.43.0
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH v3 1/8] dt-bindings: crypto: ice: Document SC7180 inline crypto engine
From: David Wronek @ 2023-12-25 11:59 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Herbert Xu, David S . Miller,
Vinod Koul, Kishon Vijay Abraham I, Manivannan Sadhasivam,
Alim Akhtar, Avri Altman, Bart Van Assche, Joe Mason, hexdump0815
Cc: cros-qcom-dts-watchers, linux-arm-msm, devicetree, linux-kernel,
linux-crypto, linux-phy, linux-scsi, ~postmarketos/upstreaming,
phone-devel, David Wronek, Rob Herring
In-Reply-To: <20231225120327.166160-1-davidwronek@gmail.com>
Document the compatible used for the inline crypto engine found on
SC7180.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: David Wronek <davidwronek@gmail.com>
---
.../devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
index 09e43157cc71..e91bc7dc6ad3 100644
--- a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
+++ b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
@@ -14,6 +14,7 @@ properties:
items:
- enum:
- qcom,sa8775p-inline-crypto-engine
+ - qcom,sc7180-inline-crypto-engine
- qcom,sm8450-inline-crypto-engine
- qcom,sm8550-inline-crypto-engine
- qcom,sm8650-inline-crypto-engine
--
2.43.0
--
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linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH v3 0/8] Add UFS support for SC7180/SM7125
From: David Wronek @ 2023-12-25 11:59 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Herbert Xu, David S . Miller,
Vinod Koul, Kishon Vijay Abraham I, Manivannan Sadhasivam,
Alim Akhtar, Avri Altman, Bart Van Assche, Joe Mason, hexdump0815
Cc: cros-qcom-dts-watchers, linux-arm-msm, devicetree, linux-kernel,
linux-crypto, linux-phy, linux-scsi, ~postmarketos/upstreaming,
phone-devel, David Wronek
This patchset introduces UFS support for SC7180 and SM7125, as well as
support for the Xiaomi Redmi Note 9S.
Signed-off-by: David Wronek <davidwronek@gmail.com>
---
Changes in v3:
- Use SM7150 UFS PHY compatible as a fallback
- Fix dts style issues
- Add regulator-allow-set-load and allowed-modes to UFS regulators
Changes in v2:
- Fix device tree binding for QMP PHY
- Separate ICE into its own node
- Fix style problems in sc7180.dtsi
---
David Wronek (7):
dt-bindings: crypto: ice: Document SC7180 inline crypto engine
dt-bindings: ufs: qcom: Add SC7180 compatible string
dt-bindings: phy: Add QMP UFS PHY compatible for SC7180
dt-bindings: arm: qcom: Add Xiaomi Redmi Note 9S
phy: qcom: qmp-ufs: Add SC7180 support
arm64: dts: qcom: sc7180: Add UFS nodes
arm64: dts: qcom: sm7125-xiaomi-common: Add UFS nodes
Joe Mason (1):
arm64: dts: qcom: Add support for Xiaomi Redmi Note 9S
.../devicetree/bindings/arm/qcom.yaml | 1 +
.../crypto/qcom,inline-crypto-engine.yaml | 1 +
.../phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 2 +
.../devicetree/bindings/ufs/qcom,ufs.yaml | 2 +
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/sc7180.dtsi | 70 +++++++++++++++++++
.../boot/dts/qcom/sm7125-xiaomi-common.dtsi | 28 ++++++++
.../boot/dts/qcom/sm7125-xiaomi-curtana.dts | 16 +++++
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 3 +
9 files changed, 124 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/sm7125-xiaomi-curtana.dts
--
2.43.0
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply
* [PATCH v9 RESEND 2/2] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
From: Can Guo @ 2023-12-25 6:47 UTC (permalink / raw)
To: quic_cang, bvanassche, mani, vkoul, abel.vesa, dmitry.baryshkov,
neil.armstrong
Cc: linux-phy, linux-arm-msm, linux-kernel, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Kishon Vijay Abraham I
In-Reply-To: <1703486842-36621-1-git-send-email-quic_cang@quicinc.com>
On SM8550, two sets of UFS PHY settings are provided, one set is to support
HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
settings are programming different values to different registers, mixing
the two sets and/or overwriting one set with another set is definitely not
blessed by UFS PHY designers.
To add HS-G5 support for SM8550, split the two sets of PHY settings into
their dedicated overlay tables, only the common parts of the two sets of
PHY settings are left in the .tbls.
Consider we are going to add even higher gear support in future, to avoid
adding more tables with different names, rename the .tbls_hs_g4 and make it
an array, a size of 2 is enough as of now.
In this case, .tbls alone is not a complete set of PHY settings, so either
tbls_hs_overlay[0] or tbls_hs_overlay[1] must be applied on top of the
.tbls to become a complete set of PHY settings.
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Can Guo <quic_cang@quicinc.com>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
.../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 9 ++
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 164 ++++++++++++++++++---
4 files changed, 156 insertions(+), 21 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
index c23d5e4..e563af5 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
@@ -18,6 +18,7 @@
#define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
#define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
#define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
+#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
#define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
#define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
#define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
@@ -27,5 +28,6 @@
#define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
#define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
#define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
+#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
index f420f8f..ef392ce 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
@@ -56,6 +56,8 @@
#define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
#define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
#define QSERDES_V6_COM_PLL_IVCO 0xf4
+#define QSERDES_V6_COM_CMN_IETRIM 0xfc
+#define QSERDES_V6_COM_CMN_IPTRIM 0x100
#define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
#define QSERDES_V6_COM_RESETSM_CNTRL 0x118
#define QSERDES_V6_COM_LOCK_CMP_EN 0x120
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
index 674f158..48f31c8 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
@@ -15,8 +15,15 @@
#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
+#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
+#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
+#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
+#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
+#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
#define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
+#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
+#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
@@ -28,6 +35,8 @@
#define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
#define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
#define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
+#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
#define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
+#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index ad91f92..4252af2 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -41,6 +41,8 @@
#define PHY_INIT_COMPLETE_TIMEOUT 10000
+#define NUM_OVERLAY 2
+
struct qmp_phy_init_tbl {
unsigned int offset;
unsigned int val;
@@ -649,15 +651,22 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
- QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
- QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
- QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
+};
+
+static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
+};
+
+static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
@@ -666,19 +675,24 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
};
-static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
- QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
+static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_serdes[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1f),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x1b),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x1c),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
};
static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = {
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05),
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
+};
+
+static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_tx[] = {
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0x4c),
};
static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c),
- QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2),
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2),
@@ -694,16 +708,45 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02),
};
+static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_rx[] = {
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
+};
+
+static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_rx[] = {
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0c),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B3, 0xb9),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B4, 0x4f),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B6, 0xff),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL, 0x30),
+};
+
static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = {
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69),
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
- QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
+};
+
+static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_pcs[] = {
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
};
+static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_pcs[] = {
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33),
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4f),
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),
+};
+
struct qmp_ufs_offsets {
u16 serdes;
u16 pcs;
@@ -723,6 +766,8 @@ struct qmp_phy_cfg_tbls {
int rx_num;
const struct qmp_phy_init_tbl *pcs;
int pcs_num;
+ /* Maximum supported Gear of this tbls */
+ u32 max_gear;
};
/* struct qmp_phy_cfg - per-PHY initialization config */
@@ -730,13 +775,15 @@ struct qmp_phy_cfg {
int lanes;
const struct qmp_ufs_offsets *offsets;
+ /* Maximum supported Gear of this config */
+ u32 max_supported_gear;
/* Main init sequence for PHY blocks - serdes, tx, rx, pcs */
const struct qmp_phy_cfg_tbls tbls;
/* Additional sequence for HS Series B */
const struct qmp_phy_cfg_tbls tbls_hs_b;
- /* Additional sequence for HS G4 */
- const struct qmp_phy_cfg_tbls tbls_hs_g4;
+ /* Additional sequence for different HS Gears */
+ const struct qmp_phy_cfg_tbls tbls_hs_overlay[NUM_OVERLAY];
/* clock ids to be requested */
const char * const *clk_list;
@@ -839,6 +886,7 @@ static const struct qmp_phy_cfg msm8996_ufsphy_cfg = {
.lanes = 1,
.offsets = &qmp_ufs_offsets,
+ .max_supported_gear = UFS_HS_G3,
.tbls = {
.serdes = msm8996_ufsphy_serdes,
@@ -864,6 +912,7 @@ static const struct qmp_phy_cfg sa8775p_ufsphy_cfg = {
.lanes = 2,
.offsets = &qmp_ufs_offsets,
+ .max_supported_gear = UFS_HS_G4,
.tbls = {
.serdes = sm8350_ufsphy_serdes,
@@ -879,13 +928,14 @@ static const struct qmp_phy_cfg sa8775p_ufsphy_cfg = {
.serdes = sm8350_ufsphy_hs_b_serdes,
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
},
- .tbls_hs_g4 = {
+ .tbls_hs_overlay[0] = {
.tx = sm8350_ufsphy_g4_tx,
.tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
.rx = sm8350_ufsphy_g4_rx,
.rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
.pcs = sm8350_ufsphy_g4_pcs,
.pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
+ .max_gear = UFS_HS_G4,
},
.clk_list = sm8450_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
@@ -898,6 +948,7 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
.lanes = 2,
.offsets = &qmp_ufs_offsets,
+ .max_supported_gear = UFS_HS_G4,
.tbls = {
.serdes = sm8350_ufsphy_serdes,
@@ -913,13 +964,14 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
.serdes = sm8350_ufsphy_hs_b_serdes,
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
},
- .tbls_hs_g4 = {
+ .tbls_hs_overlay[0] = {
.tx = sm8350_ufsphy_g4_tx,
.tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
.rx = sm8350_ufsphy_g4_rx,
.rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
.pcs = sm8350_ufsphy_g4_pcs,
.pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
+ .max_gear = UFS_HS_G4,
},
.clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
@@ -932,6 +984,7 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
.lanes = 2,
.offsets = &qmp_ufs_offsets,
+ .max_supported_gear = UFS_HS_G3,
.tbls = {
.serdes = sdm845_ufsphy_serdes,
@@ -960,6 +1013,7 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
.lanes = 1,
.offsets = &qmp_ufs_offsets,
+ .max_supported_gear = UFS_HS_G3,
.tbls = {
.serdes = sm6115_ufsphy_serdes,
@@ -988,6 +1042,7 @@ static const struct qmp_phy_cfg sm7150_ufsphy_cfg = {
.lanes = 1,
.offsets = &qmp_ufs_offsets,
+ .max_supported_gear = UFS_HS_G3,
.tbls = {
.serdes = sdm845_ufsphy_serdes,
@@ -1016,6 +1071,7 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
.lanes = 2,
.offsets = &qmp_ufs_offsets,
+ .max_supported_gear = UFS_HS_G4,
.tbls = {
.serdes = sm8150_ufsphy_serdes,
@@ -1031,13 +1087,14 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
.serdes = sm8150_ufsphy_hs_b_serdes,
.serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
},
- .tbls_hs_g4 = {
+ .tbls_hs_overlay[0] = {
.tx = sm8150_ufsphy_hs_g4_tx,
.tx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_tx),
.rx = sm8150_ufsphy_hs_g4_rx,
.rx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_rx),
.pcs = sm8150_ufsphy_hs_g4_pcs,
.pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
+ .max_gear = UFS_HS_G4,
},
.clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
@@ -1050,6 +1107,7 @@ static const struct qmp_phy_cfg sm8250_ufsphy_cfg = {
.lanes = 2,
.offsets = &qmp_ufs_offsets,
+ .max_supported_gear = UFS_HS_G4,
.tbls = {
.serdes = sm8150_ufsphy_serdes,
@@ -1065,13 +1123,14 @@ static const struct qmp_phy_cfg sm8250_ufsphy_cfg = {
.serdes = sm8150_ufsphy_hs_b_serdes,
.serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
},
- .tbls_hs_g4 = {
+ .tbls_hs_overlay[0] = {
.tx = sm8250_ufsphy_hs_g4_tx,
.tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx),
.rx = sm8250_ufsphy_hs_g4_rx,
.rx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_rx),
.pcs = sm8150_ufsphy_hs_g4_pcs,
.pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
+ .max_gear = UFS_HS_G4,
},
.clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
@@ -1084,6 +1143,7 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
.lanes = 2,
.offsets = &qmp_ufs_offsets,
+ .max_supported_gear = UFS_HS_G4,
.tbls = {
.serdes = sm8350_ufsphy_serdes,
@@ -1099,13 +1159,14 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
.serdes = sm8350_ufsphy_hs_b_serdes,
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
},
- .tbls_hs_g4 = {
+ .tbls_hs_overlay[0] = {
.tx = sm8350_ufsphy_g4_tx,
.tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
.rx = sm8350_ufsphy_g4_rx,
.rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
.pcs = sm8350_ufsphy_g4_pcs,
.pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
+ .max_gear = UFS_HS_G4,
},
.clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
@@ -1118,6 +1179,7 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
.lanes = 2,
.offsets = &qmp_ufs_offsets,
+ .max_supported_gear = UFS_HS_G4,
.tbls = {
.serdes = sm8350_ufsphy_serdes,
@@ -1133,13 +1195,14 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
.serdes = sm8350_ufsphy_hs_b_serdes,
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
},
- .tbls_hs_g4 = {
+ .tbls_hs_overlay[0] = {
.tx = sm8350_ufsphy_g4_tx,
.tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
.rx = sm8350_ufsphy_g4_rx,
.rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
.pcs = sm8350_ufsphy_g4_pcs,
.pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
+ .max_gear = UFS_HS_G4,
},
.clk_list = sm8450_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
@@ -1152,6 +1215,7 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {
.lanes = 2,
.offsets = &qmp_ufs_offsets_v6,
+ .max_supported_gear = UFS_HS_G5,
.tbls = {
.serdes = sm8550_ufsphy_serdes,
@@ -1167,6 +1231,26 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {
.serdes = sm8550_ufsphy_hs_b_serdes,
.serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes),
},
+ .tbls_hs_overlay[0] = {
+ .serdes = sm8550_ufsphy_g4_serdes,
+ .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g4_serdes),
+ .tx = sm8550_ufsphy_g4_tx,
+ .tx_num = ARRAY_SIZE(sm8550_ufsphy_g4_tx),
+ .rx = sm8550_ufsphy_g4_rx,
+ .rx_num = ARRAY_SIZE(sm8550_ufsphy_g4_rx),
+ .pcs = sm8550_ufsphy_g4_pcs,
+ .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g4_pcs),
+ .max_gear = UFS_HS_G4,
+ },
+ .tbls_hs_overlay[1] = {
+ .serdes = sm8550_ufsphy_g5_serdes,
+ .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g5_serdes),
+ .rx = sm8550_ufsphy_g5_rx,
+ .rx_num = ARRAY_SIZE(sm8550_ufsphy_g5_rx),
+ .pcs = sm8550_ufsphy_g5_pcs,
+ .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g5_pcs),
+ .max_gear = UFS_HS_G5,
+ },
.clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
.vreg_list = qmp_phy_vreg_l,
@@ -1229,17 +1313,49 @@ static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls
qmp_ufs_configure(pcs, tbls->pcs, tbls->pcs_num);
}
+static int qmp_ufs_get_gear_overlay(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
+{
+ u32 max_gear, floor_max_gear = cfg->max_supported_gear;
+ int idx, ret = -EINVAL;
+
+ for (idx = NUM_OVERLAY - 1; idx >= 0; idx--) {
+ max_gear = cfg->tbls_hs_overlay[idx].max_gear;
+
+ /* Skip if the table is not available */
+ if (max_gear == 0)
+ continue;
+
+ /* Direct matching, bail */
+ if (qmp->submode == max_gear)
+ return idx;
+
+ /* If no direct matching, the lowest gear is the best matching */
+ if (max_gear < floor_max_gear) {
+ ret = idx;
+ floor_max_gear = max_gear;
+ }
+ }
+
+ return ret;
+}
+
static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
{
+ int i;
+
qmp_ufs_serdes_init(qmp, &cfg->tbls);
- if (qmp->mode == PHY_MODE_UFS_HS_B)
- qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b);
qmp_ufs_lanes_init(qmp, &cfg->tbls);
- if (qmp->submode == UFS_HS_G4)
- qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_g4);
qmp_ufs_pcs_init(qmp, &cfg->tbls);
- if (qmp->submode == UFS_HS_G4)
- qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_g4);
+
+ i = qmp_ufs_get_gear_overlay(qmp, cfg);
+ if (i >= 0) {
+ qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_overlay[i]);
+ qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_overlay[i]);
+ qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_overlay[i]);
+ }
+
+ if (qmp->mode == PHY_MODE_UFS_HS_B)
+ qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b);
}
static int qmp_ufs_com_init(struct qmp_ufs *qmp)
@@ -1411,6 +1527,12 @@ static int qmp_ufs_disable(struct phy *phy)
static int qmp_ufs_set_mode(struct phy *phy, enum phy_mode mode, int submode)
{
struct qmp_ufs *qmp = phy_get_drvdata(phy);
+ const struct qmp_phy_cfg *cfg = qmp->cfg;
+
+ if (submode > cfg->max_supported_gear || submode == 0) {
+ dev_err(qmp->dev, "Invalid PHY submode %d\n", submode);
+ return -EINVAL;
+ }
qmp->mode = mode;
qmp->submode = submode;
--
2.7.4
--
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linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH v9 RESEND 1/2] phy: qualcomm: phy-qcom-qmp-ufs: Rectify SM8550 UFS HS-G4 PHY Settings
From: Can Guo @ 2023-12-25 6:47 UTC (permalink / raw)
To: quic_cang, bvanassche, mani, vkoul, abel.vesa, dmitry.baryshkov,
neil.armstrong
Cc: linux-phy, linux-arm-msm, linux-kernel, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Kishon Vijay Abraham I,
Johan Hovold
In-Reply-To: <1703486842-36621-1-git-send-email-quic_cang@quicinc.com>
The registers, which are being touched in current SM8550 UFS PHY settings,
and the values being programmed are mainly the ones working for HS-G4 mode,
meanwhile, there are also a few ones somehow taken from HS-G5 PHY settings.
However, even consider HS-G4 mode only, some of them are incorrect and some
are missing. Rectify the HS-G4 PHY settings by strictly aligning with the
SM8550 UFS PHY Hardware Programming Guide suggested HS-G4 PHY settings.
Fixes: 1679bfef906f ("phy: qcom-qmp-ufs: Add SM8550 support")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Can Guo <quic_cang@quicinc.com>
---
.../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 3 +++
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 28 +++++++++++++++-------
2 files changed, 22 insertions(+), 9 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
index 15bcb4b..674f158 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
@@ -10,9 +10,12 @@
#define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
#define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
#define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
+#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
+#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
+#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
#define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index 3927eba..ad91f92 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -658,22 +658,26 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
- QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c),
- QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
- QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
- QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
- QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99),
- QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
+};
+
+static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
};
static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = {
- QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x05),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05),
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0x4c),
};
static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
- QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2, 0x0c),
- QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c),
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2),
@@ -696,6 +700,8 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = {
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
};
struct qmp_ufs_offsets {
@@ -1157,6 +1163,10 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {
.pcs = sm8550_ufsphy_pcs,
.pcs_num = ARRAY_SIZE(sm8550_ufsphy_pcs),
},
+ .tbls_hs_b = {
+ .serdes = sm8550_ufsphy_hs_b_serdes,
+ .serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes),
+ },
.clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
.vreg_list = qmp_phy_vreg_l,
--
2.7.4
--
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https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH v9 RESEND 0/2] Enable HS-G5 support on SM8550
From: Can Guo @ 2023-12-25 6:47 UTC (permalink / raw)
To: quic_cang, bvanassche, mani, vkoul, abel.vesa, dmitry.baryshkov,
neil.armstrong
Cc: linux-phy, linux-arm-msm, linux-kernel
This series enables HS-G5 support on SM8550.
Please note that the changes to drivers/ufs/ have been picked up, resending this
series for the remaining two changes to UFS PHY.
This series is rebased on below changes from Mani -
https://patchwork.kernel.org/project/linux-scsi/patch/20230908145329.154024-1-manivannan.sadhasivam@linaro.org/
https://patchwork.kernel.org/project/linux-scsi/patch/20230908145329.154024-2-manivannan.sadhasivam@linaro.org/
This series is tested on below HW combinations -
SM8550 MTP + UFS4.0
SM8550 QRD + UFS3.1
SM8450 MTP + UFS3.1 (for regression test)
SM8350 MTP + UFS3.1 (for regression test)
Note that during reboot test on above platforms, I occasinally hit PA (PHY)
error during the 2nd init, this is not related with this series. A fix for
this is mentioned in below patchwork -
https://patchwork.kernel.org/project/linux-scsi/patch/1698145815-17396-1-git-send-email-quic_ziqichen@quicinc.com/
Also note that on platforms, which have two sets of UFS PHY settings are
provided (say G4 and no-G4, G5 and no-G5). The two sets of PHY settings are
basically programming different values to different registers, mixing the
two sets and/or overwriting one set with another set is definitely not
blessed by UFS PHY designers. For SM8550, this series will make sure we
honor the rule. However, for old targets Mani and I will fix them in
another series in future.
v8 -> v9:
Rebased two changes to UFS PHY to the phy/next tree
v7 -> v8:
In "scsi: ufs: ufs-qcom: Add support for UFS device version detection", fixed a BUG introduced from v6 -> v7. The spare register is added since HW ver 5, although reading the spare register on HW ver 4 is just getting 0x0, to be on the safe side, we are exluding HW ver 4.
v6 -> v7:
1. Rebased on linux-next, based SM8650 PHY settings are merged there, no changes to patches for UFS driver
2. Addressed comments from Mani
v5 -> v6:
1. Rebased on scsi-queue-6.8
2. Addressed comments from Dmitry and Mani in patches to phy-qcom-qmp-ufs.c
v4 -> v5:
Removed two useless debug prints in patch #9
v3 -> v4:
Used .tbls_hs_overlay array instead of adding more tables with different names like .tbls_hs_g5
v2 -> v3:
1. Addressed comments from Andrew, Mani and Bart in patch #1
2. Added patch #2 as per request from Andrew and Mani
3. Added patch #4 to fix a common issue on old targets, it is not necessary
for this series, but put in this series only because it would be easier
to maintain and no need to rebase
4. Addressed comments from Dmitry and Mani in patches to phy-qcom-qmp-ufs.c
v1 -> v2:
1. Removed 2 changes which were exposing power info in sysfs
2. Removed 1 change which was moving data structs to phy-qcom-qmp-ufs.h
3. Added one new change (the 1st one) to clean up usage of ufs_dev_params based on comments from Mani
4. Adjusted the logic of UFS device version detection according to comments from Mani:
4.1 For HW version < 0x5, go through dual init
4.2 For HW version >= 0x5
a. If UFS device version is populated, one init is required
b. If UFS device version is not populated, go through dual init
Can Guo (2):
phy: qualcomm: phy-qcom-qmp-ufs: Rectify SM8550 UFS HS-G4 PHY Settings
phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for
SM8550
drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
.../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 12 ++
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 186 ++++++++++++++++++---
4 files changed, 175 insertions(+), 27 deletions(-)
--
2.7.4
--
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^ permalink raw reply
* [PATCH v9 2/2] phy: qualcomm: phy-qcom-qmp-ufs: Add High Speed Gear 5 support for SM8550
From: Can Guo @ 2023-12-25 2:51 UTC (permalink / raw)
To: quic_cang, bvanassche, mani, vkoul, abel.vesa, dmitry.baryshkov,
neil.armstrong
Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio,
Kishon Vijay Abraham I, open list:ARM/QUALCOMM SUPPORT,
open list:GENERIC PHY FRAMEWORK, open list
In-Reply-To: <1703472701-34197-1-git-send-email-quic_cang@quicinc.com>
On SM8550, two sets of UFS PHY settings are provided, one set is to support
HS-G5, another set is to support HS-G4 and lower gears. The two sets of PHY
settings are programming different values to different registers, mixing
the two sets and/or overwriting one set with another set is definitely not
blessed by UFS PHY designers.
To add HS-G5 support for SM8550, split the two sets of PHY settings into
their dedicated overlay tables, only the common parts of the two sets of
PHY settings are left in the .tbls.
Consider we are going to add even higher gear support in future, to avoid
adding more tables with different names, rename the .tbls_hs_g4 and make it
an array, a size of 2 is enough as of now.
In this case, .tbls alone is not a complete set of PHY settings, so either
tbls_hs_overlay[0] or tbls_hs_overlay[1] must be applied on top of the
.tbls to become a complete set of PHY settings.
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Can Guo <quic_cang@quicinc.com>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h | 2 +
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h | 2 +
.../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 9 ++
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 164 ++++++++++++++++++---
4 files changed, 156 insertions(+), 21 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
index c23d5e4..e563af5 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v6.h
@@ -18,6 +18,7 @@
#define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
#define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
#define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
+#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
#define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
#define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
#define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
@@ -27,5 +28,6 @@
#define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
#define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
#define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
+#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
index f420f8f..ef392ce 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v6.h
@@ -56,6 +56,8 @@
#define QSERDES_V6_COM_SYS_CLK_CTRL 0xe4
#define QSERDES_V6_COM_SYSCLK_BUF_ENABLE 0xe8
#define QSERDES_V6_COM_PLL_IVCO 0xf4
+#define QSERDES_V6_COM_CMN_IETRIM 0xfc
+#define QSERDES_V6_COM_CMN_IPTRIM 0x100
#define QSERDES_V6_COM_SYSCLK_EN_SEL 0x110
#define QSERDES_V6_COM_RESETSM_CNTRL 0x118
#define QSERDES_V6_COM_LOCK_CMP_EN 0x120
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
index 674f158..48f31c8 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h
@@ -15,8 +15,15 @@
#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
+#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
+#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
+#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
+#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
+#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
#define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
+#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
+#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
@@ -28,6 +35,8 @@
#define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
#define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
#define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
+#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
#define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
+#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
#endif
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index ad91f92..4252af2 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -41,6 +41,8 @@
#define PHY_INIT_COMPLETE_TIMEOUT 10000
+#define NUM_OVERLAY 2
+
struct qmp_phy_init_tbl {
unsigned int offset;
unsigned int val;
@@ -649,15 +651,22 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),
- QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
- QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
- QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06),
+};
+
+static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
+};
+
+static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a),
QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),
@@ -666,19 +675,24 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {
QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07),
};
-static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = {
- QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44),
+static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_serdes[] = {
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1f),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x1b),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x1c),
+ QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
};
static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = {
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05),
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07),
+};
+
+static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_tx[] = {
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0x4c),
};
static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c),
- QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2),
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2),
@@ -694,16 +708,45 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = {
QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02),
};
+static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_rx[] = {
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e),
+};
+
+static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_rx[] = {
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0c),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4, 0x04),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS, 0x07),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x08),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B3, 0xb9),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B4, 0x4f),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B6, 0xff),
+ QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL, 0x30),
+};
+
static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = {
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69),
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
- QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
+};
+
+static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_pcs[] = {
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b),
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),
QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),
};
+static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_pcs[] = {
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33),
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4f),
+ QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e),
+};
+
struct qmp_ufs_offsets {
u16 serdes;
u16 pcs;
@@ -723,6 +766,8 @@ struct qmp_phy_cfg_tbls {
int rx_num;
const struct qmp_phy_init_tbl *pcs;
int pcs_num;
+ /* Maximum supported Gear of this tbls */
+ u32 max_gear;
};
/* struct qmp_phy_cfg - per-PHY initialization config */
@@ -730,13 +775,15 @@ struct qmp_phy_cfg {
int lanes;
const struct qmp_ufs_offsets *offsets;
+ /* Maximum supported Gear of this config */
+ u32 max_supported_gear;
/* Main init sequence for PHY blocks - serdes, tx, rx, pcs */
const struct qmp_phy_cfg_tbls tbls;
/* Additional sequence for HS Series B */
const struct qmp_phy_cfg_tbls tbls_hs_b;
- /* Additional sequence for HS G4 */
- const struct qmp_phy_cfg_tbls tbls_hs_g4;
+ /* Additional sequence for different HS Gears */
+ const struct qmp_phy_cfg_tbls tbls_hs_overlay[NUM_OVERLAY];
/* clock ids to be requested */
const char * const *clk_list;
@@ -839,6 +886,7 @@ static const struct qmp_phy_cfg msm8996_ufsphy_cfg = {
.lanes = 1,
.offsets = &qmp_ufs_offsets,
+ .max_supported_gear = UFS_HS_G3,
.tbls = {
.serdes = msm8996_ufsphy_serdes,
@@ -864,6 +912,7 @@ static const struct qmp_phy_cfg sa8775p_ufsphy_cfg = {
.lanes = 2,
.offsets = &qmp_ufs_offsets,
+ .max_supported_gear = UFS_HS_G4,
.tbls = {
.serdes = sm8350_ufsphy_serdes,
@@ -879,13 +928,14 @@ static const struct qmp_phy_cfg sa8775p_ufsphy_cfg = {
.serdes = sm8350_ufsphy_hs_b_serdes,
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
},
- .tbls_hs_g4 = {
+ .tbls_hs_overlay[0] = {
.tx = sm8350_ufsphy_g4_tx,
.tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
.rx = sm8350_ufsphy_g4_rx,
.rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
.pcs = sm8350_ufsphy_g4_pcs,
.pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
+ .max_gear = UFS_HS_G4,
},
.clk_list = sm8450_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
@@ -898,6 +948,7 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
.lanes = 2,
.offsets = &qmp_ufs_offsets,
+ .max_supported_gear = UFS_HS_G4,
.tbls = {
.serdes = sm8350_ufsphy_serdes,
@@ -913,13 +964,14 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
.serdes = sm8350_ufsphy_hs_b_serdes,
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
},
- .tbls_hs_g4 = {
+ .tbls_hs_overlay[0] = {
.tx = sm8350_ufsphy_g4_tx,
.tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
.rx = sm8350_ufsphy_g4_rx,
.rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
.pcs = sm8350_ufsphy_g4_pcs,
.pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
+ .max_gear = UFS_HS_G4,
},
.clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
@@ -932,6 +984,7 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
.lanes = 2,
.offsets = &qmp_ufs_offsets,
+ .max_supported_gear = UFS_HS_G3,
.tbls = {
.serdes = sdm845_ufsphy_serdes,
@@ -960,6 +1013,7 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
.lanes = 1,
.offsets = &qmp_ufs_offsets,
+ .max_supported_gear = UFS_HS_G3,
.tbls = {
.serdes = sm6115_ufsphy_serdes,
@@ -988,6 +1042,7 @@ static const struct qmp_phy_cfg sm7150_ufsphy_cfg = {
.lanes = 1,
.offsets = &qmp_ufs_offsets,
+ .max_supported_gear = UFS_HS_G3,
.tbls = {
.serdes = sdm845_ufsphy_serdes,
@@ -1016,6 +1071,7 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
.lanes = 2,
.offsets = &qmp_ufs_offsets,
+ .max_supported_gear = UFS_HS_G4,
.tbls = {
.serdes = sm8150_ufsphy_serdes,
@@ -1031,13 +1087,14 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
.serdes = sm8150_ufsphy_hs_b_serdes,
.serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
},
- .tbls_hs_g4 = {
+ .tbls_hs_overlay[0] = {
.tx = sm8150_ufsphy_hs_g4_tx,
.tx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_tx),
.rx = sm8150_ufsphy_hs_g4_rx,
.rx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_rx),
.pcs = sm8150_ufsphy_hs_g4_pcs,
.pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
+ .max_gear = UFS_HS_G4,
},
.clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
@@ -1050,6 +1107,7 @@ static const struct qmp_phy_cfg sm8250_ufsphy_cfg = {
.lanes = 2,
.offsets = &qmp_ufs_offsets,
+ .max_supported_gear = UFS_HS_G4,
.tbls = {
.serdes = sm8150_ufsphy_serdes,
@@ -1065,13 +1123,14 @@ static const struct qmp_phy_cfg sm8250_ufsphy_cfg = {
.serdes = sm8150_ufsphy_hs_b_serdes,
.serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes),
},
- .tbls_hs_g4 = {
+ .tbls_hs_overlay[0] = {
.tx = sm8250_ufsphy_hs_g4_tx,
.tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx),
.rx = sm8250_ufsphy_hs_g4_rx,
.rx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_rx),
.pcs = sm8150_ufsphy_hs_g4_pcs,
.pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs),
+ .max_gear = UFS_HS_G4,
},
.clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
@@ -1084,6 +1143,7 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
.lanes = 2,
.offsets = &qmp_ufs_offsets,
+ .max_supported_gear = UFS_HS_G4,
.tbls = {
.serdes = sm8350_ufsphy_serdes,
@@ -1099,13 +1159,14 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
.serdes = sm8350_ufsphy_hs_b_serdes,
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
},
- .tbls_hs_g4 = {
+ .tbls_hs_overlay[0] = {
.tx = sm8350_ufsphy_g4_tx,
.tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
.rx = sm8350_ufsphy_g4_rx,
.rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
.pcs = sm8350_ufsphy_g4_pcs,
.pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
+ .max_gear = UFS_HS_G4,
},
.clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
@@ -1118,6 +1179,7 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
.lanes = 2,
.offsets = &qmp_ufs_offsets,
+ .max_supported_gear = UFS_HS_G4,
.tbls = {
.serdes = sm8350_ufsphy_serdes,
@@ -1133,13 +1195,14 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
.serdes = sm8350_ufsphy_hs_b_serdes,
.serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
},
- .tbls_hs_g4 = {
+ .tbls_hs_overlay[0] = {
.tx = sm8350_ufsphy_g4_tx,
.tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx),
.rx = sm8350_ufsphy_g4_rx,
.rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx),
.pcs = sm8350_ufsphy_g4_pcs,
.pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
+ .max_gear = UFS_HS_G4,
},
.clk_list = sm8450_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
@@ -1152,6 +1215,7 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {
.lanes = 2,
.offsets = &qmp_ufs_offsets_v6,
+ .max_supported_gear = UFS_HS_G5,
.tbls = {
.serdes = sm8550_ufsphy_serdes,
@@ -1167,6 +1231,26 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {
.serdes = sm8550_ufsphy_hs_b_serdes,
.serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes),
},
+ .tbls_hs_overlay[0] = {
+ .serdes = sm8550_ufsphy_g4_serdes,
+ .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g4_serdes),
+ .tx = sm8550_ufsphy_g4_tx,
+ .tx_num = ARRAY_SIZE(sm8550_ufsphy_g4_tx),
+ .rx = sm8550_ufsphy_g4_rx,
+ .rx_num = ARRAY_SIZE(sm8550_ufsphy_g4_rx),
+ .pcs = sm8550_ufsphy_g4_pcs,
+ .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g4_pcs),
+ .max_gear = UFS_HS_G4,
+ },
+ .tbls_hs_overlay[1] = {
+ .serdes = sm8550_ufsphy_g5_serdes,
+ .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g5_serdes),
+ .rx = sm8550_ufsphy_g5_rx,
+ .rx_num = ARRAY_SIZE(sm8550_ufsphy_g5_rx),
+ .pcs = sm8550_ufsphy_g5_pcs,
+ .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g5_pcs),
+ .max_gear = UFS_HS_G5,
+ },
.clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
.vreg_list = qmp_phy_vreg_l,
@@ -1229,17 +1313,49 @@ static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls
qmp_ufs_configure(pcs, tbls->pcs, tbls->pcs_num);
}
+static int qmp_ufs_get_gear_overlay(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
+{
+ u32 max_gear, floor_max_gear = cfg->max_supported_gear;
+ int idx, ret = -EINVAL;
+
+ for (idx = NUM_OVERLAY - 1; idx >= 0; idx--) {
+ max_gear = cfg->tbls_hs_overlay[idx].max_gear;
+
+ /* Skip if the table is not available */
+ if (max_gear == 0)
+ continue;
+
+ /* Direct matching, bail */
+ if (qmp->submode == max_gear)
+ return idx;
+
+ /* If no direct matching, the lowest gear is the best matching */
+ if (max_gear < floor_max_gear) {
+ ret = idx;
+ floor_max_gear = max_gear;
+ }
+ }
+
+ return ret;
+}
+
static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg)
{
+ int i;
+
qmp_ufs_serdes_init(qmp, &cfg->tbls);
- if (qmp->mode == PHY_MODE_UFS_HS_B)
- qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b);
qmp_ufs_lanes_init(qmp, &cfg->tbls);
- if (qmp->submode == UFS_HS_G4)
- qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_g4);
qmp_ufs_pcs_init(qmp, &cfg->tbls);
- if (qmp->submode == UFS_HS_G4)
- qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_g4);
+
+ i = qmp_ufs_get_gear_overlay(qmp, cfg);
+ if (i >= 0) {
+ qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_overlay[i]);
+ qmp_ufs_lanes_init(qmp, &cfg->tbls_hs_overlay[i]);
+ qmp_ufs_pcs_init(qmp, &cfg->tbls_hs_overlay[i]);
+ }
+
+ if (qmp->mode == PHY_MODE_UFS_HS_B)
+ qmp_ufs_serdes_init(qmp, &cfg->tbls_hs_b);
}
static int qmp_ufs_com_init(struct qmp_ufs *qmp)
@@ -1411,6 +1527,12 @@ static int qmp_ufs_disable(struct phy *phy)
static int qmp_ufs_set_mode(struct phy *phy, enum phy_mode mode, int submode)
{
struct qmp_ufs *qmp = phy_get_drvdata(phy);
+ const struct qmp_phy_cfg *cfg = qmp->cfg;
+
+ if (submode > cfg->max_supported_gear || submode == 0) {
+ dev_err(qmp->dev, "Invalid PHY submode %d\n", submode);
+ return -EINVAL;
+ }
qmp->mode = mode;
qmp->submode = submode;
--
2.7.4
--
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