* [PATCH v9 11/13] ARM: dts: stm32: put ETZPC as an access controller for STM32MP15x boards
From: Gatien Chevallier @ 2024-01-05 13:04 UTC (permalink / raw)
To: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
krzysztof.kozlowski+dt, conor+dt, alexandre.torgue, vkoul, jic23,
olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
andi.shyti, ulf.hansson, edumazet, kuba, pabeni, hugues.fruchet,
lee, will, catalin.marinas, arnd, richardcochran, Frank Rowand,
peng.fan, lars, rcsekar, wg, mkl
Cc: linux-crypto, devicetree, linux-stm32, linux-arm-kernel,
linux-kernel, dmaengine, linux-i2c, linux-iio, alsa-devel,
linux-media, linux-mmc, netdev, linux-phy, linux-serial,
linux-spi, linux-usb, Gatien Chevallier
In-Reply-To: <20240105130404.301172-1-gatien.chevallier@foss.st.com>
Reference ETZPC as an access-control-provider.
For more information on which peripheral is securable or supports MCU
isolation, please read the STM32MP13 reference manual
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
---
Patch not present in V6
arch/arm/boot/dts/st/stm32mp151.dtsi | 66 ++++++++++++++++++++++++++-
arch/arm/boot/dts/st/stm32mp153.dtsi | 2 +
arch/arm/boot/dts/st/stm32mp15xc.dtsi | 1 +
3 files changed, 68 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/st/stm32mp151.dtsi b/arch/arm/boot/dts/st/stm32mp151.dtsi
index 78c0d6ccdb09..8a40df8a097b 100644
--- a/arch/arm/boot/dts/st/stm32mp151.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp151.dtsi
@@ -330,10 +330,11 @@ ts_cal2: calib@5e {
};
etzpc: bus@5c007000 {
- compatible = "st,stm32-etzpc";
+ compatible = "st,stm32-etzpc", "simple-bus";
reg = <0x5c007000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
+ #access-controller-cells = <1>;
ranges;
timers2: timer@40000000 {
@@ -351,6 +352,7 @@ timers2: timer@40000000 {
<&dmamux1 21 0x400 0x1>,
<&dmamux1 22 0x400 0x1>;
dma-names = "ch1", "ch2", "ch3", "ch4", "up";
+ access-controllers = <&etzpc 16>;
status = "disabled";
pwm {
@@ -387,6 +389,7 @@ timers3: timer@40001000 {
<&dmamux1 27 0x400 0x1>,
<&dmamux1 28 0x400 0x1>;
dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
+ access-controllers = <&etzpc 17>;
status = "disabled";
pwm {
@@ -421,6 +424,7 @@ timers4: timer@40002000 {
<&dmamux1 31 0x400 0x1>,
<&dmamux1 32 0x400 0x1>;
dma-names = "ch1", "ch2", "ch3", "ch4";
+ access-controllers = <&etzpc 18>;
status = "disabled";
pwm {
@@ -457,6 +461,7 @@ timers5: timer@40003000 {
<&dmamux1 59 0x400 0x1>,
<&dmamux1 60 0x400 0x1>;
dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
+ access-controllers = <&etzpc 19>;
status = "disabled";
pwm {
@@ -488,6 +493,7 @@ timers6: timer@40004000 {
clock-names = "int";
dmas = <&dmamux1 69 0x400 0x1>;
dma-names = "up";
+ access-controllers = <&etzpc 20>;
status = "disabled";
timer@5 {
@@ -508,6 +514,7 @@ timers7: timer@40005000 {
clock-names = "int";
dmas = <&dmamux1 70 0x400 0x1>;
dma-names = "up";
+ access-controllers = <&etzpc 21>;
status = "disabled";
timer@6 {
@@ -526,6 +533,7 @@ timers12: timer@40006000 {
interrupt-names = "global";
clocks = <&rcc TIM12_K>;
clock-names = "int";
+ access-controllers = <&etzpc 22>;
status = "disabled";
pwm {
@@ -550,6 +558,7 @@ timers13: timer@40007000 {
interrupt-names = "global";
clocks = <&rcc TIM13_K>;
clock-names = "int";
+ access-controllers = <&etzpc 23>;
status = "disabled";
pwm {
@@ -574,6 +583,7 @@ timers14: timer@40008000 {
interrupt-names = "global";
clocks = <&rcc TIM14_K>;
clock-names = "int";
+ access-controllers = <&etzpc 24>;
status = "disabled";
pwm {
@@ -598,6 +608,7 @@ lptimer1: timer@40009000 {
clocks = <&rcc LPTIM1_K>;
clock-names = "mux";
wakeup-source;
+ access-controllers = <&etzpc 25>;
status = "disabled";
pwm {
@@ -626,6 +637,7 @@ i2s2: audio-controller@4000b000 {
dmas = <&dmamux1 39 0x400 0x01>,
<&dmamux1 40 0x400 0x01>;
dma-names = "rx", "tx";
+ access-controllers = <&etzpc 27>;
status = "disabled";
};
@@ -640,6 +652,7 @@ spi2: spi@4000b000 {
dmas = <&dmamux1 39 0x400 0x05>,
<&dmamux1 40 0x400 0x05>;
dma-names = "rx", "tx";
+ access-controllers = <&etzpc 27>;
status = "disabled";
};
@@ -651,6 +664,7 @@ i2s3: audio-controller@4000c000 {
dmas = <&dmamux1 61 0x400 0x01>,
<&dmamux1 62 0x400 0x01>;
dma-names = "rx", "tx";
+ access-controllers = <&etzpc 28>;
status = "disabled";
};
@@ -665,6 +679,7 @@ spi3: spi@4000c000 {
dmas = <&dmamux1 61 0x400 0x05>,
<&dmamux1 62 0x400 0x05>;
dma-names = "rx", "tx";
+ access-controllers = <&etzpc 28>;
status = "disabled";
};
@@ -678,6 +693,7 @@ spdifrx: audio-controller@4000d000 {
dmas = <&dmamux1 93 0x400 0x01>,
<&dmamux1 94 0x400 0x01>;
dma-names = "rx", "rx-ctrl";
+ access-controllers = <&etzpc 29>;
status = "disabled";
};
@@ -690,6 +706,7 @@ usart2: serial@4000e000 {
dmas = <&dmamux1 43 0x400 0x15>,
<&dmamux1 44 0x400 0x11>;
dma-names = "rx", "tx";
+ access-controllers = <&etzpc 30>;
status = "disabled";
};
@@ -702,6 +719,7 @@ usart3: serial@4000f000 {
dmas = <&dmamux1 45 0x400 0x15>,
<&dmamux1 46 0x400 0x11>;
dma-names = "rx", "tx";
+ access-controllers = <&etzpc 31>;
status = "disabled";
};
@@ -714,6 +732,7 @@ uart4: serial@40010000 {
dmas = <&dmamux1 63 0x400 0x15>,
<&dmamux1 64 0x400 0x11>;
dma-names = "rx", "tx";
+ access-controllers = <&etzpc 32>;
status = "disabled";
};
@@ -726,6 +745,7 @@ uart5: serial@40011000 {
dmas = <&dmamux1 65 0x400 0x15>,
<&dmamux1 66 0x400 0x11>;
dma-names = "rx", "tx";
+ access-controllers = <&etzpc 33>;
status = "disabled";
};
@@ -742,6 +762,7 @@ i2c1: i2c@40012000 {
st,syscfg-fmp = <&syscfg 0x4 0x1>;
wakeup-source;
i2c-analog-filter;
+ access-controllers = <&etzpc 34>;
status = "disabled";
};
@@ -758,6 +779,7 @@ i2c2: i2c@40013000 {
st,syscfg-fmp = <&syscfg 0x4 0x2>;
wakeup-source;
i2c-analog-filter;
+ access-controllers = <&etzpc 35>;
status = "disabled";
};
@@ -774,6 +796,7 @@ i2c3: i2c@40014000 {
st,syscfg-fmp = <&syscfg 0x4 0x4>;
wakeup-source;
i2c-analog-filter;
+ access-controllers = <&etzpc 36>;
status = "disabled";
};
@@ -790,6 +813,7 @@ i2c5: i2c@40015000 {
st,syscfg-fmp = <&syscfg 0x4 0x10>;
wakeup-source;
i2c-analog-filter;
+ access-controllers = <&etzpc 37>;
status = "disabled";
};
@@ -799,6 +823,7 @@ cec: cec@40016000 {
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CEC_K>, <&rcc CEC>;
clock-names = "cec", "hdmi-cec";
+ access-controllers = <&etzpc 38>;
status = "disabled";
};
@@ -809,6 +834,7 @@ dac: dac@40017000 {
clock-names = "pclk";
#address-cells = <1>;
#size-cells = <0>;
+ access-controllers = <&etzpc 39>;
status = "disabled";
dac1: dac@1 {
@@ -835,6 +861,7 @@ uart7: serial@40018000 {
dmas = <&dmamux1 79 0x400 0x15>,
<&dmamux1 80 0x400 0x11>;
dma-names = "rx", "tx";
+ access-controllers = <&etzpc 40>;
status = "disabled";
};
@@ -847,6 +874,7 @@ uart8: serial@40019000 {
dmas = <&dmamux1 81 0x400 0x15>,
<&dmamux1 82 0x400 0x11>;
dma-names = "rx", "tx";
+ access-controllers = <&etzpc 41>;
status = "disabled";
};
@@ -871,6 +899,7 @@ timers1: timer@44000000 {
<&dmamux1 17 0x400 0x1>;
dma-names = "ch1", "ch2", "ch3", "ch4",
"up", "trig", "com";
+ access-controllers = <&etzpc 48>;
status = "disabled";
pwm {
@@ -912,6 +941,7 @@ timers8: timer@44001000 {
<&dmamux1 53 0x400 0x1>;
dma-names = "ch1", "ch2", "ch3", "ch4",
"up", "trig", "com";
+ access-controllers = <&etzpc 49>;
status = "disabled";
pwm {
@@ -941,6 +971,7 @@ usart6: serial@44003000 {
dmas = <&dmamux1 71 0x400 0x15>,
<&dmamux1 72 0x400 0x11>;
dma-names = "rx", "tx";
+ access-controllers = <&etzpc 51>;
status = "disabled";
};
@@ -952,6 +983,7 @@ i2s1: audio-controller@44004000 {
dmas = <&dmamux1 37 0x400 0x01>,
<&dmamux1 38 0x400 0x01>;
dma-names = "rx", "tx";
+ access-controllers = <&etzpc 52>;
status = "disabled";
};
@@ -966,6 +998,7 @@ spi1: spi@44004000 {
dmas = <&dmamux1 37 0x400 0x05>,
<&dmamux1 38 0x400 0x05>;
dma-names = "rx", "tx";
+ access-controllers = <&etzpc 52>;
status = "disabled";
};
@@ -980,6 +1013,7 @@ spi4: spi@44005000 {
dmas = <&dmamux1 83 0x400 0x05>,
<&dmamux1 84 0x400 0x05>;
dma-names = "rx", "tx";
+ access-controllers = <&etzpc 53>;
status = "disabled";
};
@@ -997,6 +1031,7 @@ timers15: timer@44006000 {
<&dmamux1 107 0x400 0x1>,
<&dmamux1 108 0x400 0x1>;
dma-names = "ch1", "up", "trig", "com";
+ access-controllers = <&etzpc 54>;
status = "disabled";
pwm {
@@ -1024,6 +1059,7 @@ timers16: timer@44007000 {
dmas = <&dmamux1 109 0x400 0x1>,
<&dmamux1 110 0x400 0x1>;
dma-names = "ch1", "up";
+ access-controllers = <&etzpc 55>;
status = "disabled";
pwm {
@@ -1050,6 +1086,7 @@ timers17: timer@44008000 {
dmas = <&dmamux1 111 0x400 0x1>,
<&dmamux1 112 0x400 0x1>;
dma-names = "ch1", "up";
+ access-controllers = <&etzpc 56>;
status = "disabled";
pwm {
@@ -1076,6 +1113,7 @@ spi5: spi@44009000 {
dmas = <&dmamux1 85 0x400 0x05>,
<&dmamux1 86 0x400 0x05>;
dma-names = "rx", "tx";
+ access-controllers = <&etzpc 57>;
status = "disabled";
};
@@ -1087,6 +1125,7 @@ sai1: sai@4400a000 {
reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rcc SAI1_R>;
+ access-controllers = <&etzpc 58>;
status = "disabled";
sai1a: audio-controller@4400a004 {
@@ -1119,6 +1158,7 @@ sai2: sai@4400b000 {
reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rcc SAI2_R>;
+ access-controllers = <&etzpc 59>;
status = "disabled";
sai2a: audio-controller@4400b004 {
@@ -1150,6 +1190,7 @@ sai3: sai@4400c000 {
reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rcc SAI3_R>;
+ access-controllers = <&etzpc 60>;
status = "disabled";
sai3a: audio-controller@4400c004 {
@@ -1180,6 +1221,7 @@ dfsdm: dfsdm@4400d000 {
clock-names = "dfsdm";
#address-cells = <1>;
#size-cells = <0>;
+ access-controllers = <&etzpc 61>;
status = "disabled";
dfsdm0: filter@0 {
@@ -1259,6 +1301,7 @@ dma1: dma-controller@48000000 {
#dma-cells = <4>;
st,mem2mem;
dma-requests = <8>;
+ access-controllers = <&etzpc 88>;
};
dma2: dma-controller@48001000 {
@@ -1277,6 +1320,7 @@ dma2: dma-controller@48001000 {
#dma-cells = <4>;
st,mem2mem;
dma-requests = <8>;
+ access-controllers = <&etzpc 89>;
};
dmamux1: dma-router@48002000 {
@@ -1288,6 +1332,7 @@ dmamux1: dma-router@48002000 {
dma-channels = <16>;
clocks = <&rcc DMAMUX>;
resets = <&rcc DMAMUX_R>;
+ access-controllers = <&etzpc 90>;
};
adc: adc@48003000 {
@@ -1302,6 +1347,7 @@ adc: adc@48003000 {
#interrupt-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
+ access-controllers = <&etzpc 72>;
status = "disabled";
adc1: adc@0 {
@@ -1352,6 +1398,7 @@ sdmmc3: mmc@48004000 {
cap-sd-highspeed;
cap-mmc-highspeed;
max-frequency = <120000000>;
+ access-controllers = <&etzpc 86>;
status = "disabled";
};
@@ -1369,6 +1416,7 @@ usbotg_hs: usb-otg@49000000 {
dr_mode = "otg";
otg-rev = <0x200>;
usb33d-supply = <&usb33>;
+ access-controllers = <&etzpc 85>;
status = "disabled";
};
@@ -1381,6 +1429,7 @@ dcmi: dcmi@4c006000 {
clock-names = "mclk";
dmas = <&dmamux1 75 0x400 0x01>;
dma-names = "tx";
+ access-controllers = <&etzpc 70>;
status = "disabled";
};
@@ -1393,6 +1442,7 @@ lptimer2: timer@50021000 {
clocks = <&rcc LPTIM2_K>;
clock-names = "mux";
wakeup-source;
+ access-controllers = <&etzpc 64>;
status = "disabled";
pwm {
@@ -1422,6 +1472,7 @@ lptimer3: timer@50022000 {
clocks = <&rcc LPTIM3_K>;
clock-names = "mux";
wakeup-source;
+ access-controllers = <&etzpc 65>;
status = "disabled";
pwm {
@@ -1444,6 +1495,7 @@ lptimer4: timer@50023000 {
clocks = <&rcc LPTIM4_K>;
clock-names = "mux";
wakeup-source;
+ access-controllers = <&etzpc 66>;
status = "disabled";
pwm {
@@ -1460,6 +1512,7 @@ lptimer5: timer@50024000 {
clocks = <&rcc LPTIM5_K>;
clock-names = "mux";
wakeup-source;
+ access-controllers = <&etzpc 67>;
status = "disabled";
pwm {
@@ -1475,6 +1528,7 @@ vrefbuf: vrefbuf@50025000 {
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <2500000>;
clocks = <&rcc VREF>;
+ access-controllers = <&etzpc 69>;
status = "disabled";
};
@@ -1486,6 +1540,7 @@ sai4: sai@50027000 {
reg = <0x50027000 0x4>, <0x500273f0 0x10>;
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
resets = <&rcc SAI4_R>;
+ access-controllers = <&etzpc 68>;
status = "disabled";
sai4a: audio-controller@50027004 {
@@ -1518,6 +1573,7 @@ hash1: hash@54002000 {
dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>;
dma-names = "in";
dma-maxburst = <2>;
+ access-controllers = <&etzpc 8>;
status = "disabled";
};
@@ -1526,6 +1582,7 @@ rng1: rng@54003000 {
reg = <0x54003000 0x400>;
clocks = <&rcc RNG1_K>;
resets = <&rcc RNG1_R>;
+ access-controllers = <&etzpc 7>;
status = "okay";
};
@@ -1536,6 +1593,7 @@ fmc: memory-controller@58002000 {
reg = <0x58002000 0x1000>;
clocks = <&rcc FMC_K>;
resets = <&rcc FMC_R>;
+ access-controllers = <&etzpc 91>;
status = "disabled";
ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
@@ -1575,6 +1633,7 @@ qspi: spi@58003000 {
resets = <&rcc QSPI_R>;
#address-cells = <1>;
#size-cells = <0>;
+ access-controllers = <&etzpc 92>;
status = "disabled";
};
@@ -1602,6 +1661,7 @@ ethernet0: ethernet@5800a000 {
snps,en-tx-lpi-clockgating;
snps,axi-config = <&stmmac_axi_config_0>;
snps,tso;
+ access-controllers = <&etzpc 94>;
status = "disabled";
stmmac_axi_config_0: stmmac-axi-config {
@@ -1617,6 +1677,7 @@ usart1: serial@5c000000 {
interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc USART1_K>;
wakeup-source;
+ access-controllers = <&etzpc 3>;
status = "disabled";
};
@@ -1630,6 +1691,7 @@ spi6: spi@5c001000 {
resets = <&rcc SPI6_R>;
dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
<&mdma1 35 0x0 0x40002 0x0 0x0>;
+ access-controllers = <&etzpc 4>;
dma-names = "rx", "tx";
status = "disabled";
};
@@ -1647,6 +1709,7 @@ i2c4: i2c@5c002000 {
st,syscfg-fmp = <&syscfg 0x4 0x8>;
wakeup-source;
i2c-analog-filter;
+ access-controllers = <&etzpc 5>;
status = "disabled";
};
@@ -1663,6 +1726,7 @@ i2c6: i2c@5c009000 {
st,syscfg-fmp = <&syscfg 0x4 0x20>;
wakeup-source;
i2c-analog-filter;
+ access-controllers = <&etzpc 12>;
status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/st/stm32mp153.dtsi b/arch/arm/boot/dts/st/stm32mp153.dtsi
index 36e17ea0b179..4640dafb1598 100644
--- a/arch/arm/boot/dts/st/stm32mp153.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp153.dtsi
@@ -41,6 +41,7 @@ m_can1: can@4400e000 {
clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
clock-names = "hclk", "cclk";
bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
+ access-controllers = <&etzpc 62>;
status = "disabled";
};
@@ -54,6 +55,7 @@ m_can2: can@4400f000 {
clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
clock-names = "hclk", "cclk";
bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>;
+ access-controllers = <&etzpc 62>;
status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/st/stm32mp15xc.dtsi b/arch/arm/boot/dts/st/stm32mp15xc.dtsi
index d36c3457451a..97465717f932 100644
--- a/arch/arm/boot/dts/st/stm32mp15xc.dtsi
+++ b/arch/arm/boot/dts/st/stm32mp15xc.dtsi
@@ -11,6 +11,7 @@ cryp1: cryp@54001000 {
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CRYP1>;
resets = <&rcc CRYP1_R>;
+ access-controllers = <&etzpc 9>;
status = "disabled";
};
};
--
2.35.3
--
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linux-phy@lists.infradead.org
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^ permalink raw reply related
* [PATCH v9 06/13] of: property: fw_devlink: Add support for "access-controller"
From: Gatien Chevallier @ 2024-01-05 13:03 UTC (permalink / raw)
To: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
krzysztof.kozlowski+dt, conor+dt, alexandre.torgue, vkoul, jic23,
olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
andi.shyti, ulf.hansson, edumazet, kuba, pabeni, hugues.fruchet,
lee, will, catalin.marinas, arnd, richardcochran, Frank Rowand,
peng.fan, lars, rcsekar, wg, mkl
Cc: linux-crypto, devicetree, linux-stm32, linux-arm-kernel,
linux-kernel, dmaengine, linux-i2c, linux-iio, alsa-devel,
linux-media, linux-mmc, netdev, linux-phy, linux-serial,
linux-spi, linux-usb, Gatien Chevallier, Rob Herring
In-Reply-To: <20240105130404.301172-1-gatien.chevallier@foss.st.com>
Allows tracking dependencies between devices and their access
controller.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Changes in V9:
- Added Rob's review tag
Changes in V6:
- Renamed access-controller to access-controllers
Changes in V5:
- Rename feature-domain* to access-control*
Patch not present in V1
drivers/of/property.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/of/property.c b/drivers/of/property.c
index afdaefbd03f6..7f737eac91b2 100644
--- a/drivers/of/property.c
+++ b/drivers/of/property.c
@@ -1268,6 +1268,7 @@ DEFINE_SIMPLE_PROP(leds, "leds", NULL)
DEFINE_SIMPLE_PROP(backlight, "backlight", NULL)
DEFINE_SIMPLE_PROP(panel, "panel", NULL)
DEFINE_SIMPLE_PROP(msi_parent, "msi-parent", "#msi-cells")
+DEFINE_SIMPLE_PROP(access_controllers, "access-controllers", "#access-controller-cells")
DEFINE_SUFFIX_PROP(regulators, "-supply", NULL)
DEFINE_SUFFIX_PROP(gpio, "-gpio", "#gpio-cells")
@@ -1363,6 +1364,7 @@ static const struct supplier_bindings of_supplier_bindings[] = {
{ .parse_prop = parse_regulators, },
{ .parse_prop = parse_gpio, },
{ .parse_prop = parse_gpios, },
+ { .parse_prop = parse_access_controllers, },
{}
};
--
2.35.3
--
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^ permalink raw reply related
* [PATCH v9 07/13] bus: rifsc: introduce RIFSC firewall controller driver
From: Gatien Chevallier @ 2024-01-05 13:03 UTC (permalink / raw)
To: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
krzysztof.kozlowski+dt, conor+dt, alexandre.torgue, vkoul, jic23,
olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
andi.shyti, ulf.hansson, edumazet, kuba, pabeni, hugues.fruchet,
lee, will, catalin.marinas, arnd, richardcochran, Frank Rowand,
peng.fan, lars, rcsekar, wg, mkl
Cc: linux-crypto, devicetree, linux-stm32, linux-arm-kernel,
linux-kernel, dmaengine, linux-i2c, linux-iio, alsa-devel,
linux-media, linux-mmc, netdev, linux-phy, linux-serial,
linux-spi, linux-usb, Gatien Chevallier
In-Reply-To: <20240105130404.301172-1-gatien.chevallier@foss.st.com>
RIFSC is a peripheral firewall controller that filter accesses based on
Arm TrustZone secure state, Arm CPU privilege execution level and
Compartment IDentification of the STM32 SoC subsystems.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
---
Changes in V4:
- Fix incorrect use of __set_bit() in
- stm32_rif_acquire_semaphore()
Changes in V2:
- Add controller name
- Driver is now a module_platform_driver
- Use error code returned by stm32_firewall_populate_bus()
- Fix license
MAINTAINERS | 1 +
drivers/bus/Makefile | 2 +-
drivers/bus/stm32_rifsc.c | 252 ++++++++++++++++++++++++++++++++++++++
3 files changed, 254 insertions(+), 1 deletion(-)
create mode 100644 drivers/bus/stm32_rifsc.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 8f1391f6600c..353b68fb3477 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20443,6 +20443,7 @@ ST STM32 FIREWALL
M: Gatien Chevallier <gatien.chevallier@foss.st.com>
S: Maintained
F: drivers/bus/stm32_firewall.c
+F: drivers/bus/stm32_rifsc.c
ST STM32 I2C/SMBUS DRIVER
M: Pierre-Yves MORDRET <pierre-yves.mordret@foss.st.com>
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
index fc0511450ec2..e50d18e1d141 100644
--- a/drivers/bus/Makefile
+++ b/drivers/bus/Makefile
@@ -26,7 +26,7 @@ obj-$(CONFIG_OMAP_INTERCONNECT) += omap_l3_smx.o omap_l3_noc.o
obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o
obj-$(CONFIG_QCOM_EBI2) += qcom-ebi2.o
obj-$(CONFIG_QCOM_SSC_BLOCK_BUS) += qcom-ssc-block-bus.o
-obj-$(CONFIG_STM32_FIREWALL) += stm32_firewall.o
+obj-$(CONFIG_STM32_FIREWALL) += stm32_firewall.o stm32_rifsc.o
obj-$(CONFIG_SUN50I_DE2_BUS) += sun50i-de2.o
obj-$(CONFIG_SUNXI_RSB) += sunxi-rsb.o
obj-$(CONFIG_OF) += simple-pm-bus.o
diff --git a/drivers/bus/stm32_rifsc.c b/drivers/bus/stm32_rifsc.c
new file mode 100644
index 000000000000..4cf1b60014b7
--- /dev/null
+++ b/drivers/bus/stm32_rifsc.c
@@ -0,0 +1,252 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ */
+
+#include <linux/bitfield.h>
+#include <linux/bits.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/types.h>
+
+#include "stm32_firewall.h"
+
+/*
+ * RIFSC offset register
+ */
+#define RIFSC_RISC_SECCFGR0 0x10
+#define RIFSC_RISC_PRIVCFGR0 0x30
+#define RIFSC_RISC_PER0_CIDCFGR 0x100
+#define RIFSC_RISC_PER0_SEMCR 0x104
+#define RIFSC_RISC_HWCFGR2 0xFEC
+
+/*
+ * SEMCR register
+ */
+#define SEMCR_MUTEX BIT(0)
+
+/*
+ * HWCFGR2 register
+ */
+#define HWCFGR2_CONF1_MASK GENMASK(15, 0)
+#define HWCFGR2_CONF2_MASK GENMASK(23, 16)
+#define HWCFGR2_CONF3_MASK GENMASK(31, 24)
+
+/*
+ * RIFSC miscellaneous
+ */
+#define RIFSC_RISC_CFEN_MASK BIT(0)
+#define RIFSC_RISC_SEM_EN_MASK BIT(1)
+#define RIFSC_RISC_SCID_MASK GENMASK(6, 4)
+#define RIFSC_RISC_SEML_SHIFT 16
+#define RIFSC_RISC_SEMWL_MASK GENMASK(23, 16)
+#define RIFSC_RISC_PER_ID_MASK GENMASK(31, 24)
+
+#define RIFSC_RISC_PERx_CID_MASK (RIFSC_RISC_CFEN_MASK | \
+ RIFSC_RISC_SEM_EN_MASK | \
+ RIFSC_RISC_SCID_MASK | \
+ RIFSC_RISC_SEMWL_MASK)
+
+#define IDS_PER_RISC_SEC_PRIV_REGS 32
+
+/* RIF miscellaneous */
+/*
+ * CIDCFGR register fields
+ */
+#define CIDCFGR_CFEN BIT(0)
+#define CIDCFGR_SEMEN BIT(1)
+#define CIDCFGR_SEMWL(x) BIT(RIFSC_RISC_SEML_SHIFT + (x))
+
+#define SEMWL_SHIFT 16
+
+/* Compartiment IDs */
+#define RIF_CID0 0x0
+#define RIF_CID1 0x1
+
+static bool stm32_rifsc_is_semaphore_available(void __iomem *addr)
+{
+ return !(readl(addr) & SEMCR_MUTEX);
+}
+
+static int stm32_rif_acquire_semaphore(struct stm32_firewall_controller *stm32_firewall_controller,
+ int id)
+{
+ void __iomem *addr = stm32_firewall_controller->mmio + RIFSC_RISC_PER0_SEMCR + 0x8 * id;
+
+ writel(SEMCR_MUTEX, addr);
+
+ /* Check that CID1 has the semaphore */
+ if (stm32_rifsc_is_semaphore_available(addr) ||
+ FIELD_GET(RIFSC_RISC_SCID_MASK, readl(addr)) != RIF_CID1)
+ return -EACCES;
+
+ return 0;
+}
+
+static void stm32_rif_release_semaphore(struct stm32_firewall_controller *stm32_firewall_controller,
+ int id)
+{
+ void __iomem *addr = stm32_firewall_controller->mmio + RIFSC_RISC_PER0_SEMCR + 0x8 * id;
+
+ if (stm32_rifsc_is_semaphore_available(addr))
+ return;
+
+ writel(SEMCR_MUTEX, addr);
+
+ /* Ok if another compartment takes the semaphore before the check */
+ WARN_ON(!stm32_rifsc_is_semaphore_available(addr) &&
+ FIELD_GET(RIFSC_RISC_SCID_MASK, readl(addr)) == RIF_CID1);
+}
+
+static int stm32_rifsc_grant_access(struct stm32_firewall_controller *ctrl, u32 firewall_id)
+{
+ struct stm32_firewall_controller *rifsc_controller = ctrl;
+ u32 reg_offset, reg_id, sec_reg_value, cid_reg_value;
+ int rc;
+
+ if (firewall_id >= rifsc_controller->max_entries) {
+ dev_err(rifsc_controller->dev, "Invalid sys bus ID %u", firewall_id);
+ return -EINVAL;
+ }
+
+ /*
+ * RIFSC_RISC_PRIVCFGRx and RIFSC_RISC_SECCFGRx both handle configuration access for
+ * 32 peripherals. On the other hand, there is one _RIFSC_RISC_PERx_CIDCFGR register
+ * per peripheral
+ */
+ reg_id = firewall_id / IDS_PER_RISC_SEC_PRIV_REGS;
+ reg_offset = firewall_id % IDS_PER_RISC_SEC_PRIV_REGS;
+ sec_reg_value = readl(rifsc_controller->mmio + RIFSC_RISC_SECCFGR0 + 0x4 * reg_id);
+ cid_reg_value = readl(rifsc_controller->mmio + RIFSC_RISC_PER0_CIDCFGR + 0x8 * firewall_id);
+
+ /* First check conditions for semaphore mode, which doesn't take into account static CID. */
+ if ((cid_reg_value & CIDCFGR_SEMEN) && (cid_reg_value & CIDCFGR_CFEN)) {
+ if (cid_reg_value & BIT(RIF_CID1 + SEMWL_SHIFT)) {
+ /* Static CID is irrelevant if semaphore mode */
+ goto skip_cid_check;
+ } else {
+ dev_dbg(rifsc_controller->dev,
+ "Invalid bus semaphore configuration: index %d\n", firewall_id);
+ return -EACCES;
+ }
+ }
+
+ /*
+ * Skip CID check if CID filtering isn't enabled or filtering is enabled on CID0, which
+ * corresponds to whatever CID.
+ */
+ if (!(cid_reg_value & CIDCFGR_CFEN) ||
+ FIELD_GET(RIFSC_RISC_SCID_MASK, cid_reg_value) == RIF_CID0)
+ goto skip_cid_check;
+
+ /* Coherency check with the CID configuration */
+ if (FIELD_GET(RIFSC_RISC_SCID_MASK, cid_reg_value) != RIF_CID1) {
+ dev_dbg(rifsc_controller->dev, "Invalid CID configuration for peripheral: %d\n",
+ firewall_id);
+ return -EACCES;
+ }
+
+skip_cid_check:
+ /* Check security configuration */
+ if (sec_reg_value & BIT(reg_offset)) {
+ dev_dbg(rifsc_controller->dev,
+ "Invalid security configuration for peripheral: %d\n", firewall_id);
+ return -EACCES;
+ }
+
+ /*
+ * If the peripheral is in semaphore mode, take the semaphore so that
+ * the CID1 has the ownership.
+ */
+ if ((cid_reg_value & CIDCFGR_SEMEN) && (cid_reg_value & CIDCFGR_CFEN)) {
+ rc = stm32_rif_acquire_semaphore(rifsc_controller, firewall_id);
+ if (rc) {
+ dev_err(rifsc_controller->dev,
+ "Couldn't acquire semaphore for peripheral: %d\n", firewall_id);
+ return rc;
+ }
+ }
+
+ return 0;
+}
+
+static void stm32_rifsc_release_access(struct stm32_firewall_controller *ctrl, u32 firewall_id)
+{
+ stm32_rif_release_semaphore(ctrl, firewall_id);
+}
+
+static int stm32_rifsc_probe(struct platform_device *pdev)
+{
+ struct stm32_firewall_controller *rifsc_controller;
+ struct device_node *np = pdev->dev.of_node;
+ u32 nb_risup, nb_rimu, nb_risal;
+ struct resource *res;
+ void __iomem *mmio;
+ int rc;
+
+ rifsc_controller = devm_kzalloc(&pdev->dev, sizeof(*rifsc_controller), GFP_KERNEL);
+ if (!rifsc_controller)
+ return -ENOMEM;
+
+ mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
+ if (IS_ERR(mmio))
+ return PTR_ERR(mmio);
+
+ rifsc_controller->dev = &pdev->dev;
+ rifsc_controller->mmio = mmio;
+ rifsc_controller->name = dev_driver_string(rifsc_controller->dev);
+ rifsc_controller->type = STM32_PERIPHERAL_FIREWALL | STM32_MEMORY_FIREWALL;
+ rifsc_controller->grant_access = stm32_rifsc_grant_access;
+ rifsc_controller->release_access = stm32_rifsc_release_access;
+
+ /* Get number of RIFSC entries*/
+ nb_risup = readl(rifsc_controller->mmio + RIFSC_RISC_HWCFGR2) & HWCFGR2_CONF1_MASK;
+ nb_rimu = readl(rifsc_controller->mmio + RIFSC_RISC_HWCFGR2) & HWCFGR2_CONF2_MASK;
+ nb_risal = readl(rifsc_controller->mmio + RIFSC_RISC_HWCFGR2) & HWCFGR2_CONF3_MASK;
+ rifsc_controller->max_entries = nb_risup + nb_rimu + nb_risal;
+
+ platform_set_drvdata(pdev, rifsc_controller);
+
+ rc = stm32_firewall_controller_register(rifsc_controller);
+ if (rc) {
+ dev_err(rifsc_controller->dev, "Couldn't register as a firewall controller: %d",
+ rc);
+ return rc;
+ }
+
+ rc = stm32_firewall_populate_bus(rifsc_controller);
+ if (rc) {
+ dev_err(rifsc_controller->dev, "Couldn't populate RIFSC bus: %d",
+ rc);
+ return rc;
+ }
+
+ /* Populate all allowed nodes */
+ return of_platform_populate(np, NULL, NULL, &pdev->dev);
+}
+
+static const struct of_device_id stm32_rifsc_of_match[] = {
+ { .compatible = "st,stm32mp25-rifsc" },
+ {}
+};
+MODULE_DEVICE_TABLE(of, stm32_rifsc_of_match);
+
+static struct platform_driver stm32_rifsc_driver = {
+ .probe = stm32_rifsc_probe,
+ .driver = {
+ .name = "stm32-rifsc",
+ .of_match_table = stm32_rifsc_of_match,
+ },
+};
+module_platform_driver(stm32_rifsc_driver);
+
+MODULE_AUTHOR("Gatien Chevallier <gatien.chevallier@foss.st.com>");
+MODULE_DESCRIPTION("STMicroelectronics RIFSC driver");
+MODULE_LICENSE("GPL");
--
2.35.3
--
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linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH v9 04/13] dt-bindings: bus: document ETZPC
From: Gatien Chevallier @ 2024-01-05 13:03 UTC (permalink / raw)
To: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
krzysztof.kozlowski+dt, conor+dt, alexandre.torgue, vkoul, jic23,
olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
andi.shyti, ulf.hansson, edumazet, kuba, pabeni, hugues.fruchet,
lee, will, catalin.marinas, arnd, richardcochran, Frank Rowand,
peng.fan, lars, rcsekar, wg, mkl
Cc: linux-crypto, devicetree, linux-stm32, linux-arm-kernel,
linux-kernel, dmaengine, linux-i2c, linux-iio, alsa-devel,
linux-media, linux-mmc, netdev, linux-phy, linux-serial,
linux-spi, linux-usb, Gatien Chevallier, Rob Herring
In-Reply-To: <20240105130404.301172-1-gatien.chevallier@foss.st.com>
Document ETZPC (Extended TrustZone protection controller). ETZPC is a
firewall controller.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Changes in V9:
- Added "simple-bus" to ETZPC's compatible list
- Added Rob's review tag
Changes in V6:
- Renamed access-controller to access-controllers
- Removal of access-control-provider property
- Removal of access-controller and access-controller-names
declaration in the patternProperties field. Add
additionalProperties: true in this field.
Changes in V5:
- Renamed feature-domain* to access-control*
Changes in V2:
- Corrected errors highlighted by Rob's robot
- No longer define the maxItems for the "feature-domains"
property
- Fix example (node name, status)
- Declare "feature-domain-names" as an optional
property for child nodes
- Fix description of "feature-domains" property
- Reordered the properties so it matches ETZPC
- Add missing "feature-domain-controller" property
.../bindings/bus/st,stm32-etzpc.yaml | 96 +++++++++++++++++++
1 file changed, 96 insertions(+)
create mode 100644 Documentation/devicetree/bindings/bus/st,stm32-etzpc.yaml
diff --git a/Documentation/devicetree/bindings/bus/st,stm32-etzpc.yaml b/Documentation/devicetree/bindings/bus/st,stm32-etzpc.yaml
new file mode 100644
index 000000000000..d12b62a3a5a8
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/st,stm32-etzpc.yaml
@@ -0,0 +1,96 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bus/st,stm32-etzpc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STM32 Extended TrustZone protection controller
+
+description: |
+ The ETZPC configures TrustZone security in a SoC having bus masters and
+ devices with programmable-security attributes (securable resources).
+
+maintainers:
+ - Gatien Chevallier <gatien.chevallier@foss.st.com>
+
+select:
+ properties:
+ compatible:
+ contains:
+ const: st,stm32-etzpc
+ required:
+ - compatible
+
+properties:
+ compatible:
+ items:
+ - const: st,stm32-etzpc
+ - const: simple-bus
+
+ reg:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+ ranges: true
+
+ "#access-controller-cells":
+ const: 1
+ description:
+ Contains the firewall ID associated to the peripheral.
+
+patternProperties:
+ "^.*@[0-9a-f]+$":
+ description: Peripherals
+ type: object
+
+ additionalProperties: true
+
+ required:
+ - access-controllers
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+ - "#access-controller-cells"
+ - ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ // In this example, the usart2 device refers to rifsc as its access
+ // controller.
+ // Access rights are verified before creating devices.
+
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/stm32mp13-clks.h>
+ #include <dt-bindings/reset/stm32mp13-resets.h>
+
+ etzpc: bus@5c007000 {
+ compatible = "st,stm32-etzpc", "simple-bus";
+ reg = <0x5c007000 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #access-controller-cells = <1>;
+ ranges;
+
+ usart2: serial@4c001000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x4c001000 0x400>;
+ interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&rcc USART2_K>;
+ resets = <&rcc USART2_R>;
+ wakeup-source;
+ dmas = <&dmamux1 43 0x400 0x5>,
+ <&dmamux1 44 0x400 0x1>;
+ dma-names = "rx", "tx";
+ access-controllers = <&etzpc 17>;
+ };
+ };
--
2.35.3
--
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^ permalink raw reply related
* [PATCH v9 05/13] firewall: introduce stm32_firewall framework
From: Gatien Chevallier @ 2024-01-05 13:03 UTC (permalink / raw)
To: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
krzysztof.kozlowski+dt, conor+dt, alexandre.torgue, vkoul, jic23,
olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
andi.shyti, ulf.hansson, edumazet, kuba, pabeni, hugues.fruchet,
lee, will, catalin.marinas, arnd, richardcochran, Frank Rowand,
peng.fan, lars, rcsekar, wg, mkl
Cc: linux-crypto, devicetree, linux-stm32, linux-arm-kernel,
linux-kernel, dmaengine, linux-i2c, linux-iio, alsa-devel,
linux-media, linux-mmc, netdev, linux-phy, linux-serial,
linux-spi, linux-usb, Gatien Chevallier
In-Reply-To: <20240105130404.301172-1-gatien.chevallier@foss.st.com>
Introduce a STM32 firewall framework that offers to firewall consumers
different firewall services such as the ability to check their access
rights against their firewall controller(s).
The STM32 firewall framework offers a generic API for STM32 firewall
controllers that is defined in their drivers to best fit the
specificity of each firewall.
There are various types of firewalls:
-Peripheral firewalls that filter accesses to peripherals
-Memory firewalls that filter accesses to memories or memory regions
-No type for undefined type of firewall
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
---
Changes in V8:
- Add missing dependency on OF for OF_DYNAMIC
Changes in V7:
- Select OF_DYNAMIC when STM32_FIREWALL is set in order to use
of_detach_node() in the firewall framework. Since the
simple-bus pre-probe creates devices for all subnodes. This
function is needed to detach particular nodes so that there's
no match
Changes in V6:
- Renamed access-controller to access-controllers
Changes in V5:
- Rename feature-domain* to access-control*
- Fix index out of range in stm32_firewall_get_firewall()
- Add mising "select STM32_FIREWALL" in config ARCH_STM32 in
arch/arm/mach-stm32/Kconfig
Changes in V4:
- Fix documentation syntax
- Put node in case of error in stm32_firewall_populate_bus()
- Check firewall controller presence before using it in
stm32_firewall_controller_register()
Changes in V2:
- Support multiple entries for "feature-domains"
property. Change stm32_firewall_get_firewall()
to do so.
- Better handle the device-tree parsing using
phandle+args APIs and phandle iterator.
- Remove "resource firewall" type
- Rephrase STM32_FIREWALL description in the bus
Kconfig and remove useless default value
- Add missing EXPORT_SYMBOL_GPL
- Remove useless stm32_firewall_get_id() API
- Add a field for the name of the firewall entry
in the stm32_firewall_controller structure
- Minor fixes on some traces level (err -> debug)
- Fix licenses to GPL-2.0-only
- Fix stm32_firewall_get_firewall() description
- Rephrase some sentences to better emphasize this
is STM32-specific
- Switch to list_for_each_entry() in
stm32_firewall_controller_unregister() as we only
expect one firewall controller instance per device.
The loop just breaks when found
- Do not register the firewall controller if it is
already registered to the framework
MAINTAINERS | 5 +
arch/arm/mach-stm32/Kconfig | 1 +
arch/arm64/Kconfig.platforms | 1 +
drivers/bus/Kconfig | 10 +
drivers/bus/Makefile | 1 +
drivers/bus/stm32_firewall.c | 294 ++++++++++++++++++++++
drivers/bus/stm32_firewall.h | 83 ++++++
include/linux/bus/stm32_firewall_device.h | 141 +++++++++++
8 files changed, 536 insertions(+)
create mode 100644 drivers/bus/stm32_firewall.c
create mode 100644 drivers/bus/stm32_firewall.h
create mode 100644 include/linux/bus/stm32_firewall_device.h
diff --git a/MAINTAINERS b/MAINTAINERS
index f5c2450fa4ec..8f1391f6600c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -20439,6 +20439,11 @@ T: git git://linuxtv.org/media_tree.git
F: Documentation/devicetree/bindings/media/i2c/st,st-mipid02.yaml
F: drivers/media/i2c/st-mipid02.c
+ST STM32 FIREWALL
+M: Gatien Chevallier <gatien.chevallier@foss.st.com>
+S: Maintained
+F: drivers/bus/stm32_firewall.c
+
ST STM32 I2C/SMBUS DRIVER
M: Pierre-Yves MORDRET <pierre-yves.mordret@foss.st.com>
M: Alain Volmat <alain.volmat@foss.st.com>
diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig
index 98145031586f..ae21a9f78f9c 100644
--- a/arch/arm/mach-stm32/Kconfig
+++ b/arch/arm/mach-stm32/Kconfig
@@ -12,6 +12,7 @@ menuconfig ARCH_STM32
select PINCTRL
select RESET_CONTROLLER
select STM32_EXTI
+ select STM32_FIREWALL
help
Support for STMicroelectronics STM32 processors.
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 24335565bad5..13ed0a483617 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -305,6 +305,7 @@ config ARCH_STM32
select ARM_SMC_MBOX
select ARM_SCMI_PROTOCOL
select COMMON_CLK_SCMI
+ select STM32_FIREWALL
help
This enables support for ARMv8 based STMicroelectronics
STM32 family, including:
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
index e6742998f372..7d47e0005cfe 100644
--- a/drivers/bus/Kconfig
+++ b/drivers/bus/Kconfig
@@ -163,6 +163,16 @@ config QCOM_SSC_BLOCK_BUS
i2c/spi/uart controllers, a hexagon core, and a clock controller
which provides clocks for the above.
+config STM32_FIREWALL
+ bool "STM32 Firewall framework"
+ depends on (ARCH_STM32 || COMPILE_TEST) && OF
+ select OF_DYNAMIC
+ help
+ Say y to enable STM32 firewall framework and its services. Firewall
+ controllers will be able to register to the framework. Access for
+ hardware resources linked to a firewall controller can be requested
+ through this STM32 framework.
+
config SUN50I_DE2_BUS
bool "Allwinner A64 DE2 Bus Driver"
default ARM64
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
index d90eed189a65..fc0511450ec2 100644
--- a/drivers/bus/Makefile
+++ b/drivers/bus/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_OMAP_INTERCONNECT) += omap_l3_smx.o omap_l3_noc.o
obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o
obj-$(CONFIG_QCOM_EBI2) += qcom-ebi2.o
obj-$(CONFIG_QCOM_SSC_BLOCK_BUS) += qcom-ssc-block-bus.o
+obj-$(CONFIG_STM32_FIREWALL) += stm32_firewall.o
obj-$(CONFIG_SUN50I_DE2_BUS) += sun50i-de2.o
obj-$(CONFIG_SUNXI_RSB) += sunxi-rsb.o
obj-$(CONFIG_OF) += simple-pm-bus.o
diff --git a/drivers/bus/stm32_firewall.c b/drivers/bus/stm32_firewall.c
new file mode 100644
index 000000000000..decb79449047
--- /dev/null
+++ b/drivers/bus/stm32_firewall.c
@@ -0,0 +1,294 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ */
+
+#include <linux/bitfield.h>
+#include <linux/bits.h>
+#include <linux/bus/stm32_firewall_device.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/types.h>
+#include <linux/slab.h>
+
+#include "stm32_firewall.h"
+
+/* Corresponds to STM32_FIREWALL_MAX_EXTRA_ARGS + firewall ID */
+#define STM32_FIREWALL_MAX_ARGS (STM32_FIREWALL_MAX_EXTRA_ARGS + 1)
+
+static LIST_HEAD(firewall_controller_list);
+static DEFINE_MUTEX(firewall_controller_list_lock);
+
+/* Firewall device API */
+
+int stm32_firewall_get_firewall(struct device_node *np, struct stm32_firewall *firewall,
+ unsigned int nb_firewall)
+{
+ struct stm32_firewall_controller *ctrl;
+ struct of_phandle_iterator it;
+ unsigned int i, j = 0;
+ int err;
+
+ if (!firewall || !nb_firewall)
+ return -EINVAL;
+
+ /* Parse property with phandle parsed out */
+ of_for_each_phandle(&it, err, np, "access-controllers", "#access-controller-cells", 0) {
+ struct of_phandle_args provider_args;
+ struct device_node *provider = it.node;
+ const char *fw_entry;
+ bool match = false;
+
+ if (err) {
+ pr_err("Unable to get access-controllers property for node %s\n, err: %d",
+ np->full_name, err);
+ of_node_put(provider);
+ return err;
+ }
+
+ if (j > nb_firewall) {
+ pr_err("Too many firewall controllers");
+ of_node_put(provider);
+ return -EINVAL;
+ }
+
+ provider_args.args_count = of_phandle_iterator_args(&it, provider_args.args,
+ STM32_FIREWALL_MAX_ARGS);
+
+ /* Check if the parsed phandle corresponds to a registered firewall controller */
+ mutex_lock(&firewall_controller_list_lock);
+ list_for_each_entry(ctrl, &firewall_controller_list, entry) {
+ if (ctrl->dev->of_node->phandle == it.phandle) {
+ match = true;
+ firewall[j].firewall_ctrl = ctrl;
+ break;
+ }
+ }
+ mutex_unlock(&firewall_controller_list_lock);
+
+ if (!match) {
+ firewall[j].firewall_ctrl = NULL;
+ pr_err("No firewall controller registered for %s\n", np->full_name);
+ of_node_put(provider);
+ return -ENODEV;
+ }
+
+ err = of_property_read_string_index(np, "access-controller-names", j, &fw_entry);
+ if (err == 0)
+ firewall[j].entry = fw_entry;
+
+ /* Handle the case when there are no arguments given along with the phandle */
+ if (provider_args.args_count < 0 ||
+ provider_args.args_count > STM32_FIREWALL_MAX_ARGS) {
+ of_node_put(provider);
+ return -EINVAL;
+ } else if (provider_args.args_count == 0) {
+ firewall[j].extra_args_size = 0;
+ firewall[j].firewall_id = U32_MAX;
+ j++;
+ continue;
+ }
+
+ /* The firewall ID is always the first argument */
+ firewall[j].firewall_id = provider_args.args[0];
+
+ /* Extra args start at the second argument */
+ for (i = 0; i < provider_args.args_count - 1; i++)
+ firewall[j].extra_args[i] = provider_args.args[i + 1];
+
+ /* Remove the firewall ID arg that is not an extra argument */
+ firewall[j].extra_args_size = provider_args.args_count - 1;
+
+ j++;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(stm32_firewall_get_firewall);
+
+int stm32_firewall_grant_access(struct stm32_firewall *firewall)
+{
+ struct stm32_firewall_controller *firewall_controller;
+
+ if (!firewall || firewall->firewall_id == U32_MAX)
+ return -EINVAL;
+
+ firewall_controller = firewall->firewall_ctrl;
+
+ if (!firewall_controller)
+ return -ENODEV;
+
+ return firewall_controller->grant_access(firewall_controller, firewall->firewall_id);
+}
+EXPORT_SYMBOL_GPL(stm32_firewall_grant_access);
+
+int stm32_firewall_grant_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id)
+{
+ struct stm32_firewall_controller *firewall_controller;
+
+ if (!firewall || subsystem_id == U32_MAX || firewall->firewall_id == U32_MAX)
+ return -EINVAL;
+
+ firewall_controller = firewall->firewall_ctrl;
+
+ if (!firewall_controller)
+ return -ENODEV;
+
+ return firewall_controller->grant_access(firewall_controller, subsystem_id);
+}
+EXPORT_SYMBOL_GPL(stm32_firewall_grant_access_by_id);
+
+void stm32_firewall_release_access(struct stm32_firewall *firewall)
+{
+ struct stm32_firewall_controller *firewall_controller;
+
+ if (!firewall || firewall->firewall_id == U32_MAX) {
+ pr_debug("Incorrect arguments when releasing a firewall access\n");
+ return;
+ }
+
+ firewall_controller = firewall->firewall_ctrl;
+
+ if (!firewall_controller) {
+ pr_debug("No firewall controller to release\n");
+ return;
+ }
+
+ firewall_controller->release_access(firewall_controller, firewall->firewall_id);
+}
+EXPORT_SYMBOL_GPL(stm32_firewall_release_access);
+
+void stm32_firewall_release_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id)
+{
+ struct stm32_firewall_controller *firewall_controller;
+
+ if (!firewall || subsystem_id == U32_MAX || firewall->firewall_id == U32_MAX) {
+ pr_debug("Incorrect arguments when releasing a firewall access");
+ return;
+ }
+
+ firewall_controller = firewall->firewall_ctrl;
+
+ if (!firewall_controller) {
+ pr_debug("No firewall controller to release");
+ return;
+ }
+
+ firewall_controller->release_access(firewall_controller, subsystem_id);
+}
+EXPORT_SYMBOL_GPL(stm32_firewall_release_access_by_id);
+
+/* Firewall controller API */
+
+int stm32_firewall_controller_register(struct stm32_firewall_controller *firewall_controller)
+{
+ struct stm32_firewall_controller *ctrl;
+
+ if (!firewall_controller)
+ return -ENODEV;
+
+ pr_info("Registering %s firewall controller\n", firewall_controller->name);
+
+ mutex_lock(&firewall_controller_list_lock);
+ list_for_each_entry(ctrl, &firewall_controller_list, entry) {
+ if (ctrl == firewall_controller) {
+ pr_debug("%s firewall controller already registered\n",
+ firewall_controller->name);
+ mutex_unlock(&firewall_controller_list_lock);
+ return 0;
+ }
+ }
+ list_add_tail(&firewall_controller->entry, &firewall_controller_list);
+ mutex_unlock(&firewall_controller_list_lock);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(stm32_firewall_controller_register);
+
+void stm32_firewall_controller_unregister(struct stm32_firewall_controller *firewall_controller)
+{
+ struct stm32_firewall_controller *ctrl;
+ bool controller_removed = false;
+
+ if (!firewall_controller) {
+ pr_debug("Null reference while unregistering firewall controller\n");
+ return;
+ }
+
+ mutex_lock(&firewall_controller_list_lock);
+ list_for_each_entry(ctrl, &firewall_controller_list, entry) {
+ if (ctrl == firewall_controller) {
+ controller_removed = true;
+ list_del_init(&ctrl->entry);
+ break;
+ }
+ }
+ mutex_unlock(&firewall_controller_list_lock);
+
+ if (!controller_removed)
+ pr_debug("There was no firewall controller named %s to unregister\n",
+ firewall_controller->name);
+}
+EXPORT_SYMBOL_GPL(stm32_firewall_controller_unregister);
+
+int stm32_firewall_populate_bus(struct stm32_firewall_controller *firewall_controller)
+{
+ struct stm32_firewall *firewalls;
+ struct device_node *child;
+ struct device *parent;
+ unsigned int i;
+ int len;
+ int err;
+
+ parent = firewall_controller->dev;
+
+ dev_dbg(parent, "Populating %s system bus\n", dev_name(firewall_controller->dev));
+
+ for_each_available_child_of_node(dev_of_node(parent), child) {
+ /* The access-controllers property is mandatory for firewall bus devices */
+ len = of_count_phandle_with_args(child, "access-controllers",
+ "#access-controller-cells");
+ if (len <= 0) {
+ of_node_put(child);
+ return -EINVAL;
+ }
+
+ firewalls = kcalloc(len, sizeof(*firewalls), GFP_KERNEL);
+ if (!firewalls) {
+ of_node_put(child);
+ return -ENOMEM;
+ }
+
+ err = stm32_firewall_get_firewall(child, firewalls, (unsigned int)len);
+ if (err) {
+ kfree(firewalls);
+ of_node_put(child);
+ return err;
+ }
+
+ for (i = 0; i < len; i++) {
+ if (firewall_controller->grant_access(firewall_controller,
+ firewalls[i].firewall_id)) {
+ /*
+ * Peripheral access not allowed or not defined.
+ * Mark the node as populated so platform bus won't probe it
+ */
+ of_detach_node(child);
+ dev_err(parent, "%s: Device driver will not be probed\n",
+ child->full_name);
+ }
+ }
+
+ kfree(firewalls);
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(stm32_firewall_populate_bus);
diff --git a/drivers/bus/stm32_firewall.h b/drivers/bus/stm32_firewall.h
new file mode 100644
index 000000000000..e5fac85fe346
--- /dev/null
+++ b/drivers/bus/stm32_firewall.h
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ */
+
+#ifndef _STM32_FIREWALL_H
+#define _STM32_FIREWALL_H
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/types.h>
+
+/**
+ * STM32_PERIPHERAL_FIREWALL: This type of firewall protects peripherals
+ * STM32_MEMORY_FIREWALL: This type of firewall protects memories/subsets of memory
+ * zones
+ * STM32_NOTYPE_FIREWALL: Undefined firewall type
+ */
+
+#define STM32_PERIPHERAL_FIREWALL BIT(1)
+#define STM32_MEMORY_FIREWALL BIT(2)
+#define STM32_NOTYPE_FIREWALL BIT(3)
+
+/**
+ * struct stm32_firewall_controller - Information on firewall controller supplying services
+ *
+ * @name: Name of the firewall controller
+ * @dev: Device reference of the firewall controller
+ * @mmio: Base address of the firewall controller
+ * @entry: List entry of the firewall controller list
+ * @type: Type of firewall
+ * @max_entries: Number of entries covered by the firewall
+ * @grant_access: Callback used to grant access for a device access against a
+ * firewall controller
+ * @release_access: Callback used to release resources taken by a device when access was
+ * granted
+ * @grant_memory_range_access: Callback used to grant access for a device to a given memory region
+ */
+struct stm32_firewall_controller {
+ const char *name;
+ struct device *dev;
+ void __iomem *mmio;
+ struct list_head entry;
+ unsigned int type;
+ unsigned int max_entries;
+
+ int (*grant_access)(struct stm32_firewall_controller *ctrl, u32 id);
+ void (*release_access)(struct stm32_firewall_controller *ctrl, u32 id);
+ int (*grant_memory_range_access)(struct stm32_firewall_controller *ctrl, phys_addr_t paddr,
+ size_t size);
+};
+
+/**
+ * stm32_firewall_controller_register - Register a firewall controller to the STM32 firewall
+ * framework
+ * @firewall_controller: Firewall controller to register
+ *
+ * Returns 0 in case of success or -ENODEV if no controller was given.
+ */
+int stm32_firewall_controller_register(struct stm32_firewall_controller *firewall_controller);
+
+/**
+ * stm32_firewall_controller_unregister - Unregister a firewall controller from the STM32
+ * firewall framework
+ * @firewall_controller: Firewall controller to unregister
+ */
+void stm32_firewall_controller_unregister(struct stm32_firewall_controller *firewall_controller);
+
+/**
+ * stm32_firewall_populate_bus - Populate device tree nodes that have a correct firewall
+ * configuration. This is used at boot-time only, as a sanity check
+ * between device tree and firewalls hardware configurations to
+ * prevent a kernel crash when a device driver is not granted access
+ *
+ * @firewall_controller: Firewall controller which nodes will be populated or not
+ *
+ * Returns 0 in case of success or appropriate errno code if error occurred.
+ */
+int stm32_firewall_populate_bus(struct stm32_firewall_controller *firewall_controller);
+
+#endif /* _STM32_FIREWALL_H */
diff --git a/include/linux/bus/stm32_firewall_device.h b/include/linux/bus/stm32_firewall_device.h
new file mode 100644
index 000000000000..bbbee0b24ea8
--- /dev/null
+++ b/include/linux/bus/stm32_firewall_device.h
@@ -0,0 +1,141 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
+ */
+
+#ifndef STM32_FIREWALL_DEVICE_H
+#define STM32_FIREWALL_DEVICE_H
+
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/types.h>
+
+#define STM32_FIREWALL_MAX_EXTRA_ARGS 5
+
+/* Opaque reference to stm32_firewall_controller */
+struct stm32_firewall_controller;
+
+/**
+ * struct stm32_firewall - Information on a device's firewall. Each device can have more than one
+ * firewall.
+ *
+ * @firewall_ctrl: Pointer referencing a firewall controller of the device. It is
+ * opaque so a device cannot manipulate the controller's ops or access
+ * the controller's data
+ * @extra_args: Extra arguments that are implementation dependent
+ * @entry: Name of the firewall entry
+ * @extra_args_size: Number of extra arguments
+ * @firewall_id: Firewall ID associated the device for this firewall controller
+ */
+struct stm32_firewall {
+ struct stm32_firewall_controller *firewall_ctrl;
+ u32 extra_args[STM32_FIREWALL_MAX_EXTRA_ARGS];
+ const char *entry;
+ size_t extra_args_size;
+ u32 firewall_id;
+};
+
+#if IS_ENABLED(CONFIG_STM32_FIREWALL)
+/**
+ * stm32_firewall_get_firewall - Get the firewall(s) associated to given device.
+ * The firewall controller reference is always the first argument
+ * of each of the access-controller property entries.
+ * The firewall ID is always the second argument of each of the
+ * access-controller property entries.
+ * If there's no argument linked to the phandle, then the firewall ID
+ * field is set to U32_MAX, which is an invalid ID.
+ *
+ * @np: Device node to parse
+ * @firewall: Array of firewall references
+ * @nb_firewall: Number of firewall references to get. Must be at least 1.
+ *
+ * Returns 0 on success, -ENODEV if there's no match with a firewall controller or appropriate errno
+ * code if error occurred.
+ */
+int stm32_firewall_get_firewall(struct device_node *np, struct stm32_firewall *firewall,
+ unsigned int nb_firewall);
+
+/**
+ * stm32_firewall_grant_access - Request firewall access rights and grant access.
+ *
+ * @firewall: Firewall reference containing the ID to check against its firewall
+ * controller
+ *
+ * Returns 0 if access is granted, -EACCES if access is denied, -ENODEV if firewall is null or
+ * appropriate errno code if error occurred
+ */
+int stm32_firewall_grant_access(struct stm32_firewall *firewall);
+
+/**
+ * stm32_firewall_release_access - Release access granted from a call to
+ * stm32_firewall_grant_access().
+ *
+ * @firewall: Firewall reference containing the ID to check against its firewall
+ * controller
+ */
+void stm32_firewall_release_access(struct stm32_firewall *firewall);
+
+/**
+ * stm32_firewall_grant_access_by_id - Request firewall access rights of a given device
+ * based on a specific firewall ID
+ *
+ * Warnings:
+ * There is no way to ensure that the given ID will correspond to the firewall referenced in the
+ * device node if the ID did not come from stm32_firewall_get_firewall(). In that case, this
+ * function must be used with caution.
+ * This function should be used for subsystem resources that do not have the same firewall ID
+ * as their parent.
+ * U32_MAX is an invalid ID.
+ *
+ * @firewall: Firewall reference containing the firewall controller
+ * @subsystem_id: Firewall ID of the subsystem resource
+ *
+ * Returns 0 if access is granted, -EACCES if access is denied, -ENODEV if firewall is null or
+ * appropriate errno code if error occurred
+ */
+int stm32_firewall_grant_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id);
+
+/**
+ * stm32_firewall_release_access_by_id - Release access granted from a call to
+ * stm32_firewall_grant_access_by_id().
+ *
+ * Warnings:
+ * There is no way to ensure that the given ID will correspond to the firewall referenced in the
+ * device node if the ID did not come from stm32_firewall_get_firewall(). In that case, this
+ * function must be used with caution.
+ * This function should be used for subsystem resources that do not have the same firewall ID
+ * as their parent.
+ * U32_MAX is an invalid ID.
+ *
+ * @firewall: Firewall reference containing the firewall controller
+ * @subsystem_id: Firewall ID of the subsystem resource
+ */
+void stm32_firewall_release_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id);
+
+#else /* CONFIG_STM32_FIREWALL */
+
+int stm32_firewall_get_firewall(struct device_node *np, struct stm32_firewall *firewall)
+{
+ return -ENODEV;
+}
+
+int stm32_firewall_grant_access(struct stm32_firewall *firewall)
+{
+ return -ENODEV;
+}
+
+void stm32_firewall_release_access(struct stm32_firewall *firewall)
+{
+}
+
+int stm32_firewall_grant_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id)
+{
+ return -ENODEV;
+}
+
+void stm32_firewall_release_access_by_id(struct stm32_firewall *firewall, u32 subsystem_id)
+{
+}
+
+#endif /* CONFIG_STM32_FIREWALL */
+#endif /* STM32_FIREWALL_DEVICE_H */
--
2.35.3
--
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linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH v9 02/13] dt-bindings: treewide: add access-controllers description
From: Gatien Chevallier @ 2024-01-05 13:03 UTC (permalink / raw)
To: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
krzysztof.kozlowski+dt, conor+dt, alexandre.torgue, vkoul, jic23,
olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
andi.shyti, ulf.hansson, edumazet, kuba, pabeni, hugues.fruchet,
lee, will, catalin.marinas, arnd, richardcochran, Frank Rowand,
peng.fan, lars, rcsekar, wg, mkl
Cc: linux-crypto, devicetree, linux-stm32, linux-arm-kernel,
linux-kernel, dmaengine, linux-i2c, linux-iio, alsa-devel,
linux-media, linux-mmc, netdev, linux-phy, linux-serial,
linux-spi, linux-usb, Gatien Chevallier
In-Reply-To: <20240105130404.301172-1-gatien.chevallier@foss.st.com>
access-controllers is an optional property that allows a peripheral to
refer to one or more domain access controller(s).
Description of this property is added to all peripheral binding files of
the peripheral under the STM32 firewall controller. It allows an accurate
representation of the hardware, where various peripherals are connected
to a firewall bus. The firewall can then check the peripheral accesses
before allowing its device to probe.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
---
Changes in V6:
- Minor changes in commit message
- Renamed access-controller to access-controllers
Changes in V5:
- Discarded review tags as the content has changed
- Renamed feature-domains to access-controller
Changes in V4:
- Added Jonathan's tag for IIO
Changes in V2:
- Add missing "feature-domains" property declaration
in bosch,m_can.yaml and st,stm32-cryp.yaml files
Documentation/devicetree/bindings/crypto/st,stm32-cryp.yaml | 4 ++++
Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml | 4 ++++
Documentation/devicetree/bindings/dma/st,stm32-dma.yaml | 4 ++++
Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml | 4 ++++
Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml | 4 ++++
Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml | 4 ++++
.../devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml | 4 ++++
Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml | 4 ++++
Documentation/devicetree/bindings/media/cec/st,stm32-cec.yaml | 4 ++++
Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml | 4 ++++
.../bindings/memory-controllers/st,stm32-fmc2-ebi.yaml | 4 ++++
Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml | 4 ++++
Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml | 4 ++++
Documentation/devicetree/bindings/mmc/arm,pl18x.yaml | 4 ++++
Documentation/devicetree/bindings/net/can/bosch,m_can.yaml | 4 ++++
Documentation/devicetree/bindings/net/stm32-dwmac.yaml | 4 ++++
Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml | 4 ++++
.../devicetree/bindings/regulator/st,stm32-vrefbuf.yaml | 4 ++++
Documentation/devicetree/bindings/rng/st,stm32-rng.yaml | 4 ++++
Documentation/devicetree/bindings/serial/st,stm32-uart.yaml | 4 ++++
Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml | 4 ++++
Documentation/devicetree/bindings/sound/st,stm32-sai.yaml | 4 ++++
Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml | 4 ++++
Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml | 4 ++++
Documentation/devicetree/bindings/spi/st,stm32-spi.yaml | 4 ++++
Documentation/devicetree/bindings/usb/dwc2.yaml | 4 ++++
26 files changed, 104 insertions(+)
diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-cryp.yaml b/Documentation/devicetree/bindings/crypto/st,stm32-cryp.yaml
index 0ddeb8a9a7a0..27354658d054 100644
--- a/Documentation/devicetree/bindings/crypto/st,stm32-cryp.yaml
+++ b/Documentation/devicetree/bindings/crypto/st,stm32-cryp.yaml
@@ -46,6 +46,10 @@ properties:
power-domains:
maxItems: 1
+ access-controllers:
+ minItems: 1
+ maxItems: 2
+
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml
index ac480765cde0..822318414095 100644
--- a/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml
+++ b/Documentation/devicetree/bindings/crypto/st,stm32-hash.yaml
@@ -51,6 +51,10 @@ properties:
power-domains:
maxItems: 1
+ access-controllers:
+ minItems: 1
+ maxItems: 2
+
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml b/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml
index 329847ef096a..ff935a0068ec 100644
--- a/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml
+++ b/Documentation/devicetree/bindings/dma/st,stm32-dma.yaml
@@ -82,6 +82,10 @@ properties:
description: if defined, it indicates that the controller
supports memory-to-memory transfer
+ access-controllers:
+ minItems: 1
+ maxItems: 2
+
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml b/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml
index e722fbcd8a5f..ddf82bf1e71a 100644
--- a/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml
+++ b/Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml
@@ -28,6 +28,10 @@ properties:
resets:
maxItems: 1
+ access-controllers:
+ minItems: 1
+ maxItems: 2
+
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml b/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml
index 94b75d9f66cd..39fad8f7df44 100644
--- a/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml
+++ b/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml
@@ -99,6 +99,10 @@ properties:
wakeup-source: true
+ access-controllers:
+ minItems: 1
+ maxItems: 2
+
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml
index 995cbf8cefc6..ec34c48d4878 100644
--- a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.yaml
@@ -93,6 +93,10 @@ properties:
'#size-cells':
const: 0
+ access-controllers:
+ minItems: 1
+ maxItems: 2
+
allOf:
- if:
properties:
diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml
index 1970503389aa..c1b1324fa132 100644
--- a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml
@@ -59,6 +59,10 @@ properties:
If not, SPI CLKOUT frequency will not be accurate.
maximum: 20000000
+ access-controllers:
+ minItems: 1
+ maxItems: 2
+
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml b/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml
index 04045b932bd2..b15de4eb209c 100644
--- a/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml
+++ b/Documentation/devicetree/bindings/iio/dac/st,stm32-dac.yaml
@@ -45,6 +45,10 @@ properties:
'#size-cells':
const: 0
+ access-controllers:
+ minItems: 1
+ maxItems: 2
+
additionalProperties: false
required:
diff --git a/Documentation/devicetree/bindings/media/cec/st,stm32-cec.yaml b/Documentation/devicetree/bindings/media/cec/st,stm32-cec.yaml
index 2314a9a14650..1d930d9e10fd 100644
--- a/Documentation/devicetree/bindings/media/cec/st,stm32-cec.yaml
+++ b/Documentation/devicetree/bindings/media/cec/st,stm32-cec.yaml
@@ -29,6 +29,10 @@ properties:
- const: cec
- const: hdmi-cec
+ access-controllers:
+ minItems: 1
+ maxItems: 2
+
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml b/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml
index 6b3e413cedb2..34147127192f 100644
--- a/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml
+++ b/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml
@@ -36,6 +36,10 @@ properties:
resets:
maxItems: 1
+ access-controllers:
+ minItems: 1
+ maxItems: 2
+
port:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
diff --git a/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml b/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml
index 14f1833d37c9..deef455bfd21 100644
--- a/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml
@@ -45,6 +45,10 @@ properties:
Reflects the memory layout with four integer values per bank. Format:
<bank-number> 0 <address of the bank> <size>
+ access-controllers:
+ minItems: 1
+ maxItems: 2
+
patternProperties:
"^.*@[0-4],[a-f0-9]+$":
additionalProperties: true
diff --git a/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml b/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml
index 27329c5dc38e..d41308856408 100644
--- a/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml
+++ b/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml
@@ -44,6 +44,10 @@ properties:
wakeup-source: true
+ access-controllers:
+ minItems: 1
+ maxItems: 2
+
pwm:
type: object
additionalProperties: false
diff --git a/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml b/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml
index f84e09a5743b..b0e438ff4950 100644
--- a/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml
+++ b/Documentation/devicetree/bindings/mfd/st,stm32-timers.yaml
@@ -67,6 +67,10 @@ properties:
"#size-cells":
const: 0
+ access-controllers:
+ minItems: 1
+ maxItems: 2
+
pwm:
type: object
additionalProperties: false
diff --git a/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml b/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml
index 2459a55ed540..5644927be810 100644
--- a/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml
+++ b/Documentation/devicetree/bindings/mmc/arm,pl18x.yaml
@@ -79,6 +79,10 @@ properties:
- const: rx
- const: tx
+ access-controllers:
+ minItems: 1
+ maxItems: 2
+
power-domains: true
resets:
diff --git a/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml b/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml
index f9ffb963d6b1..c4887522e8fe 100644
--- a/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml
+++ b/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml
@@ -118,6 +118,10 @@ properties:
phys:
maxItems: 1
+ access-controllers:
+ minItems: 1
+ maxItems: 2
+
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
index fc8c96b08d7d..f2714b5b6cf4 100644
--- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
+++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
@@ -93,6 +93,10 @@ properties:
select RCC clock instead of ETH_REF_CLK.
type: boolean
+ access-controllers:
+ minItems: 1
+ maxItems: 2
+
required:
- compatible
- clocks
diff --git a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
index 24a3dbde223b..ceea122ae1a6 100644
--- a/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
+++ b/Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
@@ -55,6 +55,10 @@ properties:
description: number of clock cells for ck_usbo_48m consumer
const: 0
+ access-controllers:
+ minItems: 1
+ maxItems: 2
+
# Required child nodes:
patternProperties:
diff --git a/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml b/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml
index 05f4ad2c7d3a..6ceaffb45dc9 100644
--- a/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml
+++ b/Documentation/devicetree/bindings/regulator/st,stm32-vrefbuf.yaml
@@ -30,6 +30,10 @@ properties:
vdda-supply:
description: phandle to the vdda input analog voltage.
+ access-controllers:
+ minItems: 1
+ maxItems: 2
+
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml b/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml
index 717f6b321f88..340d01d481d1 100644
--- a/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml
+++ b/Documentation/devicetree/bindings/rng/st,stm32-rng.yaml
@@ -37,6 +37,10 @@ properties:
description: If set, the RNG configuration in RNG_CR, RNG_HTCR and
RNG_NSCR will be locked.
+ access-controllers:
+ minItems: 1
+ maxItems: 2
+
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml
index 1df8ffe95fc6..1de03af4ead1 100644
--- a/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml
+++ b/Documentation/devicetree/bindings/serial/st,stm32-uart.yaml
@@ -70,6 +70,10 @@ properties:
enum: [1, 2, 4, 8, 12, 14, 16]
default: 8
+ access-controllers:
+ minItems: 1
+ maxItems: 2
+
allOf:
- $ref: rs485.yaml#
- $ref: serial.yaml#
diff --git a/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml b/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml
index b9111d375b93..8978f6bd63e5 100644
--- a/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml
+++ b/Documentation/devicetree/bindings/sound/st,stm32-i2s.yaml
@@ -65,6 +65,10 @@ properties:
$ref: audio-graph-port.yaml#
unevaluatedProperties: false
+ access-controllers:
+ minItems: 1
+ maxItems: 2
+
required:
- compatible
- "#sound-dai-cells"
diff --git a/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml b/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml
index 59df8a832310..b46a4778807d 100644
--- a/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml
+++ b/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml
@@ -48,6 +48,10 @@ properties:
clock-names:
maxItems: 3
+ access-controllers:
+ minItems: 1
+ maxItems: 2
+
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml b/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml
index bc48151b9adb..3dedc81ec12f 100644
--- a/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml
+++ b/Documentation/devicetree/bindings/sound/st,stm32-spdifrx.yaml
@@ -50,6 +50,10 @@ properties:
resets:
maxItems: 1
+ access-controllers:
+ minItems: 1
+ maxItems: 2
+
required:
- compatible
- "#sound-dai-cells"
diff --git a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml
index 8bba965a9ae6..3f1a27efff80 100644
--- a/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml
+++ b/Documentation/devicetree/bindings/spi/st,stm32-qspi.yaml
@@ -46,6 +46,10 @@ properties:
- const: tx
- const: rx
+ access-controllers:
+ minItems: 1
+ maxItems: 2
+
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml b/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml
index ae0f082bd377..0b303bf5c02c 100644
--- a/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml
+++ b/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml
@@ -50,6 +50,10 @@ properties:
- const: rx
- const: tx
+ access-controllers:
+ minItems: 1
+ maxItems: 2
+
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/usb/dwc2.yaml b/Documentation/devicetree/bindings/usb/dwc2.yaml
index 0a5c98ea711d..88c077673c8b 100644
--- a/Documentation/devicetree/bindings/usb/dwc2.yaml
+++ b/Documentation/devicetree/bindings/usb/dwc2.yaml
@@ -172,6 +172,10 @@ properties:
tpl-support: true
+ access-controllers:
+ minItems: 1
+ maxItems: 2
+
dependencies:
port: [ usb-role-switch ]
role-switch-default-mode: [ usb-role-switch ]
--
2.35.3
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH v9 03/13] dt-bindings: bus: document RIFSC
From: Gatien Chevallier @ 2024-01-05 13:03 UTC (permalink / raw)
To: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
krzysztof.kozlowski+dt, conor+dt, alexandre.torgue, vkoul, jic23,
olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
andi.shyti, ulf.hansson, edumazet, kuba, pabeni, hugues.fruchet,
lee, will, catalin.marinas, arnd, richardcochran, Frank Rowand,
peng.fan, lars, rcsekar, wg, mkl
Cc: linux-crypto, devicetree, linux-stm32, linux-arm-kernel,
linux-kernel, dmaengine, linux-i2c, linux-iio, alsa-devel,
linux-media, linux-mmc, netdev, linux-phy, linux-serial,
linux-spi, linux-usb, Gatien Chevallier, Rob Herring
In-Reply-To: <20240105130404.301172-1-gatien.chevallier@foss.st.com>
Document RIFSC (RIF security controller). RIFSC is a firewall controller
composed of different kinds of hardware resources.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Changes in V9:
- Added "simple-bus" to RIFSC's compatible list
- Added Rob's review tag
Changes in V6:
- Renamed access-controller to access-controllers
- Removal of access-control-provider property
- Removal of access-controller and access-controller-names
declaration in the patternProperties field. Add
additionalProperties: true in this field.
Changes in V5:
- Renamed feature-domain* to access-control*
Changes in V2:
- Corrected errors highlighted by Rob's robot
- No longer define the maxItems for the "feature-domains"
property
- Fix example (node name, status)
- Declare "feature-domain-names" as an optional
property for child nodes
- Fix description of "feature-domains" property
.../bindings/bus/st,stm32mp25-rifsc.yaml | 105 ++++++++++++++++++
1 file changed, 105 insertions(+)
create mode 100644 Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml
diff --git a/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml b/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml
new file mode 100644
index 000000000000..20acd1a6b173
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml
@@ -0,0 +1,105 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bus/st,stm32mp25-rifsc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STM32 Resource isolation framework security controller
+
+maintainers:
+ - Gatien Chevallier <gatien.chevallier@foss.st.com>
+
+description: |
+ Resource isolation framework (RIF) is a comprehensive set of hardware blocks
+ designed to enforce and manage isolation of STM32 hardware resources like
+ memory and peripherals.
+
+ The RIFSC (RIF security controller) is composed of three sets of registers,
+ each managing a specific set of hardware resources:
+ - RISC registers associated with RISUP logic (resource isolation device unit
+ for peripherals), assign all non-RIF aware peripherals to zero, one or
+ any security domains (secure, privilege, compartment).
+ - RIMC registers: associated with RIMU logic (resource isolation master
+ unit), assign all non RIF-aware bus master to one security domain by
+ setting secure, privileged and compartment information on the system bus.
+ Alternatively, the RISUP logic controlling the device port access to a
+ peripheral can assign target bus attributes to this peripheral master port
+ (supported attribute: CID).
+ - RISC registers associated with RISAL logic (resource isolation device unit
+ for address space - Lite version), assign address space subregions to one
+ security domains (secure, privilege, compartment).
+
+select:
+ properties:
+ compatible:
+ contains:
+ const: st,stm32mp25-rifsc
+ required:
+ - compatible
+
+properties:
+ compatible:
+ items:
+ - const: st,stm32mp25-rifsc
+ - const: simple-bus
+
+ reg:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+ ranges: true
+
+ "#access-controller-cells":
+ const: 1
+ description:
+ Contains the firewall ID associated to the peripheral.
+
+patternProperties:
+ "^.*@[0-9a-f]+$":
+ description: Peripherals
+ type: object
+
+ additionalProperties: true
+
+ required:
+ - access-controllers
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+ - "#access-controller-cells"
+ - ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ // In this example, the usart2 device refers to rifsc as its domain
+ // controller.
+ // Access rights are verified before creating devices.
+
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ rifsc: bus@42080000 {
+ compatible = "st,stm32mp25-rifsc", "simple-bus";
+ reg = <0x42080000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #access-controller-cells = <1>;
+ ranges;
+
+ usart2: serial@400e0000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x400e0000 0x400>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ck_flexgen_08>;
+ access-controllers = <&rifsc 32>;
+ };
+ };
--
2.35.3
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH v9 00/13] Introduce STM32 Firewall framework
From: Gatien Chevallier @ 2024-01-05 13:03 UTC (permalink / raw)
To: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
krzysztof.kozlowski+dt, conor+dt, alexandre.torgue, vkoul, jic23,
olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
andi.shyti, ulf.hansson, edumazet, kuba, pabeni, hugues.fruchet,
lee, will, catalin.marinas, arnd, richardcochran, Frank Rowand,
peng.fan, lars, rcsekar, wg, mkl
Cc: linux-crypto, devicetree, linux-stm32, linux-arm-kernel,
linux-kernel, dmaengine, linux-i2c, linux-iio, alsa-devel,
linux-media, linux-mmc, netdev, linux-phy, linux-serial,
linux-spi, linux-usb, Gatien Chevallier
Introduce STM32 Firewall framework for STM32MP1x and STM32MP2x
platforms. STM32MP1x(ETZPC) and STM32MP2x(RIFSC) Firewall controllers
register to the framework to offer firewall services such as access
granting.
This series of patches is a new approach on the previous STM32 system
bus, history is available here:
https://lore.kernel.org/lkml/20230127164040.1047583/
The need for such framework arises from the fact that there are now
multiple hardware firewalls implemented across multiple products.
Drivers are shared between different products, using the same code.
When it comes to firewalls, the purpose mostly stays the same: Protect
hardware resources. But the implementation differs, and there are
multiple types of firewalls: peripheral, memory, ...
Some hardware firewall controllers such as the RIFSC implemented on
STM32MP2x platforms may require to take ownership of a resource before
being able to use it, hence the requirement for firewall services to
take/release the ownership of such resources.
On the other hand, hardware firewall configurations are becoming
more and more complex. These mecanisms prevent platform crashes
or other firewall-related incoveniences by denying access to some
resources.
The stm32 firewall framework offers an API that is defined in
firewall controllers drivers to best fit the specificity of each
firewall.
For every peripherals protected by either the ETZPC or the RIFSC, the
firewall framework checks the firewall controlelr registers to see if
the peripheral's access is granted to the Linux kernel. If not, the
peripheral is configured as secure, the node is marked populated,
so that the driver is not probed for that device.
The firewall framework relies on the access-controller device tree
binding. It is used by peripherals to reference a domain access
controller. In this case a firewall controller. The bus uses the ID
referenced by the access-controller property to know where to look
in the firewall to get the security configuration for the peripheral.
This allows a device tree description rather than a hardcoded peripheral
table in the bus driver.
The STM32 ETZPC device is responsible for filtering accesses based on
security level, or co-processor isolation for any resource connected
to it.
The RIFSC is responsible for filtering accesses based on Compartment
ID / security level / privilege level for any resource connected to
it.
STM32MP13/15/25 SoC device tree files are updated in this series to
implement this mecanism.
Changes in V9:
- Added Rob's reviews tags on bindings/of files
- Added "simple-bus" to RIFSC/ETZPC compatible item list
Changes in V8:
- Add missing "simple-bus" compatible in STM32MP13/25 SoC
device tree files for the ETZPC/RIFSC nodes
- Add missing dependency on OF for OF_DYNAMIC that is selected
by STM32_FIREWALL
Changes in V7:
- Separate indentation changes from access-controllers changes
in the device tree file commits
- Select OF_DYNAMIC when STM32_FIREWALL is set in order to use
of_detach_node() in the firewall framework
- Handle previously non-present RNG and HASH nodes in the
STM32MP13 device tree file
Changes in V6:
- Rename access-controller to access-controllers
- Remove access-controller-provider
- Update device trees and other bindings accordingly
- Rework ETZPC/RIFSC bindings to define what access-controllers
cells contain inside #access-controller-cells
- Some other minor fixes
Changes in V5:
- Integrate and rework the "feature-domains" binding patch in
this patchset. The binding is renamed to "access-controller"
- Rename every feature-domain* reference to access-control*
ones
- Correct loop bug and missing select STM32_FIREWALL in 32-bit
platform Kconfig
Changes in V4:
- Fix typo in commit message and YAML check errors in
"dt-bindings: Document common device controller bindings"
Note: This patch should be ignored as stated in the cover
letter. I've done this to avoid errors on this series of
patch
- Correct code syntax/style issues reported by Simon Horman
- Added Jonathan's tag for IIO on the treewide patch
Changes in V3:
Change incorrect ordering for bindings commits leading
to an error while running
"make DT_CHECKER_FLAGS=-m dt_binding_check"
Changes in V2:
generic:
- Add fw_devlink dependency for "feature-domains"
property.
bindings:
- Corrected YAMLS errors highlighted by Rob's robot
- Firewall controllers YAMLs no longer define the
maxItems for the "feature-domains" property
- Renamed st,stm32-rifsc.yaml to
st,stm32mp25-rifsc.yaml
- Fix examples in YAML files
- Change feature-domains maxItems to 2 in firewall
consumer files as there should not be more than
2 entries for now
- Declare "feature-domain-names" as an optional
property for firewall controllers child nodes.
- Add missing "feature-domains" property declaration
in bosch,m_can.yaml and st,stm32-cryp.yaml files
firewall framework:
- Support multiple entries for "feature-domains"
property
- Better handle the device-tree parsing using
phandle+args APIs
- Remove "resource firewall" type
- Add a field for the name of the firewall entry
- Fix licenses
RIFSC:
- Add controller name
- Driver is now a module_platform_driver
- Fix license
ETZPC:
- Add controller name
- Driver is now a module_platform_driver
- Fix license
Device trees:
- Fix rifsc node name
- Move the "ranges" property under the
"feature-domains" one
Gatien Chevallier (12):
dt-bindings: treewide: add access-controllers description
dt-bindings: bus: document RIFSC
dt-bindings: bus: document ETZPC
firewall: introduce stm32_firewall framework
of: property: fw_devlink: Add support for "access-controller"
bus: rifsc: introduce RIFSC firewall controller driver
arm64: dts: st: add RIFSC as an access controller for STM32MP25x
boards
bus: etzpc: introduce ETZPC firewall controller driver
ARM: dts: stm32: add ETZPC as a system bus for STM32MP15x boards
ARM: dts: stm32: put ETZPC as an access controller for STM32MP15x
boards
ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards
ARM: dts: stm32: put ETZPC as an access controller for STM32MP13x
boards
Oleksii Moisieiev (1):
dt-bindings: document generic access controllers
.../access-controllers.yaml | 84 +
.../bindings/bus/st,stm32-etzpc.yaml | 96 +
.../bindings/bus/st,stm32mp25-rifsc.yaml | 105 +
.../bindings/crypto/st,stm32-cryp.yaml | 4 +
.../bindings/crypto/st,stm32-hash.yaml | 4 +
.../devicetree/bindings/dma/st,stm32-dma.yaml | 4 +
.../bindings/dma/st,stm32-dmamux.yaml | 4 +
.../devicetree/bindings/i2c/st,stm32-i2c.yaml | 4 +
.../bindings/iio/adc/st,stm32-adc.yaml | 4 +
.../bindings/iio/adc/st,stm32-dfsdm-adc.yaml | 4 +
.../bindings/iio/dac/st,stm32-dac.yaml | 4 +
.../bindings/media/cec/st,stm32-cec.yaml | 4 +
.../bindings/media/st,stm32-dcmi.yaml | 4 +
.../memory-controllers/st,stm32-fmc2-ebi.yaml | 4 +
.../bindings/mfd/st,stm32-lptimer.yaml | 4 +
.../bindings/mfd/st,stm32-timers.yaml | 4 +
.../devicetree/bindings/mmc/arm,pl18x.yaml | 4 +
.../bindings/net/can/bosch,m_can.yaml | 4 +
.../devicetree/bindings/net/stm32-dwmac.yaml | 4 +
.../bindings/phy/phy-stm32-usbphyc.yaml | 4 +
.../bindings/regulator/st,stm32-vrefbuf.yaml | 4 +
.../devicetree/bindings/rng/st,stm32-rng.yaml | 4 +
.../bindings/serial/st,stm32-uart.yaml | 4 +
.../bindings/sound/st,stm32-i2s.yaml | 4 +
.../bindings/sound/st,stm32-sai.yaml | 4 +
.../bindings/sound/st,stm32-spdifrx.yaml | 4 +
.../bindings/spi/st,stm32-qspi.yaml | 4 +
.../devicetree/bindings/spi/st,stm32-spi.yaml | 4 +
.../devicetree/bindings/usb/dwc2.yaml | 4 +
MAINTAINERS | 7 +
arch/arm/boot/dts/st/stm32mp131.dtsi | 1063 ++++---
arch/arm/boot/dts/st/stm32mp133.dtsi | 51 +-
arch/arm/boot/dts/st/stm32mp13xc.dtsi | 19 +-
arch/arm/boot/dts/st/stm32mp13xf.dtsi | 19 +-
arch/arm/boot/dts/st/stm32mp151.dtsi | 2756 +++++++++--------
arch/arm/boot/dts/st/stm32mp153.dtsi | 52 +-
arch/arm/boot/dts/st/stm32mp15xc.dtsi | 19 +-
arch/arm/mach-stm32/Kconfig | 1 +
arch/arm64/Kconfig.platforms | 1 +
arch/arm64/boot/dts/st/stm32mp251.dtsi | 7 +-
drivers/bus/Kconfig | 10 +
drivers/bus/Makefile | 1 +
drivers/bus/stm32_etzpc.c | 141 +
drivers/bus/stm32_firewall.c | 294 ++
drivers/bus/stm32_firewall.h | 83 +
drivers/bus/stm32_rifsc.c | 252 ++
drivers/of/property.c | 2 +
include/linux/bus/stm32_firewall_device.h | 141 +
48 files changed, 3370 insertions(+), 1938 deletions(-)
create mode 100644 Documentation/devicetree/bindings/access-controllers/access-controllers.yaml
create mode 100644 Documentation/devicetree/bindings/bus/st,stm32-etzpc.yaml
create mode 100644 Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml
create mode 100644 drivers/bus/stm32_etzpc.c
create mode 100644 drivers/bus/stm32_firewall.c
create mode 100644 drivers/bus/stm32_firewall.h
create mode 100644 drivers/bus/stm32_rifsc.c
create mode 100644 include/linux/bus/stm32_firewall_device.h
--
2.35.3
--
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^ permalink raw reply
* [PATCH v9 01/13] dt-bindings: document generic access controllers
From: Gatien Chevallier @ 2024-01-05 13:03 UTC (permalink / raw)
To: Oleksii_Moisieiev, gregkh, herbert, davem, robh+dt,
krzysztof.kozlowski+dt, conor+dt, alexandre.torgue, vkoul, jic23,
olivier.moysan, arnaud.pouliquen, mchehab, fabrice.gasnier,
andi.shyti, ulf.hansson, edumazet, kuba, pabeni, hugues.fruchet,
lee, will, catalin.marinas, arnd, richardcochran, Frank Rowand,
peng.fan, lars, rcsekar, wg, mkl
Cc: linux-crypto, devicetree, linux-stm32, linux-arm-kernel,
linux-kernel, dmaengine, linux-i2c, linux-iio, alsa-devel,
linux-media, linux-mmc, netdev, linux-phy, linux-serial,
linux-spi, linux-usb, Oleksii Moisieiev, Gatien Chevallier,
Rob Herring
In-Reply-To: <20240105130404.301172-1-gatien.chevallier@foss.st.com>
From: Oleksii Moisieiev <Oleksii_Moisieiev@epam.com>
Introducing of the generic access controllers bindings for the
access controller provider and consumer devices. Those bindings are
intended to allow a better handling of accesses to resources in a
hardware architecture supporting several compartments.
This patch is based on [1]. It is integrated in this patchset as it
provides a use-case for it.
Diffs with [1]:
- Rename feature-domain* properties to access-control* to narrow
down the scope of the binding
- YAML errors and typos corrected.
- Example updated
- Some rephrasing in the binding description
[1]: https://lore.kernel.org/lkml/0c0a82bb-18ae-d057-562b
Signed-off-by: Oleksii Moisieiev <oleksii_moisieiev@epam.com>
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Changes in V9:
- Added Rob's review tag
Changes in V6:
- Renamed access-controller to access-controllers
- Example updated
- Removal of access-control-provider property
Changes in V5:
- Diffs with [1]
- Discarded the [IGNORE] tag as the patch is now part of the
patchset
.../access-controllers.yaml | 84 +++++++++++++++++++
1 file changed, 84 insertions(+)
create mode 100644 Documentation/devicetree/bindings/access-controllers/access-controllers.yaml
diff --git a/Documentation/devicetree/bindings/access-controllers/access-controllers.yaml b/Documentation/devicetree/bindings/access-controllers/access-controllers.yaml
new file mode 100644
index 000000000000..99e2865f0e46
--- /dev/null
+++ b/Documentation/devicetree/bindings/access-controllers/access-controllers.yaml
@@ -0,0 +1,84 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/access-controllers/access-controllers.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Generic Domain Access Controllers
+
+maintainers:
+ - Oleksii Moisieiev <oleksii_moisieiev@epam.com>
+
+description: |+
+ Common access controllers properties
+
+ Access controllers are in charge of stating which of the hardware blocks under
+ their responsibility (their domain) can be accesssed by which compartment. A
+ compartment can be a cluster of CPUs (or coprocessors), a range of addresses
+ or a group of hardware blocks. An access controller's domain is the set of
+ resources covered by the access controller.
+
+ This device tree binding can be used to bind devices to their access
+ controller provided by access-controllers property. In this case, the device
+ is a consumer and the access controller is the provider.
+
+ An access controller can be represented by any node in the device tree and
+ can provide one or more configuration parameters, needed to control parameters
+ of the consumer device. A consumer node can refer to the provider by phandle
+ and a set of phandle arguments, specified by '#access-controller-cells'
+ property in the access controller node.
+
+ Access controllers are typically used to set/read the permissions of a
+ hardware block and grant access to it. Any of which depends on the access
+ controller. The capabilities of each access controller are defined by the
+ binding of the access controller device.
+
+ Each node can be a consumer for the several access controllers.
+
+# always select the core schema
+select: true
+
+properties:
+ "#access-controller-cells":
+ description:
+ Number of cells in an access-controllers specifier;
+ Can be any value as specified by device tree binding documentation
+ of a particular provider. The node is an access controller.
+
+ access-controller-names:
+ $ref: /schemas/types.yaml#/definitions/string-array
+ description:
+ A list of access-controllers names, sorted in the same order as
+ access-controllers entries. Consumer drivers will use
+ access-controller-names to match with existing access-controllers entries.
+
+ access-controllers:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description:
+ A list of access controller specifiers, as defined by the
+ bindings of the access-controllers provider.
+
+additionalProperties: true
+
+examples:
+ - |
+ clock_controller: access-controllers@50000 {
+ reg = <0x50000 0x400>;
+ #access-controller-cells = <2>;
+ };
+
+ bus_controller: bus@60000 {
+ reg = <0x60000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ #access-controller-cells = <3>;
+
+ uart4: serial@60100 {
+ reg = <0x60100 0x400>;
+ clocks = <&clk_serial>;
+ access-controllers = <&clock_controller 1 2>,
+ <&bus_controller 1 3 5>;
+ access-controller-names = "clock", "bus";
+ };
+ };
--
2.35.3
--
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^ permalink raw reply related
* Re: [PATCH v2 2/2] phy: qualcomm: eusb2-repeater: Rework init to drop redundant zero-out loop
From: Dmitry Baryshkov @ 2024-01-05 12:22 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Abel Vesa, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I,
Elliot Berman, linux-arm-msm, linux-phy, linux-kernel
In-Reply-To: <158df3b2-a7fa-449d-9cc8-1e4cdf6ef49b@linaro.org>
On Fri, 5 Jan 2024 at 13:44, Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>
> On 5.01.2024 11:16, Abel Vesa wrote:
> > The device match config init table already has zero values, so rework
> > the container struct to hold a copy of the init table that can be
> > override be the DT specified values. By doing this, only the number of
> > vregs remain in the device match config that will be later needed, so
> > instead of holding the cfg after probe, store the number of vregs in the
> > container struct.
> >
> > Fixes: 99a517a582fc ("phy: qualcomm: phy-qcom-eusb2-repeater: Zero out untouched tuning regs")
> > Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> > ---
>
> This looks good as-is, though I think my proposal of storing the
> peripheral base reg instead is still better, as it'd require less
> memory (no kmemdup as the regs wouldn't be modified).
I'd second this. We usually handle such cases via the base + offset
rather than patching the data. If regfields can not handle this, then
the regfield should be fixed.
--
With best wishes
Dmitry
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^ permalink raw reply
* Re: [PATCH v2 2/2] phy: qualcomm: eusb2-repeater: Rework init to drop redundant zero-out loop
From: Konrad Dybcio @ 2024-01-05 11:44 UTC (permalink / raw)
To: Abel Vesa, Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I
Cc: Elliot Berman, linux-arm-msm, linux-phy, linux-kernel
In-Reply-To: <20240105-phy-qcom-eusb2-repeater-fixes-v2-2-775d98e7df05@linaro.org>
On 5.01.2024 11:16, Abel Vesa wrote:
> The device match config init table already has zero values, so rework
> the container struct to hold a copy of the init table that can be
> override be the DT specified values. By doing this, only the number of
> vregs remain in the device match config that will be later needed, so
> instead of holding the cfg after probe, store the number of vregs in the
> container struct.
>
> Fixes: 99a517a582fc ("phy: qualcomm: phy-qcom-eusb2-repeater: Zero out untouched tuning regs")
> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> ---
This looks good as-is, though I think my proposal of storing the
peripheral base reg instead is still better, as it'd require less
memory (no kmemdup as the regs wouldn't be modified).
Konrad
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^ permalink raw reply
* Re: [PATCH] phy: renesas: rcar-gen3-usb2: Fix returning wrong error code
From: Geert Uytterhoeven @ 2024-01-05 10:25 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: vkoul, kishon, error27, linux-phy, linux-renesas-soc,
kernel test robot
In-Reply-To: <20240105093703.3359949-1-yoshihiro.shimoda.uh@renesas.com>
On Fri, Jan 5, 2024 at 10:42 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> Even if device_create_file() returns error code,
> rcar_gen3_phy_usb2_probe() will return zero because the "ret" is
> variable shadowing.
>
> Reported-by: kernel test robot <lkp@intel.com>
> Reported-by: Dan Carpenter <error27@gmail.com>
> Closes: https://lore.kernel.org/r/202312161021.gOLDl48K-lkp@intel.com/
> Fixes: 441a681b8843 ("phy: rcar-gen3-usb2: fix implementation for runtime PM")
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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^ permalink raw reply
* Re: [PATCH 2/2] phy: qualcomm: eusb2-repeater: Drop the redundant zeroing
From: Abel Vesa @ 2024-01-05 10:19 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I,
linux-arm-msm, linux-phy, linux-kernel
In-Reply-To: <e216c027-dc23-415d-8d00-e6b1cbbd4248@linaro.org>
On 24-01-05 11:09:33, Konrad Dybcio wrote:
> On 5.01.2024 10:16, Abel Vesa wrote:
> > On 24-01-04 23:50:48, Konrad Dybcio wrote:
> >> On 4.01.2024 15:52, Abel Vesa wrote:
> >>> The local init_tlb is already zero initialized, so the entire zeroing loop
> >>> is useless in this case, since the initial values are copied over anyway,
> >>> before being written.
> >>>
> >>> Fixes: 99a517a582fc ("phy: qualcomm: phy-qcom-eusb2-repeater: Zero out untouched tuning regs")
> >>> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> >>> ---
> >>
> >> That's another good spot.. partial struct initialization of
> >> pm8550b_init_tbl zeroes out the uninitialized fields.
> >>
> >>
> >>> drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c | 10 ----------
> >>> 1 file changed, 10 deletions(-)
> >>>
> >>> diff --git a/drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c b/drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c
> >>> index 5f5862a68b73..3060c0749797 100644
> >>> --- a/drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c
> >>> +++ b/drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c
> >>> @@ -156,16 +156,6 @@ static int eusb2_repeater_init(struct phy *phy)
> >>>
> >>> regmap_field_update_bits(rptr->regs[F_EN_CTL1], EUSB2_RPTR_EN, EUSB2_RPTR_EN);
> >>>
> >>> - for (i = 0; i < F_NUM_TUNE_FIELDS; i++) {
> >>> - if (init_tbl[i]) {
> >>> - regmap_field_update_bits(rptr->regs[i], init_tbl[i], init_tbl[i]);
> >>> - } else {
> >>> - /* Write 0 if there's no value set */
> >>> - u32 mask = GENMASK(regfields[i].msb, regfields[i].lsb);
> >>> -
> >>> - regmap_field_update_bits(rptr->regs[i], mask, 0);
> >>> - }
> >>> - }
> >>> memcpy(init_tbl, rptr->cfg->init_tbl, sizeof(init_tbl));
> >>
> >> I think this patchset can be made even better, this memcpy is also
> >> useless and we can simply initialize init_tbl=rptr->cfg->init_tbl.
> >
> > Actually no. The init_tbl in cfg is a pointer to const. Plus, if you do
> > that, you will end up with the same situation like in the other patch,
> > as there are some overrides based on DT values below this.
>
> Hm, you're right. Maybe we should simple store *base and stop
> modifying these tables then. There's not a whole lot of regmap_rw
> calls, so making the first argument "rptr->base + rptr->regs[ASDF]"
> shouldn't add much fluff. Then we can make the cfg referernce const.
>
Oh, sorry, did not see your reply in time before sending v2.
Have a look at v2 and we can decide if we want something different then.
https://lore.kernel.org/all/20240105-phy-qcom-eusb2-repeater-fixes-v2-0-775d98e7df05@linaro.org/
Thanks for reviewing.
> Konrad
>
> >
> > But now that I've had another look, maybe doing the exact same thing as
> > the other patch does (kmemdup) will probably look better anyway,
> > specially if we do that on probe.
> >
> >>
> >> Konrad
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^ permalink raw reply
* [PATCH v2 2/2] phy: qualcomm: eusb2-repeater: Rework init to drop redundant zero-out loop
From: Abel Vesa @ 2024-01-05 10:16 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I
Cc: Elliot Berman, linux-arm-msm, linux-phy, linux-kernel, Abel Vesa
In-Reply-To: <20240105-phy-qcom-eusb2-repeater-fixes-v2-0-775d98e7df05@linaro.org>
The device match config init table already has zero values, so rework
the container struct to hold a copy of the init table that can be
override be the DT specified values. By doing this, only the number of
vregs remain in the device match config that will be later needed, so
instead of holding the cfg after probe, store the number of vregs in the
container struct.
Fixes: 99a517a582fc ("phy: qualcomm: phy-qcom-eusb2-repeater: Zero out untouched tuning regs")
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c | 42 ++++++++++++--------------
1 file changed, 19 insertions(+), 23 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c b/drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c
index 5f5862a68b73..d28106e71ce3 100644
--- a/drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c
+++ b/drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c
@@ -102,7 +102,8 @@ struct eusb2_repeater {
struct phy *phy;
struct regulator_bulk_data *vregs;
struct reg_field *regfields;
- const struct eusb2_repeater_cfg *cfg;
+ u32 *init_tbl;
+ int num_vregs;
enum phy_mode mode;
};
@@ -123,9 +124,10 @@ static const struct eusb2_repeater_cfg pm8550b_eusb2_cfg = {
.num_vregs = ARRAY_SIZE(pm8550b_vreg_l),
};
-static int eusb2_repeater_init_vregs(struct eusb2_repeater *rptr)
+static int eusb2_repeater_init_vregs(struct eusb2_repeater *rptr,
+ const struct eusb2_repeater_cfg *cfg)
{
- int num = rptr->cfg->num_vregs;
+ int num = cfg->num_vregs;
struct device *dev = rptr->dev;
int i;
@@ -134,7 +136,7 @@ static int eusb2_repeater_init_vregs(struct eusb2_repeater *rptr)
return -ENOMEM;
for (i = 0; i < num; i++)
- rptr->vregs[i].supply = rptr->cfg->vreg_list[i];
+ rptr->vregs[i].supply = cfg->vreg_list[i];
return devm_regulator_bulk_get(dev, num, rptr->vregs);
}
@@ -142,32 +144,19 @@ static int eusb2_repeater_init_vregs(struct eusb2_repeater *rptr)
static int eusb2_repeater_init(struct phy *phy)
{
struct eusb2_repeater *rptr = phy_get_drvdata(phy);
- struct reg_field *regfields = rptr->regfields;
struct device_node *np = rptr->dev->of_node;
- u32 init_tbl[F_NUM_TUNE_FIELDS] = { 0 };
+ u32 *init_tbl = rptr->init_tbl;
u8 override;
u32 val;
int ret;
int i;
- ret = regulator_bulk_enable(rptr->cfg->num_vregs, rptr->vregs);
+ ret = regulator_bulk_enable(rptr->num_vregs, rptr->vregs);
if (ret)
return ret;
regmap_field_update_bits(rptr->regs[F_EN_CTL1], EUSB2_RPTR_EN, EUSB2_RPTR_EN);
- for (i = 0; i < F_NUM_TUNE_FIELDS; i++) {
- if (init_tbl[i]) {
- regmap_field_update_bits(rptr->regs[i], init_tbl[i], init_tbl[i]);
- } else {
- /* Write 0 if there's no value set */
- u32 mask = GENMASK(regfields[i].msb, regfields[i].lsb);
-
- regmap_field_update_bits(rptr->regs[i], mask, 0);
- }
- }
- memcpy(init_tbl, rptr->cfg->init_tbl, sizeof(init_tbl));
-
if (!of_property_read_u8(np, "qcom,tune-usb2-amplitude", &override))
init_tbl[F_TUNE_IUSB2] = override;
@@ -228,7 +217,7 @@ static int eusb2_repeater_exit(struct phy *phy)
{
struct eusb2_repeater *rptr = phy_get_drvdata(phy);
- return regulator_bulk_disable(rptr->cfg->num_vregs, rptr->vregs);
+ return regulator_bulk_disable(rptr->num_vregs, rptr->vregs);
}
static const struct phy_ops eusb2_repeater_ops = {
@@ -240,6 +229,7 @@ static const struct phy_ops eusb2_repeater_ops = {
static int eusb2_repeater_probe(struct platform_device *pdev)
{
+ const struct eusb2_repeater_cfg *cfg;
struct eusb2_repeater *rptr;
struct device *dev = &pdev->dev;
struct phy_provider *phy_provider;
@@ -255,8 +245,8 @@ static int eusb2_repeater_probe(struct platform_device *pdev)
rptr->dev = dev;
dev_set_drvdata(dev, rptr);
- rptr->cfg = of_device_get_match_data(dev);
- if (!rptr->cfg)
+ cfg = of_device_get_match_data(dev);
+ if (!cfg)
return -EINVAL;
regmap = dev_get_regmap(dev->parent, NULL);
@@ -269,6 +259,12 @@ static int eusb2_repeater_probe(struct platform_device *pdev)
if (!rptr->regfields)
return -ENOMEM;
+ rptr->init_tbl = devm_kmemdup(dev, cfg->init_tbl,
+ sizeof(cfg->init_tbl),
+ GFP_KERNEL);
+ if (!rptr->init_tbl)
+ return -ENOMEM;
+
ret = of_property_read_u32(np, "reg", &res);
if (ret < 0)
return ret;
@@ -282,7 +278,7 @@ static int eusb2_repeater_probe(struct platform_device *pdev)
if (ret)
return ret;
- ret = eusb2_repeater_init_vregs(rptr);
+ ret = eusb2_repeater_init_vregs(rptr, cfg);
if (ret < 0) {
dev_err(dev, "unable to get supplies\n");
return ret;
--
2.34.1
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* [PATCH v2 0/2] phy: qualcomm: eusb2-repeater: Some fixes after the regmap rework
From: Abel Vesa @ 2024-01-05 10:16 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I
Cc: Elliot Berman, linux-arm-msm, linux-phy, linux-kernel, Abel Vesa
Found the first issue (from first patch) while adding support
for X Elite (X1E80100) which comes with more than one repeaters.
The second fix is just bonus.
---
Changes in v2:
- The regfields is being dropped from the repeater init, but it's done
in the second patch in order to not break bisectability, as it is
still needed by the zero-out loop.
- Added Konrad's R-b tag to the first patch. Did not add Elliot's T-b
tag as the second patch has been reworked massively.
- The zero-out loop is dropped now by holding a copy of the init_tlb in
the container struct. This led to dropping the cfg from the container
struct (see second patch commit message for more details).
- Link to v1: https://lore.kernel.org/r/20240104-phy-qcom-eusb2-repeater-fixes-v1-0-047b7b6b8333@linaro.org
---
Abel Vesa (2):
phy: qualcomm: eusb2-repeater: Fix the regfields for multiple instances
phy: qualcomm: eusb2-repeater: Rework init to drop redundant zero-out loop
drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c | 53 ++++++++++++++------------
1 file changed, 28 insertions(+), 25 deletions(-)
---
base-commit: e2425464bc87159274879ab30f9d4fe624b9fcd2
change-id: 20240104-phy-qcom-eusb2-repeater-fixes-c9201113032c
Best regards,
--
Abel Vesa <abel.vesa@linaro.org>
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* [PATCH v2 1/2] phy: qualcomm: eusb2-repeater: Fix the regfields for multiple instances
From: Abel Vesa @ 2024-01-05 10:16 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I
Cc: Elliot Berman, linux-arm-msm, linux-phy, linux-kernel, Abel Vesa
In-Reply-To: <20240105-phy-qcom-eusb2-repeater-fixes-v2-0-775d98e7df05@linaro.org>
The global regmap fields offsets currently get incremented with the base
address of the repeater. This issue doesn't get noticed unless the probe
defers or there are multiple repeaters on that platform. So instead of
incrementing the global ones, copy them for each instance of the
repeater.
Fixes: 4ba2e52718c0 ("phy: qualcomm: phy-qcom-eusb2-repeater: Use regmap_fields")
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c | 13 ++++++++++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c b/drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c
index a623f092b11f..5f5862a68b73 100644
--- a/drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c
+++ b/drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c
@@ -101,6 +101,7 @@ struct eusb2_repeater {
struct regmap_field *regs[F_NUM_FIELDS];
struct phy *phy;
struct regulator_bulk_data *vregs;
+ struct reg_field *regfields;
const struct eusb2_repeater_cfg *cfg;
enum phy_mode mode;
};
@@ -140,8 +141,8 @@ static int eusb2_repeater_init_vregs(struct eusb2_repeater *rptr)
static int eusb2_repeater_init(struct phy *phy)
{
- struct reg_field *regfields = eusb2_repeater_tune_reg_fields;
struct eusb2_repeater *rptr = phy_get_drvdata(phy);
+ struct reg_field *regfields = rptr->regfields;
struct device_node *np = rptr->dev->of_node;
u32 init_tbl[F_NUM_TUNE_FIELDS] = { 0 };
u8 override;
@@ -262,15 +263,21 @@ static int eusb2_repeater_probe(struct platform_device *pdev)
if (!regmap)
return -ENODEV;
+ rptr->regfields = devm_kmemdup(dev, eusb2_repeater_tune_reg_fields,
+ sizeof(eusb2_repeater_tune_reg_fields),
+ GFP_KERNEL);
+ if (!rptr->regfields)
+ return -ENOMEM;
+
ret = of_property_read_u32(np, "reg", &res);
if (ret < 0)
return ret;
for (i = 0; i < F_NUM_FIELDS; i++)
- eusb2_repeater_tune_reg_fields[i].reg += res;
+ rptr->regfields[i].reg += res;
ret = devm_regmap_field_bulk_alloc(dev, regmap, rptr->regs,
- eusb2_repeater_tune_reg_fields,
+ rptr->regfields,
F_NUM_FIELDS);
if (ret)
return ret;
--
2.34.1
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* Re: [PATCH 2/2] phy: qualcomm: eusb2-repeater: Drop the redundant zeroing
From: Konrad Dybcio @ 2024-01-05 10:09 UTC (permalink / raw)
To: Abel Vesa
Cc: Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I,
linux-arm-msm, linux-phy, linux-kernel
In-Reply-To: <ZZfI66Mj6v/Qjp5X@linaro.org>
On 5.01.2024 10:16, Abel Vesa wrote:
> On 24-01-04 23:50:48, Konrad Dybcio wrote:
>> On 4.01.2024 15:52, Abel Vesa wrote:
>>> The local init_tlb is already zero initialized, so the entire zeroing loop
>>> is useless in this case, since the initial values are copied over anyway,
>>> before being written.
>>>
>>> Fixes: 99a517a582fc ("phy: qualcomm: phy-qcom-eusb2-repeater: Zero out untouched tuning regs")
>>> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
>>> ---
>>
>> That's another good spot.. partial struct initialization of
>> pm8550b_init_tbl zeroes out the uninitialized fields.
>>
>>
>>> drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c | 10 ----------
>>> 1 file changed, 10 deletions(-)
>>>
>>> diff --git a/drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c b/drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c
>>> index 5f5862a68b73..3060c0749797 100644
>>> --- a/drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c
>>> +++ b/drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c
>>> @@ -156,16 +156,6 @@ static int eusb2_repeater_init(struct phy *phy)
>>>
>>> regmap_field_update_bits(rptr->regs[F_EN_CTL1], EUSB2_RPTR_EN, EUSB2_RPTR_EN);
>>>
>>> - for (i = 0; i < F_NUM_TUNE_FIELDS; i++) {
>>> - if (init_tbl[i]) {
>>> - regmap_field_update_bits(rptr->regs[i], init_tbl[i], init_tbl[i]);
>>> - } else {
>>> - /* Write 0 if there's no value set */
>>> - u32 mask = GENMASK(regfields[i].msb, regfields[i].lsb);
>>> -
>>> - regmap_field_update_bits(rptr->regs[i], mask, 0);
>>> - }
>>> - }
>>> memcpy(init_tbl, rptr->cfg->init_tbl, sizeof(init_tbl));
>>
>> I think this patchset can be made even better, this memcpy is also
>> useless and we can simply initialize init_tbl=rptr->cfg->init_tbl.
>
> Actually no. The init_tbl in cfg is a pointer to const. Plus, if you do
> that, you will end up with the same situation like in the other patch,
> as there are some overrides based on DT values below this.
Hm, you're right. Maybe we should simple store *base and stop
modifying these tables then. There's not a whole lot of regmap_rw
calls, so making the first argument "rptr->base + rptr->regs[ASDF]"
shouldn't add much fluff. Then we can make the cfg referernce const.
Konrad
>
> But now that I've had another look, maybe doing the exact same thing as
> the other patch does (kmemdup) will probably look better anyway,
> specially if we do that on probe.
>
>>
>> Konrad
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* [PATCH] phy: renesas: rcar-gen3-usb2: Fix returning wrong error code
From: Yoshihiro Shimoda @ 2024-01-05 9:37 UTC (permalink / raw)
To: vkoul, kishon
Cc: error27, linux-phy, linux-renesas-soc, Yoshihiro Shimoda,
kernel test robot
Even if device_create_file() returns error code,
rcar_gen3_phy_usb2_probe() will return zero because the "ret" is
variable shadowing.
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <error27@gmail.com>
Closes: https://lore.kernel.org/r/202312161021.gOLDl48K-lkp@intel.com/
Fixes: 441a681b8843 ("phy: rcar-gen3-usb2: fix implementation for runtime PM")
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
---
drivers/phy/renesas/phy-rcar-gen3-usb2.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb2.c b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
index e53eace7c91e..6387c0d34c55 100644
--- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c
+++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
@@ -673,8 +673,6 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
channel->irq = platform_get_irq_optional(pdev, 0);
channel->dr_mode = rcar_gen3_get_dr_mode(dev->of_node);
if (channel->dr_mode != USB_DR_MODE_UNKNOWN) {
- int ret;
-
channel->is_otg_channel = true;
channel->uses_otg_pins = !of_property_read_bool(dev->of_node,
"renesas,no-otg-pins");
@@ -738,8 +736,6 @@ static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
ret = PTR_ERR(provider);
goto error;
} else if (channel->is_otg_channel) {
- int ret;
-
ret = device_create_file(dev, &dev_attr_role);
if (ret < 0)
goto error;
--
2.25.1
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* Re: [PATCH 2/2] phy: qualcomm: eusb2-repeater: Drop the redundant zeroing
From: Abel Vesa @ 2024-01-05 9:16 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Bjorn Andersson, Vinod Koul, Kishon Vijay Abraham I,
linux-arm-msm, linux-phy, linux-kernel
In-Reply-To: <33b32e2b-fa35-448c-8b4c-c5c51a514922@linaro.org>
On 24-01-04 23:50:48, Konrad Dybcio wrote:
> On 4.01.2024 15:52, Abel Vesa wrote:
> > The local init_tlb is already zero initialized, so the entire zeroing loop
> > is useless in this case, since the initial values are copied over anyway,
> > before being written.
> >
> > Fixes: 99a517a582fc ("phy: qualcomm: phy-qcom-eusb2-repeater: Zero out untouched tuning regs")
> > Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> > ---
>
> That's another good spot.. partial struct initialization of
> pm8550b_init_tbl zeroes out the uninitialized fields.
>
>
> > drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c | 10 ----------
> > 1 file changed, 10 deletions(-)
> >
> > diff --git a/drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c b/drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c
> > index 5f5862a68b73..3060c0749797 100644
> > --- a/drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c
> > +++ b/drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c
> > @@ -156,16 +156,6 @@ static int eusb2_repeater_init(struct phy *phy)
> >
> > regmap_field_update_bits(rptr->regs[F_EN_CTL1], EUSB2_RPTR_EN, EUSB2_RPTR_EN);
> >
> > - for (i = 0; i < F_NUM_TUNE_FIELDS; i++) {
> > - if (init_tbl[i]) {
> > - regmap_field_update_bits(rptr->regs[i], init_tbl[i], init_tbl[i]);
> > - } else {
> > - /* Write 0 if there's no value set */
> > - u32 mask = GENMASK(regfields[i].msb, regfields[i].lsb);
> > -
> > - regmap_field_update_bits(rptr->regs[i], mask, 0);
> > - }
> > - }
> > memcpy(init_tbl, rptr->cfg->init_tbl, sizeof(init_tbl));
>
> I think this patchset can be made even better, this memcpy is also
> useless and we can simply initialize init_tbl=rptr->cfg->init_tbl.
Actually no. The init_tbl in cfg is a pointer to const. Plus, if you do
that, you will end up with the same situation like in the other patch,
as there are some overrides based on DT values below this.
But now that I've had another look, maybe doing the exact same thing as
the other patch does (kmemdup) will probably look better anyway,
specially if we do that on probe.
>
> Konrad
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* Re: [PATCH v8 03/13] dt-bindings: bus: document RIFSC
From: Gatien CHEVALLIER @ 2024-01-05 8:19 UTC (permalink / raw)
To: Rob Herring
Cc: Oleksii_Moisieiev, gregkh, herbert, davem, krzysztof.kozlowski+dt,
conor+dt, alexandre.torgue, vkoul, jic23, olivier.moysan,
arnaud.pouliquen, mchehab, fabrice.gasnier, andi.shyti,
ulf.hansson, edumazet, kuba, pabeni, hugues.fruchet, lee, will,
catalin.marinas, arnd, richardcochran, Frank Rowand, peng.fan,
lars, rcsekar, wg, mkl, linux-crypto, devicetree, linux-stm32,
linux-arm-kernel, linux-kernel, dmaengine, linux-i2c, linux-iio,
alsa-devel, linux-medi.a, linux-mmc, netdev, linux-phy,
linux-serial, linux-spi, linux-usb
In-Reply-To: <20231221215316.GA155023-robh@kernel.org>
Hi Rob,
On 12/21/23 22:53, Rob Herring wrote:
> On Tue, Dec 12, 2023 at 04:23:46PM +0100, Gatien Chevallier wrote:
>> Document RIFSC (RIF security controller). RIFSC is a firewall controller
>> composed of different kinds of hardware resources.
>>
>> Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
>> ---
>>
>> Changes in V6:
>> - Renamed access-controller to access-controllers
>> - Removal of access-control-provider property
>> - Removal of access-controller and access-controller-names
>> declaration in the patternProperties field. Add
>> additionalProperties: true in this field.
>>
>> Changes in V5:
>> - Renamed feature-domain* to access-control*
>>
>> Changes in V2:
>> - Corrected errors highlighted by Rob's robot
>> - No longer define the maxItems for the "feature-domains"
>> property
>> - Fix example (node name, status)
>> - Declare "feature-domain-names" as an optional
>> property for child nodes
>> - Fix description of "feature-domains" property
>>
>> .../bindings/bus/st,stm32mp25-rifsc.yaml | 96 +++++++++++++++++++
>> 1 file changed, 96 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml b/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml
>> new file mode 100644
>> index 000000000000..95aa7f04c739
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml
>> @@ -0,0 +1,96 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/bus/st,stm32mp25-rifsc.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: STM32 Resource isolation framework security controller
>> +
>> +maintainers:
>> + - Gatien Chevallier <gatien.chevallier@foss.st.com>
>> +
>> +description: |
>> + Resource isolation framework (RIF) is a comprehensive set of hardware blocks
>> + designed to enforce and manage isolation of STM32 hardware resources like
>> + memory and peripherals.
>> +
>> + The RIFSC (RIF security controller) is composed of three sets of registers,
>> + each managing a specific set of hardware resources:
>> + - RISC registers associated with RISUP logic (resource isolation device unit
>> + for peripherals), assign all non-RIF aware peripherals to zero, one or
>> + any security domains (secure, privilege, compartment).
>> + - RIMC registers: associated with RIMU logic (resource isolation master
>> + unit), assign all non RIF-aware bus master to one security domain by
>> + setting secure, privileged and compartment information on the system bus.
>> + Alternatively, the RISUP logic controlling the device port access to a
>> + peripheral can assign target bus attributes to this peripheral master port
>> + (supported attribute: CID).
>> + - RISC registers associated with RISAL logic (resource isolation device unit
>> + for address space - Lite version), assign address space subregions to one
>> + security domains (secure, privilege, compartment).
>> +
>> +properties:
>> + compatible:
>> + contains:
>> + const: st,stm32mp25-rifsc
>
> This needs to be exact and include 'simple-bus'. You'll need a custom
> 'select' with the above to avoid matching all other 'simple-bus' cases.
>
> With that,
>
> Reviewed-by: Rob Herring <robh@kernel.org>
Thank you for the review,
I'll update this for the next version whilst applying your tag
Gatien
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^ permalink raw reply
* RE: [EXT] Re: [PATCH v11 7/7] phy: freescale: Add HDMI PHY driver for i.MX8MQ
From: Sandor Yu @ 2024-01-05 3:20 UTC (permalink / raw)
To: Alexander Stein, dmitry.baryshkov@linaro.org,
andrzej.hajda@intel.com, neil.armstrong@linaro.org,
Laurent Pinchart, jonas@kwiboo.se, jernej.skrabec@gmail.com,
airlied@gmail.com, daniel@ffwll.ch, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, shawnguo@kernel.org,
s.hauer@pengutronix.de, festevam@gmail.com, vkoul@kernel.org,
dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org
Cc: kernel@pengutronix.de, dl-linux-imx, Oliver Brown,
sam@ravnborg.org
In-Reply-To: <3572518.LM0AJKV5NW@steina-w>
Hi Alexander,
Thanks for your comments,
> -----Original Message-----
> From: Alexander Stein <alexander.stein@ew.tq-group.com>
> Sent: 2023年10月17日 21:17
> To: dmitry.baryshkov@linaro.org; andrzej.hajda@intel.com;
> neil.armstrong@linaro.org; Laurent.pinchart@ideasonboard.com;
> jonas@kwiboo.se; jernej.skrabec@gmail.com; airlied@gmail.com;
> daniel@ffwll.ch; robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org;
> shawnguo@kernel.org; s.hauer@pengutronix.de; festevam@gmail.com;
> vkoul@kernel.org; dri-devel@lists.freedesktop.org;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-kernel@vger.kernel.org; linux-phy@lists.infradead.org; Sandor Yu
> <sandor.yu@nxp.com>
> Cc: kernel@pengutronix.de; dl-linux-imx <linux-imx@nxp.com>; Sandor Yu
> <sandor.yu@nxp.com>; Oliver Brown <oliver.brown@nxp.com>;
> sam@ravnborg.org
> Subject: [EXT] Re: [PATCH v11 7/7] phy: freescale: Add HDMI PHY driver for
> i.MX8MQ
>
> Caution: This is an external email. Please take care when clicking links or
> opening attachments. When in doubt, report the message using the 'Report
> this email' button
>
>
> Hi Sandor,
>
> thanks for the patch.
>
> Am Dienstag, 17. Oktober 2023, 09:04:03 CEST schrieb Sandor Yu:
> > Add Cadence HDP-TX HDMI PHY driver for i.MX8MQ.
> >
> > Cadence HDP-TX PHY could be put in either DP mode or HDMI mode base
> on
> > the configuration chosen.
> > HDMI PHY mode is configurated in the driver.
> >
> > Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
> > Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> > ---
> > v9->v11:
> > *No change.
> >
> > drivers/phy/freescale/Kconfig | 10 +
> > drivers/phy/freescale/Makefile | 1 +
> > drivers/phy/freescale/phy-fsl-imx8mq-hdmi.c | 961
> > ++++++++++++++++++++
> > 3 files changed, 972 insertions(+)
> > create mode 100644 drivers/phy/freescale/phy-fsl-imx8mq-hdmi.c
> >
> > diff --git a/drivers/phy/freescale/Kconfig
> > b/drivers/phy/freescale/Kconfig index c39709fd700ac..14f47b7cc77ab
> > 100644
> > --- a/drivers/phy/freescale/Kconfig
> > +++ b/drivers/phy/freescale/Kconfig
> > @@ -45,6 +45,16 @@ config PHY_FSL_IMX8MQ_DP
> > Enable this to support the Cadence HDPTX DP PHY driver
> > on i.MX8MQ SOC.
> >
> > +config PHY_FSL_IMX8MQ_HDMI
> > + tristate "Freescale i.MX8MQ HDMI PHY support"
> > + depends on OF && HAS_IOMEM
> > + depends on COMMON_CLK
> > + select GENERIC_PHY
> > + select CDNS_MHDP_HELPER
> > + help
> > + Enable this to support the Cadence HDPTX HDMI PHY driver
> > + on i.MX8MQ SOC.
> > +
> > endif
> >
> > config PHY_FSL_LYNX_28G
> > diff --git a/drivers/phy/freescale/Makefile
> > b/drivers/phy/freescale/Makefile index 47e5285209fa8..1380ac31c2ead
> > 100644
> > --- a/drivers/phy/freescale/Makefile
> > +++ b/drivers/phy/freescale/Makefile
> > @@ -1,5 +1,6 @@
> > # SPDX-License-Identifier: GPL-2.0-only
> > obj-$(CONFIG_PHY_FSL_IMX8MQ_DP) +=
> phy-fsl-imx8mq-dp.o
> > +obj-$(CONFIG_PHY_FSL_IMX8MQ_HDMI) += phy-fsl-imx8mq-hdmi.o
> > obj-$(CONFIG_PHY_FSL_IMX8MQ_USB) += phy-fsl-imx8mq-usb.o
> > obj-$(CONFIG_PHY_MIXEL_LVDS_PHY) +=
> phy-fsl-imx8qm-lvds-phy.o
> > obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY) += phy-fsl-imx8-mipi-dphy.o
> > diff --git a/drivers/phy/freescale/phy-fsl-imx8mq-hdmi.c
> > b/drivers/phy/freescale/phy-fsl-imx8mq-hdmi.c new file mode 100644
> > index 0000000000000..9722b5e1803c7
> > --- /dev/null
> > +++ b/drivers/phy/freescale/phy-fsl-imx8mq-hdmi.c
> > @@ -0,0 +1,961 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Cadence High-Definition Multimedia Interface (HDMI) PHY driver
> > + *
> > + * Copyright (C) 2022,2023 NXP Semiconductor, Inc.
> > + */
> > +#include <asm/unaligned.h>
> > +#include <drm/bridge/cdns-mhdp-helper.h> #include <linux/clk.h>
> > +#include <linux/kernel.h> #include <linux/phy/phy.h> #include
> > +<linux/platform_device.h> #include <linux/io.h>
> > +
> > +#define ADDR_PHY_AFE 0x80000
> > +
> > +/* PHY registers */
> > +#define CMN_SSM_BIAS_TMR 0x0022
> > +#define CMN_PLLSM0_USER_DEF_CTRL 0x002f
> > +#define CMN_PSM_CLK_CTRL 0x0061
> > +#define CMN_CDIAG_REFCLK_CTRL 0x0062
> > +#define CMN_PLL0_VCOCAL_START 0x0081
> > +#define CMN_PLL0_VCOCAL_INIT_TMR 0x0084
> > +#define CMN_PLL0_VCOCAL_ITER_TMR 0x0085
> > +#define CMN_TXPUCAL_CTRL 0x00e0
> > +#define CMN_TXPDCAL_CTRL 0x00f0
> > +#define CMN_TXPU_ADJ_CTRL 0x0108
> > +#define CMN_TXPD_ADJ_CTRL 0x010c
> > +#define CMN_DIAG_PLL0_FBH_OVRD 0x01c0
> > +#define CMN_DIAG_PLL0_FBL_OVRD 0x01c1
> > +#define CMN_DIAG_PLL0_OVRD 0x01c2
> > +#define CMN_DIAG_PLL0_TEST_MODE 0x01c4
> > +#define CMN_DIAG_PLL0_V2I_TUNE 0x01c5
> > +#define CMN_DIAG_PLL0_CP_TUNE 0x01c6
> > +#define CMN_DIAG_PLL0_LF_PROG 0x01c7
> > +#define CMN_DIAG_PLL0_PTATIS_TUNE1 0x01c8
> > +#define CMN_DIAG_PLL0_PTATIS_TUNE2 0x01c9
> > +#define CMN_DIAG_PLL0_INCLK_CTRL 0x01ca
> > +#define CMN_DIAG_PLL0_PXL_DIVH 0x01cb
> > +#define CMN_DIAG_PLL0_PXL_DIVL 0x01cc
> > +#define CMN_DIAG_HSCLK_SEL 0x01e0
> > +#define XCVR_PSM_RCTRL 0x4001
> > +#define TX_TXCC_CAL_SCLR_MULT_0 0x4047
> > +#define TX_TXCC_CPOST_MULT_00_0 0x404c
> > +#define XCVR_DIAG_PLLDRC_CTRL 0x40e0
> > +#define XCVR_DIAG_PLLDRC_CTRL 0x40e0
> > +#define XCVR_DIAG_HSCLK_SEL 0x40e1
> > +#define XCVR_DIAG_BIDI_CTRL 0x40e8
> > +#define TX_PSC_A0 0x4100
> > +#define TX_PSC_A1 0x4101
> > +#define TX_PSC_A2 0x4102
> > +#define TX_PSC_A3 0x4103
> > +#define TX_DIAG_TX_CTRL 0x41e0
> > +#define TX_DIAG_TX_DRV 0x41e1
> > +#define TX_DIAG_BGREF_PREDRV_DELAY 0x41e7
> > +#define TX_DIAG_ACYA_0 0x41ff
> > +#define TX_DIAG_ACYA_1 0x43ff
> > +#define TX_DIAG_ACYA_2 0x45ff
> > +#define TX_DIAG_ACYA_3 0x47ff
> > +#define TX_ANA_CTRL_REG_1 0x5020
> > +#define TX_ANA_CTRL_REG_2 0x5021
> > +#define TX_DIG_CTRL_REG_2 0x5024
> > +#define TXDA_CYA_AUXDA_CYA 0x5025
> > +#define TX_ANA_CTRL_REG_3 0x5026
> > +#define TX_ANA_CTRL_REG_4 0x5027
> > +#define TX_ANA_CTRL_REG_5 0x5029
> > +#define RX_PSC_A0 0x8000
> > +#define RX_PSC_CAL 0x8006
> > +#define PHY_HDP_MODE_CTRL 0xc008
> > +#define PHY_HDP_CLK_CTL 0xc009
> > +#define PHY_ISO_CMN_CTRL 0xc010
> > +#define PHY_PMA_CMN_CTRL1 0xc800
> > +#define PHY_PMA_ISO_CMN_CTRL 0xc810
> > +#define PHY_PMA_ISO_PLL_CTRL1 0xc812
> > +#define PHY_PMA_ISOLATION_CTRL 0xc81f
> > +
> > +/* PHY_HDP_CLK_CTL */
> > +#define PLL_DATA_RATE_CLK_DIV_MASK GENMASK(15, 8)
> > +#define PLL_DATA_RATE_CLK_DIV_HBR 0x24
> > +#define PLL_DATA_RATE_CLK_DIV_HBR2 0x12
> > +#define PLL_CLK_EN_ACK_EN BIT(3)
> > +#define PLL_CLK_EN BIT(2)
> > +#define PLL_READY BIT(1)
> > +#define PLL_EN BIT(0)
> > +
> > +/* PHY_PMA_CMN_CTRL1 */
> > +#define CMA_REF_CLK_DIG_DIV_MASK GENMASK(13, 12)
> > +#define CMA_REF_CLK_SEL_MASK GENMASK(6, 4)
> > +#define CMA_REF_CLK_RCV_EN_MASK BIT(3)
> > +#define CMA_REF_CLK_RCV_EN 1
> > +#define CMN_READY BIT(0)
> > +
> > +/* PHY_PMA_ISO_PLL_CTRL1 */
> > +#define CMN_PLL0_CLK_DATART_DIV_MASK GENMASK(7, 0)
> > +
> > +/* TX_DIAG_TX_DRV */
> > +#define TX_DRIVER_PROG_BOOST_ENABLE BIT(10)
> > +#define TX_DRIVER_PROG_BOOST_LEVEL_MASK
> GENMASK(9, 8)
> > +#define TX_DRIVER_LDO_BG_DEPENDENT_REF_ENABLE BIT(7)
> > +#define TX_DRIVER_LDO_BANDGAP_REF_ENABLE BIT(6)
> > +
> > +/* TX_TXCC_CAL_SCLR_MULT_0 */
> > +#define SCALED_RESISTOR_CALIBRATION_CODE_ADD BIT(8)
> > +#define RESISTOR_CAL_MULT_VAL_32_128 BIT(5)
> > +
> > +/* CMN_CDIAG_REFCLK_CTRL */
> > +#define DIG_REF_CLK_DIV_SCALER_MASK GENMASK(14, 12)
> > +#define REFCLK_TERMINATION_EN_OVERRIDE_EN BIT(7)
> > +#define REFCLK_TERMINATION_EN_OVERRIDE BIT(6)
> > +
> > +/* CMN_DIAG_HSCLK_SEL */
> > +#define HSCLK1_SEL_MASK
> GENMASK(5, 4)
> > +#define HSCLK0_SEL_MASK
> GENMASK(1, 0)
> > +
> > +/* XCVR_DIAG_HSCLK_SEL */
> > +#define HSCLK_SEL_MODE3_MASK GENMASK(13, 12)
> > +#define HSCLK_SEL_MODE3_HSCLK1 1
> > +
> > +/* CMN_PLL0_VCOCAL_START */
> > +#define VCO_CALIB_CODE_START_POINT_VAL_MASK GENMASK(8, 0)
> > +
> > +/* CMN_DIAG_PLL0_FBH_OVRD */
> > +#define PLL_FEEDBACK_DIV_HI_OVERRIDE_EN BIT(15)
> > +
> > +/* CMN_DIAG_PLL0_FBL_OVRD */
> > +#define PLL_FEEDBACK_DIV_LO_OVERRIDE_EN BIT(15)
> > +
> > +/* CMN_DIAG_PLL0_PXL_DIVH */
> > +#define PLL_PCLK_DIV_EN BIT(15)
> > +
> > +/* XCVR_DIAG_PLLDRC_CTRL */
> > +#define DPLL_CLK_SEL_MODE3 BIT(14)
> > +
> > +/* TX_DIAG_TX_CTRL */
> > +#define TX_IF_SUBRATE_MODE3_MASK GENMASK(7, 6)
> > +
> > +/* PHY_HDP_MODE_CTRL */
> > +#define POWER_STATE_A3_ACK BIT(7)
> > +#define POWER_STATE_A2_ACK BIT(6)
> > +#define POWER_STATE_A1_ACK BIT(5)
> > +#define POWER_STATE_A0_ACK BIT(4)
> > +#define POWER_STATE_A3 BIT(3)
> > +#define POWER_STATE_A2 BIT(2)
> > +#define POWER_STATE_A1 BIT(1)
> > +#define POWER_STATE_A0 BIT(0)
> > +
> > +/* PHY_PMA_ISO_CMN_CTRL */
> > +#define CMN_MACRO_PWR_EN_ACK BIT(5)
> > +
> > +#define KEEP_ALIVE 0x18
> > +
> > +#define REF_CLK_27MHZ 27000000
> > +
> > +/* HDMI TX clock control settings */
> > +struct hdptx_hdmi_ctrl {
> > + u32 pixel_clk_freq_min;
> > + u32 pixel_clk_freq_max;
> > + u32 feedback_factor;
> > + u32 data_range_kbps_min;
> > + u32 data_range_kbps_max;
> > + u32 cmnda_pll0_ip_div;
> > + u32 cmn_ref_clk_dig_div;
> > + u32 ref_clk_divider_scaler;
> > + u32 pll_fb_div_total;
> > + u32 cmnda_pll0_fb_div_low;
> > + u32 cmnda_pll0_fb_div_high;
> > + u32 pixel_div_total;
> > + u32 cmnda_pll0_pxdiv_low;
> > + u32 cmnda_pll0_pxdiv_high;
> > + u32 vco_freq_min;
> > + u32 vco_freq_max;
> > + u32 vco_ring_select;
> > + u32 cmnda_hs_clk_0_sel;
> > + u32 cmnda_hs_clk_1_sel;
> > + u32 hsclk_div_at_xcvr;
> > + u32 hsclk_div_tx_sub_rate;
> > + u32 cmnda_pll0_hs_sym_div_sel;
> > + u32 cmnda_pll0_clk_freq_min;
> > + u32 cmnda_pll0_clk_freq_max;
> > +};
> > +
> > +struct cdns_hdptx_hdmi_phy {
> > + struct cdns_mhdp_base base;
> > +
> > + void __iomem *regs; /* DPTX registers base */
> > + struct mutex mbox_mutex; /* mutex to protect mailbox */
> > + struct device *dev;
> > + struct phy *phy;
> > + struct clk *ref_clk, *apb_clk;
> > + u32 ref_clk_rate;
> > + u32 pixel_clk_rate;
> > + enum hdmi_colorspace color_space;
> > + u32 bpc;
> > +};
> > +
> > +/* HDMI TX clock control settings, pixel clock is output */ static
> > +const struct hdptx_hdmi_ctrl pixel_clk_output_ctrl_table[] = {
> > +/*Minclk Maxclk Fdbak DR_min DR_max ip_d dig DS Totl
> */
> > +{ 27000, 27000, 1000, 270000, 270000, 0x03, 0x1, 0x1, 240, 0x0bc,
> > 0x030, 80, 0x026, 0x026, 2160000, 2160000, 0, 2, 2, 2, 4, 0x3,
> > 27000, 27000}, +{ 27000, 27000, 1250, 337500, 337500, 0x03, 0x1,
> > 0x1, 300, 0x0ec, 0x03c, 100, 0x030, 0x030, 2700000, 2700000, 0, 2, 2,
> > 2, 4, 0x3, 33750, 33750}, +{ 27000, 27000, 1500, 405000, 405000,
> > 0x03, 0x1, 0x1, 360, 0x11c, 0x048, 120, 0x03a, 0x03a, 3240000,
> > 3240000, 0, 2, 2, 2, 4, 0x3, 40500, 40500}, +{ 27000, 27000, 2000,
> > 540000, 540000, 0x03, 0x1, 0x1, 240, 0x0bc, 0x030, 80, 0x026, 0x026,
> > 2160000, 2160000, 0, 2, 2, 2, 4, 0x2, 54000, 54000}, +{ 54000,
> > 54000, 1000, 540000, 540000, 0x03, 0x1, 0x1, 480, 0x17c, 0x060, 80,
> > 0x026, 0x026, 4320000, 4320000, 1, 2, 2, 2, 4, 0x3, 54000, 54000},
> > +{ 54000, 54000, 1250, 675000, 675000, 0x04, 0x1, 0x1, 400, 0x13c,
> > 0x050, 50, 0x017, 0x017, 2700000, 2700000, 0, 1, 1, 2, 4, 0x2,
> > 67500, 67500}, +{ 54000, 54000, 1500, 810000, 810000, 0x04, 0x1,
> > 0x1, 480, 0x17c, 0x060, 60, 0x01c, 0x01c, 3240000, 3240000, 0, 2, 2,
> > 2, 2, 0x2, 81000, 81000}, +{ 54000, 54000, 2000, 1080000, 1080000,
> > 0x03, 0x1, 0x1, 240, 0x0bc, 0x030, 40, 0x012, 0x012, 2160000,
> > 2160000, 0, 2, 2, 2, 1, 0x1, 108000, 108000}, +{ 74250, 74250, 1000,
> > 742500, 742500, 0x03, 0x1, 0x1, 660, 0x20c, 0x084, 80, 0x026, 0x026,
> > 5940000, 5940000, 1, 2, 2, 2, 4, 0x3, 74250, 74250}, +{ 74250,
> > 74250, 1250, 928125, 928125, 0x04, 0x1, 0x1, 550, 0x1b4, 0x06e, 50,
> > 0x017, 0x017, 3712500, 3712500, 1, 1, 1, 2, 4, 0x2, 92812, 92812},
> > +{ 74250, 74250, 1500, 1113750, 1113750, 0x04, 0x1, 0x1, 660, 0x20c,
> > 0x084, 60, 0x01c, 0x01c, 4455000, 4455000, 1, 2, 2, 2, 2, 0x2,
> > 111375, 111375}, +{ 74250, 74250, 2000, 1485000, 1485000, 0x03, 0x1,
> > 0x1, 330, 0x104, 0x042, 40, 0x012, 0x012, 2970000, 2970000, 0, 2, 2,
> > 2, 1, 0x1, 148500, 148500}, +{ 99000, 99000, 1000, 990000, 990000,
> > 0x03, 0x1, 0x1, 440, 0x15c, 0x058, 40, 0x012, 0x012, 3960000,
> > 3960000, 1, 2, 2, 2, 2, 0x2, 99000, 99000}, +{ 99000, 99000, 1250,
> > 1237500, 1237500, 0x03, 0x1, 0x1, 275, 0x0d8, 0x037, 25, 0x00b,
> > 0x00a, 2475000, 2475000, 0, 1, 1, 2, 2, 0x1, 123750, 123750}, +{
> > 99000, 99000, 1500, 1485000, 1485000, 0x03, 0x1, 0x1, 330, 0x104,
> > 0x042, 30, 0x00d, 0x00d, 2970000, 2970000, 0, 2, 2, 2, 1, 0x1,
> > 148500, 148500}, +{ 99000, 99000, 2000, 1980000, 1980000, 0x03, 0x1,
> > 0x1, 440, 0x15c, 0x058, 40, 0x012, 0x012, 3960000, 3960000, 1, 2, 2,
> > 2, 1, 0x1, 198000, 198000}, +{148500, 148500, 1000, 1485000, 1485000,
> > 0x03, 0x1, 0x1, 660, 0x20c, 0x084, 40, 0x012, 0x012, 5940000,
> > 5940000, 1, 2, 2, 2, 2, 0x2, 148500, 148500}, +{148500, 148500, 1250,
> > 1856250, 1856250, 0x04, 0x1, 0x1, 550, 0x1b4, 0x06e, 25, 0x00b,
> > 0x00a, 3712500, 3712500, 1, 1, 1, 2, 2, 0x1, 185625, 185625},
> > +{148500, 148500, 1500, 2227500, 2227500, 0x03, 0x1, 0x1, 495, 0x188,
> > 0x063, 30, 0x00d, 0x00d, 4455000, 4455000, 1, 1, 1, 2, 2, 0x1,
> > 222750, 222750}, +{148500, 148500, 2000, 2970000, 2970000, 0x03, 0x1,
> > 0x1, 660, 0x20c, 0x084, 40, 0x012, 0x012, 5940000, 5940000, 1, 2, 2,
> > 2, 1, 0x1, 297000, 297000}, +{198000, 198000, 1000, 1980000, 1980000,
> > 0x03, 0x1, 0x1, 220, 0x0ac, 0x02c, 10, 0x003, 0x003, 1980000,
> > 1980000, 0, 1, 1, 2, 1, 0x0, 198000, 198000}, +{198000, 198000, 1250,
> > 2475000, 2475000, 0x03, 0x1, 0x1, 550, 0x1b4, 0x06e, 25, 0x00b,
> > 0x00a, 4950000, 4950000, 1, 1, 1, 2, 2, 0x1, 247500, 247500},
> > +{198000, 198000, 1500, 2970000, 2970000, 0x03, 0x1, 0x1, 330, 0x104,
> > 0x042, 15, 0x006, 0x005, 2970000, 2970000, 0, 1, 1, 2, 1, 0x0,
> > 297000, 297000}, +{198000, 198000, 2000, 3960000, 3960000, 0x03, 0x1,
> > 0x1, 440, 0x15c, 0x058, 20, 0x008, 0x008, 3960000, 3960000, 1, 1, 1,
> > 2, 1, 0x0, 396000, 396000}, +{297000, 297000, 1000, 2970000, 2970000,
> > 0x03, 0x1, 0x1, 330, 0x104, 0x042, 10, 0x003, 0x003, 2970000,
> > 2970000, 0, 1, 1, 2, 1, 0x0, 297000, 297000}, +{297000, 297000, 1500,
> > 4455000, 4455000, 0x03, 0x1, 0x1, 495, 0x188, 0x063, 15, 0x006,
> > 0x005, 4455000, 4455000, 1, 1, 1, 2, 1, 0x0, 445500, 445500},
> > +{297000, 297000, 2000, 5940000, 5940000, 0x03, 0x1, 0x1, 660, 0x20c,
> > 0x084, 20, 0x008, 0x008, 5940000, 5940000, 1, 1, 1, 2, 1, 0x0,
> > 594000, 594000}, +{594000, 594000, 1000, 5940000, 5940000, 0x03, 0x1,
> > 0x1, 660, 0x20c, 0x084, 10, 0x003, 0x003, 5940000, 5940000, 1, 1, 1,
> > 2, 1, 0x0, 594000, 594000}, +{594000, 594000, 750, 4455000, 4455000,
> > 0x03, 0x1, 0x1, 495, 0x188, 0x063, 10, 0x003, 0x003, 4455000,
> > 4455000, 1, 1, 1, 2, 1, 0x0, 445500, 445500}, +{594000, 594000, 625,
> > 3712500, 3712500, 0x04, 0x1, 0x1, 550, 0x1b4, 0x06e, 10, 0x003,
> > 0x003, 3712500, 3712500, 1, 1, 1, 2, 1, 0x0, 371250, 371250},
> > +{594000, 594000, 500, 2970000, 2970000, 0x03, 0x1, 0x1, 660, 0x20c,
> > 0x084, 10, 0x003, 0x003, 5940000, 5940000, 1, 1, 1, 2, 2, 0x1,
> > 297000, 297000}, +};
> > +
> > +/* HDMI TX PLL tuning settings */
> > +struct hdptx_hdmi_pll_tuning {
> > + u32 vco_freq_bin;
> > + u32 vco_freq_min;
> > + u32 vco_freq_max;
> > + u32 volt_to_current_coarse;
> > + u32 volt_to_current;
> > + u32 ndac_ctrl;
> > + u32 pmos_ctrl;
> > + u32 ptat_ndac_ctrl;
> > + u32 feedback_div_total;
> > + u32 charge_pump_gain;
> > + u32 coarse_code;
> > + u32 v2i_code;
> > + u32 vco_cal_code;
> > +};
> > +
> > +/* HDMI TX PLL tuning settings, pixel clock is output */ static const
> > +struct hdptx_hdmi_pll_tuning pixel_clk_output_pll_table[] = { /*bin
> > +VCO_freq min/max coar cod NDAC PMOS PTAT div-T P-Gain Coa V2I
> CAL
> > */ +{ 1, 1980000, 1980000, 0x4, 0x3, 0x0, 0x09, 0x09, 220, 0x42, 160,
> > 5,
> > 183 }, +{ 2, 2160000, 2160000, 0x4, 0x3, 0x0, 0x09, 0x09, 240, 0x42,
> > 166, 6, 208 }, +{ 3, 2475000, 2475000, 0x5, 0x3, 0x1, 0x00, 0x07,
> > 275, 0x42, 167, 6, 209 }, +{ 4, 2700000, 2700000, 0x5, 0x3, 0x1,
> > 0x00, 0x07, 300, 0x42, 188, 6, 230 }, +{ 4, 2700000, 2700000, 0x5,
> > 0x3, 0x1, 0x00, 0x07, 400, 0x4c, 188, 6, 230 }, +{ 5, 2970000,
> > 2970000, 0x6, 0x3, 0x1, 0x00, 0x07, 330, 0x42, 183, 6, 225 }, +{ 6,
> > 3240000, 3240000, 0x6, 0x3, 0x1, 0x00, 0x07, 360, 0x42, 203, 7, 256 },
> > +{ 6, 3240000, 3240000, 0x6, 0x3, 0x1, 0x00, 0x07, 480, 0x4c, 203, 7,
> > 256 }, +{ 7, 3712500, 3712500, 0x4, 0x3, 0x0, 0x07, 0x0F, 550, 0x4c,
> > 212, 7, 257 }, +{ 8, 3960000, 3960000, 0x5, 0x3, 0x0, 0x07, 0x0F,
> > 440, 0x42, 184, 6, 226 }, +{ 9, 4320000, 4320000, 0x5, 0x3, 0x1,
> > 0x07, 0x0F, 480, 0x42, 205, 7, 258 }, +{ 10, 4455000, 4455000, 0x5,
> > 0x3, 0x0, 0x07, 0x0F, 495, 0x42, 219, 7, 272 }, +{ 10, 4455000,
> > 4455000, 0x5, 0x3, 0x0, 0x07, 0x0F, 660, 0x4c, 219, 7, 272 },
> > +{ 11, 4950000, 4950000, 0x6, 0x3, 0x1, 0x00, 0x07, 550, 0x42, 213, 7,
> > +258
> > }, +{ 12, 5940000, 5940000, 0x7, 0x3, 0x1, 0x00, 0x07, 660, 0x42, 244,
> > 8,
> > 292 }, +};
> > +
> > +static int cdns_phy_reg_write(struct cdns_hdptx_hdmi_phy *cdns_phy,
> > +u32
> > addr, u32 val) +{
> > + return cdns_mhdp_reg_write(&cdns_phy->base, ADDR_PHY_AFE +
> (addr
> > + <<
> 2),
> > val); +}
> > +
> > +static u32 cdns_phy_reg_read(struct cdns_hdptx_hdmi_phy *cdns_phy,
> > +u32
> > addr) +{
> > + u32 reg32;
> > +
> > + cdns_mhdp_reg_read(&cdns_phy->base, ADDR_PHY_AFE + (addr <<
> 2),
> ®32);
> > +
> > + return reg32;
> > +}
> > +
> > +static int wait_for_ack(struct cdns_hdptx_hdmi_phy *cdns_phy, u32
> > +reg, u32
> > mask, + const char *err_msg)
> > +{
> > + u32 val, i;
> > +
> > + for (i = 0; i < 10; i++) {
> > + val = cdns_phy_reg_read(cdns_phy, reg);
> > + if (val & mask)
> > + return 0;
> > + msleep(20);
> > + }
> > +
> > + dev_err(cdns_phy->dev, "%s\n", err_msg);
> > + return -1;
>
> return -ETIMEDOUT?
OK.
>
> > +}
> > +
> > +static bool hdptx_phy_check_alive(struct cdns_hdptx_hdmi_phy
> > +*cdns_phy) {
> > + u32 alive, newalive;
> > + u8 retries_left = 50;
> > +
> > + alive = readl(cdns_phy->regs + KEEP_ALIVE);
> > +
> > + while (retries_left--) {
> > + udelay(2);
> > +
> > + newalive = readl(cdns_phy->regs + KEEP_ALIVE);
> > + if (alive == newalive)
> > + continue;
> > + return true;
> > + }
> > + return false;
> > +}
> > +
> > +static int hdptx_hdmi_clk_enable(struct cdns_hdptx_hdmi_phy
> > +*cdns_phy) {
> > + struct device *dev = cdns_phy->dev;
> > + u32 ref_clk_rate;
> > + int ret;
> > +
> > + cdns_phy->ref_clk = devm_clk_get(dev, "ref");
> > + if (IS_ERR(cdns_phy->ref_clk)) {
> > + dev_err(dev, "phy ref clock not found\n");
> > + return PTR_ERR(cdns_phy->ref_clk);
> > + }
> > +
> > + cdns_phy->apb_clk = devm_clk_get(dev, "apb");
> > + if (IS_ERR(cdns_phy->apb_clk)) {
> > + dev_err(dev, "phy apb clock not found\n");
> > + return PTR_ERR(cdns_phy->apb_clk);
> > + }
> > +
> > + ret = clk_prepare_enable(cdns_phy->ref_clk);
> > + if (ret) {
> > + dev_err(cdns_phy->dev, "Failed to prepare ref clock\n");
> > + return ret;
> > + }
> > +
> > + ref_clk_rate = clk_get_rate(cdns_phy->ref_clk);
> > + if (!ref_clk_rate) {
> > + dev_err(cdns_phy->dev, "Failed to get ref clock rate\n");
> > + goto err_ref_clk;
> > + }
> > +
> > + if (ref_clk_rate == REF_CLK_27MHZ) {
> > + cdns_phy->ref_clk_rate = ref_clk_rate;
> > + } else {
> > + dev_err(cdns_phy->dev, "Not support Ref Clock
> Rate(%dHz)
> \n",
> > ref_clk_rate); + goto err_ref_clk;
> > + }
> > +
> > + ret = clk_prepare_enable(cdns_phy->apb_clk);
> > + if (ret) {
> > + dev_err(cdns_phy->dev, "Failed to prepare apb clock\n");
> > + goto err_ref_clk;
> > + }
> > +
> > + return 0;
> > +
> > +err_ref_clk:
> > + clk_disable_unprepare(cdns_phy->ref_clk);
> > + return -EINVAL;
> > +}
> > +
> > +static void hdptx_hdmi_clk_disable(struct cdns_hdptx_hdmi_phy
> > +*cdns_phy) {
> > + clk_disable_unprepare(cdns_phy->ref_clk);
> > + clk_disable_unprepare(cdns_phy->apb_clk);
>
> Shouldn't the clocks be disabled in reverse order to enabling path?
OK, I will change it.
>
> > +}
> > +
> > +static void hdptx_hdmi_arc_config(struct cdns_hdptx_hdmi_phy
> > +*cdns_phy) {
> > + u16 txpu_calib_code;
> > + u16 txpd_calib_code;
> > + u16 txpu_adj_calib_code;
> > + u16 txpd_adj_calib_code;
> > + u16 prev_calib_code;
> > + u16 new_calib_code;
> > + u16 rdata;
> > +
> > + /* Power ARC */
> > + cdns_phy_reg_write(cdns_phy, TXDA_CYA_AUXDA_CYA, 0x0001);
> > +
> > + prev_calib_code = cdns_phy_reg_read(cdns_phy,
> TX_DIG_CTRL_REG_2);
> > + txpu_calib_code = cdns_phy_reg_read(cdns_phy,
> CMN_TXPUCAL_CTRL);
> > + txpd_calib_code = cdns_phy_reg_read(cdns_phy,
> CMN_TXPDCAL_CTRL);
> > + txpu_adj_calib_code = cdns_phy_reg_read(cdns_phy,
> CMN_TXPU_ADJ_CTRL);
> > + txpd_adj_calib_code = cdns_phy_reg_read(cdns_phy,
> CMN_TXPD_ADJ_CTRL);
> > +
> > + new_calib_code = ((txpu_calib_code + txpd_calib_code) / 2)
> > + + txpu_adj_calib_code + txpd_adj_calib_code;
> > +
> > + if (new_calib_code != prev_calib_code) {
> > + rdata = cdns_phy_reg_read(cdns_phy,
> TX_ANA_CTRL_REG_1);
> > + rdata &= 0xdfff;
> > + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1,
> rdata);
> > + cdns_phy_reg_write(cdns_phy, TX_DIG_CTRL_REG_2,
> new_calib_code);
> > + mdelay(10);
> > + rdata |= 0x2000;
> > + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1,
> rdata);
> > + usleep_range(150, 250);
> > + }
> > +
> > + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x0100);
> > + usleep_range(100, 200);
> > + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x0300);
> > + usleep_range(100, 200);
> > + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_3, 0x0000);
> > + usleep_range(100, 200);
> > + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, 0x2008);
> > + usleep_range(100, 200);
> > + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, 0x2018);
> > + usleep_range(100, 200);
> > + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, 0x2098);
> > + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x030c);
> > + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_5, 0x0010);
> > + usleep_range(100, 200);
> > + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_4, 0x4001);
> > + mdelay(5);
> > + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, 0x2198);
> > + mdelay(5);
> > + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x030d);
> > + usleep_range(100, 200);
> > + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x030f); }
> > +
> > +static void hdptx_hdmi_phy_set_vswing(struct cdns_hdptx_hdmi_phy
> > +*cdns_phy) {
> > + u32 k;
> > + const u32 num_lanes = 4;
> > +
> > + for (k = 0; k < num_lanes; k++) {
> > + cdns_phy_reg_write(cdns_phy, (TX_DIAG_TX_DRV | (k <<
> 9)),
> > +
> TX_DRIVER_PROG_BOOST_ENABLE |
> > +
> FIELD_PREP(TX_DRIVER_PROG_BOOST_LEVEL_MASK, 3) |
> > +
> TX_DRIVER_LDO_BG_DEPENDENT_REF_ENABLE |
> > +
> TX_DRIVER_LDO_BANDGAP_REF_ENABLE);
> > + cdns_phy_reg_write(cdns_phy,
> (TX_TXCC_CPOST_MULT_00_0 |
> > + (k
> << 9)), 0x0);
> > + cdns_phy_reg_write(cdns_phy,
> (TX_TXCC_CAL_SCLR_MULT_0 |
> > + (k
> << 9)),
> > +
> SCALED_RESISTOR_CALIBRATION_CODE_ADD |
> > +
> RESISTOR_CAL_MULT_VAL_32_128);
> > + }
> > +}
> > +
> > +static int hdptx_hdmi_feedback_factor(struct cdns_hdptx_hdmi_phy
> > +*cdns_phy) {
> > + u32 feedback_factor;
> > +
> > + switch (cdns_phy->color_space) {
> > + case HDMI_COLORSPACE_YUV422:
> > + feedback_factor = 1000;
> > + break;
> > +
> > + case HDMI_COLORSPACE_YUV420:
> > + switch (cdns_phy->bpc) {
> > + case 8:
> > + feedback_factor = 500;
> > + break;
> > + case 10:
> > + feedback_factor = 625;
> > + break;
> > + case 12:
> > + feedback_factor = 750;
> > + break;
> > + case 16:
> > + feedback_factor = 1000;
> > + break;
> > + default:
> > + dev_dbg(cdns_phy->dev, "Invalid
> ColorDepth\n");
> > + return 0;
> > + }
> > + break;
> > +
> > + default:
> > + /* Assume RGB/YUV444 */
> > + switch (cdns_phy->bpc) {
> > + case 10:
> > + feedback_factor = 1250;
> > + break;
> > + case 12:
> > + feedback_factor = 1500;
> > + break;
> > + case 16:
> > + feedback_factor = 2000;
> > + break;
> > + default:
> > + feedback_factor = 1000;
> > + }
> > + }
> > +
> > + return feedback_factor;
> > +}
> > +
> > +static int hdptx_hdmi_phy_config(struct cdns_hdptx_hdmi_phy *cdns_phy,
> > + const struct hdptx_hdmi_ctrl
> *p_ctrl_table,
> > + const struct hdptx_hdmi_pll_tuning
> *p_pll_table,
> > + char pclk_in)
>
> bool pclk_in
OK.
>
> > +{
> > + const u32 num_lanes = 4;
> > + u32 val, k;
> > +
> > + /* enable PHY isolation mode only for CMN */
> > + cdns_phy_reg_write(cdns_phy, PHY_PMA_ISOLATION_CTRL,
> 0xd000);
> > +
> > + /* set cmn_pll0_clk_datart1_div/cmn_pll0_clk_datart0_div dividers
> */
> > + val = cdns_phy_reg_read(cdns_phy, PHY_PMA_ISO_PLL_CTRL1);
> > + val &= ~CMN_PLL0_CLK_DATART_DIV_MASK;
> > + val |= FIELD_PREP(CMN_PLL0_CLK_DATART_DIV_MASK, 0x12);
> > + cdns_phy_reg_write(cdns_phy, PHY_PMA_ISO_PLL_CTRL1, val);
> > +
> > + /* assert PHY reset from isolation register */
> > + cdns_phy_reg_write(cdns_phy, PHY_ISO_CMN_CTRL, 0x0000);
> > + /* assert PMA CMN reset */
> > + cdns_phy_reg_write(cdns_phy, PHY_PMA_ISO_CMN_CTRL,
> 0x0000);
> > +
> > + /* register XCVR_DIAG_BIDI_CTRL */
> > + for (k = 0; k < num_lanes; k++)
> > + cdns_phy_reg_write(cdns_phy, XCVR_DIAG_BIDI_CTRL |
> (k <<
> 9), 0x00ff);
> > +
> > + /* Describing Task phy_cfg_hdp */
> > + val = cdns_phy_reg_read(cdns_phy, PHY_PMA_CMN_CTRL1);
> > + val &= ~CMA_REF_CLK_RCV_EN_MASK;
> > + val |= FIELD_PREP(CMA_REF_CLK_RCV_EN_MASK,
> CMA_REF_CLK_RCV_EN);
> > + cdns_phy_reg_write(cdns_phy, PHY_PMA_CMN_CTRL1, val);
> > +
> > + /* PHY Registers */
> > + val = cdns_phy_reg_read(cdns_phy, PHY_PMA_CMN_CTRL1);
> > + val &= ~CMA_REF_CLK_DIG_DIV_MASK;
> > + val |= FIELD_PREP(CMA_REF_CLK_DIG_DIV_MASK,
> > p_ctrl_table->cmn_ref_clk_dig_div); + cdns_phy_reg_write(cdns_phy,
> > PHY_PMA_CMN_CTRL1, val);
> > +
> > + val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
> > + val &= ~PLL_DATA_RATE_CLK_DIV_MASK;
> > + val |= FIELD_PREP(PLL_DATA_RATE_CLK_DIV_MASK,
> > + PLL_DATA_RATE_CLK_DIV_HBR2);
> > + cdns_phy_reg_write(cdns_phy, PHY_HDP_CLK_CTL, val);
> > +
> > + /* Common control module control and diagnostic registers */
> > + val = cdns_phy_reg_read(cdns_phy, CMN_CDIAG_REFCLK_CTRL);
> > + val &= ~DIG_REF_CLK_DIV_SCALER_MASK;
> > + val |= FIELD_PREP(DIG_REF_CLK_DIV_SCALER_MASK,
> > p_ctrl_table->ref_clk_divider_scaler); + val |=
> > REFCLK_TERMINATION_EN_OVERRIDE_EN |
> REFCLK_TERMINATION_EN_OVERRIDE;
> > + cdns_phy_reg_write(cdns_phy, CMN_CDIAG_REFCLK_CTRL, val);
> > +
> > + /* High speed clock used */
> > + val = cdns_phy_reg_read(cdns_phy, CMN_DIAG_HSCLK_SEL);
> > + val &= ~(HSCLK1_SEL_MASK | HSCLK0_SEL_MASK);
> > + val |= FIELD_PREP(HSCLK1_SEL_MASK,
> > + (p_ctrl_table->cmnda_hs_clk_1_sel
> >>
> > 1)); + val |= FIELD_PREP(HSCLK0_SEL_MASK,
> (p_ctrl_table->cmnda_hs_clk_0_sel
> > >> 1)); + cdns_phy_reg_write(cdns_phy, CMN_DIAG_HSCLK_SEL, val);
> > +
> > + for (k = 0; k < num_lanes; k++) {
> > + val = cdns_phy_reg_read(cdns_phy,
> (XCVR_DIAG_HSCLK_SEL |
> (k << 9)));
> > + val &= ~HSCLK_SEL_MODE3_MASK;
> > + val |= FIELD_PREP(HSCLK_SEL_MODE3_MASK,
> > +
> (p_ctrl_table->cmnda_hs_clk_0_sel >>
> 1));
> > + cdns_phy_reg_write(cdns_phy, (XCVR_DIAG_HSCLK_SEL |
> (k
> > + <<
> 9)), val);
> > + }
> > +
> > + /* PLL 0 control state machine registers */
> > + val = p_ctrl_table->vco_ring_select << 12;
> > + cdns_phy_reg_write(cdns_phy, CMN_PLLSM0_USER_DEF_CTRL,
> val);
> > +
> > + if (pclk_in) {
> > + val = 0x30a0;
> > + } else {
> > + val = cdns_phy_reg_read(cdns_phy,
> CMN_PLL0_VCOCAL_START);
> > + val &= ~VCO_CALIB_CODE_START_POINT_VAL_MASK;
> > + val |=
> FIELD_PREP(VCO_CALIB_CODE_START_POINT_VAL_MASK,
> > + p_pll_table->vco_cal_code);
> > + }
> > + cdns_phy_reg_write(cdns_phy, CMN_PLL0_VCOCAL_START, val);
> > +
> > + cdns_phy_reg_write(cdns_phy, CMN_PLL0_VCOCAL_INIT_TMR,
> 0x0064);
> > + cdns_phy_reg_write(cdns_phy, CMN_PLL0_VCOCAL_ITER_TMR,
> 0x000a);
> > +
> > + /* Common functions control and diagnostics registers */
> > + val = p_ctrl_table->cmnda_pll0_hs_sym_div_sel << 8;
> > + val |= p_ctrl_table->cmnda_pll0_ip_div;
> > + cdns_phy_reg_write(cdns_phy, CMN_DIAG_PLL0_INCLK_CTRL, val);
> > +
> > + cdns_phy_reg_write(cdns_phy, CMN_DIAG_PLL0_OVRD, 0x0000);
> > +
> > + val = p_ctrl_table->cmnda_pll0_fb_div_high;
> > + val |= PLL_FEEDBACK_DIV_HI_OVERRIDE_EN;
> > + cdns_phy_reg_write(cdns_phy, CMN_DIAG_PLL0_FBH_OVRD, val);
> > +
> > + val = p_ctrl_table->cmnda_pll0_fb_div_low;
> > + val |= PLL_FEEDBACK_DIV_LO_OVERRIDE_EN;
> > + cdns_phy_reg_write(cdns_phy, CMN_DIAG_PLL0_FBL_OVRD, val);
> > +
> > + if (!pclk_in) {
> > + val = p_ctrl_table->cmnda_pll0_pxdiv_low;
> > + cdns_phy_reg_write(cdns_phy,
> CMN_DIAG_PLL0_PXL_DIVL,
> > + val);
> > +
> > + val = p_ctrl_table->cmnda_pll0_pxdiv_high;
> > + val |= PLL_PCLK_DIV_EN;
> > + cdns_phy_reg_write(cdns_phy,
> CMN_DIAG_PLL0_PXL_DIVH, val);
> > + }
> > +
> > + val = p_pll_table->volt_to_current_coarse;
> > + val |= (p_pll_table->volt_to_current) << 4;
> > + cdns_phy_reg_write(cdns_phy, CMN_DIAG_PLL0_V2I_TUNE, val);
> > +
> > + val = p_pll_table->charge_pump_gain;
> > + cdns_phy_reg_write(cdns_phy, CMN_DIAG_PLL0_CP_TUNE, val);
> > +
> > + cdns_phy_reg_write(cdns_phy, CMN_DIAG_PLL0_LF_PROG,
> 0x0008);
> > +
> > + val = p_pll_table->pmos_ctrl;
> > + val |= (p_pll_table->ndac_ctrl) << 8;
> > + cdns_phy_reg_write(cdns_phy, CMN_DIAG_PLL0_PTATIS_TUNE1,
> val);
> > +
> > + val = p_pll_table->ptat_ndac_ctrl;
> > + cdns_phy_reg_write(cdns_phy, CMN_DIAG_PLL0_PTATIS_TUNE2,
> val);
> > +
> > + if (pclk_in)
> > + cdns_phy_reg_write(cdns_phy,
> CMN_DIAG_PLL0_TEST_MODE,
> 0x0022);
> > + else
> > + cdns_phy_reg_write(cdns_phy,
> CMN_DIAG_PLL0_TEST_MODE,
> 0x0020);
> > +
> > + cdns_phy_reg_write(cdns_phy, CMN_PSM_CLK_CTRL, 0x0016);
> > +
> > + /* Transceiver control and diagnostic registers */
> > + for (k = 0; k < num_lanes; k++) {
> > + val = cdns_phy_reg_read(cdns_phy,
> (XCVR_DIAG_PLLDRC_CTRL
> > + |
> (k << 9)));
> > + val &= ~DPLL_CLK_SEL_MODE3;
> > + cdns_phy_reg_write(cdns_phy,
> (XCVR_DIAG_PLLDRC_CTRL | (k
> << 9)), val);
> > + }
> > +
> > + for (k = 0; k < num_lanes; k++) {
> > + val = cdns_phy_reg_read(cdns_phy, (TX_DIAG_TX_CTRL |
> (k
> > + <<
> 9)));
> > + val &= ~TX_IF_SUBRATE_MODE3_MASK;
> > + val |= FIELD_PREP(TX_IF_SUBRATE_MODE3_MASK,
> > +
> (p_ctrl_table->hsclk_div_tx_sub_rate
> >> 1));
> > + cdns_phy_reg_write(cdns_phy, (TX_DIAG_TX_CTRL | (k <<
> > + 9)),
> val);
> > + }
> > +
> > + val = cdns_phy_reg_read(cdns_phy, PHY_PMA_CMN_CTRL1);
> > + val &= ~CMA_REF_CLK_SEL_MASK;
> > + /*
> > + * single ended reference clock (val |= 0x0030);
> > + * differential clock (val |= 0x0000);
> > + * for differential clock on the refclk_p and
> > + * refclk_m off chip pins: CMN_DIAG_ACYA[8]=1'b1
> > + * cdns_phy_reg_write(cdns_phy, CMN_DIAG_ACYA, 0x0100);
> > + */
> > + val |= FIELD_PREP(CMA_REF_CLK_SEL_MASK, 3);
> > + cdns_phy_reg_write(cdns_phy, PHY_PMA_CMN_CTRL1, val);
> > +
> > + /* Deassert PHY reset */
> > + cdns_phy_reg_write(cdns_phy, PHY_ISO_CMN_CTRL, 0x0001);
> > + cdns_phy_reg_write(cdns_phy, PHY_PMA_ISO_CMN_CTRL,
> 0x0003);
> > +
> > + /* Power state machine registers */
> > + for (k = 0; k < num_lanes; k++)
> > + cdns_phy_reg_write(cdns_phy, XCVR_PSM_RCTRL | (k <<
> 9),
> 0xfefc);
> > +
> > + /* Assert cmn_macro_pwr_en */
> > + cdns_phy_reg_write(cdns_phy, PHY_PMA_ISO_CMN_CTRL,
> 0x0013);
> > +
> > + /* wait for cmn_macro_pwr_en_ack */
> > + if (wait_for_ack(cdns_phy, PHY_PMA_ISO_CMN_CTRL,
> CMN_MACRO_PWR_EN_ACK,
> > + "MA output macro power up failed"))
> > + return -1;
>
> Return the error value of wait_for_ack.
OK.
>
> > + /* wait for cmn_ready */
> > + if (wait_for_ack(cdns_phy, PHY_PMA_CMN_CTRL1, CMN_READY,
> > + "PMA output ready failed"))
> > + return -1;
>
> Return the error value of wait_for_ack.
OK.
>
> > + for (k = 0; k < num_lanes; k++) {
> > + cdns_phy_reg_write(cdns_phy, TX_PSC_A0 | (k << 9),
> 0x6791);
> > + cdns_phy_reg_write(cdns_phy, TX_PSC_A1 | (k << 9),
> 0x6790);
> > + cdns_phy_reg_write(cdns_phy, TX_PSC_A2 | (k << 9),
> 0x0090);
> > + cdns_phy_reg_write(cdns_phy, TX_PSC_A3 | (k << 9),
> 0x0090);
> > +
> > + val = cdns_phy_reg_read(cdns_phy, RX_PSC_CAL | (k <<
> 9));
> > + val &= 0xffbb;
> > + cdns_phy_reg_write(cdns_phy, RX_PSC_CAL | (k << 9),
> > + val);
> > +
> > + val = cdns_phy_reg_read(cdns_phy, RX_PSC_A0 | (k << 9));
> > + val &= 0xffbb;
> > + cdns_phy_reg_write(cdns_phy, RX_PSC_A0 | (k << 9), val);
> > + }
> > + return 0;
> > +}
> > +
> > +static int hdptx_hdmi_phy_cfg(struct cdns_hdptx_hdmi_phy *cdns_phy,
> > +u32
> > rate) +{
> > + const struct hdptx_hdmi_ctrl *p_ctrl_table;
> > + const struct hdptx_hdmi_pll_tuning *p_pll_table;
> > + const u32 refclk_freq_khz = cdns_phy->ref_clk_rate / 1000;
> > + const u8 pclk_in = false;
>
> const bool pclk_in = false;
OK.
>
> > + u32 pixel_freq = rate;
> > + u32 vco_freq, char_freq;
> > + u32 div_total, feedback_factor;
> > + u32 i, ret;
> > +
> > + feedback_factor = hdptx_hdmi_feedback_factor(cdns_phy);
> > +
> > + char_freq = pixel_freq * feedback_factor / 1000;
> > +
> > + dev_dbg(cdns_phy->dev,
> > + "Pixel clock: (%d KHz), character clock: %d, bpc is
> > + (%0d-
> bit)\n",
> > + pixel_freq, char_freq, cdns_phy->bpc);
> > +
> > + /* Get right row from the ctrl_table table.
> > + * Check if 'pixel_freq_khz' value matches the PIXEL_CLK_FREQ
> column.
> > + * Consider only the rows with FEEDBACK_FACTOR column matching
> > feedback_factor. + */
> > + for (i = 0; i < ARRAY_SIZE(pixel_clk_output_ctrl_table); i++) {
> > + if (feedback_factor ==
> pixel_clk_output_ctrl_table[i].feedback_factor &&
> > + pixel_freq ==
> pixel_clk_output_ctrl_table[i].pixel_clk_freq_min) {
> > + p_ctrl_table = &pixel_clk_output_ctrl_table[i];
> > + break;
> > + }
> > + }
> > + if (i == ARRAY_SIZE(pixel_clk_output_ctrl_table)) {
> > + dev_warn(cdns_phy->dev,
> > + "Pixel clk (%d KHz) not supported, bpc is (%0d-
> bit)\n",
> > + pixel_freq, cdns_phy->bpc);
> > + return 0;
>
> Returning 0 doesn't seem correct. The caller checks for small than 0. I suggest
> returning 0 if configuration was successful, and some error code otherwise.
OK, it should be change to return error code.
>
> > + }
> > +
> > + div_total = p_ctrl_table->pll_fb_div_total;
> > + vco_freq = refclk_freq_khz * div_total / p_ctrl_table-
> >cmnda_pll0_ip_div;
> > +
> > + /* Get right row from the pixel_clk_output_pll_table table.
> > + * Check if vco_freq_khz and feedback_div_total
> > + * column matching with pixel_clk_output_pll_table.
> > + */
> > + for (i = 0; i < ARRAY_SIZE(pixel_clk_output_pll_table); i++) {
> > + if (vco_freq ==
> > + pixel_clk_output_pll_table[i].vco_freq_min
> &&
> > + div_total ==
> pixel_clk_output_pll_table[i].feedback_div_total) {
> > + p_pll_table = &pixel_clk_output_pll_table[i];
> > + break;
> > + }
> > + }
> > + if (i == ARRAY_SIZE(pixel_clk_output_pll_table)) {
> > + dev_warn(cdns_phy->dev, "VCO (%d KHz) not
> supported\n",
> vco_freq);
> > + return -1;
>
> return -EINVAL?
OK.
>
> > + }
> > + dev_dbg(cdns_phy->dev, "VCO frequency is (%d KHz)\n", vco_freq);
> > +
> > + ret = hdptx_hdmi_phy_config(cdns_phy, p_ctrl_table, p_pll_table,
> pclk_in);
> > + if (ret < 0)
> > + return ret;
> > +
> > + return char_freq;
>
> See above. There is no need to return the character clock here.
OK.
>
> > +}
> > +
> > +static int hdptx_hdmi_phy_power_up(struct cdns_hdptx_hdmi_phy
> > +*cdns_phy) {
> > + /* set Power State to A2 */
> > + cdns_phy_reg_write(cdns_phy, PHY_HDP_MODE_CTRL,
> POWER_STATE_A2);
> > +
> > + cdns_phy_reg_write(cdns_phy, TX_DIAG_ACYA_0, 1);
> > + cdns_phy_reg_write(cdns_phy, TX_DIAG_ACYA_1, 1);
> > + cdns_phy_reg_write(cdns_phy, TX_DIAG_ACYA_2, 1);
> > + cdns_phy_reg_write(cdns_phy, TX_DIAG_ACYA_3, 1);
> > +
> > + if (wait_for_ack(cdns_phy, PHY_HDP_MODE_CTRL,
> POWER_STATE_A2_ACK,
> > + "Wait A2 Ack failed"))
> > + return -1;
>
> Return the error value of wait_for_ack.
OK.
>
> > +
> > + /* Power up ARC */
> > + hdptx_hdmi_arc_config(cdns_phy);
> > +
> > + /* Configure PHY in A0 mode (PHY must be in the A0 power
> > + * state in order to transmit data)
> > + */
> > + cdns_phy_reg_write(cdns_phy, PHY_HDP_MODE_CTRL,
> POWER_STATE_A0);
> > + if (wait_for_ack(cdns_phy, PHY_HDP_MODE_CTRL,
> POWER_STATE_A0_ACK,
> > + "Wait A0 Ack failed"))
> > + return -1;
>
> Return the error value of wait_for_ack.
OK.
>
> > +
> > + return 0;
> > +}
> > +
> > +static int hdptx_hdmi_phy_power_down(struct cdns_hdptx_hdmi_phy
> > +*cdns_phy) {
> > + u32 val;
> > +
> > + val = cdns_phy_reg_read(cdns_phy, PHY_HDP_MODE_CTRL);
> > + val &= ~(POWER_STATE_A0 | POWER_STATE_A1 |
> POWER_STATE_A2 |
> > POWER_STATE_A3); + /* PHY_DP_MODE_CTL set to A3 power state */
> > + cdns_phy_reg_write(cdns_phy, PHY_HDP_MODE_CTRL, val |
> POWER_STATE_A3);
> > +
> > + if (wait_for_ack(cdns_phy, PHY_HDP_MODE_CTRL,
> POWER_STATE_A3_ACK,
> > + "Wait A3 Ack failed"))
> > + return -1;
>
> Return the error value of wait_for_ack.
OK.
>
> > +
> > + return 0;
> > +}
> > +
> > +static int cdns_hdptx_hdmi_phy_on(struct phy *phy) {
> > + struct cdns_hdptx_hdmi_phy *cdns_phy = phy_get_drvdata(phy);
> > +
> > + return hdptx_hdmi_phy_power_up(cdns_phy);
> > +}
> > +
> > +static int cdns_hdptx_hdmi_phy_off(struct phy *phy) {
> > + struct cdns_hdptx_hdmi_phy *cdns_phy = phy_get_drvdata(phy);
> > +
> > + hdptx_hdmi_phy_power_down(cdns_phy);
> > + return 0;
> > +}
> > +
> > +int cdns_hdptx_hdmi_phy_valid(struct phy *phy, enum phy_mode mode,
> > +int
> > submode, + union phy_configure_opts
> *opts)
> > +{
> > + u32 rate = opts->hdmi.pixel_clk_rate;
> > + int i;
> > +
> > + for (i = 0; i < ARRAY_SIZE(pixel_clk_output_ctrl_table); i++)
> > + if (rate ==
> pixel_clk_output_ctrl_table[i].pixel_clk_freq_min)
> > + return 0;
> > +
> > + return -EINVAL;
> > +}
> > +
> > +static int cdns_hdptx_hdmi_phy_init(struct phy *phy) {
> > + return 0;
> > +}
> > +
> > +static int cdns_hdptx_hdmi_configure(struct phy *phy,
> > + union phy_configure_opts *opts)
> {
> > + struct cdns_hdptx_hdmi_phy *cdns_phy = phy_get_drvdata(phy);
> > + int ret;
> > +
> > + cdns_phy->pixel_clk_rate = opts->hdmi.pixel_clk_rate;
> > + cdns_phy->color_space = opts->hdmi.color_space;
> > + cdns_phy->bpc = opts->hdmi.bpc;
> > +
> > + /* Check HDMI FW alive before HDMI PHY init */
> > + ret = hdptx_phy_check_alive(cdns_phy);
> > + if (!ret) {
> > + dev_err(cdns_phy->dev, "NO HDMI FW running\n");
> > + return -ENXIO;
> > + }
> > +
> > + /* Configure PHY */
> > + if (hdptx_hdmi_phy_cfg(cdns_phy, cdns_phy->pixel_clk_rate) < 0) {
> > + dev_err(cdns_phy->dev, "failed to set phy pclock\n");
> > + return -EINVAL;
> > + }
> > +
> > + ret = hdptx_hdmi_phy_power_up(cdns_phy);
> > + if (ret < 0)
> > + return ret;
> > +
> > + hdptx_hdmi_phy_set_vswing(cdns_phy);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct phy_ops cdns_hdptx_hdmi_phy_ops = {
> > + .init = cdns_hdptx_hdmi_phy_init,
> > + .configure = cdns_hdptx_hdmi_configure,
> > + .power_on = cdns_hdptx_hdmi_phy_on,
> > + .power_off = cdns_hdptx_hdmi_phy_off,
> > + .validate = cdns_hdptx_hdmi_phy_valid,
> > + .owner = THIS_MODULE,
> > +};
> > +
> > +static int cdns_hdptx_hdmi_phy_probe(struct platform_device *pdev) {
> > + struct cdns_hdptx_hdmi_phy *cdns_phy;
> > + struct device *dev = &pdev->dev;
> > + struct device_node *node = dev->of_node;
> > + struct phy_provider *phy_provider;
> > + struct resource *res;
> > + struct phy *phy;
> > + int ret;
> > +
> > + cdns_phy = devm_kzalloc(dev, sizeof(*cdns_phy), GFP_KERNEL);
> > + if (!cdns_phy)
> > + return -ENOMEM;
> > +
> > + dev_set_drvdata(dev, cdns_phy);
> > + cdns_phy->dev = dev;
> > + mutex_init(&cdns_phy->mbox_mutex);
> > +
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + if (!res)
> > + return -ENODEV;
> > + cdns_phy->regs = devm_ioremap(dev, res->start,
> resource_size(res));
> > + if (IS_ERR(cdns_phy->regs))
> > + return PTR_ERR(cdns_phy->regs);
> > +
> > + phy = devm_phy_create(dev, node, &cdns_hdptx_hdmi_phy_ops);
> > + if (IS_ERR(phy))
> > + return PTR_ERR(phy);
> > +
> > + phy->attrs.mode = PHY_MODE_HDMI;
> > +
> > + cdns_phy->phy = phy;
> > + phy_set_drvdata(phy, cdns_phy);
> > +
> > + /* init base struct for access mhdp mailbox */
> > + cdns_phy->base.dev = cdns_phy->dev;
> > + cdns_phy->base.regs = cdns_phy->regs;
> > + cdns_phy->base.mbox_mutex = &cdns_phy->mbox_mutex;
>
> The same as for the DP PHY driver applies here.
Same as reply in DP PHY driver.
Best, regards,
Sandor
>
> Best regards,
> Alexander
>
> > +
> > + ret = hdptx_hdmi_clk_enable(cdns_phy);
> > + if (ret) {
> > + dev_err(dev, "Init clk fail\n");
> > + return -EINVAL;
> > + }
> > +
> > + phy_provider = devm_of_phy_provider_register(dev,
> of_phy_simple_xlate);
> > + if (IS_ERR(phy_provider)) {
> > + ret = PTR_ERR(phy_provider);
> > + goto clk_disable;
> > + }
> > +
> > + dev_dbg(dev, "probe success!\n");
> > +
> > + return 0;
> > +
> > +clk_disable:
> > + hdptx_hdmi_clk_disable(cdns_phy);
> > +
> > + return -EINVAL;
> > +}
> > +
> > +static int cdns_hdptx_hdmi_phy_remove(struct platform_device *pdev) {
> > + struct cdns_hdptx_hdmi_phy *cdns_phy =
> > +platform_get_drvdata(pdev);
> > +
> > + hdptx_hdmi_clk_disable(cdns_phy);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct of_device_id cdns_hdptx_hdmi_phy_of_match[] = {
> > + {.compatible = "fsl,imx8mq-hdmi-phy" },
> > + { /* sentinel */ }
> > +};
> > +MODULE_DEVICE_TABLE(of, cdns_hdptx_hdmi_phy_of_match);
> > +
> > +static struct platform_driver cdns_hdptx_hdmi_phy_driver = {
> > + .probe = cdns_hdptx_hdmi_phy_probe,
> > + .remove = cdns_hdptx_hdmi_phy_remove,
> > + .driver = {
> > + .name = "cdns-hdptx-hdmi-phy",
> > + .of_match_table = cdns_hdptx_hdmi_phy_of_match,
> > + }
> > +};
> > +module_platform_driver(cdns_hdptx_hdmi_phy_driver);
> > +
> > +MODULE_AUTHOR("Sandor Yu <sandor.yu@nxp.com>");
> > +MODULE_DESCRIPTION("Cadence HDP-TX HDMI PHY driver");
> > +MODULE_LICENSE("GPL");
>
>
> --
> TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
> Amtsgericht München, HRB 105018
> Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
> http://www.tq/
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^ permalink raw reply
* RE: [EXT] Re: [PATCH v11 6/7] phy: freescale: Add DisplayPort PHY driver for i.MX8MQ
From: Sandor Yu @ 2024-01-05 3:20 UTC (permalink / raw)
To: Alexander Stein, dmitry.baryshkov@linaro.org,
andrzej.hajda@intel.com, neil.armstrong@linaro.org,
Laurent Pinchart, jonas@kwiboo.se, jernej.skrabec@gmail.com,
airlied@gmail.com, daniel@ffwll.ch, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, shawnguo@kernel.org,
s.hauer@pengutronix.de, festevam@gmail.com, vkoul@kernel.org,
dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org
Cc: kernel@pengutronix.de, dl-linux-imx, Oliver Brown,
sam@ravnborg.org
In-Reply-To: <2101977.bB369e8A3T@steina-w>
Hi Alexander,
Thanks for your comments,
> -----Original Message-----
> From: Alexander Stein <alexander.stein@ew.tq-group.com>
>
> Hi Sandor,
>
> thanks for the patch.
>
> Am Dienstag, 17. Oktober 2023, 09:04:02 CEST schrieb Sandor Yu:
> > Add Cadence HDP-TX DisplayPort PHY driver for i.MX8MQ
> >
> > Cadence HDP-TX PHY could be put in either DP mode or HDMI mode base on
> > the configuration chosen.
> > DisplayPort PHY mode is configurated in the driver.
> >
> > Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
> > ---
> > v9->v11:
> > *No change.
> >
> > drivers/phy/freescale/Kconfig | 10 +
> > drivers/phy/freescale/Makefile | 1 +
> > drivers/phy/freescale/phy-fsl-imx8mq-dp.c | 720
> > ++++++++++++++++++++++
> > 3 files changed, 731 insertions(+)
> > create mode 100644 drivers/phy/freescale/phy-fsl-imx8mq-dp.c
> >
> > diff --git a/drivers/phy/freescale/Kconfig
> > b/drivers/phy/freescale/Kconfig index 853958fb2c063..c39709fd700ac
> > 100644
> > --- a/drivers/phy/freescale/Kconfig
> > +++ b/drivers/phy/freescale/Kconfig
> > @@ -35,6 +35,16 @@ config PHY_FSL_IMX8M_PCIE
> > Enable this to add support for the PCIE PHY as found on
> > i.MX8M family of SOCs.
> >
> > +config PHY_FSL_IMX8MQ_DP
> > + tristate "Freescale i.MX8MQ DP PHY support"
> > + depends on OF && HAS_IOMEM
> > + depends on COMMON_CLK
> > + select GENERIC_PHY
> > + select CDNS_MHDP_HELPER
> > + help
> > + Enable this to support the Cadence HDPTX DP PHY driver
> > + on i.MX8MQ SOC.
> > +
> > endif
> >
> > config PHY_FSL_LYNX_28G
> > diff --git a/drivers/phy/freescale/Makefile
> > b/drivers/phy/freescale/Makefile index cedb328bc4d28..47e5285209fa8
> > 100644
> > --- a/drivers/phy/freescale/Makefile
> > +++ b/drivers/phy/freescale/Makefile
> > @@ -1,4 +1,5 @@
> > # SPDX-License-Identifier: GPL-2.0-only
> > +obj-$(CONFIG_PHY_FSL_IMX8MQ_DP) +=
> phy-fsl-imx8mq-dp.o
> > obj-$(CONFIG_PHY_FSL_IMX8MQ_USB) += phy-fsl-imx8mq-usb.o
> > obj-$(CONFIG_PHY_MIXEL_LVDS_PHY) += phy-fsl-imx8qm-lvds-phy.o
> > obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY) += phy-fsl-imx8-mipi-dphy.o
> > diff --git a/drivers/phy/freescale/phy-fsl-imx8mq-dp.c
> > b/drivers/phy/freescale/phy-fsl-imx8mq-dp.c new file mode 100644 index
> > 0000000000000..5f0d7da16b422
> > --- /dev/null
> > +++ b/drivers/phy/freescale/phy-fsl-imx8mq-dp.c
> > @@ -0,0 +1,720 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Cadence HDP-TX Display Port Interface (DP) PHY driver
> > + *
> > + * Copyright (C) 2022, 2023 NXP Semiconductor, Inc.
> > + */
> > +#include <asm/unaligned.h>
> > +#include <drm/bridge/cdns-mhdp-helper.h> #include <linux/clk.h>
> > +#include <linux/kernel.h> #include <linux/phy/phy.h> #include
> > +<linux/platform_device.h> #include <linux/io.h> #include
> > +<linux/iopoll.h>
> > +
> > +#define ADDR_PHY_AFE 0x80000
> > +
> > +/* PHY registers */
> > +#define CMN_SSM_BIAS_TMR 0x0022
> > +#define CMN_PLLSM0_PLLEN_TMR 0x0029
> > +#define CMN_PLLSM0_PLLPRE_TMR 0x002a
> > +#define CMN_PLLSM0_PLLVREF_TMR 0x002b
> > +#define CMN_PLLSM0_PLLLOCK_TMR 0x002c
> > +#define CMN_PLLSM0_USER_DEF_CTRL 0x002f
> > +#define CMN_PSM_CLK_CTRL 0x0061
> > +#define CMN_PLL0_VCOCAL_START 0x0081
> > +#define CMN_PLL0_VCOCAL_INIT_TMR 0x0084
> > +#define CMN_PLL0_VCOCAL_ITER_TMR 0x0085
> > +#define CMN_PLL0_INTDIV 0x0094
> > +#define CMN_PLL0_FRACDIV 0x0095
> > +#define CMN_PLL0_HIGH_THR 0x0096
> > +#define CMN_PLL0_DSM_DIAG 0x0097
> > +#define CMN_PLL0_SS_CTRL2 0x0099
> > +#define CMN_ICAL_INIT_TMR 0x00c4
> > +#define CMN_ICAL_ITER_TMR 0x00c5
> > +#define CMN_RXCAL_INIT_TMR 0x00d4
> > +#define CMN_RXCAL_ITER_TMR 0x00d5
> > +#define CMN_TXPUCAL_INIT_TMR 0x00e4
> > +#define CMN_TXPUCAL_ITER_TMR 0x00e5
> > +#define CMN_TXPDCAL_INIT_TMR 0x00f4
> > +#define CMN_TXPDCAL_ITER_TMR 0x00f5
> > +#define CMN_ICAL_ADJ_INIT_TMR 0x0102
> > +#define CMN_ICAL_ADJ_ITER_TMR 0x0103
> > +#define CMN_RX_ADJ_INIT_TMR 0x0106
> > +#define CMN_RX_ADJ_ITER_TMR 0x0107
> > +#define CMN_TXPU_ADJ_INIT_TMR 0x010a
> > +#define CMN_TXPU_ADJ_ITER_TMR 0x010b
> > +#define CMN_TXPD_ADJ_INIT_TMR 0x010e
> > +#define CMN_TXPD_ADJ_ITER_TMR 0x010f
> > +#define CMN_DIAG_PLL0_FBH_OVRD 0x01c0
> > +#define CMN_DIAG_PLL0_FBL_OVRD 0x01c1
> > +#define CMN_DIAG_PLL0_OVRD 0x01c2
> > +#define CMN_DIAG_PLL0_TEST_MODE 0x01c4
> > +#define CMN_DIAG_PLL0_V2I_TUNE 0x01c5
> > +#define CMN_DIAG_PLL0_CP_TUNE 0x01c6
> > +#define CMN_DIAG_PLL0_LF_PROG 0x01c7
> > +#define CMN_DIAG_PLL0_PTATIS_TUNE1 0x01c8
> > +#define CMN_DIAG_PLL0_PTATIS_TUNE2 0x01c9
> > +#define CMN_DIAG_HSCLK_SEL 0x01e0
> > +#define CMN_DIAG_PER_CAL_ADJ 0x01ec
> > +#define CMN_DIAG_CAL_CTRL 0x01ed
> > +#define CMN_DIAG_ACYA 0x01ff
> > +#define XCVR_PSM_RCTRL 0x4001
> > +#define XCVR_PSM_CAL_TMR 0x4002
> > +#define XCVR_PSM_A0IN_TMR 0x4003
> > +#define TX_TXCC_CAL_SCLR_MULT_0 0x4047
> > +#define TX_TXCC_CPOST_MULT_00_0 0x404c
> > +#define XCVR_DIAG_PLLDRC_CTRL 0x40e0
> > +#define XCVR_DIAG_PLLDRC_CTRL 0x40e0
> > +#define XCVR_DIAG_HSCLK_SEL 0x40e1
> > +#define XCVR_DIAG_LANE_FCM_EN_MGN_TMR 0x40f2
> > +#define TX_PSC_A0 0x4100
> > +#define TX_PSC_A1 0x4101
> > +#define TX_PSC_A2 0x4102
> > +#define TX_PSC_A3 0x4103
> > +#define TX_RCVDET_EN_TMR 0x4122
> > +#define TX_RCVDET_ST_TMR 0x4123
> > +#define TX_DIAG_BGREF_PREDRV_DELAY 0x41e7
> > +#define TX_DIAG_BGREF_PREDRV_DELAY 0x41e7
> > +#define TX_DIAG_ACYA_0 0x41ff
> > +#define TX_DIAG_ACYA_1 0x43ff
> > +#define TX_DIAG_ACYA_2 0x45ff
> > +#define TX_DIAG_ACYA_3 0x47ff
> > +#define TX_ANA_CTRL_REG_1 0x5020
> > +#define TX_ANA_CTRL_REG_2 0x5021
> > +#define TX_DIG_CTRL_REG_1 0x5023
> > +#define TX_DIG_CTRL_REG_2 0x5024
> > +#define TXDA_CYA_AUXDA_CYA 0x5025
> > +#define TX_ANA_CTRL_REG_3 0x5026
> > +#define TX_ANA_CTRL_REG_4 0x5027
> > +#define TX_ANA_CTRL_REG_5 0x5029
> > +#define RX_PSC_A0 0x8000
> > +#define RX_PSC_CAL 0x8006
> > +#define PHY_HDP_MODE_CTRL 0xc008
> > +#define PHY_HDP_CLK_CTL 0xc009
> > +#define PHY_PMA_CMN_CTRL1 0xc800
> > +
> > +/* PHY_PMA_CMN_CTRL1 */
> > +#define CMA_REF_CLK_SEL_MASK GENMASK(6, 4)
> > +#define CMA_REF_CLK_RCV_EN_MASK BIT(3)
> > +#define CMA_REF_CLK_RCV_EN 1
> > +
> > +/* PHY_HDP_CLK_CTL */
> > +#define PLL_DATA_RATE_CLK_DIV_MASK GENMASK(15, 8)
> > +#define PLL_DATA_RATE_CLK_DIV_HBR 0x24
> > +#define PLL_DATA_RATE_CLK_DIV_HBR2 0x12
> > +#define PLL_CLK_EN_ACK BIT(3)
> > +#define PLL_CLK_EN BIT(2)
> > +#define PLL_READY BIT(1)
> > +#define PLL_EN BIT(0)
> > +
> > +/* CMN_DIAG_HSCLK_SEL */
> > +#define HSCLK1_SEL_MASK GENMASK(5,
> 4)
> > +#define HSCLK0_SEL_MASK GENMASK(1,
> 0)
> > +#define HSCLK_PLL0_DIV2 1
> > +
> > +/* XCVR_DIAG_HSCLK_SEL */
> > +#define HSCLK_SEL_MODE3_MASK GENMASK(13, 12)
> > +#define HSCLK_SEL_MODE3_HSCLK1 1
> > +
> > +/* XCVR_DIAG_PLLDRC_CTRL */
> > +#define DPLL_CLK_SEL_MODE3 BIT(14)
> > +#define DPLL_DATA_RATE_DIV_MODE3_MASK
> GENMASK(13, 12)
> > +
> > +/* PHY_HDP_MODE_CTRL */
> > +#define POWER_STATE_A3_ACK BIT(7)
> > +#define POWER_STATE_A2_ACK BIT(6)
> > +#define POWER_STATE_A1_ACK BIT(5)
> > +#define POWER_STATE_A0_ACK BIT(4)
> > +#define POWER_STATE_A3 BIT(3)
> > +#define POWER_STATE_A2 BIT(2)
> > +#define POWER_STATE_A1 BIT(1)
> > +#define POWER_STATE_A0 BIT(0)
> > +
> > +#define REF_CLK_27MHZ 27000000
> > +
> > +enum dp_link_rate {
> > + RATE_1_6 = 162000,
> > + RATE_2_1 = 216000,
> > + RATE_2_4 = 243000,
> > + RATE_2_7 = 270000,
> > + RATE_3_2 = 324000,
> > + RATE_4_3 = 432000,
> > + RATE_5_4 = 540000,
> > + RATE_8_1 = 810000,
>
> RATE_8_1 is unused.
OK, will remove it.
>
> > +};
> > +
> > +#define MAX_LINK_RATE RATE_5_4
> > +
> > +struct phy_pll_reg {
> > + u16 val[7];
> > + u32 addr;
> > +};
> > +
> > +static const struct phy_pll_reg phy_pll_27m_cfg[] = {
> > + /* 1.62 2.16 2.43 2.7 3.24 4.32 5.4
> register
> > address */ + {{ 0x010e, 0x010e, 0x010e, 0x010e, 0x010e, 0x010e,
> > 0x010e
> },
> > CMN_PLL0_VCOCAL_INIT_TMR }, + {{ 0x001b, 0x001b, 0x001b, 0x001b,
> 0x001b,
> > 0x001b, 0x001b }, CMN_PLL0_VCOCAL_ITER_TMR }, + {{ 0x30b9,
> 0x3087, 0x3096,
> > 0x30b4, 0x30b9, 0x3087, 0x30b4 }, CMN_PLL0_VCOCAL_START }, + {{
> 0x0077,
> > 0x009f, 0x00b3, 0x00c7, 0x0077, 0x009f, 0x00c7 }, CMN_PLL0_INTDIV }, +
> {{
> > 0xf9da, 0xf7cd, 0xf6c7, 0xf5c1, 0xf9da, 0xf7cd, 0xf5c1 },
> > CMN_PLL0_FRACDIV }, + {{ 0x001e, 0x0028, 0x002d, 0x0032, 0x001e,
> 0x0028, 0x0032 },
> > CMN_PLL0_HIGH_THR }, + {{ 0x0020, 0x0020, 0x0020, 0x0020,
> 0x0020,
> 0x0020,
> > 0x0020 }, CMN_PLL0_DSM_DIAG }, + {{ 0x0000, 0x1000, 0x1000,
> 0x1000,
> 0x0000,
> > 0x1000, 0x1000 }, CMN_PLLSM0_USER_DEF_CTRL }, + {{ 0x0000,
> 0x0000, 0x0000,
> > 0x0000, 0x0000, 0x0000, 0x0000 }, CMN_DIAG_PLL0_OVRD }, +
> {{ 0x0000,
> > 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 },
> > CMN_DIAG_PLL0_FBH_OVRD },
> > + {{ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 },
> > CMN_DIAG_PLL0_FBL_OVRD }, + {{ 0x0006, 0x0007, 0x0007, 0x0007,
> 0x0006,
> > 0x0007, 0x0007 }, CMN_DIAG_PLL0_V2I_TUNE }, + {{ 0x0043, 0x0043,
> > 0x0043, 0x0042, 0x0043, 0x0043, 0x0042 }, CMN_DIAG_PLL0_CP_TUNE }, +
> > {{
> 0x0008,
> > 0x0008, 0x0008, 0x0008, 0x0008, 0x0008, 0x0008 },
> > CMN_DIAG_PLL0_LF_PROG },
> > + {{ 0x0100, 0x0001, 0x0001, 0x0001, 0x0100, 0x0001, 0x0001 },
> > CMN_DIAG_PLL0_PTATIS_TUNE1 }, + {{ 0x0007, 0x0001, 0x0001,
> 0x0001,
> 0x0007,
> > 0x0001, 0x0001 }, CMN_DIAG_PLL0_PTATIS_TUNE2 }, + {{ 0x0020,
> 0x0020,
> > 0x0020, 0x0020, 0x0020, 0x0020, 0x0020 }, CMN_DIAG_PLL0_TEST_MODE},
> +
> > {{ 0x0016, 0x0016, 0x0016, 0x0016, 0x0016, 0x0016, 0x0016 },
> > CMN_PSM_CLK_CTRL } +};
> > +
> > +struct cdns_hdptx_dp_phy {
> > + struct cdns_mhdp_base base;
> > +
> > + void __iomem *regs; /* DPTX registers base */
> > + struct device *dev;
> > + struct phy *phy;
> > + struct mutex mbox_mutex; /* mutex to protect mailbox */
> > + struct clk *ref_clk, *apb_clk;
> > + u32 ref_clk_rate;
> > + u32 num_lanes;
> > + u32 link_rate;
> > + bool power_up;
> > +};
> > +
> > +static int cdns_phy_reg_write(struct cdns_hdptx_dp_phy *cdns_phy, u32
> > +addr,
> > u32 val) +{
> > + return cdns_mhdp_reg_write(&cdns_phy->base, ADDR_PHY_AFE +
> (addr
> > + <<
> 2),
> > val); +}
> > +
> > +static u32 cdns_phy_reg_read(struct cdns_hdptx_dp_phy *cdns_phy, u32
> > +addr) {
> > + u32 reg32;
> > +
> > + cdns_mhdp_reg_read(&cdns_phy->base, ADDR_PHY_AFE + (addr <<
> 2),
> ®32);
> > + return reg32;
> > +}
> > +
> > +static int link_rate_index(u32 rate)
> > +{
> > + switch (rate) {
> > + case RATE_1_6:
> > + return 0;
> > + case RATE_2_1:
> > + return 1;
> > + case RATE_2_4:
> > + return 2;
> > + case RATE_2_7:
> > + return 3;
> > + case RATE_3_2:
> > + return 4;
> > + case RATE_4_3:
> > + return 5;
> > + case RATE_5_4:
> > + return 6;
> > + default:
> > + return -1;
> > + }
> > +}
> > +
> > +static int hdptx_dp_clk_enable(struct cdns_hdptx_dp_phy *cdns_phy) {
> > + struct device *dev = cdns_phy->dev;
> > + u32 ref_clk_rate;
> > + int ret;
> > +
> > + cdns_phy->ref_clk = devm_clk_get(dev, "ref");
> > + if (IS_ERR(cdns_phy->ref_clk)) {
> > + dev_err(dev, "phy ref clock not found\n");
> > + return PTR_ERR(cdns_phy->ref_clk);
> > + }
> > +
> > + cdns_phy->apb_clk = devm_clk_get(dev, "apb");
> > + if (IS_ERR(cdns_phy->apb_clk)) {
> > + dev_err(dev, "phy apb clock not found\n");
> > + return PTR_ERR(cdns_phy->apb_clk);
> > + }
> > +
> > + ret = clk_prepare_enable(cdns_phy->ref_clk);
> > + if (ret) {
> > + dev_err(cdns_phy->dev, "Failed to prepare ref clock\n");
> > + return ret;
> > + }
> > +
> > + ref_clk_rate = clk_get_rate(cdns_phy->ref_clk);
> > + if (!ref_clk_rate) {
> > + dev_err(cdns_phy->dev, "Failed to get ref clock rate\n");
> > + goto err_ref_clk;
> > + }
> > +
> > + if (ref_clk_rate == REF_CLK_27MHZ) {
> > + cdns_phy->ref_clk_rate = ref_clk_rate;
> > + } else {
> > + dev_err(cdns_phy->dev, "Not support Ref Clock Rate(%dHz)
> \n",
> > ref_clk_rate); + goto err_ref_clk;
> > + }
> > +
> > + ret = clk_prepare_enable(cdns_phy->apb_clk);
> > + if (ret) {
> > + dev_err(cdns_phy->dev, "Failed to prepare apb clock\n");
> > + goto err_ref_clk;
> > + }
> > +
> > + return 0;
> > +
> > +err_ref_clk:
> > + clk_disable_unprepare(cdns_phy->ref_clk);
> > + return -EINVAL;
> > +}
> > +
> > +static void hdptx_dp_clk_disable(struct cdns_hdptx_dp_phy *cdns_phy)
> > +{
> > + clk_disable_unprepare(cdns_phy->ref_clk);
> > + clk_disable_unprepare(cdns_phy->apb_clk);
> > +}
> > +
> > +static void hdptx_dp_aux_cfg(struct cdns_hdptx_dp_phy *cdns_phy) {
> > + /* Power up Aux */
> > + cdns_phy_reg_write(cdns_phy, TXDA_CYA_AUXDA_CYA, 1);
> > +
> > + cdns_phy_reg_write(cdns_phy, TX_DIG_CTRL_REG_1, 0x3);
> > + ndelay(150);
> > + cdns_phy_reg_write(cdns_phy, TX_DIG_CTRL_REG_2, 36);
> > + ndelay(150);
> > + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x0100);
> > + ndelay(150);
> > + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x0300);
> > + ndelay(150);
> > + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_3, 0x0000);
> > + ndelay(150);
> > + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, 0x2008);
> > + ndelay(150);
> > + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, 0x2018);
> > + ndelay(150);
> > + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, 0xa018);
> > + ndelay(150);
> > + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x030c);
> > + ndelay(150);
> > + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_5, 0x0000);
> > + ndelay(150);
> > + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_4, 0x1001);
> > + ndelay(150);
> > + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, 0xa098);
> > + ndelay(150);
> > + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, 0xa198);
> > + ndelay(150);
> > + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x030d);
> > + ndelay(150);
> > + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x030f); }
> > +
> > +/* PMA common configuration for 27MHz */ static void
> > +hdptx_dp_phy_pma_cmn_cfg_27mhz(struct cdns_hdptx_dp_phy
> > *cdns_phy) +{
> > + u32 num_lanes = cdns_phy->num_lanes;
> > + u16 val;
> > + int k;
> > +
> > + /* Enable PMA input ref clk(CMN_REF_CLK_RCV_EN) */
> > + val = cdns_phy_reg_read(cdns_phy, PHY_PMA_CMN_CTRL1);
> > + val &= ~CMA_REF_CLK_RCV_EN_MASK;
> > + val |= FIELD_PREP(CMA_REF_CLK_RCV_EN_MASK,
> CMA_REF_CLK_RCV_EN);
> > + cdns_phy_reg_write(cdns_phy, PHY_PMA_CMN_CTRL1, val);
> > +
> > + /* Startup state machine registers */
> > + cdns_phy_reg_write(cdns_phy, CMN_SSM_BIAS_TMR, 0x0087);
> > + cdns_phy_reg_write(cdns_phy, CMN_PLLSM0_PLLEN_TMR, 0x001b);
> > + cdns_phy_reg_write(cdns_phy, CMN_PLLSM0_PLLPRE_TMR, 0x0036);
> > + cdns_phy_reg_write(cdns_phy, CMN_PLLSM0_PLLVREF_TMR,
> 0x001b);
> > + cdns_phy_reg_write(cdns_phy, CMN_PLLSM0_PLLLOCK_TMR,
> 0x006c);
> > +
> > + /* Current calibration registers */
> > + cdns_phy_reg_write(cdns_phy, CMN_ICAL_INIT_TMR, 0x0044);
> > + cdns_phy_reg_write(cdns_phy, CMN_ICAL_ITER_TMR, 0x0006);
> > + cdns_phy_reg_write(cdns_phy, CMN_ICAL_ADJ_INIT_TMR, 0x0022);
> > + cdns_phy_reg_write(cdns_phy, CMN_ICAL_ADJ_ITER_TMR, 0x0006);
> > +
> > + /* Resistor calibration registers */
> > + cdns_phy_reg_write(cdns_phy, CMN_TXPUCAL_INIT_TMR, 0x0022);
> > + cdns_phy_reg_write(cdns_phy, CMN_TXPUCAL_ITER_TMR, 0x0006);
> > + cdns_phy_reg_write(cdns_phy, CMN_TXPU_ADJ_INIT_TMR, 0x0022);
> > + cdns_phy_reg_write(cdns_phy, CMN_TXPU_ADJ_ITER_TMR, 0x0006);
> > + cdns_phy_reg_write(cdns_phy, CMN_TXPDCAL_INIT_TMR, 0x0022);
> > + cdns_phy_reg_write(cdns_phy, CMN_TXPDCAL_ITER_TMR, 0x0006);
> > + cdns_phy_reg_write(cdns_phy, CMN_TXPD_ADJ_INIT_TMR, 0x0022);
> > + cdns_phy_reg_write(cdns_phy, CMN_TXPD_ADJ_ITER_TMR, 0x0006);
> > + cdns_phy_reg_write(cdns_phy, CMN_RXCAL_INIT_TMR, 0x0022);
> > + cdns_phy_reg_write(cdns_phy, CMN_RXCAL_ITER_TMR, 0x0006);
> > + cdns_phy_reg_write(cdns_phy, CMN_RX_ADJ_INIT_TMR, 0x0022);
> > + cdns_phy_reg_write(cdns_phy, CMN_RX_ADJ_ITER_TMR, 0x0006);
> > +
> > + for (k = 0; k < num_lanes; k = k + 1) {
> > + /* Power state machine registers */
> > + cdns_phy_reg_write(cdns_phy, XCVR_PSM_CAL_TMR | (k
> <<
> > + 9),
> 0x016d);
> > + cdns_phy_reg_write(cdns_phy, XCVR_PSM_A0IN_TMR | (k
> <<
> > + 9),
> 0x016d);
> > + /* Transceiver control and diagnostic registers */
> > + cdns_phy_reg_write(cdns_phy,
> > + XCVR_DIAG_LANE_FCM_EN_MGN_TMR
> | (k << 9),
> > 0x00a2); + cdns_phy_reg_write(cdns_phy,
> TX_DIAG_BGREF_PREDRV_DELAY | (k <<
> > 9), 0x0097); + /* Transmitter receiver detect registers */
> > + cdns_phy_reg_write(cdns_phy, TX_RCVDET_EN_TMR | (k <<
> > + 9),
> 0x0a8c);
> > + cdns_phy_reg_write(cdns_phy, TX_RCVDET_ST_TMR | (k <<
> > + 9),
> 0x0036);
> > + }
> > +
> > + cdns_phy_reg_write(cdns_phy, TX_DIAG_ACYA_0, 1);
> > + cdns_phy_reg_write(cdns_phy, TX_DIAG_ACYA_1, 1);
> > + cdns_phy_reg_write(cdns_phy, TX_DIAG_ACYA_2, 1);
> > + cdns_phy_reg_write(cdns_phy, TX_DIAG_ACYA_3, 1); }
> > +
> > +static void hdptx_dp_phy_pma_cmn_pll0_27mhz(struct
> cdns_hdptx_dp_phy
> > *cdns_phy) +{
> > + u32 num_lanes = cdns_phy->num_lanes;
> > + u32 link_rate = cdns_phy->link_rate;
> > + u16 val;
> > + int index, i, k;
> > +
> > + /* DP PLL data rate 0/1 clock divider value */
> > + val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
> > + val &= ~PLL_DATA_RATE_CLK_DIV_MASK;
> > + if (link_rate <= RATE_2_7)
> > + val |= FIELD_PREP(PLL_DATA_RATE_CLK_DIV_MASK,
> > + PLL_DATA_RATE_CLK_DIV_HBR);
> > + else
> > + val |= FIELD_PREP(PLL_DATA_RATE_CLK_DIV_MASK,
> > + PLL_DATA_RATE_CLK_DIV_HBR2);
> > + cdns_phy_reg_write(cdns_phy, PHY_HDP_CLK_CTL, val);
> > +
> > + /* High speed clock 0/1 div */
> > + val = cdns_phy_reg_read(cdns_phy, CMN_DIAG_HSCLK_SEL);
> > + val &= ~(HSCLK1_SEL_MASK | HSCLK0_SEL_MASK);
> > + if (link_rate <= RATE_2_7) {
> > + val |= FIELD_PREP(HSCLK1_SEL_MASK, HSCLK_PLL0_DIV2);
> > + val |= FIELD_PREP(HSCLK0_SEL_MASK, HSCLK_PLL0_DIV2);
> > + }
> > + cdns_phy_reg_write(cdns_phy, CMN_DIAG_HSCLK_SEL, val);
> > +
> > + for (k = 0; k < num_lanes; k++) {
> > + val = cdns_phy_reg_read(cdns_phy, (XCVR_DIAG_HSCLK_SEL
> |
> (k << 9)));
> > + val &= ~HSCLK_SEL_MODE3_MASK;
> > + if (link_rate <= RATE_2_7)
> > + val |= FIELD_PREP(HSCLK_SEL_MODE3_MASK,
> HSCLK_SEL_MODE3_HSCLK1);
> > + cdns_phy_reg_write(cdns_phy, (XCVR_DIAG_HSCLK_SEL | (k
> > + <<
> 9)), val);
> > + }
> > +
> > + /* DP PHY PLL 27MHz configuration */
> > + index = link_rate_index(link_rate);
> > + for (i = 0; i < ARRAY_SIZE(phy_pll_27m_cfg); i++)
> > + cdns_phy_reg_write(cdns_phy, phy_pll_27m_cfg[i].addr,
> > + phy_pll_27m_cfg[i].val[index]);
> > +
> > + /* Transceiver control and diagnostic registers */
> > + for (k = 0; k < num_lanes; k++) {
> > + val = cdns_phy_reg_read(cdns_phy,
> (XCVR_DIAG_PLLDRC_CTRL
> > + |
> (k << 9)));
> > + val &= ~(DPLL_DATA_RATE_DIV_MODE3_MASK |
> DPLL_CLK_SEL_MODE3);
> > + if (link_rate <= RATE_2_7)
> > + val |=
> FIELD_PREP(DPLL_DATA_RATE_DIV_MODE3_MASK,
> 2);
> > + else
> > + val |=
> FIELD_PREP(DPLL_DATA_RATE_DIV_MODE3_MASK,
> 1);
> > + cdns_phy_reg_write(cdns_phy, (XCVR_DIAG_PLLDRC_CTRL |
> (k
> << 9)), val);
> > + }
> > +
> > + for (k = 0; k < num_lanes; k = k + 1) {
> > + /* Power state machine registers */
> > + cdns_phy_reg_write(cdns_phy, (XCVR_PSM_RCTRL | (k <<
> > + 9)),
> 0xbefc);
> > + cdns_phy_reg_write(cdns_phy, (TX_PSC_A0 | (k << 9)),
> 0x6799);
> > + cdns_phy_reg_write(cdns_phy, (TX_PSC_A1 | (k << 9)),
> 0x6798);
> > + cdns_phy_reg_write(cdns_phy, (TX_PSC_A2 | (k << 9)),
> 0x0098);
> > + cdns_phy_reg_write(cdns_phy, (TX_PSC_A3 | (k << 9)),
> 0x0098);
> > + /* Receiver calibration power state definition register */
> > + val = cdns_phy_reg_read(cdns_phy, RX_PSC_CAL | (k << 9));
> > + val &= 0xffbb;
> > + cdns_phy_reg_write(cdns_phy, (RX_PSC_CAL | (k << 9)),
> val);
> > + val = cdns_phy_reg_read(cdns_phy, RX_PSC_A0 | (k << 9));
> > + val &= 0xffbb;
> > + cdns_phy_reg_write(cdns_phy, (RX_PSC_A0 | (k << 9)), val);
> > + }
> > +}
> > +
> > +static void hdptx_dp_phy_ref_clock_type(struct cdns_hdptx_dp_phy
> > +*cdns_phy) {
> > + u32 val;
> > +
> > + val = cdns_phy_reg_read(cdns_phy, PHY_PMA_CMN_CTRL1);
> > + val &= ~CMA_REF_CLK_SEL_MASK;
> > + /*
> > + * single ended reference clock (val |= 0x0030);
> > + * differential clock (val |= 0x0000);
> > + *
> > + * for differential clock on the refclk_p and
> > + * refclk_m off chip pins: CMN_DIAG_ACYA[8]=1'b1
> > + * cdns_phy_reg_write(cdns_phy, CMN_DIAG_ACYA, 0x0100);
> > + */
> > + val |= FIELD_PREP(CMA_REF_CLK_SEL_MASK, 3);
> > + cdns_phy_reg_write(cdns_phy, PHY_PMA_CMN_CTRL1, val); }
> > +
> > +static int wait_for_ack(struct cdns_hdptx_dp_phy *cdns_phy, u32 reg,
> > +u32
> > mask, + const char *err_msg)
> > +{
> > + u32 val, i;
> > +
> > + for (i = 0; i < 10; i++) {
> > + val = cdns_phy_reg_read(cdns_phy, reg);
> > + if (val & mask)
> > + return 0;
> > + msleep(20);
> > + }
> > +
> > + dev_err(cdns_phy->dev, "%s\n", err_msg);
> > + return -1;
>
> return -ETIMEDOUT?
OK.
>
> > +}
> > +
> > +static int wait_for_ack_clear(struct cdns_hdptx_dp_phy *cdns_phy, u32
> > +reg,
> > u32 mask, + const char *err_msg)
> > +{
> > + u32 val, i;
> > +
> > + for (i = 0; i < 10; i++) {
> > + val = cdns_phy_reg_read(cdns_phy, reg);
> > + if (!(val & mask))
> > + return 0;
> > + msleep(20);
> > + }
> > +
> > + dev_err(cdns_phy->dev, "%s\n", err_msg);
> > + return -1;
>
> return -ETIMEDOUT?
OK.
>
> > +}
> > +
> > +static int hdptx_dp_phy_power_up(struct cdns_hdptx_dp_phy *cdns_phy)
> > +{
> > + u32 val;
> > +
> > + /* Enable HDP PLL’s for high speed clocks */
> > + val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
> > + val |= PLL_EN;
> > + cdns_phy_reg_write(cdns_phy, PHY_HDP_CLK_CTL, val);
> > + if (wait_for_ack(cdns_phy, PHY_HDP_CLK_CTL, PLL_READY,
> > + "Wait PLL Ack failed"))
> > + return -1;
> > +
> > + /* Enable HDP PLL’s data rate and full rate clocks out of PMA. */
> > + val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
> > + val |= PLL_CLK_EN;
> > + cdns_phy_reg_write(cdns_phy, PHY_HDP_CLK_CTL, val);
> > + if (wait_for_ack(cdns_phy, PHY_HDP_CLK_CTL, PLL_CLK_EN_ACK,
> > + "Wait PLL clock enable ACK failed"))
> > + return -1;
> > +
> > + /* Configure PHY in A2 Mode */
> > + cdns_phy_reg_write(cdns_phy, PHY_HDP_MODE_CTRL,
> POWER_STATE_A2);
> > + if (wait_for_ack(cdns_phy, PHY_HDP_MODE_CTRL,
> POWER_STATE_A2_ACK,
> > + "Wait A2 Ack failed"))
> > + return -1;
> > +
> > + /* Configure PHY in A0 mode (PHY must be in the A0 power
> > + * state in order to transmit data)
> > + */
> > + cdns_phy_reg_write(cdns_phy, PHY_HDP_MODE_CTRL,
> POWER_STATE_A0);
> > + if (wait_for_ack(cdns_phy, PHY_HDP_MODE_CTRL,
> POWER_STATE_A0_ACK,
> > + "Wait A0 Ack failed"))
> > + return -1;
>
> Maybe you should just return the return value of wait_for_ack() in each error
> case.
OK.
>
> > + cdns_phy->power_up = true;
> > +
> > + return 0;
> > +}
> > +
> > +static void hdptx_dp_phy_power_down(struct cdns_hdptx_dp_phy
> > +*cdns_phy) {
> > + u16 val;
> > +
> > + if (!cdns_phy->power_up)
> > + return;
> > +
> > + /* Place the PHY lanes in the A3 power state. */
> > + cdns_phy_reg_write(cdns_phy, PHY_HDP_MODE_CTRL,
> POWER_STATE_A3);
> > + if (wait_for_ack(cdns_phy, PHY_HDP_MODE_CTRL,
> POWER_STATE_A3_ACK,
> > + "Wait A3 Ack failed"))
> > + return;
> > +
> > + /* Disable HDP PLL’s data rate and full rate clocks out of PMA. */
> > + val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
> > + val &= ~PLL_CLK_EN;
> > + cdns_phy_reg_write(cdns_phy, PHY_HDP_CLK_CTL, val);
> > + if (wait_for_ack_clear(cdns_phy, PHY_HDP_CLK_CTL,
> PLL_CLK_EN_ACK,
> > + "Wait PLL clock Ack clear failed"))
> > + return;
> > +
> > + /* Disable HDP PLL’s for high speed clocks */
> > + val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
> > + val &= ~PLL_EN;
> > + cdns_phy_reg_write(cdns_phy, PHY_HDP_CLK_CTL, val);
> > + if (wait_for_ack_clear(cdns_phy, PHY_HDP_CLK_CTL, PLL_READY,
> > + "Wait PLL Ack clear failed"))
> > + return;
>
> I would have expected cdns_phy->power_up = false somewhere in this
> function.
>
I will added it.
> > +}
> > +
> > +static int cdns_hdptx_dp_phy_on(struct phy *phy) {
> > + struct cdns_hdptx_dp_phy *cdns_phy = phy_get_drvdata(phy);
> > +
> > + return hdptx_dp_phy_power_up(cdns_phy); }
> > +
> > +static int cdns_hdptx_dp_phy_off(struct phy *phy) {
> > + struct cdns_hdptx_dp_phy *cdns_phy = phy_get_drvdata(phy);
> > +
> > + hdptx_dp_phy_power_down(cdns_phy);
> > +
> > + return 0;
> > +}
> > +
> > +static int cdns_hdptx_dp_phy_init(struct phy *phy) {
> > + struct cdns_hdptx_dp_phy *cdns_phy = phy_get_drvdata(phy);
> > + int ret;
> > +
> > + hdptx_dp_phy_ref_clock_type(cdns_phy);
> > +
> > + /* PHY power up */
> > + ret = hdptx_dp_phy_power_up(cdns_phy);
> > + if (ret < 0)
> > + return ret;
> > +
> > + hdptx_dp_aux_cfg(cdns_phy);
> > +
> > + return ret;
> > +}
> > +
> > +static int cdns_hdptx_dp_configure(struct phy *phy,
> > + union phy_configure_opts *opts) {
> > + struct cdns_hdptx_dp_phy *cdns_phy = phy_get_drvdata(phy);
> > + int ret;
> > +
> > + cdns_phy->link_rate = opts->dp.link_rate;
> > + cdns_phy->num_lanes = opts->dp.lanes;
> > +
> > + if (cdns_phy->link_rate > MAX_LINK_RATE) {
> > + dev_err(cdns_phy->dev, "Link Rate(%d) Not supported\n",
> > cdns_phy->link_rate); + return false;
> > + }
> > +
> > + /* Disable phy clock if PHY in power up state */
> > + hdptx_dp_phy_power_down(cdns_phy);
> > +
> > + if (cdns_phy->ref_clk_rate == REF_CLK_27MHZ) {
> > + hdptx_dp_phy_pma_cmn_cfg_27mhz(cdns_phy);
> > + hdptx_dp_phy_pma_cmn_pll0_27mhz(cdns_phy);
> > + } else {
> > + dev_err(cdns_phy->dev, "Not support ref clock rate\n");
> > + }
> > +
> > + /* PHY power up */
> > + ret = hdptx_dp_phy_power_up(cdns_phy);
> > +
> > + return ret;
> > +}
> > +
> > +static const struct phy_ops cdns_hdptx_dp_phy_ops = {
> > + .init = cdns_hdptx_dp_phy_init,
> > + .configure = cdns_hdptx_dp_configure,
> > + .power_on = cdns_hdptx_dp_phy_on,
> > + .power_off = cdns_hdptx_dp_phy_off,
> > + .owner = THIS_MODULE,
> > +};
> > +
> > +static int cdns_hdptx_dp_phy_probe(struct platform_device *pdev) {
> > + struct cdns_hdptx_dp_phy *cdns_phy;
> > + struct device *dev = &pdev->dev;
> > + struct device_node *node = dev->of_node;
> > + struct phy_provider *phy_provider;
> > + struct resource *res;
> > + struct phy *phy;
> > + int ret;
> > +
> > + cdns_phy = devm_kzalloc(dev, sizeof(*cdns_phy), GFP_KERNEL);
> > + if (!cdns_phy)
> > + return -ENOMEM;
> > +
> > + dev_set_drvdata(dev, cdns_phy);
> > + cdns_phy->dev = dev;
> > + mutex_init(&cdns_phy->mbox_mutex);
> > +
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + if (!res)
> > + return -ENODEV;
> > + cdns_phy->regs = devm_ioremap(dev, res->start, resource_size(res));
> > + if (IS_ERR(cdns_phy->regs))
> > + return PTR_ERR(cdns_phy->regs);
> > +
> > + phy = devm_phy_create(dev, node, &cdns_hdptx_dp_phy_ops);
> > + if (IS_ERR(phy))
> > + return PTR_ERR(phy);
> > +
> > + phy->attrs.mode = PHY_MODE_DP;
> > + cdns_phy->phy = phy;
> > + phy_set_drvdata(phy, cdns_phy);
> > +
> > + /* init base struct for access mhdp mailbox */
> > + cdns_phy->base.dev = cdns_phy->dev;
> > + cdns_phy->base.regs = cdns_phy->regs;
> > + cdns_phy->base.mbox_mutex = &cdns_phy->mbox_mutex;
>
> How is this mutex supposed to work? From the name
> cdns_phy->base.mbox_mutex is supposed to protect the mailbox access in the
> cdns-mhdp base, right?
> But this mutex is different, initialized separately and thus is independent from
> mhdp->mbox_mutex in cdns-mhdp8501-core.c.
Yes, this mutex use to protect mailbox access in PHY driver only.
In cdns-mhdp8501-core.c driver, every access PHY API functions are protected by core driver's mbox_mutex.
Best regards,
Sandor
>
> Best regards,
> Alexander
>
> > +
> > + ret = hdptx_dp_clk_enable(cdns_phy);
> > + if (ret) {
> > + dev_err(dev, "Init clk fail\n");
> > + return -EINVAL;
> > + }
> > +
> > + phy_provider = devm_of_phy_provider_register(dev,
> of_phy_simple_xlate);
> > + if (IS_ERR(phy_provider)) {
> > + ret = PTR_ERR(phy_provider);
> > + goto clk_disable;
> > + }
> > +
> > + return 0;
> > +
> > +clk_disable:
> > + hdptx_dp_clk_disable(cdns_phy);
> > +
> > + return -EINVAL;
> > +}
> > +
> > +static int cdns_hdptx_dp_phy_remove(struct platform_device *pdev) {
> > + struct cdns_hdptx_dp_phy *cdns_phy = platform_get_drvdata(pdev);
> > +
> > + hdptx_dp_clk_disable(cdns_phy);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct of_device_id cdns_hdptx_dp_phy_of_match[] = {
> > + {.compatible = "fsl,imx8mq-dp-phy" },
> > + { /* sentinel */ }
> > +};
> > +MODULE_DEVICE_TABLE(of, cdns_hdptx_dp_phy_of_match);
> > +
> > +static struct platform_driver cdns_hdptx_dp_phy_driver = {
> > + .probe = cdns_hdptx_dp_phy_probe,
> > + .remove = cdns_hdptx_dp_phy_remove,
> > + .driver = {
> > + .name = "cdns-hdptx-dp-phy",
> > + .of_match_table = cdns_hdptx_dp_phy_of_match,
> > + }
> > +};
> > +module_platform_driver(cdns_hdptx_dp_phy_driver);
> > +
> > +MODULE_AUTHOR("Sandor Yu <sandor.yu@nxp.com>");
> > +MODULE_DESCRIPTION("Cadence HDP-TX DisplayPort PHY driver");
> > +MODULE_LICENSE("GPL");
>
>
> --
> TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
> Amtsgericht München, HRB 105018
> Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
> http://www.tq-/
> group.com%2F&data=05%7C01%7CSandor.yu%40nxp.com%7C8c4206b83ee9
> 49f73f2108dbcf1072ea%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0
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^ permalink raw reply
* RE: [EXT] Re: [PATCH v11 4/7] drm: bridge: Cadence: Add MHDP8501 DP/HDMI driver
From: Sandor Yu @ 2024-01-05 3:20 UTC (permalink / raw)
To: Alexander Stein, dmitry.baryshkov@linaro.org,
andrzej.hajda@intel.com, neil.armstrong@linaro.org,
Laurent Pinchart, jonas@kwiboo.se, jernej.skrabec@gmail.com,
airlied@gmail.com, daniel@ffwll.ch, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, shawnguo@kernel.org,
s.hauer@pengutronix.de, festevam@gmail.com, vkoul@kernel.org,
dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org
Cc: kernel@pengutronix.de, dl-linux-imx, Oliver Brown,
sam@ravnborg.org
In-Reply-To: <3064881.CbtlEUcBR6@steina-w>
Hi Alexander,
Thanks for your comments,
>
> Hi Sandor,
>
> thanks for the patch.
>
> Am Dienstag, 17. Oktober 2023, 09:04:00 CEST schrieb Sandor Yu:
> > Add a new DRM DisplayPort and HDMI bridge driver for Candence
> MHDP8501
> > used in i.MX8MQ SOC. MHDP8501 could support HDMI or DisplayPort
> > standards according embedded Firmware running in the uCPU.
> >
> > For iMX8MQ SOC, the DisplayPort/HDMI FW was loaded and activated by
> > SOC's ROM code. Bootload binary included respective specific firmware
> > is required.
> >
> > Driver will check display connector type and
> > then load the corresponding driver.
> >
> > Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
> > Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> > ---
> > v10->v11:
> > - remove MODULE_ALIAS() from mhdp8501 driver.
> >
> > v9->v10:
> > - struct cdns_mhdp_device is renamed to cdns_mhdp8501_device.
> > - update for mhdp helper driver is introduced.
> > Remove head file cdns-mhdp-mailbox.h and add cdns-mhdp-helper.h
> > Add struct cdns_mhdp_base base to struct cdns_mhdp8501_device.
> > Init struct cdns_mhdp_base base when driver probe.
> >
> > drivers/gpu/drm/bridge/cadence/Kconfig | 16 +
> > drivers/gpu/drm/bridge/cadence/Makefile | 2 +
> > .../drm/bridge/cadence/cdns-mhdp8501-core.c | 315 ++++++++
> > .../drm/bridge/cadence/cdns-mhdp8501-core.h | 365 +++++++++
> > .../gpu/drm/bridge/cadence/cdns-mhdp8501-dp.c | 708
> ++++++++++++++++++
> > .../drm/bridge/cadence/cdns-mhdp8501-hdmi.c | 673
> +++++++++++++++++
> > 6 files changed, 2079 insertions(+)
> > create mode 100644
> drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-core.c
> > create mode 100644
> drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-core.h
> > create mode 100644
> drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-dp.c
> > create mode 100644
> drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-hdmi.c
> >
> > diff --git a/drivers/gpu/drm/bridge/cadence/Kconfig
> > b/drivers/gpu/drm/bridge/cadence/Kconfig index
> 0b7b4626a7af0..81685ab4e874a
> > 100644
> > --- a/drivers/gpu/drm/bridge/cadence/Kconfig
> > +++ b/drivers/gpu/drm/bridge/cadence/Kconfig
> > @@ -50,3 +50,19 @@ config DRM_CDNS_MHDP8546_J721E
> > initializes the J721E Display Port and sets up the
> > clock and data muxes.
> > endif
> > +
> > +config DRM_CDNS_MHDP8501
> > + tristate "Cadence MHDP8501 DP/HDMI bridge"
> > + select DRM_KMS_HELPER
> > + select DRM_PANEL_BRIDGE
> > + select DRM_DISPLAY_DP_HELPER
> > + select DRM_DISPLAY_HELPER
> > + select CDNS_MHDP_HELPER
> > + select DRM_CDNS_AUDIO
> > + depends on OF
> > + help
> > + Support Cadence MHDP8501 DisplayPort/HDMI bridge.
> > + Cadence MHDP8501 support one or more protocols,
> > + including DisplayPort and HDMI.
> > + To use the DP and HDMI drivers, their respective
> > + specific firmware is required.
> > diff --git a/drivers/gpu/drm/bridge/cadence/Makefile
> > b/drivers/gpu/drm/bridge/cadence/Makefile index
> > 087dc074820d7..02c1a9f3cf6fc 100644
> > --- a/drivers/gpu/drm/bridge/cadence/Makefile
> > +++ b/drivers/gpu/drm/bridge/cadence/Makefile
> > @@ -6,3 +6,5 @@ obj-$(CONFIG_CDNS_MHDP_HELPER) +=
> cdns-mhdp-helper.o
> > obj-$(CONFIG_DRM_CDNS_MHDP8546) += cdns-mhdp8546.o
> > cdns-mhdp8546-y := cdns-mhdp8546-core.o cdns-mhdp8546-hdcp.o
> > cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) +=
> cdns-mhdp8546-j721e.o
> > +obj-$(CONFIG_DRM_CDNS_MHDP8501) += cdns-mhdp8501.o
> > +cdns-mhdp8501-y := cdns-mhdp8501-core.o cdns-mhdp8501-dp.o
> > cdns-mhdp8501-hdmi.o diff --git
> > a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-core.c
> > b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-core.c new file mode
> 100644
> > index 0000000000000..23860a260e637
> > --- /dev/null
> > +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-core.c
> > @@ -0,0 +1,315 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Cadence Display Port Interface (DP) driver
> > + *
> > + * Copyright (C) 2023 NXP Semiconductor, Inc.
> > + *
> > + */
> > +#include <drm/drm_of.h>
> > +#include <drm/drm_print.h>
> > +#include <linux/clk.h>
> > +#include <linux/irq.h>
> > +#include <linux/mutex.h>
> > +#include <linux/of_device.h>
> > +#include <linux/phy/phy.h>
> > +
> > +#include "cdns-mhdp8501-core.h"
> > +
> > +static int cdns_mhdp8501_read_hpd(struct cdns_mhdp8501_device
> *mhdp)
> > +{
> > + u8 status;
> > + int ret;
> > +
> > + mutex_lock(&mhdp->mbox_mutex);
> > +
> > + ret = cdns_mhdp_mailbox_send(&mhdp->base,
> MB_MODULE_ID_GENERAL,
> > + GENERAL_GET_HPD_STATE, 0,
> NULL);
> > + if (ret)
> > + goto err_get_hpd;
> > +
> > + ret = cdns_mhdp_mailbox_recv_header(&mhdp->base,
> MB_MODULE_ID_GENERAL,
> > +
> GENERAL_GET_HPD_STATE,
> > + sizeof(status));
> > + if (ret)
> > + goto err_get_hpd;
> > +
> > + ret = cdns_mhdp_mailbox_recv_data(&mhdp->base, &status,
> sizeof(status));
> > + if (ret)
> > + goto err_get_hpd;
> > +
> > + mutex_unlock(&mhdp->mbox_mutex);
> > +
> > + return status;
> > +
> > +err_get_hpd:
> > + DRM_ERROR("read hpd failed: %d\n", ret);
>
> Use dev_err() instead, there is a device pointer available.
OK.
>
> > + mutex_unlock(&mhdp->mbox_mutex);
> > +
> > + return ret;
> > +}
> > +
> > +enum drm_connector_status cdns_mhdp8501_detect(struct
> cdns_mhdp8501_device
> > *mhdp) +{
> > + u8 hpd = 0xf;
> > +
> > + hpd = cdns_mhdp8501_read_hpd(mhdp);
> > + if (hpd == 1)
> > + return connector_status_connected;
> > + else if (hpd == 0)
> > + return connector_status_disconnected;
> > +
> > + DRM_INFO("Unknown cable status, hdp=%u\n", hpd);
>
> I suppose this is a somewhat unexpected return value. Shouldn't this be
> DRM_WARN instead to indicate something went wrong?
> Despite that dev_warn (or dev_info) should be used.
OK, will use dev_warn.
>
> > + return connector_status_unknown;
> > +}
> > +
> > +static void hotplug_work_func(struct work_struct *work)
> > +{
> > + struct cdns_mhdp8501_device *mhdp = container_of(work,
> > + struct
> cdns_mhdp8501_device,
> > +
> hotplug_work.work);
> > + enum drm_connector_status status =
> cdns_mhdp8501_detect(mhdp);
> > +
> > + drm_bridge_hpd_notify(&mhdp->bridge, status);
> > +
> > + if (status == connector_status_connected) {
> > + /* Cable connedted */
>
> Small typo: Cable connected
OK, thanks.
>
> > + DRM_INFO("HDMI/DP Cable Plug In\n");
>
> drm_info()
>
> > + enable_irq(mhdp->irq[IRQ_OUT]);
> > + } else if (status == connector_status_disconnected) {
> > + /* Cable Disconnedted */
>
> Small typo: Cable Disconnected
OK.
>
> > + DRM_INFO("HDMI/DP Cable Plug Out\n");
>
> drm_info()
>
> > + enable_irq(mhdp->irq[IRQ_IN]);
> > + }
> > +}
> > +
> > +static irqreturn_t cdns_mhdp8501_irq_thread(int irq, void *data)
> > +{
> > + struct cdns_mhdp8501_device *mhdp = data;
> > +
> > + disable_irq_nosync(irq);
>
> Is it really necessary to enable/disable the IRQ_IN and IRQ_OUT interrupts
> upon each IRQ event?
There are no mask and status registers for IRQ_IN and IRQ_OUT, so they should not enable at the same time.
We has to disable one IRQ here and enable another in hotplug_work_func().
> The actual status is returned by the firmware using
> cdns_mhdp8501_read_hpd()
> anyway. There is a small window between the IRQ happening here and
> enabling
> the other one in hotplug_work_func() where an IRQ event is lost.
Yes, IRQ event will lost in the small window,
but the HPD status is not missing,
HDMI/DP firmware will keep updating latest HPD status in the windows,
then driver will get the correct status from FW by function cdns_mhdp8501_read_hpd() before enable IRQ.
> IMHO both IRQs should be enabled at all time and let
> cdns_mhdp8501_read_hpd()
> return whether the connector is connected or disconnected.
>
> > +
> > + mod_delayed_work(system_wq, &mhdp->hotplug_work,
> > + msecs_to_jiffies(HOTPLUG_DEBOUNCE_MS));
> > +
> > + return IRQ_HANDLED;
> > +}
> > +
> > +static int cdns_mhdp8501_dt_parse(struct cdns_mhdp8501_device
> *mhdp,
> > + struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct device_node *np = dev->of_node;
> > + struct device_node *remote;
> > +
> > + remote = of_graph_get_remote_node(np, 1, 0);
> > + if (!remote) {
> > + dev_err(dev, "fail to get remote node\n");
> > + of_node_put(remote);
> > + return -EINVAL;
> > + }
> > +
> > + /* get connector type */
> > + if (of_device_is_compatible(remote, "hdmi-connector")) {
> > + mhdp->connector_type =
> DRM_MODE_CONNECTOR_HDMIA;
> > +
> > + } else if (of_device_is_compatible(remote, "dp-connector")) {
> > + mhdp->connector_type =
> DRM_MODE_CONNECTOR_DisplayPort;
> > +
> > + } else {
> > + dev_err(dev, "Unknown connector type\n");
> > + of_node_put(remote);
> > + return -EINVAL;
> > + }
> > +
> > + of_node_put(remote);
> > + return true;
> > +}
> > +
> > +static void cdns_mhdp8501_add_bridge(struct cdns_mhdp8501_device
> *mhdp)
> > +{
> > + if (mhdp->connector_type == DRM_MODE_CONNECTOR_HDMIA) {
> > + mhdp->bridge.funcs = &cdns_hdmi_bridge_funcs;
> > + } else if (mhdp->connector_type ==
> DRM_MODE_CONNECTOR_DisplayPort) {
> > + mhdp->bridge.funcs = &cdns_dp_bridge_funcs;
> > + } else {
> > + dev_err(mhdp->dev, "Unsupported connector type!\n");
> > + return;
> > + }
> > +
> > + mhdp->bridge.type = mhdp->connector_type;
> > + mhdp->bridge.driver_private = mhdp;
> > + mhdp->bridge.of_node = mhdp->dev->of_node;
> > + mhdp->bridge.ops = DRM_BRIDGE_OP_DETECT |
> DRM_BRIDGE_OP_EDID |
> > + DRM_BRIDGE_OP_HPD;
> > + drm_bridge_add(&mhdp->bridge);
> > +}
> > +
> > +static int cdns_mhdp8501_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct cdns_mhdp8501_device *mhdp;
> > + struct resource *res;
> > + u32 reg;
> > + int ret;
> > +
> > + mhdp = devm_kzalloc(dev, sizeof(*mhdp), GFP_KERNEL);
> > + if (!mhdp)
> > + return -ENOMEM;
> > +
> > + mutex_init(&mhdp->mbox_mutex);
> > + mhdp->dev = dev;
> > +
> > + INIT_DELAYED_WORK(&mhdp->hotplug_work, hotplug_work_func);
> > +
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + if (!res)
> > + return -ENODEV;
> > +
> > + mhdp->regs = devm_ioremap(dev, res->start, resource_size(res));
> > + if (IS_ERR(mhdp->regs))
> > + return PTR_ERR(mhdp->regs);
>
> You can use devm_platform_ioremap_resource instead, no?
No, this base address should be share with PHY drivers.
>
> > +
> > + ret = cdns_mhdp8501_dt_parse(mhdp, pdev);
> > + if (ret < 0)
> > + return -EINVAL;
> > +
> > + mhdp->phy = devm_of_phy_get_by_index(dev, pdev->dev.of_node,
> 0);
> > + if (IS_ERR(mhdp->phy))
> > + return dev_err_probe(dev, PTR_ERR(mhdp->phy), "no PHY
> configured\n");
> > +
> > + mhdp->irq[IRQ_IN] = platform_get_irq_byname(pdev, "plug_in");
> > + if (mhdp->irq[IRQ_IN] < 0)
> > + return dev_err_probe(dev, mhdp->irq[IRQ_IN], "No
> plug_in
> irq number\n");
> > +
> > + mhdp->irq[IRQ_OUT] = platform_get_irq_byname(pdev,
> "plug_out");
> > + if (mhdp->irq[IRQ_OUT] < 0)
> > + return dev_err_probe(dev, mhdp->irq[IRQ_OUT], "No
> plug_out
> irq
> > number\n"); +
> > + irq_set_status_flags(mhdp->irq[IRQ_IN], IRQ_NOAUTOEN);
>
> As mentioned above both interrupts should be enabled at all the time.
Same reason as above.
>
> > + ret = devm_request_threaded_irq(dev, mhdp->irq[IRQ_IN],
> > + NULL,
> cdns_mhdp8501_irq_thread,
> > + IRQF_ONESHOT,
> dev_name(dev),
> mhdp);
> > + if (ret < 0) {
> > + dev_err(dev, "can't claim irq %d\n", mhdp->irq[IRQ_IN]);
> > + return -EINVAL;
> > + }
> > +
> > + irq_set_status_flags(mhdp->irq[IRQ_OUT], IRQ_NOAUTOEN);
>
> See above.
Same reason as above.
>
> > + ret = devm_request_threaded_irq(dev, mhdp->irq[IRQ_OUT],
> > + NULL,
> cdns_mhdp8501_irq_thread,
> > + IRQF_ONESHOT,
> dev_name(dev),
> mhdp);
> > + if (ret < 0) {
> > + dev_err(dev, "can't claim irq %d\n",
> mhdp->irq[IRQ_OUT]);
> > + return -EINVAL;
> > + }
> > +
> > + /* set default lane mapping */
> > + mhdp->lane_mapping = LANE_MAPPING_NORMAL;
> > +
> > + mhdp->plat_data = of_device_get_match_data(dev);
> > + if (mhdp->plat_data) {
> > + if (mhdp->connector_type ==
> DRM_MODE_CONNECTOR_DisplayPort)
> > + mhdp->lane_mapping = mhdp->plat_data-
> >dp_lane_mapping;
> > + else if (mhdp->connector_type ==
> DRM_MODE_CONNECTOR_HDMIA)
> > + mhdp->lane_mapping = mhdp->plat_data-
> >hdmi_lane_mapping;
> > + }
> > +
> > + dev_set_drvdata(dev, mhdp);
> > +
> > + /* init base struct for access mhdp mailbox */
> > + mhdp->base.dev = mhdp->dev;
> > + mhdp->base.regs = mhdp->regs;
> > + mhdp->base.mbox_mutex = &mhdp->mbox_mutex;
> > +
> > + if (mhdp->connector_type ==
> DRM_MODE_CONNECTOR_DisplayPort) {
> > + drm_dp_aux_init(&mhdp->dp.aux);
> > + mhdp->dp.aux.name = "mhdp8501_dp_aux";
> > + mhdp->dp.aux.dev = dev;
> > + mhdp->dp.aux.transfer = cdns_dp_aux_transfer;
> > + }
> > +
> > + /* Enable APB clock */
> > + mhdp->apb_clk = devm_clk_get(dev, NULL);
> > + if (IS_ERR(mhdp->apb_clk))
> > + return dev_err_probe(dev, PTR_ERR(mhdp->apb_clk),
> > + "couldn't get apb clk\n");
> > +
> > + clk_prepare_enable(mhdp->apb_clk);
> > +
> > + /*
> > + * Wait for the KEEP_ALIVE "message" on the first 8 bits.
> > + * Updated each sched "tick" (~2ms)
> > + */
> > + ret = readl_poll_timeout(mhdp->regs + KEEP_ALIVE, reg,
> > + reg & CDNS_KEEP_ALIVE_MASK,
> 500,
> > + CDNS_KEEP_ALIVE_TIMEOUT);
> > + if (ret) {
> > + dev_err(dev, "device didn't give any life sign: reg %d\n",
> reg);
> > + goto clk_disable;
> > + }
> > +
> > + /* Mailbox protect for HDMI PHY access */
> > + mutex_lock(&mhdp->mbox_mutex);
> > + ret = phy_init(mhdp->phy);
> > + mutex_unlock(&mhdp->mbox_mutex);
> > + if (ret) {
> > + dev_err(dev, "Failed to initialize PHY: %d\n", ret);
> > + goto clk_disable;
> > + }
> > +
> > + /* Enable cable hotplug detect */
> > + if (cdns_mhdp8501_read_hpd(mhdp))
> > + enable_irq(mhdp->irq[IRQ_OUT]);
> > + else
> > + enable_irq(mhdp->irq[IRQ_IN]);
> > +
> > + cdns_mhdp8501_add_bridge(mhdp);
> > +
> > + return 0;
> > +
> > +clk_disable:
> > + clk_disable_unprepare(mhdp->apb_clk);
> > +
> > + return -EINVAL;
> > +}
> > +
> > +static int cdns_mhdp8501_remove(struct platform_device *pdev)
> > +{
> > + struct cdns_mhdp8501_device *mhdp =
> platform_get_drvdata(pdev);
> > +
> > + if (mhdp->connector_type ==
> DRM_MODE_CONNECTOR_DisplayPort)
> > + cdns_dp_aux_destroy(mhdp);
> > +
> > + drm_bridge_remove(&mhdp->bridge);
> > + clk_disable_unprepare(mhdp->apb_clk);
> > +
> > + return 0;
> > +}
> > +
> > +static struct mhdp8501_plat_data imx8mq_mhdp_drv_data = {
> > + .hdmi_lane_mapping = LANE_MAPPING_FLIPPED,
> > + .dp_lane_mapping = LANE_MAPPING_IMX8MQ_DP,
> > +};
> > +
> > +static const struct of_device_id cdns_mhdp8501_dt_ids[] = {
> > + { .compatible = "fsl,imx8mq-mhdp8501",
> > + .data = &imx8mq_mhdp_drv_data
> > + },
> > + { },
> > +};
> > +MODULE_DEVICE_TABLE(of, cdns_mhdp8501_dt_ids);
> > +
> > +static struct platform_driver cdns_mhdp8501_driver = {
> > + .probe = cdns_mhdp8501_probe,
> > + .remove = cdns_mhdp8501_remove,
> > + .driver = {
> > + .name = "cdns-mhdp8501",
> > + .of_match_table = cdns_mhdp8501_dt_ids,
> > + },
> > +};
> > +
> > +module_platform_driver(cdns_mhdp8501_driver);
> > +
> > +MODULE_AUTHOR("Sandor Yu <sandor.yu@nxp.com>");
> > +MODULE_DESCRIPTION("Cadence MHDP8501 bridge driver");
> > +MODULE_LICENSE("GPL");
> > diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-core.h
> > b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-core.h new file mode
> 100644
> > index 0000000000000..97170be57ffcb
> > --- /dev/null
> > +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-core.h
> > @@ -0,0 +1,365 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * Cadence MHDP 8501 Common head file
> > + *
> > + * Copyright (C) 2019-2023 NXP Semiconductor, Inc.
> > + *
> > + */
> > +
> > +#ifndef _CDNS_MHDP8501_CORE_H_
> > +#define _CDNS_MHDP8501_CORE_H_
> > +
> > +#include <drm/bridge/cdns-mhdp-helper.h>
> > +#include <drm/drm_bridge.h>
> > +#include <drm/drm_connector.h>
> > +#include <drm/display/drm_dp_helper.h>
> > +#include <linux/bitops.h>
> > +
> > +#define ADDR_IMEM 0x10000
> > +#define ADDR_DMEM 0x20000
> > +
> > +/* APB CFG addr */
> > +#define APB_CTRL 0
> > +#define XT_INT_CTRL 0x04
> > +#define MAILBOX_FULL_ADDR 0x08
> > +#define MAILBOX_EMPTY_ADDR 0x0c
> > +#define MAILBOX0_WR_DATA 0x10
> > +#define MAILBOX0_RD_DATA 0x14
> > +#define KEEP_ALIVE 0x18
> > +#define VER_L 0x1c
> > +#define VER_H 0x20
> > +#define VER_LIB_L_ADDR 0x24
> > +#define VER_LIB_H_ADDR 0x28
> > +#define SW_DEBUG_L 0x2c
> > +#define SW_DEBUG_H 0x30
> > +#define MAILBOX_INT_MASK 0x34
> > +#define MAILBOX_INT_STATUS 0x38
> > +#define SW_CLK_L 0x3c
> > +#define SW_CLK_H 0x40
> > +#define SW_EVENTS0 0x44
> > +#define SW_EVENTS1 0x48
> > +#define SW_EVENTS2 0x4c
> > +#define SW_EVENTS3 0x50
> > +#define XT_OCD_CTRL 0x60
> > +#define APB_INT_MASK 0x6c
> > +#define APB_STATUS_MASK 0x70
> > +
> > +/* Source phy comp */
> > +#define PHY_DATA_SEL 0x0818
> > +#define LANES_CONFIG 0x0814
> > +
> > +/* Source CAR Addr */
> > +#define SOURCE_HDTX_CAR 0x0900
> > +#define SOURCE_DPTX_CAR 0x0904
> > +#define SOURCE_PHY_CAR 0x0908
> > +#define SOURCE_CEC_CAR 0x090c
> > +#define SOURCE_CBUS_CAR 0x0910
> > +#define SOURCE_PKT_CAR 0x0918
> > +#define SOURCE_AIF_CAR 0x091c
> > +#define SOURCE_CIPHER_CAR 0x0920
> > +#define SOURCE_CRYPTO_CAR 0x0924
> > +
> > +/* clock meters addr */
> > +#define CM_CTRL 0x0a00
> > +#define CM_I2S_CTRL 0x0a04
> > +#define CM_SPDIF_CTRL 0x0a08
> > +#define CM_VID_CTRL 0x0a0c
> > +#define CM_LANE_CTRL 0x0a10
> > +#define I2S_NM_STABLE 0x0a14
> > +#define I2S_NCTS_STABLE 0x0a18
> > +#define SPDIF_NM_STABLE 0x0a1c
> > +#define SPDIF_NCTS_STABLE 0x0a20
> > +#define NMVID_MEAS_STABLE 0x0a24
> > +#define I2S_MEAS 0x0a40
> > +#define SPDIF_MEAS 0x0a80
> > +#define NMVID_MEAS 0x0ac0
> > +
> > +/* source vif addr */
> > +#define BND_HSYNC2VSYNC 0x0b00
> > +#define HSYNC2VSYNC_F1_L1 0x0b04
> > +#define HSYNC2VSYNC_STATUS 0x0b0c
> > +#define HSYNC2VSYNC_POL_CTRL 0x0b10
> > +
> > +/* MHDP TX_top_comp */
> > +#define SCHEDULER_H_SIZE 0x1000
> > +#define SCHEDULER_V_SIZE 0x1004
> > +#define HDTX_SIGNAL_FRONT_WIDTH 0x100c
> > +#define HDTX_SIGNAL_SYNC_WIDTH 0x1010
> > +#define HDTX_SIGNAL_BACK_WIDTH 0x1014
> > +#define HDTX_CONTROLLER 0x1018
> > +#define HDTX_HPD 0x1020
> > +#define HDTX_CLOCK_REG_0 0x1024
> > +#define HDTX_CLOCK_REG_1 0x1028
> > +
> > +/* DPTX hpd addr */
> > +#define HPD_IRQ_DET_MIN_TIMER 0x2100
> > +#define HPD_IRQ_DET_MAX_TIMER 0x2104
> > +#define HPD_UNPLGED_DET_MIN_TIMER 0x2108
> > +#define HPD_STABLE_TIMER 0x210c
> > +#define HPD_FILTER_TIMER 0x2110
> > +#define HPD_EVENT_MASK 0x211c
> > +#define HPD_EVENT_DET 0x2120
> > +
> > +/* DPTX framer addr */
> > +#define DP_FRAMER_GLOBAL_CONFIG 0x2200
> > +#define DP_SW_RESET 0x2204
> > +#define DP_FRAMER_TU 0x2208
> > +#define DP_FRAMER_PXL_REPR 0x220c
> > +#define DP_FRAMER_SP 0x2210
> > +#define AUDIO_PACK_CONTROL 0x2214
> > +#define DP_VC_TABLE(x) (0x2218 + ((x) << 2))
> > +#define DP_VB_ID 0x2258
> > +#define DP_MTPH_LVP_CONTROL 0x225c
> > +#define DP_MTPH_SYMBOL_VALUES 0x2260
> > +#define DP_MTPH_ECF_CONTROL 0x2264
> > +#define DP_MTPH_ACT_CONTROL 0x2268
> > +#define DP_MTPH_STATUS 0x226c
> > +#define DP_INTERRUPT_SOURCE 0x2270
> > +#define DP_INTERRUPT_MASK 0x2274
> > +#define DP_FRONT_BACK_PORCH 0x2278
> > +#define DP_BYTE_COUNT 0x227c
> > +
> > +/* DPTX stream addr */
> > +#define MSA_HORIZONTAL_0 0x2280
> > +#define MSA_HORIZONTAL_1 0x2284
> > +#define MSA_VERTICAL_0 0x2288
> > +#define MSA_VERTICAL_1 0x228c
> > +#define MSA_MISC 0x2290
> > +#define STREAM_CONFIG 0x2294
> > +#define AUDIO_PACK_STATUS 0x2298
> > +#define VIF_STATUS 0x229c
> > +#define PCK_STUFF_STATUS_0 0x22a0
> > +#define PCK_STUFF_STATUS_1 0x22a4
> > +#define INFO_PACK_STATUS 0x22a8
> > +#define RATE_GOVERNOR_STATUS 0x22ac
> > +#define DP_HORIZONTAL 0x22b0
> > +#define DP_VERTICAL_0 0x22b4
> > +#define DP_VERTICAL_1 0x22b8
> > +#define DP_BLOCK_SDP 0x22bc
> > +
> > +/* DPTX glbl addr */
> > +#define DPTX_LANE_EN 0x2300
> > +#define DPTX_ENHNCD 0x2304
> > +#define DPTX_INT_MASK 0x2308
> > +#define DPTX_INT_STATUS 0x230c
> > +
> > +/* DP AUX Addr */
> > +#define DP_AUX_HOST_CONTROL 0x2800
> > +#define DP_AUX_INTERRUPT_SOURCE 0x2804
> > +#define DP_AUX_INTERRUPT_MASK 0x2808
> > +#define DP_AUX_SWAP_INVERSION_CONTROL 0x280c
> > +#define DP_AUX_SEND_NACK_TRANSACTION 0x2810
> > +#define DP_AUX_CLEAR_RX 0x2814
> > +#define DP_AUX_CLEAR_TX 0x2818
> > +#define DP_AUX_TIMER_STOP 0x281c
> > +#define DP_AUX_TIMER_CLEAR 0x2820
> > +#define DP_AUX_RESET_SW 0x2824
> > +#define DP_AUX_DIVIDE_2M 0x2828
> > +#define DP_AUX_TX_PREACHARGE_LENGTH 0x282c
> > +#define DP_AUX_FREQUENCY_1M_MAX 0x2830
> > +#define DP_AUX_FREQUENCY_1M_MIN 0x2834
> > +#define DP_AUX_RX_PRE_MIN 0x2838
> > +#define DP_AUX_RX_PRE_MAX 0x283c
> > +#define DP_AUX_TIMER_PRESET 0x2840
> > +#define DP_AUX_NACK_FORMAT 0x2844
> > +#define DP_AUX_TX_DATA 0x2848
> > +#define DP_AUX_RX_DATA 0x284c
> > +#define DP_AUX_TX_STATUS 0x2850
> > +#define DP_AUX_RX_STATUS 0x2854
> > +#define DP_AUX_RX_CYCLE_COUNTER 0x2858
> > +#define DP_AUX_MAIN_STATES 0x285c
> > +#define DP_AUX_MAIN_TIMER 0x2860
> > +#define DP_AUX_AFE_OUT 0x2864
> > +
> > +/* source pif addr */
> > +#define SOURCE_PIF_WR_ADDR 0x30800
> > +#define SOURCE_PIF_WR_REQ 0x30804
> > +#define SOURCE_PIF_RD_ADDR 0x30808
> > +#define SOURCE_PIF_RD_REQ 0x3080c
> > +#define SOURCE_PIF_DATA_WR 0x30810
> > +#define SOURCE_PIF_DATA_RD 0x30814
> > +#define SOURCE_PIF_FIFO1_FLUSH 0x30818
> > +#define SOURCE_PIF_FIFO2_FLUSH 0x3081c
> > +#define SOURCE_PIF_STATUS 0x30820
> > +#define SOURCE_PIF_INTERRUPT_SOURCE 0x30824
> > +#define SOURCE_PIF_INTERRUPT_MASK 0x30828
> > +#define SOURCE_PIF_PKT_ALLOC_REG 0x3082c
> > +#define SOURCE_PIF_PKT_ALLOC_WR_EN 0x30830
> > +#define SOURCE_PIF_SW_RESET 0x30834
> > +
> > +#define LINK_TRAINING_NOT_ACTIV 0
> > +#define LINK_TRAINING_RUN 1
> > +#define LINK_TRAINING_RESTART 2
> > +
> > +#define CONTROL_VIDEO_IDLE 0
> > +#define CONTROL_VIDEO_VALID 1
> > +
> > +#define INTERLACE_FMT_DET BIT(12)
> > +#define VIF_BYPASS_INTERLACE BIT(13)
> > +#define TU_CNT_RST_EN BIT(15)
> > +#define INTERLACE_DTCT_WIN 0x20
> > +
> > +#define DP_FRAMER_SP_INTERLACE_EN BIT(2)
> > +#define DP_FRAMER_SP_HSP BIT(1)
> > +#define DP_FRAMER_SP_VSP BIT(0)
> > +
> > +/* Capability */
> > +#define AUX_HOST_INVERT 3
> > +#define FAST_LT_SUPPORT 1
> > +#define FAST_LT_NOT_SUPPORT 0
> > +#define LANE_MAPPING_NORMAL 0x1b
> > +#define LANE_MAPPING_FLIPPED 0xe4
> > +#define LANE_MAPPING_IMX8MQ_DP 0xc6
> > +#define ENHANCED 1
> > +#define SCRAMBLER_EN BIT(4)
> > +
> > +#define FULL_LT_STARTED BIT(0)
> > +#define FASE_LT_STARTED BIT(1)
> > +#define CLK_RECOVERY_FINISHED BIT(2)
> > +#define EQ_PHASE_FINISHED BIT(3)
> > +#define FASE_LT_START_FINISHED BIT(4)
> > +#define CLK_RECOVERY_FAILED BIT(5)
> > +#define EQ_PHASE_FAILED BIT(6)
> > +#define FASE_LT_FAILED BIT(7)
> > +
> > +#define TU_SIZE 30
> > +#define CDNS_DP_MAX_LINK_RATE 540000
> > +
> > +#define F_HDMI_ENCODING(x) (((x) & ((1 << 2) - 1)) << 16)
> > +#define F_VIF_DATA_WIDTH(x) (((x) & ((1 << 2) - 1)) << 2)
> > +#define F_HDMI_MODE(x) (((x) & ((1 << 2) - 1)) << 0)
> > +#define F_GCP_EN(x) (((x) & ((1 << 1) - 1)) << 12)
> > +#define F_DATA_EN(x) (((x) & ((1 << 1) - 1)) << 15)
> > +#define F_HDMI2_PREAMBLE_EN(x) (((x) & ((1 << 1) - 1)) << 18)
> > +#define F_PIC_3D(x) (((x) & ((1 << 4) - 1)) << 7)
> > +#define F_BCH_EN(x) (((x) & ((1 << 1) - 1)) << 11)
> > +#define F_SOURCE_PHY_MHDP_SEL(x) (((x) & ((1 << 2) - 1)) << 3)
> > +#define F_HPD_VALID_WIDTH(x) (((x) & ((1 << 12) - 1)) << 0)
> > +#define F_HPD_GLITCH_WIDTH(x) (((x) & ((1 << 8) - 1)) << 12)
> > +#define F_HDMI2_CTRL_IL_MODE(x) (((x) & ((1 << 1) - 1)) << 19)
> > +#define F_SOURCE_PHY_LANE0_SWAP(x) (((x) & ((1 << 2) - 1)) << 0)
> > +#define F_SOURCE_PHY_LANE1_SWAP(x) (((x) & ((1 << 2) - 1)) << 2)
> > +#define F_SOURCE_PHY_LANE2_SWAP(x) (((x) & ((1 << 2) - 1)) << 4)
> > +#define F_SOURCE_PHY_LANE3_SWAP(x) (((x) & ((1 << 2) - 1)) << 6)
> > +#define F_SOURCE_PHY_COMB_BYPASS(x) (((x) & ((1 << 1) - 1)) << 21)
> > +#define F_SOURCE_PHY_20_10(x) (((x) & ((1 << 1) - 1)) << 22)
> > +#define F_PKT_ALLOC_ADDRESS(x) (((x) & ((1 << 4) - 1)) << 0)
> > +#define F_ACTIVE_IDLE_TYPE(x) (((x) & ((1 << 1) - 1)) << 17)
> > +#define F_FIFO1_FLUSH(x) (((x) & ((1 << 1) - 1)) << 0)
> > +#define F_PKT_ALLOC_WR_EN(x) (((x) & ((1 << 1) - 1)) << 0)
> > +#define F_DATA_WR(x) (x)
> > +#define F_WR_ADDR(x) (((x) & ((1 << 4) - 1)) << 0)
> > +#define F_HOST_WR(x) (((x) & ((1 << 1) - 1)) << 0)
> > +#define F_TYPE_VALID(x) (((x) & ((1 << 1) - 1)) << 16)
> > +#define F_PACKET_TYPE(x) (((x) & ((1 << 8) - 1)) << 8)
> > +
> > +/* Reference cycles when using lane clock as reference */
> > +#define LANE_REF_CYC 0x8000
> > +
> > +/* HPD Debounce */
> > +#define HOTPLUG_DEBOUNCE_MS 200
> > +
> > +/* HPD IRQ Index */
> > +#define IRQ_IN 0
> > +#define IRQ_OUT 1
> > +#define IRQ_NUM 2
> > +
> > +/* FW check alive timeout */
> > +#define CDNS_KEEP_ALIVE_TIMEOUT 2000
> > +#define CDNS_KEEP_ALIVE_MASK GENMASK(7, 0)
> > +
> > +enum voltage_swing_level {
> > + VOLTAGE_LEVEL_0,
> > + VOLTAGE_LEVEL_1,
> > + VOLTAGE_LEVEL_2,
> > + VOLTAGE_LEVEL_3,
> > +};
> > +
> > +enum pre_emphasis_level {
> > + PRE_EMPHASIS_LEVEL_0,
> > + PRE_EMPHASIS_LEVEL_1,
> > + PRE_EMPHASIS_LEVEL_2,
> > + PRE_EMPHASIS_LEVEL_3,
> > +};
> > +
> > +enum pattern_set {
> > + PTS1 = BIT(0),
> > + PTS2 = BIT(1),
> > + PTS3 = BIT(2),
> > + PTS4 = BIT(3),
> > + DP_NONE = BIT(4)
> > +};
> > +
> > +enum vic_color_depth {
> > + BCS_6 = 0x1,
> > + BCS_8 = 0x2,
> > + BCS_10 = 0x4,
> > + BCS_12 = 0x8,
> > + BCS_16 = 0x10,
> > +};
> > +
> > +enum vic_bt_type {
> > + BT_601 = 0x0,
> > + BT_709 = 0x1,
> > +};
> > +
> > +enum {
> > + MODE_DVI,
> > + MODE_HDMI_1_4,
> > + MODE_HDMI_2_0,
> > +};
> > +
> > +struct video_info {
> > + int bpc;
> > + int color_fmt;
> > +};
> > +
> > +struct mhdp8501_plat_data {
> > + int hdmi_lane_mapping;
> > + int dp_lane_mapping;
> > +};
> > +
> > +struct cdns_mhdp8501_device {
> > + struct cdns_mhdp_base base;
> > +
> > + struct device *dev;
> > + void __iomem *regs;
> > + struct drm_connector *curr_conn;
> > + struct drm_bridge bridge;
> > + struct clk *apb_clk;
> > + struct phy *phy;
> > +
> > + struct video_info video_info;
> > + struct drm_display_mode mode;
> > +
> > + int irq[IRQ_NUM];
> > + struct delayed_work hotplug_work;
> > + int connector_type;
> > + u32 lane_mapping;
> > +
> > + /* protect mailbox communications with the firmware */
> > + struct mutex mbox_mutex;
> > +
> > + const struct mhdp8501_plat_data *plat_data;
> > +
> > + union {
> > + struct _dp_data {
> > + u32 rate;
> > + u8 num_lanes;
> > + struct drm_dp_aux aux;
> > + u8 dpcd[DP_RECEIVER_CAP_SIZE];
> > + } dp;
> > + struct _hdmi_data {
> > + u32 hdmi_type;
> > + } hdmi;
> > + };
> > +};
> > +
> > +extern const struct drm_bridge_funcs cdns_dp_bridge_funcs;
> > +extern const struct drm_bridge_funcs cdns_hdmi_bridge_funcs;
> > +
> > +ssize_t cdns_dp_aux_transfer(struct drm_dp_aux *aux, struct
> drm_dp_aux_msg
> > *msg); +enum drm_connector_status cdns_mhdp8501_detect(struct
> > cdns_mhdp8501_device *mhdp); +int cdns_dp_aux_destroy(struct
> > cdns_mhdp8501_device *mhdp);
> > +
> > +#endif
> > diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-dp.c
> > b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-dp.c new file mode
> 100644
> > index 0000000000000..5576db967cac6
> > --- /dev/null
> > +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-dp.c
> > @@ -0,0 +1,708 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Cadence MHDP8501 DisplayPort(DP) bridge driver
> > + *
> > + * Copyright (C) 2019-2023 NXP Semiconductor, Inc.
> > + *
> > + */
> > +#include <drm/drm_atomic_helper.h>
> > +#include <drm/drm_edid.h>
> > +#include <drm/drm_print.h>
> > +#include <linux/phy/phy.h>
> > +#include <linux/phy/phy-dp.h>
> > +
> > +#include "cdns-mhdp8501-core.h"
> > +
> > +#define LINK_TRAINING_TIMEOUT_MS 500
> > +#define LINK_TRAINING_RETRY_MS 20
> > +
> > +ssize_t cdns_dp_aux_transfer(struct drm_dp_aux *aux,
> > + struct drm_dp_aux_msg *msg)
> > +{
> > + struct cdns_mhdp8501_device *mhdp =
> dev_get_drvdata(aux->dev);
> > + bool native = msg->request & (DP_AUX_NATIVE_WRITE &
> DP_AUX_NATIVE_READ);
> > + int ret;
> > +
> > + /* Ignore address only message */
> > + if (!msg->size || !msg->buffer) {
> > + msg->reply = native ?
> > + DP_AUX_NATIVE_REPLY_ACK :
> DP_AUX_I2C_REPLY_ACK;
> > + return msg->size;
> > + }
> > +
> > + if (!native) {
> > + dev_err(mhdp->dev, "%s: only native messages
> supported\n",
> __func__);
> > + return -EINVAL;
> > + }
> > +
> > + /* msg sanity check */
> > + if (msg->size > DP_AUX_MAX_PAYLOAD_BYTES) {
> > + dev_err(mhdp->dev, "%s: invalid msg: size(%zu),
> request(%x)\n",
> > + __func__, msg->size, (unsigned int)msg-
> >request);
> > + return -EINVAL;
> > + }
> > +
> > + if (msg->request == DP_AUX_NATIVE_WRITE) {
> > + const u8 *buf = msg->buffer;
> > + int i;
> > +
> > + for (i = 0; i < msg->size; ++i) {
> > + ret = cdns_mhdp_dpcd_write(&mhdp->base,
> > + msg->address
> +
> i, buf[i]);
> > + if (!ret)
> > + continue;
>
> I personally don't like this style. I would prefer checking for 'if (ret)' to
> bail out in error case.
OK.
>
> > + DRM_DEV_ERROR(mhdp->dev, "Failed to write
> DPCD\n");
>
> Please replace all DRM_ macros, see [1] for details. As you don't have a
> drm_dev you will most probably need a dev_err & friends.
OK I will do it.
>
> > +
> > + return ret;
> > + }
> > + msg->reply = DP_AUX_NATIVE_REPLY_ACK;
> > + return msg->size;
> > + }
> > +
> > + if (msg->request == DP_AUX_NATIVE_READ) {
> > + ret = cdns_mhdp_dpcd_read(&mhdp->base,
> msg->address,
> > + msg->buffer, msg->size);
> > + if (ret < 0)
> > + return -EIO;
>
> Any specific reason to return -EIO instead of ret? You return ret in case of
> error from cdns_mhdp_dpcd_write as well.
No, will return ret in next version.
>
> > + msg->reply = DP_AUX_NATIVE_REPLY_ACK;
> > + return msg->size;
> > + }
> > + return 0;
> > +}
> > +
> > +int cdns_dp_aux_destroy(struct cdns_mhdp8501_device *mhdp)
> > +{
> > + drm_dp_aux_unregister(&mhdp->dp.aux);
> > +
> > + return 0;
> > +}
> > +
> > +static int cdns_dp_get_msa_misc(struct video_info *video,
> > + struct drm_display_mode *mode)
>
> mode is unused.
OK will remove it.
>
> > +{
> > + u32 msa_misc;
> > + u8 val[2] = {0};
>
> Please use two separate variables for color space and bpc.
OK.
>
> > +
> > + switch (video->color_fmt) {
> > + /* set YUV default color space conversion to BT601 */
> > + case DRM_COLOR_FORMAT_YCBCR444:
> > + val[0] = 6 + BT_601 * 8;
> > + break;
> > + case DRM_COLOR_FORMAT_YCBCR422:
> > + val[0] = 5 + BT_601 * 8;
> > + break;
> > + case DRM_COLOR_FORMAT_YCBCR420:
> > + val[0] = 5;
> > + break;
> > + case DRM_COLOR_FORMAT_RGB444:
> > + default:
> > + val[0] = 0;
> > + break;
> > + };
> > +
> > + switch (video->bpc) {
> > + case 6:
> > + val[1] = 0;
> > + break;
> > + case 10:
> > + val[1] = 2;
> > + break;
> > + case 12:
> > + val[1] = 3;
> > + break;
> > + case 16:
> > + val[1] = 4;
> > + break;
> > + case 8:
> > + default:
> > + val[1] = 1;
> > + break;
> > + };
> > +
> > + msa_misc = 2 * val[0] + 32 * val[1];
>
> Is this multiplication intended to do bit shifting?
Yes, it will replace by bit shifting.
>
> > +
> > + return msa_misc;
> > +}
> > +
> > +static int cdns_dp_config_video(struct cdns_mhdp8501_device *mhdp)
> > +{
> > + struct video_info *video = &mhdp->video_info;
> > + struct drm_display_mode *mode = &mhdp->mode;
> > + bool h_sync_polarity, v_sync_polarity;
> > + u64 symbol;
> > + u32 val, link_rate, rem;
> > + u8 bit_per_pix, tu_size_reg = TU_SIZE;
> > + int ret;
> > +
> > + bit_per_pix = (video->color_fmt ==
> DRM_COLOR_FORMAT_YCBCR422) ?
> > + (video->bpc * 2) : (video->bpc * 3);
> > +
> > + link_rate = mhdp->dp.rate / 1000;
> > +
> > + ret = cdns_mhdp_reg_write(&mhdp->base, BND_HSYNC2VSYNC,
> > VIF_BYPASS_INTERLACE); + if (ret)
> > + goto err_config_video;
> > +
> > + ret = cdns_mhdp_reg_write(&mhdp->base,
> HSYNC2VSYNC_POL_CTRL, 0);
> > + if (ret)
> > + goto err_config_video;
> > +
> > + /*
> > + * get a best tu_size and valid symbol:
> > + * 1. chose Lclk freq(162Mhz, 270Mhz, 540Mhz), set TU to 32
> > + * 2. calculate VS(valid symbol) = TU * Pclk * Bpp / (Lclk * Lanes)
> > + * 3. if VS > *.85 or VS < *.1 or VS < 2 or TU < VS + 4, then set
> > + * TU += 2 and repeat 2nd step.
> > + */
> > + do {
> > + tu_size_reg += 2;
> > + symbol = tu_size_reg * mode->clock * bit_per_pix;
> > + do_div(symbol, mhdp->dp.num_lanes * link_rate * 8);
> > + rem = do_div(symbol, 1000);
> > + if (tu_size_reg > 64) {
> > + ret = -EINVAL;
> > + DRM_DEV_ERROR(mhdp->dev,
> > + "tu error, clk:%d, lanes:%d,
> rate:%d\n",
> > + mode->clock,
> mhdp->dp.num_lanes,
> link_rate);
> > + goto err_config_video;
> > + }
> > + } while ((symbol <= 1) || (tu_size_reg - symbol < 4) ||
> > + (rem > 850) || (rem < 100));
> > +
> > + val = symbol + (tu_size_reg << 8);
> > + val |= TU_CNT_RST_EN;
> > + ret = cdns_mhdp_reg_write(&mhdp->base, DP_FRAMER_TU, val);
> > + if (ret)
> > + goto err_config_video;
> > +
> > + /* set the FIFO Buffer size */
> > + val = div_u64(mode->clock * (symbol + 1), 1000) + link_rate;
> > + val /= (mhdp->dp.num_lanes * link_rate);
> > + val = div_u64(8 * (symbol + 1), bit_per_pix) - val;
> > + val += 2;
> > + ret = cdns_mhdp_reg_write(&mhdp->base, DP_VC_TABLE(15), val);
> > +
> > + switch (video->bpc) {
> > + case 6:
> > + val = BCS_6;
> > + break;
> > + case 10:
> > + val = BCS_10;
> > + break;
> > + case 12:
> > + val = BCS_12;
> > + break;
> > + case 16:
> > + val = BCS_16;
> > + break;
> > + case 8:
> > + default:
> > + val = BCS_8;
> > + break;
> > + };
> > +
> > + val += video->color_fmt << 8;
> > + ret = cdns_mhdp_reg_write(&mhdp->base, DP_FRAMER_PXL_REPR,
> val);
> > + if (ret)
> > + goto err_config_video;
> > +
> > + v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
> > + h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
> > +
> > + val = h_sync_polarity ? DP_FRAMER_SP_HSP : 0;
> > + val |= v_sync_polarity ? DP_FRAMER_SP_VSP : 0;
> > + ret = cdns_mhdp_reg_write(&mhdp->base, DP_FRAMER_SP, val);
> > + if (ret)
> > + goto err_config_video;
> > +
> > + val = (mode->hsync_start - mode->hdisplay) << 16;
> > + val |= mode->htotal - mode->hsync_end;
> > + ret = cdns_mhdp_reg_write(&mhdp->base,
> DP_FRONT_BACK_PORCH, val);
> > + if (ret)
> > + goto err_config_video;
> > +
> > + val = mode->hdisplay * bit_per_pix / 8;
> > + ret = cdns_mhdp_reg_write(&mhdp->base, DP_BYTE_COUNT, val);
> > + if (ret)
> > + goto err_config_video;
> > +
> > + val = mode->htotal | ((mode->htotal - mode->hsync_start) << 16);
> > + ret = cdns_mhdp_reg_write(&mhdp->base, MSA_HORIZONTAL_0,
> val);
> > + if (ret)
> > + goto err_config_video;
> > +
> > + val = mode->hsync_end - mode->hsync_start;
> > + val |= (mode->hdisplay << 16) | (h_sync_polarity << 15);
> > + ret = cdns_mhdp_reg_write(&mhdp->base, MSA_HORIZONTAL_1,
> val);
> > + if (ret)
> > + goto err_config_video;
> > +
> > + val = mode->vtotal;
> > + val |= (mode->vtotal - mode->vsync_start) << 16;
> > + ret = cdns_mhdp_reg_write(&mhdp->base, MSA_VERTICAL_0, val);
> > + if (ret)
> > + goto err_config_video;
> > +
> > + val = mode->vsync_end - mode->vsync_start;
> > + val |= (mode->vdisplay << 16) | (v_sync_polarity << 15);
> > + ret = cdns_mhdp_reg_write(&mhdp->base, MSA_VERTICAL_1, val);
> > + if (ret)
> > + goto err_config_video;
> > +
> > + val = cdns_dp_get_msa_misc(video, mode);
> > + ret = cdns_mhdp_reg_write(&mhdp->base, MSA_MISC, val);
> > + if (ret)
> > + goto err_config_video;
> > +
> > + ret = cdns_mhdp_reg_write(&mhdp->base, STREAM_CONFIG, 1);
> > + if (ret)
> > + goto err_config_video;
> > +
> > + val = mode->hsync_end - mode->hsync_start;
> > + val |= mode->hdisplay << 16;
> > + ret = cdns_mhdp_reg_write(&mhdp->base, DP_HORIZONTAL, val);
> > + if (ret)
> > + goto err_config_video;
> > +
> > + val = mode->vdisplay;
> > + val |= (mode->vtotal - mode->vsync_start) << 16;
> > + ret = cdns_mhdp_reg_write(&mhdp->base, DP_VERTICAL_0, val);
> > + if (ret)
> > + goto err_config_video;
> > +
> > + val = mode->vtotal;
> > + ret = cdns_mhdp_reg_write(&mhdp->base, DP_VERTICAL_1, val);
> > + if (ret)
> > + goto err_config_video;
> > +
> > + ret = cdns_mhdp_dp_reg_write_bit(&mhdp->base, DP_VB_ID, 2, 1,
> 0);
> > +
> > +err_config_video:
> > + if (ret)
> > + DRM_DEV_ERROR(mhdp->dev, "config video
> failed: %d\n",
> ret);
> > + return ret;
> > +}
> > +
> > +static void cdns_dp_pixel_clk_reset(struct cdns_mhdp8501_device *mhdp)
> > +{
> > + u32 val;
> > +
> > + /* reset pixel clk */
> > + cdns_mhdp_reg_read(&mhdp->base, SOURCE_HDTX_CAR, &val);
> > + cdns_mhdp_reg_write(&mhdp->base, SOURCE_HDTX_CAR, val &
> 0xFD);
> > + cdns_mhdp_reg_write(&mhdp->base, SOURCE_HDTX_CAR, val);
> > +}
> > +
> > +static int cdns_dp_set_video_status(struct cdns_mhdp8501_device *mhdp,
> int
> > active) +{
> > + u8 msg;
> > + int ret;
> > +
> > + msg = !!active;
> > +
> > + mutex_lock(&mhdp->mbox_mutex);
> > +
> > + ret = cdns_mhdp_mailbox_send(&mhdp->base,
> MB_MODULE_ID_DP_TX,
> > DPTX_SET_VIDEO, + sizeof(msg),
> &msg);
> > + if (ret)
> > + DRM_DEV_ERROR(mhdp->dev, "set video status
> failed: %d\n",
> ret);
> > +
> > + mutex_unlock(&mhdp->mbox_mutex);
> > +
> > + return ret;
> > +}
> > +
> > +static int cdns_dp_training_start(struct cdns_mhdp8501_device *mhdp)
> > +{
> > + unsigned long timeout;
> > + u8 msg, event[2];
> > + int ret;
> > +
> > + msg = LINK_TRAINING_RUN;
> > +
> > + mutex_lock(&mhdp->mbox_mutex);
> > +
> > + /* start training */
> > + ret = cdns_mhdp_mailbox_send(&mhdp->base,
> MB_MODULE_ID_DP_TX,
> > + DPTX_TRAINING_CONTROL,
> sizeof(msg), &msg);
> > + if (ret)
> > + goto err_training_start;
> > +
> > + timeout = jiffies + msecs_to_jiffies(LINK_TRAINING_TIMEOUT_MS);
> > + while (time_before(jiffies, timeout)) {
> > + msleep(LINK_TRAINING_RETRY_MS);
> > + ret = cdns_mhdp_mailbox_send(&mhdp->base,
> MB_MODULE_ID_DP_TX,
> > + DPTX_READ_EVENT,
> 0,
> NULL);
> > + if (ret)
> > + goto err_training_start;
> > +
> > + ret = cdns_mhdp_mailbox_recv_header(&mhdp->base,
> MB_MODULE_ID_DP_TX,
> > +
> DPTX_READ_EVENT, sizeof(event));
> > + if (ret)
> > + goto err_training_start;
> > +
> > + ret = cdns_mhdp_mailbox_recv_data(&mhdp->base,
> event,
> sizeof(event));
> > + if (ret)
> > + goto err_training_start;
> > +
> > + if (event[1] & CLK_RECOVERY_FAILED) {
> > + DRM_DEV_ERROR(mhdp->dev, "clock recovery
> failed\n");
> > + } else if (event[1] & EQ_PHASE_FINISHED) {
> > + mutex_unlock(&mhdp->mbox_mutex);
> > + return 0;
> > + }
> > + }
> > +
> > + ret = -ETIMEDOUT;
> > +
> > +err_training_start:
> > + mutex_unlock(&mhdp->mbox_mutex);
> > +
> > + DRM_DEV_ERROR(mhdp->dev, "training failed: %d\n", ret);
> > + return ret;
> > +}
> > +
> > +static int cdns_dp_get_training_status(struct cdns_mhdp8501_device
> *mhdp)
> > +{
> > + u8 status[13];
> > + int ret;
> > +
> > + mutex_lock(&mhdp->mbox_mutex);
> > +
> > + ret = cdns_mhdp_mailbox_send(&mhdp->base,
> MB_MODULE_ID_DP_TX,
> > + DPTX_READ_LINK_STAT, 0,
> NULL);
> > + if (ret)
> > + goto err_get_training_status;
> > +
> > + ret = cdns_mhdp_mailbox_recv_header(&mhdp->base,
> MB_MODULE_ID_DP_TX,
> > +
> DPTX_READ_LINK_STAT,
> > + sizeof(status));
> > + if (ret)
> > + goto err_get_training_status;
> > +
> > + ret = cdns_mhdp_mailbox_recv_data(&mhdp->base, status,
> sizeof(status));
> > + if (ret)
> > + goto err_get_training_status;
> > +
> > + mhdp->dp.rate = drm_dp_bw_code_to_link_rate(status[0]);
> > + mhdp->dp.num_lanes = status[1];
> > +
> > +err_get_training_status:
> > + mutex_unlock(&mhdp->mbox_mutex);
> > +
> > + if (ret)
> > + DRM_DEV_ERROR(mhdp->dev, "get training status failed:
> %d\n",
> > + ret);
> > + return ret;
> > +}
> > +
> > +static int cdns_dp_train_link(struct cdns_mhdp8501_device *mhdp)
> > +{
> > + int ret;
> > +
> > + ret = cdns_dp_training_start(mhdp);
> > + if (ret) {
> > + DRM_DEV_ERROR(mhdp->dev, "Failed to start
> training %d\n",
> > + ret);
> > + return ret;
> > + }
> > +
> > + ret = cdns_dp_get_training_status(mhdp);
> > + if (ret) {
> > + DRM_DEV_ERROR(mhdp->dev, "Failed to get training stat
> %d\n",
> > + ret);
> > + return ret;
> > + }
> > +
> > + DRM_DEV_DEBUG_KMS(mhdp->dev, "rate:0x%x, lanes:%d\n",
> mhdp->dp.rate,
> > + mhdp->dp.num_lanes);
> > + return ret;
> > +}
> > +
> > +int cdns_dp_set_host_cap(struct cdns_mhdp8501_device *mhdp)
> > +{
> > + u8 msg[8];
> > + int ret;
> > +
> > + msg[0] = drm_dp_link_rate_to_bw_code(mhdp->dp.rate);
> > + msg[1] = mhdp->dp.num_lanes | SCRAMBLER_EN;
> > + msg[2] = VOLTAGE_LEVEL_2;
> > + msg[3] = PRE_EMPHASIS_LEVEL_3;
> > + msg[4] = PTS1 | PTS2 | PTS3 | PTS4;
> > + msg[5] = FAST_LT_NOT_SUPPORT;
> > + msg[6] = mhdp->lane_mapping;
> > + msg[7] = ENHANCED;
> > +
> > + mutex_lock(&mhdp->mbox_mutex);
> > +
> > + ret = cdns_mhdp_mailbox_send(&mhdp->base,
> MB_MODULE_ID_DP_TX,
> > + DPTX_SET_HOST_CAPABILITIES,
> > + sizeof(msg), msg);
> > +
> > + mutex_unlock(&mhdp->mbox_mutex);
> > +
> > + if (ret)
> > + DRM_DEV_ERROR(mhdp->dev, "set host cap
> failed: %d\n",
> ret);
> > +
> > + return ret;
> > +}
> > +
> > +static int cdns_dp_get_edid_block(void *data, u8 *edid,
> > + unsigned int block, size_t length)
> > +{
> > + struct cdns_mhdp8501_device *mhdp = data;
> > + u8 msg[2], reg[2], i;
> > + int ret;
> > +
> > + mutex_lock(&mhdp->mbox_mutex);
> > +
> > + for (i = 0; i < 4; i++) {
> > + msg[0] = block / 2;
> > + msg[1] = block % 2;
> > +
> > + ret = cdns_mhdp_mailbox_send(&mhdp->base,
> MB_MODULE_ID_DP_TX,
> > + DPTX_GET_EDID,
> sizeof(msg), msg);
> > + if (ret)
> > + continue;
> > +
> > + ret = cdns_mhdp_mailbox_recv_header(&mhdp->base,
> MB_MODULE_ID_DP_TX,
> > +
> DPTX_GET_EDID,
> > + sizeof(reg) +
> length);
> > + if (ret)
> > + continue;
> > +
> > + ret = cdns_mhdp_mailbox_recv_data(&mhdp->base, reg,
> sizeof(reg));
> > + if (ret)
> > + continue;
> > +
> > + ret = cdns_mhdp_mailbox_recv_data(&mhdp->base, edid,
> length);
> > + if (ret)
> > + continue;
> > +
> > + if (reg[0] == length && reg[1] == block / 2)
> > + break;
> > + }
> > +
> > + if (ret)
> > + DRM_DEV_ERROR(mhdp->dev, "get block[%d] edid failed:
> %d\n",
> > + block, ret);
> > +
> > + mutex_unlock(&mhdp->mbox_mutex);
> > + return ret;
> > +}
> > +
> > +static void cdns_dp_mode_set(struct cdns_mhdp8501_device *mhdp)
> > +{
> > + union phy_configure_opts phy_cfg;
> > + int ret;
> > +
> > + cdns_dp_pixel_clk_reset(mhdp);
> > +
> > + /* Get DP Caps */
> > + ret = drm_dp_dpcd_read(&mhdp->dp.aux, DP_DPCD_REV,
> mhdp->dp.dpcd,
> > + DP_RECEIVER_CAP_SIZE);
> > + if (ret < 0) {
> > + DRM_ERROR("Failed to get caps %d\n", ret);
> > + return;
> > + }
> > +
> > + mhdp->dp.rate = drm_dp_max_link_rate(mhdp->dp.dpcd);
> > + mhdp->dp.num_lanes = drm_dp_max_lane_count(mhdp->dp.dpcd);
> > +
> > + /* check the max link rate */
> > + if (mhdp->dp.rate > CDNS_DP_MAX_LINK_RATE)
> > + mhdp->dp.rate = CDNS_DP_MAX_LINK_RATE;
> > +
> > + phy_cfg.dp.lanes = mhdp->dp.num_lanes;
> > + phy_cfg.dp.link_rate = mhdp->dp.rate;
> > + phy_cfg.dp.set_lanes = false;
> > + phy_cfg.dp.set_rate = false;
> > + phy_cfg.dp.set_voltages = true;
> > +
> > + /* Mailbox protect for DP PHY access */
> > + mutex_lock(&mhdp->mbox_mutex);
> > + ret = phy_configure(mhdp->phy, &phy_cfg);
> > + mutex_unlock(&mhdp->mbox_mutex);
> > + if (ret) {
> > + dev_err(mhdp->dev, "%s: phy_configure() failed: %d\n",
> > + __func__, ret);
> > + return;
> > + }
> > +
> > + /* Video off */
> > + ret = cdns_dp_set_video_status(mhdp, CONTROL_VIDEO_IDLE);
> > + if (ret) {
> > + DRM_DEV_ERROR(mhdp->dev, "Failed to valid
> video %d\n",
> ret);
> > + return;
> > + }
> > +
> > + /* Line swapping */
> > + cdns_mhdp_reg_write(&mhdp->base, LANES_CONFIG, 0x00400000
> |
> > mhdp->lane_mapping); +
> > + /* Set DP host capability */
> > + ret = cdns_dp_set_host_cap(mhdp);
> > + if (ret) {
> > + DRM_DEV_ERROR(mhdp->dev, "Failed to set host
> cap %d\n",
> ret);
> > + return;
> > + }
> > +
> > + ret = cdns_mhdp_reg_write(&mhdp->base,
> DP_AUX_SWAP_INVERSION_CONTROL,
> > + AUX_HOST_INVERT);
> > + if (ret) {
> > + DRM_DEV_ERROR(mhdp->dev, "Failed to set host
> invert %d\n",
> ret);
> > + return;
> > + }
> > +
> > + ret = cdns_dp_config_video(mhdp);
> > + if (ret) {
> > + DRM_DEV_ERROR(mhdp->dev, "Failed to config
> video %d\n",
> ret);
> > + return;
> > + }
> > +}
> > +
> > +static int cdns_dp_bridge_attach(struct drm_bridge *bridge,
> > + enum drm_bridge_attach_flags flags)
> > +{
> > + struct cdns_mhdp8501_device *mhdp = bridge->driver_private;
> > +
> > + if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
> > + DRM_ERROR("do not support creating a
> drm_connector\n");
> > + return -EINVAL;
> > + }
> > +
> > + mhdp->dp.aux.drm_dev = bridge->dev;
> > +
> > + return drm_dp_aux_register(&mhdp->dp.aux);
> > +}
> > +
> > +static enum drm_mode_status
> > +cdns_dp_bridge_mode_valid(struct drm_bridge *bridge,
> > + const struct drm_display_info *info,
> > + const struct drm_display_mode *mode)
> > +{
> > + enum drm_mode_status mode_status = MODE_OK;
> > +
> > + /* We don't support double-clocked modes */
> > + if (mode->flags & DRM_MODE_FLAG_DBLCLK ||
> > + mode->flags & DRM_MODE_FLAG_INTERLACE)
> > + return MODE_BAD;
> > +
> > + /* MAX support pixel clock rate 594MHz */
> > + if (mode->clock > 594000)
> > + return MODE_CLOCK_HIGH;
> > +
> > + /* 4096x2160 is not supported */
> > + if (mode->hdisplay > 3840)
>
> Comment does not match code.
OK.
>
> > + return MODE_BAD_HVALUE;
> > +
> > + if (mode->vdisplay > 2160)
> > + return MODE_BAD_VVALUE;
> > +
> > + return mode_status;
> > +}
> > +
> > +static enum drm_connector_status
> > +cdns_dp_bridge_detect(struct drm_bridge *bridge)
> > +{
> > + struct cdns_mhdp8501_device *mhdp = bridge->driver_private;
> > +
> > + return cdns_mhdp8501_detect(mhdp);
> > +}
> > +
> > +static struct edid *cdns_dp_bridge_get_edid(struct drm_bridge *bridge,
> > + struct drm_connector
> *connector)
> > +{
> > + struct cdns_mhdp8501_device *mhdp = bridge->driver_private;
> > +
> > + return drm_do_get_edid(connector, cdns_dp_get_edid_block,
> mhdp);
> > +}
> > +
> > +static void cdns_dp_bridge_atomic_disable(struct drm_bridge *bridge,
> > + struct drm_bridge_state
> *old_state)
> > +{
> > + struct cdns_mhdp8501_device *mhdp = bridge->driver_private;
> > +
> > + cdns_dp_set_video_status(mhdp, CONTROL_VIDEO_IDLE);
> > + mhdp->curr_conn = NULL;
> > +
> > + /* Mailbox protect for DP PHY access */
> > + mutex_lock(&mhdp->mbox_mutex);
> > + phy_power_off(mhdp->phy);
> > + mutex_unlock(&mhdp->mbox_mutex);
> > +}
> > +
> > +static void cdns_dp_bridge_atomic_enable(struct drm_bridge *bridge,
> > + struct drm_bridge_state
> *old_state)
> > +{
> > + struct cdns_mhdp8501_device *mhdp = bridge->driver_private;
> > + struct drm_atomic_state *state = old_state->base.state;
> > + struct drm_connector *connector;
> > + struct video_info *video = &mhdp->video_info;
> > + struct drm_crtc_state *crtc_state;
> > + struct drm_connector_state *conn_state;
> > + const struct drm_display_mode *mode;
> > + int ret;
> > +
> > + connector = drm_atomic_get_new_connector_for_encoder(state,
> > +
> bridge->encoder);
> > + if (WARN_ON(!connector))
> > + return;
> > +
> > + mhdp->curr_conn = connector;
> > +
> > + conn_state = drm_atomic_get_new_connector_state(state,
> connector);
> > + if (WARN_ON(!conn_state))
> > + return;
> > +
> > + crtc_state = drm_atomic_get_new_crtc_state(state,
> conn_state->crtc);
> > + if (WARN_ON(!crtc_state))
> > + return;
> > +
> > + mode = &crtc_state->adjusted_mode;
> > +
> > + switch (connector->display_info.bpc) {
> > + case 10:
> > + video->bpc = 10;
> > + break;
> > + case 6:
> > + video->bpc = 6;
> > + break;
> > + default:
> > + video->bpc = 8;
> > + break;
> > + }
> > +
> > + /* The only currently supported format */
> > + video->color_fmt = DRM_COLOR_FORMAT_RGB444;
> > +
> > + DRM_INFO("Mode: %dx%dp%d\n", mode->hdisplay, mode->vdisplay,
> mode-
> >clock);
> > + memcpy(&mhdp->mode, mode, sizeof(struct drm_display_mode));
> > +
> > + cdns_dp_mode_set(mhdp);
> > +
> > + /* Link trainning */
> > + ret = cdns_dp_train_link(mhdp);
> > + if (ret) {
> > + DRM_DEV_ERROR(mhdp->dev, "Failed link train %d\n",
> ret);
> > + return;
> > + }
> > +
> > + ret = cdns_dp_set_video_status(mhdp, CONTROL_VIDEO_VALID);
> > + if (ret) {
> > + DRM_DEV_ERROR(mhdp->dev, "Failed to valid
> video %d\n",
> ret);
> > + return;
> > + }
> > +}
> > +
> > +const struct drm_bridge_funcs cdns_dp_bridge_funcs = {
> > + .attach = cdns_dp_bridge_attach,
> > + .mode_valid = cdns_dp_bridge_mode_valid,
> > + .detect = cdns_dp_bridge_detect,
> > + .get_edid = cdns_dp_bridge_get_edid,
> > + .atomic_enable = cdns_dp_bridge_atomic_enable,
> > + .atomic_disable = cdns_dp_bridge_atomic_disable,
> > + .atomic_duplicate_state =
> drm_atomic_helper_bridge_duplicate_state,
> > + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
> > + .atomic_reset = drm_atomic_helper_bridge_reset,
>
> Can you please sort the entries in the same order as
> cdns_hdmi_bridge_funcs?
> This makes it easier to detect which entries are provided in both files.
>
OK.
> > +};
> > diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-hdmi.c
> > b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-hdmi.c new file mode
> 100644
> > index 0000000000000..73d1c35a74599
> > --- /dev/null
> > +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-hdmi.c
> > @@ -0,0 +1,673 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Cadence MHDP8501 HDMI bridge driver
> > + *
> > + * Copyright (C) 2019-2023 NXP Semiconductor, Inc.
> > + *
> > + */
> > +#include <drm/display/drm_hdmi_helper.h>
> > +#include <drm/display/drm_scdc_helper.h>
> > +#include <drm/drm_atomic_helper.h>
> > +#include <drm/drm_edid.h>
> > +#include <drm/drm_print.h>
> > +#include <linux/phy/phy.h>
> > +#include <linux/phy/phy-hdmi.h>
> > +
> > +#include "cdns-mhdp8501-core.h"
> > +
> > +/**
> > + * cdns_hdmi_infoframe_set() - fill the HDMI AVI infoframe
> > + * @mhdp: phandle to mhdp device.
> > + * @entry_id: The packet memory address in which the data is written.
> > + * @packet_len: 32, only 32 bytes now.
> > + * @packet: point to InfoFrame Packet.
> > + * packet[0] = 0
> > + * packet[1-3] = HB[0-2] InfoFrame Packet Header
> > + * packet[4-31 = PB[0-27] InfoFrame Packet Contents
> > + * @packet_type: Packet Type of InfoFrame in HDMI Specification.
> > + *
> > + */
> > +static void cdns_hdmi_infoframe_set(struct cdns_mhdp8501_device
> *mhdp,
> > + u8 entry_id, u8 packet_len,
> > + u8 *packet, u8 packet_type)
> > +{
> > + u32 packet32, len32;
> > + u32 val, i;
> > +
> > + /* only support 32 bytes now */
> > + if (packet_len != 32)
> > + return;
> > +
> > + /* invalidate entry */
> > + val = F_ACTIVE_IDLE_TYPE(1) | F_PKT_ALLOC_ADDRESS(entry_id);
> > + writel(val, mhdp->regs + SOURCE_PIF_PKT_ALLOC_REG);
> > + writel(F_PKT_ALLOC_WR_EN(1), mhdp->regs +
> SOURCE_PIF_PKT_ALLOC_WR_EN);
> > +
> > + /* flush fifo 1 */
> > + writel(F_FIFO1_FLUSH(1), mhdp->regs +
> SOURCE_PIF_FIFO1_FLUSH);
> > +
> > + /* write packet into memory */
> > + len32 = packet_len / 4;
> > + for (i = 0; i < len32; i++) {
> > + packet32 = get_unaligned_le32(packet + 4 * i);
> > + writel(F_DATA_WR(packet32), mhdp->regs +
> SOURCE_PIF_DATA_WR);
> > + }
> > +
> > + /* write entry id */
> > + writel(F_WR_ADDR(entry_id), mhdp->regs +
> SOURCE_PIF_WR_ADDR);
> > +
> > + /* write request */
> > + writel(F_HOST_WR(1), mhdp->regs + SOURCE_PIF_WR_REQ);
> > +
> > + /* update entry */
> > + val = F_ACTIVE_IDLE_TYPE(1) | F_TYPE_VALID(1) |
> > + F_PACKET_TYPE(packet_type) |
> F_PKT_ALLOC_ADDRESS(entry_id);
> > + writel(val, mhdp->regs + SOURCE_PIF_PKT_ALLOC_REG);
> > +
> > + writel(F_PKT_ALLOC_WR_EN(1), mhdp->regs +
> SOURCE_PIF_PKT_ALLOC_WR_EN);
> > +}
> > +
> > +static int cdns_hdmi_get_edid_block(void *data, u8 *edid,
> > + u32 block, size_t length)
> > +{
> > + struct cdns_mhdp8501_device *mhdp = data;
> > + u8 msg[2], reg[5], i;
> > + int ret;
> > +
> > + mutex_lock(&mhdp->mbox_mutex);
> > +
> > + for (i = 0; i < 4; i++) {
> > + msg[0] = block / 2;
> > + msg[1] = block % 2;
> > +
> > + ret = cdns_mhdp_mailbox_send(&mhdp->base,
> MB_MODULE_ID_HDMI_TX,
> > HDMI_TX_EDID, +
> sizeof(msg),
> msg);
> > + if (ret)
> > + continue;
> > +
> > + ret = cdns_mhdp_mailbox_recv_header(&mhdp->base,
> MB_MODULE_ID_HDMI_TX,
> > +
> HDMI_TX_EDID,
> sizeof(reg) + length);
> > + if (ret)
> > + continue;
> > +
> > + ret = cdns_mhdp_mailbox_recv_data(&mhdp->base, reg,
> sizeof(reg));
> > + if (ret)
> > + continue;
> > +
> > + ret = cdns_mhdp_mailbox_recv_data(&mhdp->base, edid,
> length);
> > + if (ret)
> > + continue;
> > +
> > + if ((reg[3] << 8 | reg[4]) == length)
> > + break;
> > + }
> > +
> > + mutex_unlock(&mhdp->mbox_mutex);
> > +
> > + if (ret)
> > + DRM_ERROR("get block[%d] edid failed: %d\n", block,
> ret);
>
> Please replace all DRM_ macros, see [1] for details. As you don't have a
> drm_dev you will most probably need a dev_err & friends.
>
> [1]
> https://lore.ke/
> rnel.org%2Flinux-arm-kernel%2F285db5bc-f901-e09f-7f86-6638d260c283%4
> 0linaro.org%2FT%2F%23ma30715ccd9004ad19a6741c3f6b3dfd68d526018&
> data=05%7C01%7CSandor.yu%40nxp.com%7Cf09434a5d5fd48d090e308dbcf
> 0deb19%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C638331430
> 937142084%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIj
> oiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata
> =h72fs%2BkA2pTNbM1MuAPYSHbkw0ScLLYu2zeeSmdKE5I%3D&reserved=0
>
OK
> > + return ret;
> > +}
> > +
> > +static int cdns_hdmi_scdc_write(struct cdns_mhdp8501_device *mhdp, u8
> addr,
> > u8 value) +{
> > + u8 msg[5], reg[5];
> > + int ret;
> > +
> > + msg[0] = 0x54;
> > + msg[1] = addr;
> > + msg[2] = 0;
> > + msg[3] = 1;
> > + msg[4] = value;
> > +
> > + mutex_lock(&mhdp->mbox_mutex);
> > +
> > + ret = cdns_mhdp_mailbox_send(&mhdp->base,
> MB_MODULE_ID_HDMI_TX,
> > HDMI_TX_WRITE, + sizeof(msg),
> msg);
> > + if (ret)
> > + goto err_scdc_write;
> > +
> > + ret = cdns_mhdp_mailbox_recv_header(&mhdp->base,
> MB_MODULE_ID_HDMI_TX,
> > + HDMI_TX_WRITE,
> sizeof(reg));
> > + if (ret)
> > + goto err_scdc_write;
> > +
> > + ret = cdns_mhdp_mailbox_recv_data(&mhdp->base, reg,
> sizeof(reg));
> > + if (ret)
> > + goto err_scdc_write;
> > +
> > + if (reg[0] != 0)
> > + ret = -EINVAL;
> > +
> > +err_scdc_write:
> > +
> > + mutex_unlock(&mhdp->mbox_mutex);
> > +
> > + if (ret)
> > + DRM_ERROR("scdc write failed: %d\n", ret);
> > + return ret;
> > +}
> > +
> > +static int cdns_hdmi_ctrl_init(struct cdns_mhdp8501_device *mhdp, int
> > protocol) +{
> > + u32 reg0, reg1, val;
> > + int ret;
> > +
> > + /* Set PHY to HDMI data */
> > + ret = cdns_mhdp_reg_write(&mhdp->base, PHY_DATA_SEL,
> > F_SOURCE_PHY_MHDP_SEL(1)); + if (ret < 0)
> > + return ret;
> > +
> > + ret = cdns_mhdp_reg_write(&mhdp->base, HDTX_HPD,
> > + F_HPD_VALID_WIDTH(4) |
> F_HPD_GLITCH_WIDTH(0));
> > + if (ret < 0)
> > + return ret;
> > +
> > + /* open CARS */
> > + ret = cdns_mhdp_reg_write(&mhdp->base, SOURCE_PHY_CAR,
> 0xF);
> > + if (ret < 0)
> > + return ret;
> > + ret = cdns_mhdp_reg_write(&mhdp->base, SOURCE_HDTX_CAR,
> 0xFF);
> > + if (ret < 0)
> > + return ret;
> > + ret = cdns_mhdp_reg_write(&mhdp->base, SOURCE_PKT_CAR, 0xF);
> > + if (ret < 0)
> > + return ret;
> > + ret = cdns_mhdp_reg_write(&mhdp->base, SOURCE_AIF_CAR, 0xF);
> > + if (ret < 0)
> > + return ret;
> > + ret = cdns_mhdp_reg_write(&mhdp->base, SOURCE_CIPHER_CAR,
> 0xF);
> > + if (ret < 0)
> > + return ret;
> > + ret = cdns_mhdp_reg_write(&mhdp->base, SOURCE_CRYPTO_CAR,
> 0xF);
> > + if (ret < 0)
> > + return ret;
> > + ret = cdns_mhdp_reg_write(&mhdp->base, SOURCE_CEC_CAR, 3);
> > + if (ret < 0)
> > + return ret;
> > +
> > + reg0 = 0x7c1f;
> > + reg1 = 0x7c1f;
> > + if (protocol == MODE_HDMI_2_0) {
> > + reg0 = 0;
> > + reg1 = 0xFFFFF;
> > + }
> > + ret = cdns_mhdp_reg_write(&mhdp->base, HDTX_CLOCK_REG_0,
> reg0);
> > + if (ret < 0)
> > + return ret;
> > + ret = cdns_mhdp_reg_write(&mhdp->base, HDTX_CLOCK_REG_1,
> reg1);
> > + if (ret < 0)
> > + return ret;
> > +
> > + /* set hdmi mode and preemble mode data enable */
>
> Please stick to consistent uppercase when naming HDMI.
>
OK.
> > + val = F_HDMI_MODE(protocol) | F_HDMI2_PREAMBLE_EN(1) |
> F_DATA_EN(1)
> |
> > + F_HDMI2_CTRL_IL_MODE(1) | F_BCH_EN(1) |
> F_PIC_3D(0XF);
> > + ret = cdns_mhdp_reg_write(&mhdp->base, HDTX_CONTROLLER,
> val);
> > +
> > + return ret;
> > +}
> > +
> > +static int cdns_hdmi_mode_config(struct cdns_mhdp8501_device *mhdp,
> > + struct drm_display_mode *mode,
> > + struct video_info *video_info)
> > +{
> > + int ret;
> > + u32 val;
> > + u32 vsync_lines = mode->vsync_end - mode->vsync_start;
> > + u32 eof_lines = mode->vsync_start - mode->vdisplay;
> > + u32 sof_lines = mode->vtotal - mode->vsync_end;
> > + u32 hblank = mode->htotal - mode->hdisplay;
> > + u32 hactive = mode->hdisplay;
> > + u32 vblank = mode->vtotal - mode->vdisplay;
> > + u32 vactive = mode->vdisplay;
> > + u32 hfront = mode->hsync_start - mode->hdisplay;
> > + u32 hback = mode->htotal - mode->hsync_end;
> > + u32 vfront = eof_lines;
> > + u32 hsync = hblank - hfront - hback;
> > + u32 vsync = vsync_lines;
> > + u32 vback = sof_lines;
> > + u32 v_h_polarity = ((mode->flags & DRM_MODE_FLAG_NHSYNC) ?
> 0 : 1) +
> > + ((mode->flags & DRM_MODE_FLAG_NVSYNC) ?
> 0 : 2);
> > +
> > + ret = cdns_mhdp_reg_write(&mhdp->base, SCHEDULER_H_SIZE,
> (hactive <<
> 16) +
> > hblank); + if (ret < 0)
> > + return ret;
> > +
> > + ret = cdns_mhdp_reg_write(&mhdp->base, SCHEDULER_V_SIZE,
> (vactive <<
> 16) +
> > vblank); + if (ret < 0)
> > + return ret;
> > +
> > + ret = cdns_mhdp_reg_write(&mhdp->base,
> HDTX_SIGNAL_FRONT_WIDTH,
> (vfront <<
> > 16) + hfront); + if (ret < 0)
> > + return ret;
> > +
> > + ret = cdns_mhdp_reg_write(&mhdp->base,
> HDTX_SIGNAL_SYNC_WIDTH,
> (vsync <<
> > 16) + hsync); + if (ret < 0)
> > + return ret;
> > +
> > + ret = cdns_mhdp_reg_write(&mhdp->base,
> HDTX_SIGNAL_BACK_WIDTH,
> (vback <<
> > 16) + hback); + if (ret < 0)
> > + return ret;
> > +
> > + ret = cdns_mhdp_reg_write(&mhdp->base,
> HSYNC2VSYNC_POL_CTRL,
> > v_h_polarity); + if (ret < 0)
> > + return ret;
> > +
> > + /* Reset Data Enable */
> > + cdns_mhdp_reg_read(&mhdp->base, HDTX_CONTROLLER, &val);
> > + val &= ~F_DATA_EN(1);
> > + ret = cdns_mhdp_reg_write(&mhdp->base, HDTX_CONTROLLER,
> val);
> > + if (ret < 0)
> > + return ret;
> > +
> > + /* Set bpc */
> > + val &= ~F_VIF_DATA_WIDTH(3);
> > + switch (video_info->bpc) {
> > + case 10:
> > + val |= F_VIF_DATA_WIDTH(1);
> > + break;
> > + case 12:
> > + val |= F_VIF_DATA_WIDTH(2);
> > + break;
> > + case 16:
> > + val |= F_VIF_DATA_WIDTH(3);
> > + break;
> > + case 8:
> > + default:
> > + val |= F_VIF_DATA_WIDTH(0);
> > + break;
> > + }
> > +
> > + /* select color encoding */
> > + val &= ~F_HDMI_ENCODING(3);
> > + switch (video_info->color_fmt) {
> > + case DRM_COLOR_FORMAT_YCBCR444:
> > + val |= F_HDMI_ENCODING(2);
> > + break;
> > + case DRM_COLOR_FORMAT_YCBCR422:
> > + val |= F_HDMI_ENCODING(1);
> > + break;
> > + case DRM_COLOR_FORMAT_YCBCR420:
> > + val |= F_HDMI_ENCODING(3);
> > + break;
> > + case DRM_COLOR_FORMAT_RGB444:
> > + default:
> > + val |= F_HDMI_ENCODING(0);
> > + break;
> > + }
> > +
> > + ret = cdns_mhdp_reg_write(&mhdp->base, HDTX_CONTROLLER,
> val);
> > + if (ret < 0)
> > + return ret;
> > +
> > + /* set data enable */
> > + val |= F_DATA_EN(1);
> > + ret = cdns_mhdp_reg_write(&mhdp->base, HDTX_CONTROLLER,
> val);
> > +
> > + return ret;
> > +}
> > +
> > +static int cdns_hdmi_disable_gcp(struct cdns_mhdp8501_device *mhdp)
> > +{
> > + u32 val;
> > +
> > + cdns_mhdp_reg_read(&mhdp->base, HDTX_CONTROLLER, &val);
> > + val &= ~F_GCP_EN(1);
> > +
> > + return cdns_mhdp_reg_write(&mhdp->base, HDTX_CONTROLLER,
> val);
> > +}
> > +
> > +static int cdns_hdmi_enable_gcp(struct cdns_mhdp8501_device *mhdp)
> > +{
> > + u32 val;
> > +
> > + cdns_mhdp_reg_read(&mhdp->base, HDTX_CONTROLLER, &val);
> > + val |= F_GCP_EN(1);
> > +
> > + return cdns_mhdp_reg_write(&mhdp->base, HDTX_CONTROLLER,
> val);
> > +}
> > +
> > +static void cdns_hdmi_sink_config(struct cdns_mhdp8501_device *mhdp)
> > +{
> > + struct drm_scdc *scdc =
> &mhdp->curr_conn->display_info.hdmi.scdc;
> > + u32 char_rate = mhdp->mode.clock * mhdp->video_info.bpc / 8;
> > + u8 buff = 0;
> > +
> > + /* Default work in HDMI1.4 */
> > + mhdp->hdmi.hdmi_type = MODE_HDMI_1_4;
> > +
> > + /* check sink support SCDC or not */
> > + if (!scdc->supported) {
> > + DRM_INFO("Sink Not Support SCDC\n");
> > + return;
> > + }
> > +
> > + if (char_rate > 340000) {
> > + /*
> > + * TMDS Character Rate above 340MHz should working in
> HDMI2.0
> > + * Enable scrambling and TMDS_Bit_Clock_Ratio
> > + */
> > + buff = SCDC_TMDS_BIT_CLOCK_RATIO_BY_40 |
> SCDC_SCRAMBLING_ENABLE;
> > + mhdp->hdmi.hdmi_type = MODE_HDMI_2_0;
> > + } else if (scdc->scrambling.low_rates) {
> > + /*
> > + * Enable scrambling and HDMI2.0 when scrambling
> capability of sink
> > + * be indicated in the HF-VSDB LTE_340Mcsc_scramble bit
> > + */
> > + buff = SCDC_SCRAMBLING_ENABLE;
> > + mhdp->hdmi.hdmi_type = MODE_HDMI_2_0;
> > + }
> > +
> > + /* TMDS config */
> > + cdns_hdmi_scdc_write(mhdp, SCDC_TMDS_CONFIG, buff);
> > +}
> > +
> > +static void cdns_hdmi_lanes_config(struct cdns_mhdp8501_device *mhdp)
> > +{
> > + /* Line swapping */
> > + cdns_mhdp_reg_write(&mhdp->base, LANES_CONFIG, 0x00400000
> |
> > mhdp->lane_mapping); +}
> > +
> > +static int cdns_hdmi_colorspace(int color_fmt)
> > +{
> > + int color_space;
> > +
> > + switch (color_fmt) {
> > + case DRM_COLOR_FORMAT_YCBCR444:
> > + color_space = HDMI_COLORSPACE_YUV444;
> > + break;
> > + case DRM_COLOR_FORMAT_YCBCR422:
> > + color_space = HDMI_COLORSPACE_YUV422;
> > + break;
> > + case DRM_COLOR_FORMAT_YCBCR420:
> > + color_space = HDMI_COLORSPACE_YUV420;
> > + break;
> > + case DRM_COLOR_FORMAT_RGB444:
> > + default:
> > + color_space = HDMI_COLORSPACE_RGB;
> > + break;
> > + }
> > +
> > + return color_space;
> > +}
> > +
> > +static int cdns_hdmi_avi_info_set(struct cdns_mhdp8501_device *mhdp,
> > + struct drm_display_mode *mode)
> > +{
> > + struct hdmi_avi_infoframe frame;
> > + struct drm_connector_state *conn_state = mhdp->curr_conn->state;
> > + struct drm_display_mode *adj_mode;
> > + enum hdmi_quantization_range qr;
> > + u8 buf[32];
> > + int ret;
> > +
> > + /* Initialise info frame from DRM mode */
> > + drm_hdmi_avi_infoframe_from_display_mode(&frame,
> mhdp->curr_conn,
> mode);
> > +
> > + frame.colorspace =
> cdns_hdmi_colorspace(mhdp->video_info.color_fmt);
> > +
> > + drm_hdmi_avi_infoframe_colorimetry(&frame, conn_state);
> > +
> > + adj_mode = &mhdp->bridge.encoder->crtc->state->adjusted_mode;
> > +
> > + qr = drm_default_rgb_quant_range(adj_mode);
> > +
> > + drm_hdmi_avi_infoframe_quant_range(&frame, mhdp->curr_conn,
> > + adj_mode, qr);
> > +
> > + ret = hdmi_avi_infoframe_pack(&frame, buf + 1, sizeof(buf) - 1);
> > + if (ret < 0) {
> > + DRM_ERROR("failed to pack AVI infoframe: %d\n", ret);
> > + return -1;
> > + }
> > +
> > + buf[0] = 0;
> > + cdns_hdmi_infoframe_set(mhdp, 0, sizeof(buf), buf,
> > HDMI_INFOFRAME_TYPE_AVI); +
> > + return 0;
> > +}
> > +
> > +static void cdns_hdmi_vendor_info_set(struct cdns_mhdp8501_device
> *mhdp,
> > + struct drm_display_mode
> *mode)
> > +{
> > + struct hdmi_vendor_infoframe frame;
> > + u8 buf[32];
> > + int ret;
> > +
> > + /* Initialise vendor frame from DRM mode */
> > + ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame,
> mhdp-
> >curr_conn,
> > mode); + if (ret < 0) {
> > + DRM_INFO("No vendor infoframe\n");
> > + return;
> > + }
> > +
> > + ret = hdmi_vendor_infoframe_pack(&frame, buf + 1, sizeof(buf) - 1);
> > + if (ret < 0) {
> > + DRM_WARN("Unable to pack vendor infoframe: %d\n",
> ret);
> > + return;
> > + }
> > +
> > + buf[0] = 0;
> > + cdns_hdmi_infoframe_set(mhdp, 3, sizeof(buf), buf,
> > HDMI_INFOFRAME_TYPE_VENDOR); +}
> > +
> > +static void cdns_hdmi_drm_info_set(struct cdns_mhdp8501_device
> *mhdp)
> > +{
> > + struct drm_connector_state *conn_state;
> > + struct hdmi_drm_infoframe frame;
> > + u8 buf[32];
> > + int ret;
> > +
> > + conn_state = mhdp->curr_conn->state;
> > +
> > + if (!conn_state->hdr_output_metadata)
> > + return;
> > +
> > + ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, conn_state);
> > + if (ret < 0) {
> > + DRM_DEBUG_KMS("couldn't set HDR metadata in
> infoframe\n");
> > + return;
> > + }
> > +
> > + ret = hdmi_drm_infoframe_pack(&frame, buf + 1, sizeof(buf) - 1);
> > + if (ret < 0) {
> > + DRM_DEBUG_KMS("couldn't pack HDR infoframe\n");
> > + return;
> > + }
> > +
> > + buf[0] = 0;
> > + cdns_hdmi_infoframe_set(mhdp, 3, sizeof(buf), buf,
> > HDMI_INFOFRAME_TYPE_DRM); +}
> > +
> > +static void cdns_hdmi_mode_set(struct cdns_mhdp8501_device *mhdp)
> > +{
> > + struct drm_display_mode *mode = &mhdp->mode;
> > + union phy_configure_opts phy_cfg;
> > + int ret;
> > +
> > + /* video mode check */
> > + if (mode->clock == 0 || mode->hdisplay == 0 || mode->vdisplay ==
> 0)
> > + return;
> > +
> > + cdns_hdmi_lanes_config(mhdp);
> > +
> > + phy_cfg.hdmi.pixel_clk_rate = mode->clock;
> > + phy_cfg.hdmi.bpc = mhdp->video_info.bpc;
> > + phy_cfg.hdmi.color_space =
> > cdns_hdmi_colorspace(mhdp->video_info.color_fmt); +
> > + /* Mailbox protect for HDMI PHY access */
> > + mutex_lock(&mhdp->mbox_mutex);
> > + ret = phy_configure(mhdp->phy, &phy_cfg);
> > + mutex_unlock(&mhdp->mbox_mutex);
> > + if (ret) {
> > + dev_err(mhdp->dev, "%s: phy_configure() failed: %d\n",
> > + __func__, ret);
> > + return;
> > + }
> > +
> > + cdns_hdmi_sink_config(mhdp);
> > +
> > + ret = cdns_hdmi_ctrl_init(mhdp, mhdp->hdmi.hdmi_type);
> > + if (ret < 0) {
> > + DRM_ERROR("%s, ret = %d\n", __func__, ret);
> > + return;
> > + }
> > +
> > + /* Config GCP */
> > + if (mhdp->video_info.bpc == 8)
> > + cdns_hdmi_disable_gcp(mhdp);
> > + else
> > + cdns_hdmi_enable_gcp(mhdp);
> > +
> > + ret = cdns_hdmi_avi_info_set(mhdp, mode);
> > + if (ret < 0) {
> > + DRM_ERROR("%s ret = %d\n", __func__, ret);
> > + return;
> > + }
> > +
> > + /* vendor info frame is enabled only for HDMI1.4 4K mode */
> > + cdns_hdmi_vendor_info_set(mhdp, mode);
> > +
> > + cdns_hdmi_drm_info_set(mhdp);
> > +
> > + ret = cdns_hdmi_mode_config(mhdp, mode, &mhdp->video_info);
> > + if (ret < 0) {
> > + DRM_ERROR("CDN_API_HDMITX_SetVic_blocking ret
> = %d\n",
> ret);
> > + return;
> > + }
> > +}
> > +
> > +static int cdns_hdmi_bridge_attach(struct drm_bridge *bridge,
> > + enum drm_bridge_attach_flags
> flags)
> > +{
> > + if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
> > + DRM_ERROR("do not support creating a
> drm_connector\n");
> > + return -EINVAL;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static enum drm_mode_status
> > +cdns_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
> > + const struct drm_display_info *info,
> > + const struct drm_display_mode *mode)
> > +{
> > + struct cdns_mhdp8501_device *mhdp = bridge->driver_private;
> > + enum drm_mode_status mode_status = MODE_OK;
> > + union phy_configure_opts phy_cfg;
> > + int ret;
> > +
> > + /* We don't support double-clocked and Interlaced modes */
> > + if (mode->flags & DRM_MODE_FLAG_DBLCLK ||
> > + mode->flags & DRM_MODE_FLAG_INTERLACE)
> > + return MODE_BAD;
> > +
> > + /* MAX support pixel clock rate 594MHz */
> > + if (mode->clock > 594000)
> > + return MODE_CLOCK_HIGH;
> > +
> > + /* 4096x2160 is not supported */
> > + if (mode->hdisplay > 3840 || mode->vdisplay > 2160)
>
> Comment does not match code. Despite that separately check for vdisplay
> and
> return MODE_BAD_VVALUE if it's too big.
>
OK, thanks your detail review comments.
Sandor
> Best regards,
> Alexander
>
> > + return MODE_BAD_HVALUE;
> > +
> > + /* Check modes supported by PHY */
> > + phy_cfg.hdmi.pixel_clk_rate = mode->clock;
> > +
> > + /* Mailbox protect for HDMI PHY access */
> > + mutex_lock(&mhdp->mbox_mutex);
> > + ret = phy_validate(mhdp->phy, PHY_MODE_HDMI, 0, &phy_cfg);
> > + mutex_unlock(&mhdp->mbox_mutex);
> > + if (ret < 0)
> > + return MODE_CLOCK_RANGE;
> > +
> > + return mode_status;
> > +}
> > +
> > +bool cdns_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
> > + const struct drm_display_mode
> *mode,
> > + struct drm_display_mode
> *adjusted_mode)
> > +{
> > + struct cdns_mhdp8501_device *mhdp = bridge->driver_private;
> > + struct video_info *video = &mhdp->video_info;
> > +
> > + /* The only currently supported format */
> > + video->bpc = 8;
> > + video->color_fmt = DRM_COLOR_FORMAT_RGB444;
> > +
> > + return true;
> > +}
> > +
> > +static enum drm_connector_status
> > +cdns_hdmi_bridge_detect(struct drm_bridge *bridge)
> > +{
> > + struct cdns_mhdp8501_device *mhdp = bridge->driver_private;
> > +
> > + return cdns_mhdp8501_detect(mhdp);
> > +}
> > +
> > +static struct edid *cdns_hdmi_bridge_get_edid(struct drm_bridge *bridge,
> > + struct
> drm_connector
> *connector)
> > +{
> > + struct cdns_mhdp8501_device *mhdp = bridge->driver_private;
> > +
> > + return drm_do_get_edid(connector, cdns_hdmi_get_edid_block,
> mhdp);
> > +}
> > +
> > +static void cdns_hdmi_bridge_atomic_disable(struct drm_bridge *bridge,
> > + struct
> drm_bridge_state
> *old_state)
> > +{
> > + struct cdns_mhdp8501_device *mhdp = bridge->driver_private;
> > +
> > + mhdp->curr_conn = NULL;
> > +
> > + /* Mailbox protect for HDMI PHY access */
> > + mutex_lock(&mhdp->mbox_mutex);
> > + phy_power_off(mhdp->phy);
> > + mutex_unlock(&mhdp->mbox_mutex);
> > +}
> > +
> > +static void cdns_hdmi_bridge_atomic_enable(struct drm_bridge *bridge,
> > + struct drm_bridge_state
> *old_state)
> > +{
> > + struct cdns_mhdp8501_device *mhdp = bridge->driver_private;
> > + struct drm_atomic_state *state = old_state->base.state;
> > + struct drm_connector *connector;
> > + struct drm_crtc_state *crtc_state;
> > + struct drm_connector_state *conn_state;
> > + const struct drm_display_mode *mode;
> > +
> > + connector = drm_atomic_get_new_connector_for_encoder(state,
> > +
> bridge->encoder);
> > + if (WARN_ON(!connector))
> > + return;
> > +
> > + mhdp->curr_conn = connector;
> > +
> > + conn_state = drm_atomic_get_new_connector_state(state,
> connector);
> > + if (WARN_ON(!conn_state))
> > + return;
> > +
> > + crtc_state = drm_atomic_get_new_crtc_state(state,
> conn_state->crtc);
> > + if (WARN_ON(!crtc_state))
> > + return;
> > +
> > + mode = &crtc_state->adjusted_mode;
> > + DRM_INFO("Mode: %dx%dp%d\n", mode->hdisplay, mode->vdisplay,
> mode-
> >clock);
> > + memcpy(&mhdp->mode, mode, sizeof(struct drm_display_mode));
> > +
> > + cdns_hdmi_mode_set(mhdp);
> > +}
> > +
> > +const struct drm_bridge_funcs cdns_hdmi_bridge_funcs = {
> > + .attach = cdns_hdmi_bridge_attach,
> > + .detect = cdns_hdmi_bridge_detect,
> > + .get_edid = cdns_hdmi_bridge_get_edid,
> > + .mode_valid = cdns_hdmi_bridge_mode_valid,
> > + .mode_fixup = cdns_hdmi_bridge_mode_fixup,
> > + .atomic_enable = cdns_hdmi_bridge_atomic_enable,
> > + .atomic_disable = cdns_hdmi_bridge_atomic_disable,
> > + .atomic_duplicate_state =
> drm_atomic_helper_bridge_duplicate_state,
> > + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
> > + .atomic_reset = drm_atomic_helper_bridge_reset,
> > +};
>
>
> --
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^ permalink raw reply
* RE: [EXT] Re: [PATCH v11 1/7] drm: bridge: Cadence: Creat mhdp helper driver
From: Sandor Yu @ 2024-01-05 3:20 UTC (permalink / raw)
To: Alexander Stein, dmitry.baryshkov@linaro.org,
andrzej.hajda@intel.com, neil.armstrong@linaro.org,
Laurent Pinchart, jonas@kwiboo.se, jernej.skrabec@gmail.com,
airlied@gmail.com, daniel@ffwll.ch, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, shawnguo@kernel.org,
s.hauer@pengutronix.de, festevam@gmail.com, vkoul@kernel.org,
dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org
Cc: kernel@pengutronix.de, dl-linux-imx, Oliver Brown,
sam@ravnborg.org
In-Reply-To: <2582168.Lt9SDvczpP@steina-w>
Hi Alexander,
Thanks for your comments,
>
> Hi Sandor,
>
> thanks for the update.
>
> One small typo in the commit message: 'Creat' -> 'Create'
>
> Am Dienstag, 17. Oktober 2023, 09:03:57 CEST schrieb Sandor Yu:
> > MHDP8546 mailbox access functions will be share to other mhdp driver
> > and Cadence HDP-TX HDMI/DP PHY drivers.
> > Create a new mhdp helper driver and move all those functions into.
> >
> > cdns_mhdp_reg_write() is renamed to cdns_mhdp_dp_reg_write(), because
> > it use the DPTX command ID DPTX_WRITE_REGISTER.
> >
> > New cdns_mhdp_reg_write() is created with the general command ID
> > GENERAL_REGISTER_WRITE.
> >
> > rewrite cdns_mhdp_set_firmware_active() in mhdp8546 core driver, use
> > cdns_mhdp_mailbox_send() to replace cdns_mhdp_mailbox_write() same
> as
> > the other mailbox access functions.
> >
> > Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
> > ---
> > v10->v11:
> > - rewrite cdns_mhdp_set_firmware_active() in mhdp8546 core driver, use
> > cdns_mhdp_mailbox_send() to replace cdns_mhdp_mailbox_write() same
> as
> > the other mailbox access functions.
> > - use static for cdns_mhdp_mailbox_write() and
> > cdns_mhdp_mailbox_read() and remove them from
> EXPORT_SYMBOL_GPL().
> >
> > v9->v10:
> > *use mhdp helper driver to replace macro functions, move maibox
> > access function and mhdp hdmi/dp common API functions into the
> > driver.
> >
> > drivers/gpu/drm/bridge/cadence/Kconfig | 4 +
> > drivers/gpu/drm/bridge/cadence/Makefile | 1 +
> > .../gpu/drm/bridge/cadence/cdns-mhdp-helper.c | 304 +++++++++++++
> > .../drm/bridge/cadence/cdns-mhdp8546-core.c | 403 +++---------------
> > .../drm/bridge/cadence/cdns-mhdp8546-core.h | 44 +-
> > include/drm/bridge/cdns-mhdp-helper.h | 94 ++++
> > 6 files changed, 476 insertions(+), 374 deletions(-) create mode
> > 100644 drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c
> > create mode 100644 include/drm/bridge/cdns-mhdp-helper.h
> >
> > diff --git a/drivers/gpu/drm/bridge/cadence/Kconfig
> > b/drivers/gpu/drm/bridge/cadence/Kconfig index
> > ec35215a20034..0b7b4626a7af0
> > 100644
> > --- a/drivers/gpu/drm/bridge/cadence/Kconfig
> > +++ b/drivers/gpu/drm/bridge/cadence/Kconfig
> > @@ -20,6 +20,9 @@ config DRM_CDNS_DSI_J721E
> > the routing of the DSS DPI signal to the Cadence DSI.
> > endif
> >
> > +config CDNS_MHDP_HELPER
> > + tristate
> > +
> > config DRM_CDNS_MHDP8546
> > tristate "Cadence DPI/DP bridge"
> > select DRM_DISPLAY_DP_HELPER
> > @@ -27,6 +30,7 @@ config DRM_CDNS_MHDP8546
> > select DRM_DISPLAY_HELPER
> > select DRM_KMS_HELPER
> > select DRM_PANEL_BRIDGE
> > + select CDNS_MHDP_HELPER
> > depends on OF
> > help
> > Support Cadence DPI to DP bridge. This is an internal diff
> > --git a/drivers/gpu/drm/bridge/cadence/Makefile
> > b/drivers/gpu/drm/bridge/cadence/Makefile index
> > c95fd5b81d137..087dc074820d7 100644
> > --- a/drivers/gpu/drm/bridge/cadence/Makefile
> > +++ b/drivers/gpu/drm/bridge/cadence/Makefile
> > @@ -2,6 +2,7 @@
> > obj-$(CONFIG_DRM_CDNS_DSI) += cdns-dsi.o cdns-dsi-y :=
> > cdns-dsi-core.o
> > cdns-dsi-$(CONFIG_DRM_CDNS_DSI_J721E) += cdns-dsi-j721e.o
> > +obj-$(CONFIG_CDNS_MHDP_HELPER) += cdns-mhdp-helper.o
> > obj-$(CONFIG_DRM_CDNS_MHDP8546) += cdns-mhdp8546.o
> cdns-mhdp8546-y
> > := cdns-mhdp8546-core.o cdns-mhdp8546-hdcp.o
> > cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) +=
> > cdns-mhdp8546-j721e.o diff --git
> > a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c
> > b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c new file mode
> > 100644 index 0000000000000..8cabd79ad9663
> > --- /dev/null
> > +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-helper.c
> > @@ -0,0 +1,304 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (C) 2023 NXP Semiconductor, Inc.
> > + *
> > + */
> > +#include <drm/bridge/cdns-mhdp-helper.h> #include
> > +<linux/dev_printk.h> #include <linux/module.h>
> > +
> > +/* Mailbox helper functions */
> > +static int cdns_mhdp_mailbox_read(struct cdns_mhdp_base *base) {
> > + int ret, empty;
> > +
> > + WARN_ON(!mutex_is_locked(base->mbox_mutex));
>
> Actually this should be moved to cdns_mhdp_mailbox_recv_header() and
> cdns_mhdp_mailbox_recv_data().
Yes, it could be moved to cdns_mhdp_mailbox_send() only and removed from cdns_mhdp_mailbox_read()
cdns_mhdp_mailbox_write(), but those mailbox access functions are move from cdns-mhdp8546-core.c,
I think it had better keep the same implement in this patch set. Another patch may need to fix it.
>
> > + ret = readx_poll_timeout(readl, base->regs +
> CDNS_MAILBOX_EMPTY,
> > + empty, !empty, MAILBOX_RETRY_US,
> > + MAILBOX_TIMEOUT_US);
> > + if (ret < 0)
> > + return ret;
> > +
> > + return readl(base->regs + CDNS_MAILBOX_RX_DATA) & 0xff; }
> > +
> > +static int cdns_mhdp_mailbox_write(struct cdns_mhdp_base *base, u8
> > +val) {
> > + int ret, full;
> > +
> > + WARN_ON(!mutex_is_locked(base->mbox_mutex));
>
> I think this should be moved to cdns_mhdp_mailbox_send() as well.
Same reply as above.
>
> > + ret = readx_poll_timeout(readl, base->regs + CDNS_MAILBOX_FULL,
> > + full, !full, MAILBOX_RETRY_US,
> > + MAILBOX_TIMEOUT_US);
> > + if (ret < 0)
> > + return ret;
> > +
> > + writel(val, base->regs + CDNS_MAILBOX_TX_DATA);
> > +
> > + return 0;
> > +}
>
> Nice, much better having these as static now.
Thanks.
>
> > +int cdns_mhdp_mailbox_recv_header(struct cdns_mhdp_base *base,
> > + u8 module_id, u8 opcode,
> > + u16 req_size) {
> > + u32 mbox_size, i;
> > + u8 header[4];
> > + int ret;
> > +
> > + /* read the header of the message */
> > + for (i = 0; i < sizeof(header); i++) {
> > + ret = cdns_mhdp_mailbox_read(base);
> > + if (ret < 0)
> > + return ret;
> > +
> > + header[i] = ret;
> > + }
> > +
> > + mbox_size = get_unaligned_be16(header + 2);
> > +
> > + if (opcode != header[0] || module_id != header[1] ||
> > + req_size != mbox_size) {
> > + /*
> > + * If the message in mailbox is not what we want, we
> > + need
> to
> > + * clear the mailbox by reading its contents.
> > + */
> > + for (i = 0; i < mbox_size; i++)
> > + if (cdns_mhdp_mailbox_read(base) < 0)
> > + break;
> > +
> > + return -EINVAL;
> > + }
> > +
> > + return 0;
> > +}
> > +EXPORT_SYMBOL_GPL(cdns_mhdp_mailbox_recv_header);
> > +
> > +int cdns_mhdp_mailbox_recv_data(struct cdns_mhdp_base *base,
> > + u8 *buff, u16 buff_size) {
> > + u32 i;
> > + int ret;
> > +
> > + for (i = 0; i < buff_size; i++) {
> > + ret = cdns_mhdp_mailbox_read(base);
> > + if (ret < 0)
> > + return ret;
> > +
> > + buff[i] = ret;
> > + }
> > +
> > + return 0;
> > +}
> > +EXPORT_SYMBOL_GPL(cdns_mhdp_mailbox_recv_data);
> > +
> > +int cdns_mhdp_mailbox_send(struct cdns_mhdp_base *base, u8
> module_id,
> > + u8 opcode, u16 size, u8 *message) {
> > + u8 header[4];
> > + int ret, i;
> > +
> > + header[0] = opcode;
> > + header[1] = module_id;
> > + put_unaligned_be16(size, header + 2);
> > +
> > + for (i = 0; i < sizeof(header); i++) {
> > + ret = cdns_mhdp_mailbox_write(base, header[i]);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + for (i = 0; i < size; i++) {
> > + ret = cdns_mhdp_mailbox_write(base, message[i]);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + return 0;
> > +}
> > +EXPORT_SYMBOL_GPL(cdns_mhdp_mailbox_send);
> > +
> > +/* General helper functions */
> > +int cdns_mhdp_reg_read(struct cdns_mhdp_base *base, u32 addr, u32
> > +*value) {
> > + u8 msg[4], resp[8];
> > + int ret;
> > +
> > + put_unaligned_be32(addr, msg);
> > +
> > + mutex_lock(base->mbox_mutex);
> > +
> > + ret = cdns_mhdp_mailbox_send(base, MB_MODULE_ID_GENERAL,
> > + GENERAL_REGISTER_READ,
> > + sizeof(msg), msg);
> > + if (ret)
> > + goto out;
> > +
> > + ret = cdns_mhdp_mailbox_recv_header(base,
> MB_MODULE_ID_GENERAL,
> > +
> GENERAL_REGISTER_READ,
> > + sizeof(resp));
> > + if (ret)
> > + goto out;
> > +
> > + ret = cdns_mhdp_mailbox_recv_data(base, resp, sizeof(resp));
> > + if (ret)
> > + goto out;
> > +
> > + /* Returned address value should be the same as requested */
> > + if (memcmp(msg, resp, sizeof(msg))) {
> > + ret = -EINVAL;
> > + goto out;
> > + }
> > +
> > + *value = get_unaligned_be32(resp + 4);
> > +
> > +out:
> > + mutex_unlock(base->mbox_mutex);
> > + if (ret) {
> > + dev_err(base->dev, "Failed to read register\n");
> > + *value = 0;
> > + }
> > +
> > + return ret;
> > +}
> > +EXPORT_SYMBOL_GPL(cdns_mhdp_reg_read);
> > +
> > +int cdns_mhdp_reg_write(struct cdns_mhdp_base *base, u32 addr, u32
> > +val) {
> > + u8 msg[8];
> > + int ret;
> > +
> > + put_unaligned_be32(addr, msg);
> > + put_unaligned_be32(val, msg + 4);
> > +
> > + mutex_lock(base->mbox_mutex);
> > +
> > + ret = cdns_mhdp_mailbox_send(base, MB_MODULE_ID_GENERAL,
> > + GENERAL_REGISTER_WRITE,
> > + sizeof(msg), msg);
> > +
> > + mutex_unlock(base->mbox_mutex);
> > +
> > + return ret;
> > +}
> > +EXPORT_SYMBOL_GPL(cdns_mhdp_reg_write);
> > +
> > +/* DPTX helper functions */
> > +int cdns_mhdp_dp_reg_write(struct cdns_mhdp_base *base, u16 addr,
> u32
> > +val) {
> > + u8 msg[6];
> > + int ret;
> > +
> > + put_unaligned_be16(addr, msg);
> > + put_unaligned_be32(val, msg + 2);
> > +
> > + mutex_lock(base->mbox_mutex);
> > +
> > + ret = cdns_mhdp_mailbox_send(base, MB_MODULE_ID_DP_TX,
> > + DPTX_WRITE_REGISTER,
> sizeof(msg),
> msg);
> > +
> > + mutex_unlock(base->mbox_mutex);
> > +
> > + return ret;
> > +}
> > +EXPORT_SYMBOL_GPL(cdns_mhdp_dp_reg_write);
> > +
> > +int cdns_mhdp_dp_reg_write_bit(struct cdns_mhdp_base *base, u16 addr,
> > + u8 start_bit, u8 bits_no, u32 val) {
> > + u8 field[8];
> > + int ret;
> > +
> > + put_unaligned_be16(addr, field);
> > + field[2] = start_bit;
> > + field[3] = bits_no;
> > + put_unaligned_be32(val, field + 4);
> > +
> > + mutex_lock(base->mbox_mutex);
> > +
> > + ret = cdns_mhdp_mailbox_send(base, MB_MODULE_ID_DP_TX,
> > + DPTX_WRITE_FIELD,
> sizeof(field),
> field);
> > +
> > + mutex_unlock(base->mbox_mutex);
> > +
> > + return ret;
> > +}
> > +EXPORT_SYMBOL_GPL(cdns_mhdp_dp_reg_write_bit);
> > +
> > +int cdns_mhdp_dpcd_read(struct cdns_mhdp_base *base,
> > + u32 addr, u8 *data, u16 len) {
> > + u8 msg[5], reg[5];
> > + int ret;
> > +
> > + put_unaligned_be16(len, msg);
> > + put_unaligned_be24(addr, msg + 2);
> > +
> > + mutex_lock(base->mbox_mutex);
> > +
> > + ret = cdns_mhdp_mailbox_send(base, MB_MODULE_ID_DP_TX,
> > + DPTX_READ_DPCD, sizeof(msg),
> msg);
> > + if (ret)
> > + goto out;
> > +
> > + ret = cdns_mhdp_mailbox_recv_header(base,
> MB_MODULE_ID_DP_TX,
> > + DPTX_READ_DPCD,
> > + sizeof(reg) + len);
> > + if (ret)
> > + goto out;
> > +
> > + ret = cdns_mhdp_mailbox_recv_data(base, reg, sizeof(reg));
> > + if (ret)
> > + goto out;
> > +
> > + ret = cdns_mhdp_mailbox_recv_data(base, data, len);
> > +
> > +out:
> > + mutex_unlock(base->mbox_mutex);
> > +
> > + return ret;
> > +}
> > +EXPORT_SYMBOL_GPL(cdns_mhdp_dpcd_read);
> > +
> > +int cdns_mhdp_dpcd_write(struct cdns_mhdp_base *base, u32 addr, u8
> > +value) {
> > + u8 msg[6], reg[5];
> > + int ret;
> > +
> > + put_unaligned_be16(1, msg);
> > + put_unaligned_be24(addr, msg + 2);
> > + msg[5] = value;
> > +
> > + mutex_lock(base->mbox_mutex);
> > +
> > + ret = cdns_mhdp_mailbox_send(base, MB_MODULE_ID_DP_TX,
> > + DPTX_WRITE_DPCD,
> sizeof(msg),
> msg);
> > + if (ret)
> > + goto out;
> > +
> > + ret = cdns_mhdp_mailbox_recv_header(base,
> MB_MODULE_ID_DP_TX,
> > + DPTX_WRITE_DPCD,
> sizeof(reg));
> > + if (ret)
> > + goto out;
> > +
> > + ret = cdns_mhdp_mailbox_recv_data(base, reg, sizeof(reg));
> > + if (ret)
> > + goto out;
> > +
> > + if (addr != get_unaligned_be24(reg + 2))
> > + ret = -EINVAL;
>
> No need to have the mutex locked while doing this check. This should be
> moved below 'out' label.
It is to check the recv data for cdns_mhdp_mailbox_recv_data() only,
if moved below "out" label, it will run for every maibox failed.
So it have to be keep in mutex lock.
>
> > +out:
> > + mutex_unlock(base->mbox_mutex);
> > +
> > + if (ret)
> > + dev_err(base->dev, "dpcd write failed: %d\n", ret);
> > + return ret;
> > +}
> > +EXPORT_SYMBOL_GPL(cdns_mhdp_dpcd_write);
> > +
> > +MODULE_DESCRIPTION("Cadence MHDP Helper driver");
> > +MODULE_AUTHOR("Sandor Yu <Sandor.yu@nxp.com>");
> > +MODULE_LICENSE("GPL");
> > diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
> > b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c index
> > 6af565ac307ae..9d9dbb976868c 100644
> > --- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
> > +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
> > @@ -73,298 +73,28 @@ static void cdns_mhdp_bridge_hpd_disable(struct
> > drm_bridge *bridge) mhdp->regs + CDNS_APB_INT_MASK); }
> >
> > -static int cdns_mhdp_mailbox_read(struct cdns_mhdp_device *mhdp) -{
> > - int ret, empty;
> > -
> > - WARN_ON(!mutex_is_locked(&mhdp->mbox_mutex));
> > -
> > - ret = readx_poll_timeout(readl, mhdp->regs +
> CDNS_MAILBOX_EMPTY,
> > - empty, !empty, MAILBOX_RETRY_US,
> > - MAILBOX_TIMEOUT_US);
> > - if (ret < 0)
> > - return ret;
> > -
> > - return readl(mhdp->regs + CDNS_MAILBOX_RX_DATA) & 0xff;
> > -}
> > -
> > -static int cdns_mhdp_mailbox_write(struct cdns_mhdp_device *mhdp, u8
> > val) -{
> > - int ret, full;
> > -
> > - WARN_ON(!mutex_is_locked(&mhdp->mbox_mutex));
> > -
> > - ret = readx_poll_timeout(readl, mhdp->regs +
> CDNS_MAILBOX_FULL,
> > - full, !full, MAILBOX_RETRY_US,
> > - MAILBOX_TIMEOUT_US);
> > - if (ret < 0)
> > - return ret;
> > -
> > - writel(val, mhdp->regs + CDNS_MAILBOX_TX_DATA);
> > -
> > - return 0;
> > -}
> > -
> > -static int cdns_mhdp_mailbox_recv_header(struct cdns_mhdp_device
> *mhdp,
> > - u8 module_id, u8 opcode,
> > - u16 req_size)
> > -{
> > - u32 mbox_size, i;
> > - u8 header[4];
> > - int ret;
> > -
> > - /* read the header of the message */
> > - for (i = 0; i < sizeof(header); i++) {
> > - ret = cdns_mhdp_mailbox_read(mhdp);
> > - if (ret < 0)
> > - return ret;
> > -
> > - header[i] = ret;
> > - }
> > -
> > - mbox_size = get_unaligned_be16(header + 2);
> > -
> > - if (opcode != header[0] || module_id != header[1] ||
> > - req_size != mbox_size) {
> > - /*
> > - * If the message in mailbox is not what we want, we need
> to
> > - * clear the mailbox by reading its contents.
> > - */
> > - for (i = 0; i < mbox_size; i++)
> > - if (cdns_mhdp_mailbox_read(mhdp) < 0)
> > - break;
> > -
> > - return -EINVAL;
> > - }
> > -
> > - return 0;
> > -}
> > -
> > -static int cdns_mhdp_mailbox_recv_data(struct cdns_mhdp_device
> *mhdp,
> > - u8 *buff, u16 buff_size)
> > -{
> > - u32 i;
> > - int ret;
> > -
> > - for (i = 0; i < buff_size; i++) {
> > - ret = cdns_mhdp_mailbox_read(mhdp);
> > - if (ret < 0)
> > - return ret;
> > -
> > - buff[i] = ret;
> > - }
> > -
> > - return 0;
> > -}
> > -
> > -static int cdns_mhdp_mailbox_send(struct cdns_mhdp_device *mhdp, u8
> > module_id, - u8 opcode, u16 size, u8
> *message)
> > -{
> > - u8 header[4];
> > - int ret, i;
> > -
> > - header[0] = opcode;
> > - header[1] = module_id;
> > - put_unaligned_be16(size, header + 2);
> > -
> > - for (i = 0; i < sizeof(header); i++) {
> > - ret = cdns_mhdp_mailbox_write(mhdp, header[i]);
> > - if (ret)
> > - return ret;
> > - }
> > -
> > - for (i = 0; i < size; i++) {
> > - ret = cdns_mhdp_mailbox_write(mhdp, message[i]);
> > - if (ret)
> > - return ret;
> > - }
> > -
> > - return 0;
> > -}
> > -
> > -static
> > -int cdns_mhdp_reg_read(struct cdns_mhdp_device *mhdp, u32 addr, u32
> > *value) -{
> > - u8 msg[4], resp[8];
> > - int ret;
> > -
> > - put_unaligned_be32(addr, msg);
> > -
> > - mutex_lock(&mhdp->mbox_mutex);
> > -
> > - ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_GENERAL,
> > - GENERAL_REGISTER_READ,
> > - sizeof(msg), msg);
> > - if (ret)
> > - goto out;
> > -
> > - ret = cdns_mhdp_mailbox_recv_header(mhdp,
> MB_MODULE_ID_GENERAL,
> > -
> GENERAL_REGISTER_READ,
> > - sizeof(resp));
> > - if (ret)
> > - goto out;
> > -
> > - ret = cdns_mhdp_mailbox_recv_data(mhdp, resp, sizeof(resp));
> > - if (ret)
> > - goto out;
> > -
> > - /* Returned address value should be the same as requested */
> > - if (memcmp(msg, resp, sizeof(msg))) {
> > - ret = -EINVAL;
> > - goto out;
> > - }
> > -
> > - *value = get_unaligned_be32(resp + 4);
> > -
> > -out:
> > - mutex_unlock(&mhdp->mbox_mutex);
> > - if (ret) {
> > - dev_err(mhdp->dev, "Failed to read register\n");
> > - *value = 0;
> > - }
> > -
> > - return ret;
> > -}
> > -
> > -static
> > -int cdns_mhdp_reg_write(struct cdns_mhdp_device *mhdp, u16 addr, u32
> > val) -{
> > - u8 msg[6];
> > - int ret;
> > -
> > - put_unaligned_be16(addr, msg);
> > - put_unaligned_be32(val, msg + 2);
> > -
> > - mutex_lock(&mhdp->mbox_mutex);
> > -
> > - ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX,
> > - DPTX_WRITE_REGISTER,
> sizeof(msg),
> msg);
> > -
> > - mutex_unlock(&mhdp->mbox_mutex);
> > -
> > - return ret;
> > -}
> > -
> > static
> > -int cdns_mhdp_reg_write_bit(struct cdns_mhdp_device *mhdp, u16 addr,
> > - u8 start_bit, u8 bits_no, u32 val)
> > -{
> > - u8 field[8];
> > - int ret;
> > -
> > - put_unaligned_be16(addr, field);
> > - field[2] = start_bit;
> > - field[3] = bits_no;
> > - put_unaligned_be32(val, field + 4);
> > -
> > - mutex_lock(&mhdp->mbox_mutex);
> > -
> > - ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX,
> > - DPTX_WRITE_FIELD,
> sizeof(field),
> field);
> > -
> > - mutex_unlock(&mhdp->mbox_mutex);
> > -
> > - return ret;
> > -}
> > -
> > -static
> > -int cdns_mhdp_dpcd_read(struct cdns_mhdp_device *mhdp,
> > - u32 addr, u8 *data, u16 len)
> > -{
> > - u8 msg[5], reg[5];
> > - int ret;
> > -
> > - put_unaligned_be16(len, msg);
> > - put_unaligned_be24(addr, msg + 2);
> > -
> > - mutex_lock(&mhdp->mbox_mutex);
> > -
> > - ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX,
> > - DPTX_READ_DPCD, sizeof(msg),
> msg);
> > - if (ret)
> > - goto out;
> > -
> > - ret = cdns_mhdp_mailbox_recv_header(mhdp,
> MB_MODULE_ID_DP_TX,
> > - DPTX_READ_DPCD,
> > - sizeof(reg) + len);
> > - if (ret)
> > - goto out;
> > -
> > - ret = cdns_mhdp_mailbox_recv_data(mhdp, reg, sizeof(reg));
> > - if (ret)
> > - goto out;
> > -
> > - ret = cdns_mhdp_mailbox_recv_data(mhdp, data, len);
> > -
> > -out:
> > - mutex_unlock(&mhdp->mbox_mutex);
> > -
> > - return ret;
> > -}
> > -
> > -static
> > -int cdns_mhdp_dpcd_write(struct cdns_mhdp_device *mhdp, u32 addr, u8
> > value)
> > +int cdns_mhdp_set_firmware_active(struct cdns_mhdp_device *mhdp,
> bool
> > enable) {
> > - u8 msg[6], reg[5];
> > + u8 status;
> > int ret;
> >
> > - put_unaligned_be16(1, msg);
> > - put_unaligned_be24(addr, msg + 2);
> > - msg[5] = value;
> > -
> > mutex_lock(&mhdp->mbox_mutex);
> >
> > - ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX,
> > - DPTX_WRITE_DPCD,
> sizeof(msg),
> msg);
> > - if (ret)
> > - goto out;
> > -
> > - ret = cdns_mhdp_mailbox_recv_header(mhdp,
> MB_MODULE_ID_DP_TX,
> > - DPTX_WRITE_DPCD,
> sizeof(reg));
> > - if (ret)
> > - goto out;
> > + status = enable ? FW_ACTIVE : FW_STANDBY;
>
> Initialising status can be done outside of the locked mutex.
OK.
>
> > - ret = cdns_mhdp_mailbox_recv_data(mhdp, reg, sizeof(reg));
> > + ret = cdns_mhdp_mailbox_send(&mhdp->base,
> MB_MODULE_ID_GENERAL,
> > + GENERAL_MAIN_CONTROL,
> sizeof(status), &status);
> > if (ret)
> > goto out;
> >
> > - if (addr != get_unaligned_be24(reg + 2))
> > - ret = -EINVAL;
> > -
> > -out:
> > - mutex_unlock(&mhdp->mbox_mutex);
> > -
> > - if (ret)
> > - dev_err(mhdp->dev, "dpcd write failed: %d\n", ret);
> > - return ret;
> > -}
> > -
> > -static
> > -int cdns_mhdp_set_firmware_active(struct cdns_mhdp_device *mhdp,
> bool
> > enable) -{
> > - u8 msg[5];
> > - int ret, i;
> > -
> > - msg[0] = GENERAL_MAIN_CONTROL;
> > - msg[1] = MB_MODULE_ID_GENERAL;
> > - msg[2] = 0;
> > - msg[3] = 1;
> > - msg[4] = enable ? FW_ACTIVE : FW_STANDBY;
> > -
> > - mutex_lock(&mhdp->mbox_mutex);
> > -
> > - for (i = 0; i < sizeof(msg); i++) {
> > - ret = cdns_mhdp_mailbox_write(mhdp, msg[i]);
> > - if (ret)
> > - goto out;
> > - }
> > -
> > - /* read the firmware state */
> > - ret = cdns_mhdp_mailbox_recv_data(mhdp, msg, sizeof(msg));
> > + ret = cdns_mhdp_mailbox_recv_header(&mhdp->base,
> MB_MODULE_ID_GENERAL,
> > +
> GENERAL_MAIN_CONTROL,
> > + sizeof(status));
> > if (ret)
> > goto out;
> >
> > - ret = 0;
> > + ret = cdns_mhdp_mailbox_recv_data(&mhdp->base, &status,
> sizeof(status));
> >
> > out:
> > mutex_unlock(&mhdp->mbox_mutex); @@ -382,18 +112,18 @@
> int
> > cdns_mhdp_get_hpd_status(struct cdns_mhdp_device
> > *mhdp)
> >
> > mutex_lock(&mhdp->mbox_mutex);
> >
> > - ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX,
> > + ret = cdns_mhdp_mailbox_send(&mhdp->base,
> MB_MODULE_ID_DP_TX,
> > DPTX_HPD_STATE, 0, NULL);
> > if (ret)
> > goto err_get_hpd;
> >
> > - ret = cdns_mhdp_mailbox_recv_header(mhdp,
> MB_MODULE_ID_DP_TX,
> > + ret = cdns_mhdp_mailbox_recv_header(&mhdp->base,
> > + MB_MODULE_ID_DP_TX,
> > DPTX_HPD_STATE,
> > sizeof(status));
> > if (ret)
> > goto err_get_hpd;
> >
> > - ret = cdns_mhdp_mailbox_recv_data(mhdp, &status, sizeof(status));
> > + ret = cdns_mhdp_mailbox_recv_data(&mhdp->base, &status,
> sizeof(status));
> > if (ret)
> > goto err_get_hpd;
> >
> > @@ -424,22 +154,22 @@ int cdns_mhdp_get_edid_block(void *data, u8
> *edid,
> > msg[0] = block / 2;
> > msg[1] = block % 2;
> >
> > - ret = cdns_mhdp_mailbox_send(mhdp,
> MB_MODULE_ID_DP_TX,
> > + ret = cdns_mhdp_mailbox_send(&mhdp->base,
> MB_MODULE_ID_DP_TX,
> > DPTX_GET_EDID,
> sizeof(msg), msg);
> > if (ret)
> > continue;
> >
> > - ret = cdns_mhdp_mailbox_recv_header(mhdp,
> MB_MODULE_ID_DP_TX,
> > + ret = cdns_mhdp_mailbox_recv_header(&mhdp->base,
> MB_MODULE_ID_DP_TX,
> >
> DPTX_GET_EDID,
> > sizeof(reg) +
> length);
> > if (ret)
> > continue;
> >
> > - ret = cdns_mhdp_mailbox_recv_data(mhdp, reg,
> sizeof(reg));
> > + ret = cdns_mhdp_mailbox_recv_data(&mhdp->base, reg,
> sizeof(reg));
> > if (ret)
> > continue;
> >
> > - ret = cdns_mhdp_mailbox_recv_data(mhdp, edid, length);
> > + ret = cdns_mhdp_mailbox_recv_data(&mhdp->base, edid,
> length);
> > if (ret)
> > continue;
> >
> > @@ -464,17 +194,17 @@ int cdns_mhdp_read_hpd_event(struct
> > cdns_mhdp_device
> > *mhdp)
> >
> > mutex_lock(&mhdp->mbox_mutex);
> >
> > - ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX,
> > + ret = cdns_mhdp_mailbox_send(&mhdp->base,
> MB_MODULE_ID_DP_TX,
> > DPTX_READ_EVENT, 0, NULL);
> > if (ret)
> > goto out;
> >
> > - ret = cdns_mhdp_mailbox_recv_header(mhdp,
> MB_MODULE_ID_DP_TX,
> > + ret = cdns_mhdp_mailbox_recv_header(&mhdp->base,
> > + MB_MODULE_ID_DP_TX,
> > DPTX_READ_EVENT,
> sizeof(event));
> > if (ret < 0)
> > goto out;
> >
> > - ret = cdns_mhdp_mailbox_recv_data(mhdp, &event, sizeof(event));
> > + ret = cdns_mhdp_mailbox_recv_data(&mhdp->base, &event,
> sizeof(event));
> > out:
> > mutex_unlock(&mhdp->mbox_mutex);
> >
> > @@ -512,20 +242,20 @@ int cdns_mhdp_adjust_lt(struct
> cdns_mhdp_device
> > *mhdp, unsigned int nlanes,
> >
> > mutex_lock(&mhdp->mbox_mutex);
> >
> > - ret = cdns_mhdp_mailbox_send(mhdp, MB_MODULE_ID_DP_TX,
> > + ret = cdns_mhdp_mailbox_send(&mhdp->base,
> MB_MODULE_ID_DP_TX,
> > DPTX_ADJUST_LT,
> > sizeof(payload), payload);
> > if (ret)
> > goto out;
> >
> > /* Yes, read the DPCD read command response */
> > - ret = cdns_mhdp_mailbox_recv_header(mhdp,
> MB_MODULE_ID_DP_TX,
> > + ret = cdns_mhdp_mailbox_recv_header(&mhdp->base,
> > + MB_MODULE_ID_DP_TX,
> > DPTX_READ_DPCD,
> > sizeof(hdr) +
> DP_LINK_STATUS_SIZE);
> > if (ret)
> > goto out;
> >
> > - ret = cdns_mhdp_mailbox_recv_data(mhdp, hdr, sizeof(hdr));
> > + ret = cdns_mhdp_mailbox_recv_data(&mhdp->base, hdr,
> > + sizeof(hdr));
> > if (ret)
> > goto out;
> >
> > @@ -533,7 +263,7 @@ int cdns_mhdp_adjust_lt(struct cdns_mhdp_device
> > *mhdp, unsigned int nlanes, if (addr != DP_LANE0_1_STATUS)
> > goto out;
> >
> > - ret = cdns_mhdp_mailbox_recv_data(mhdp, link_status,
> > + ret = cdns_mhdp_mailbox_recv_data(&mhdp->base, link_status,
> > DP_LINK_STATUS_SIZE);
> >
> > out:
> > @@ -847,7 +577,7 @@ static ssize_t cdns_mhdp_transfer(struct
> > drm_dp_aux *aux, unsigned int i;
> >
> > for (i = 0; i < msg->size; ++i) {
> > - ret = cdns_mhdp_dpcd_write(mhdp,
> > + ret = cdns_mhdp_dpcd_write(&mhdp->base,
> > msg->address
> +
> i, buf[i]);
> > if (!ret)
> > continue; @@ -859,7 +589,7 @@
> static
> > ssize_t cdns_mhdp_transfer(struct drm_dp_aux *aux, return ret;
> > }
> > } else {
> > - ret = cdns_mhdp_dpcd_read(mhdp, msg->address,
> > + ret = cdns_mhdp_dpcd_read(&mhdp->base,
> msg->address,
> > msg->buffer, msg->size);
> > if (ret) {
> > dev_err(mhdp->dev, @@ -887,12 +617,12 @@
> static
> > int cdns_mhdp_link_training_init(struct
> > cdns_mhdp_device *mhdp) if (!mhdp->host.scrambler)
> > reg32 |= CDNS_PHY_SCRAMBLER_BYPASS;
> >
> > - cdns_mhdp_reg_write(mhdp, CDNS_DPTX_PHY_CONFIG, reg32);
> > + cdns_mhdp_reg_write(&mhdp->base, CDNS_DPTX_PHY_CONFIG,
> reg32);
> >
> > - cdns_mhdp_reg_write(mhdp, CDNS_DP_ENHNCD,
> > + cdns_mhdp_reg_write(&mhdp->base, CDNS_DP_ENHNCD,
> > mhdp->sink.enhanced &
> mhdp->host.enhanced);
> >
> > - cdns_mhdp_reg_write(mhdp, CDNS_DP_LANE_EN,
> > + cdns_mhdp_reg_write(&mhdp->base, CDNS_DP_LANE_EN,
> > CDNS_DP_LANE_EN_LANES(mhdp-
> >link.num_lanes));
> >
> > cdns_mhdp_link_configure(&mhdp->aux, &mhdp->link); @@ -913,7
> > +643,7 @@ static int cdns_mhdp_link_training_init(struct
> > cdns_mhdp_device *mhdp) return ret;
> > }
> >
> > - cdns_mhdp_reg_write(mhdp, CDNS_DPTX_PHY_CONFIG,
> > + cdns_mhdp_reg_write(&mhdp->base, CDNS_DPTX_PHY_CONFIG,
> > CDNS_PHY_COMMON_CONFIG |
> > CDNS_PHY_TRAINING_EN |
> > CDNS_PHY_TRAINING_TYPE(1) | @@
> -1058,7
> > +788,7 @@ static bool cdns_mhdp_link_training_channel_eq(struct
> > cdns_mhdp_device *mhdp, CDNS_PHY_TRAINING_TYPE(eq_tps);
> > if (eq_tps != 4)
> > reg32 |= CDNS_PHY_SCRAMBLER_BYPASS;
> > - cdns_mhdp_reg_write(mhdp, CDNS_DPTX_PHY_CONFIG, reg32);
> > + cdns_mhdp_reg_write(&mhdp->base, CDNS_DPTX_PHY_CONFIG,
> reg32);
> >
> > drm_dp_dpcd_writeb(&mhdp->aux, DP_TRAINING_PATTERN_SET,
> > (eq_tps != 4) ? eq_tps |
> DP_LINK_SCRAMBLING_DISABLE :
> > @@ -1322,7 +1052,7 @@ static int cdns_mhdp_link_training(struct
> > cdns_mhdp_device *mhdp, mhdp->host.scrambler ? 0 :
> > DP_LINK_SCRAMBLING_DISABLE);
> >
> > - ret = cdns_mhdp_reg_read(mhdp,
> CDNS_DP_FRAMER_GLOBAL_CONFIG,
> ®32);
> > + ret = cdns_mhdp_reg_read(&mhdp->base,
> > + CDNS_DP_FRAMER_GLOBAL_CONFIG,
> > ®32); if (ret < 0) {
> > dev_err(mhdp->dev,
> > "Failed to read
> CDNS_DP_FRAMER_GLOBAL_CONFIG
> %d\n",
> > @@ -1333,13 +1063,13 @@ static int cdns_mhdp_link_training(struct
> > cdns_mhdp_device *mhdp, reg32 |=
> CDNS_DP_NUM_LANES(mhdp->link.num_lanes);
> > reg32 |= CDNS_DP_WR_FAILING_EDGE_VSYNC;
> > reg32 |= CDNS_DP_FRAMER_EN;
> > - cdns_mhdp_reg_write(mhdp, CDNS_DP_FRAMER_GLOBAL_CONFIG,
> reg32);
> > + cdns_mhdp_reg_write(&mhdp->base,
> CDNS_DP_FRAMER_GLOBAL_CONFIG,
> reg32);
> >
> > /* Reset PHY config */
> > reg32 = CDNS_PHY_COMMON_CONFIG |
> CDNS_PHY_TRAINING_TYPE(1);
> > if (!mhdp->host.scrambler)
> > reg32 |= CDNS_PHY_SCRAMBLER_BYPASS;
> > - cdns_mhdp_reg_write(mhdp, CDNS_DPTX_PHY_CONFIG, reg32);
> > + cdns_mhdp_reg_write(&mhdp->base, CDNS_DPTX_PHY_CONFIG,
> reg32);
> >
> > return 0;
> > err:
> > @@ -1347,7 +1077,7 @@ static int cdns_mhdp_link_training(struct
> > cdns_mhdp_device *mhdp, reg32 = CDNS_PHY_COMMON_CONFIG |
> > CDNS_PHY_TRAINING_TYPE(1);
> > if (!mhdp->host.scrambler)
> > reg32 |= CDNS_PHY_SCRAMBLER_BYPASS;
> > - cdns_mhdp_reg_write(mhdp, CDNS_DPTX_PHY_CONFIG, reg32);
> > + cdns_mhdp_reg_write(&mhdp->base, CDNS_DPTX_PHY_CONFIG,
> reg32);
> >
> > drm_dp_dpcd_writeb(&mhdp->aux, DP_TRAINING_PATTERN_SET,
> > DP_TRAINING_PATTERN_DISABLE); @@
> -1461,7
> > +1191,7 @@ static int cdns_mhdp_link_up(struct cdns_mhdp_device
> > *mhdp) mhdp->link.num_lanes = cdns_mhdp_max_num_lanes(mhdp);
> >
> > /* Disable framer for link training */
> > - err = cdns_mhdp_reg_read(mhdp,
> CDNS_DP_FRAMER_GLOBAL_CONFIG, &resp);
> > + err = cdns_mhdp_reg_read(&mhdp->base,
> > + CDNS_DP_FRAMER_GLOBAL_CONFIG,
> > &resp); if (err < 0) {
> > dev_err(mhdp->dev,
> > "Failed to read
> CDNS_DP_FRAMER_GLOBAL_CONFIG
> %d\n",
> > @@ -1470,7 +1200,7 @@ static int cdns_mhdp_link_up(struct
> > cdns_mhdp_device
> > *mhdp) }
> >
> > resp &= ~CDNS_DP_FRAMER_EN;
> > - cdns_mhdp_reg_write(mhdp, CDNS_DP_FRAMER_GLOBAL_CONFIG,
> resp);
> > + cdns_mhdp_reg_write(&mhdp->base,
> CDNS_DP_FRAMER_GLOBAL_CONFIG,
> resp);
> >
> > /* Spread AMP if required, enable 8b/10b coding */
> > amp[0] = cdns_mhdp_get_ssc_supported(mhdp) ?
> DP_SPREAD_AMP_0_5 :
> > 0; @@ -1837,7 +1567,7 @@ static void cdns_mhdp_configure_video(struct
> > cdns_mhdp_device *mhdp, if (mode->flags &
> DRM_MODE_FLAG_INTERLACE)
> > bnd_hsync2vsync |=
> CDNS_IP_DET_INTERLACE_FORMAT;
> >
> > - cdns_mhdp_reg_write(mhdp,
> CDNS_BND_HSYNC2VSYNC(stream_id),
> > + cdns_mhdp_reg_write(&mhdp->base,
> > + CDNS_BND_HSYNC2VSYNC(stream_id),
> > bnd_hsync2vsync);
> >
> > hsync2vsync_pol_ctrl = 0;
> > @@ -1845,10 +1575,10 @@ static void cdns_mhdp_configure_video(struct
> > cdns_mhdp_device *mhdp, hsync2vsync_pol_ctrl |=
> > CDNS_H2V_HSYNC_POL_ACTIVE_LOW;
> > if (mode->flags & DRM_MODE_FLAG_NVSYNC)
> > hsync2vsync_pol_ctrl |=
> CDNS_H2V_VSYNC_POL_ACTIVE_LOW;
> > - cdns_mhdp_reg_write(mhdp,
> CDNS_HSYNC2VSYNC_POL_CTRL(stream_id),
> > + cdns_mhdp_reg_write(&mhdp->base,
> CDNS_HSYNC2VSYNC_POL_CTRL(stream_id),
> > hsync2vsync_pol_ctrl);
> >
> > - cdns_mhdp_reg_write(mhdp,
> CDNS_DP_FRAMER_PXL_REPR(stream_id),
> pxl_repr);
> > + cdns_mhdp_reg_write(&mhdp->base,
> > + CDNS_DP_FRAMER_PXL_REPR(stream_id),
> > pxl_repr);
> >
> > if (mode->flags & DRM_MODE_FLAG_INTERLACE)
> > dp_framer_sp |= CDNS_DP_FRAMER_INTERLACE; @@
> -1856,19
> > +1586,19 @@ static void cdns_mhdp_configure_video(struct
> > cdns_mhdp_device *mhdp, dp_framer_sp |=
> CDNS_DP_FRAMER_HSYNC_POL_LOW;
> > if (mode->flags & DRM_MODE_FLAG_NVSYNC)
> > dp_framer_sp |= CDNS_DP_FRAMER_VSYNC_POL_LOW;
> > - cdns_mhdp_reg_write(mhdp, CDNS_DP_FRAMER_SP(stream_id),
> dp_framer_sp);
> > + cdns_mhdp_reg_write(&mhdp->base,
> CDNS_DP_FRAMER_SP(stream_id),
> > dp_framer_sp);
> >
> > front_porch = mode->crtc_hsync_start - mode->crtc_hdisplay;
> > back_porch = mode->crtc_htotal - mode->crtc_hsync_end;
> > - cdns_mhdp_reg_write(mhdp,
> CDNS_DP_FRONT_BACK_PORCH(stream_id),
> > + cdns_mhdp_reg_write(&mhdp->base,
> CDNS_DP_FRONT_BACK_PORCH(stream_id),
> > CDNS_DP_FRONT_PORCH(front_porch) |
> > CDNS_DP_BACK_PORCH(back_porch));
> >
> > - cdns_mhdp_reg_write(mhdp, CDNS_DP_BYTE_COUNT(stream_id),
> > + cdns_mhdp_reg_write(&mhdp->base,
> CDNS_DP_BYTE_COUNT(stream_id),
> > mode->crtc_hdisplay * bpp / 8);
> >
> > msa_h0 = mode->crtc_htotal - mode->crtc_hsync_start;
> > - cdns_mhdp_reg_write(mhdp,
> CDNS_DP_MSA_HORIZONTAL_0(stream_id),
> > + cdns_mhdp_reg_write(&mhdp->base,
> CDNS_DP_MSA_HORIZONTAL_0(stream_id),
> >
> CDNS_DP_MSAH0_H_TOTAL(mode->crtc_htotal) |
> >
> CDNS_DP_MSAH0_HSYNC_START(msa_h0));
> >
> > @@ -1877,11 +1607,11 @@ static void cdns_mhdp_configure_video(struct
> > cdns_mhdp_device *mhdp,
> CDNS_DP_MSAH1_HDISP_WIDTH(mode->crtc_hdisplay);
> > if (mode->flags & DRM_MODE_FLAG_NHSYNC)
> > msa_horizontal_1 |=
> CDNS_DP_MSAH1_HSYNC_POL_LOW;
> > - cdns_mhdp_reg_write(mhdp,
> CDNS_DP_MSA_HORIZONTAL_1(stream_id),
> > + cdns_mhdp_reg_write(&mhdp->base,
> CDNS_DP_MSA_HORIZONTAL_1(stream_id),
> > msa_horizontal_1);
> >
> > msa_v0 = mode->crtc_vtotal - mode->crtc_vsync_start;
> > - cdns_mhdp_reg_write(mhdp,
> CDNS_DP_MSA_VERTICAL_0(stream_id),
> > + cdns_mhdp_reg_write(&mhdp->base,
> > + CDNS_DP_MSA_VERTICAL_0(stream_id),
> >
> CDNS_DP_MSAV0_V_TOTAL(mode->crtc_vtotal) |
> >
> CDNS_DP_MSAV0_VSYNC_START(msa_v0));
> >
> > @@ -1890,7 +1620,7 @@ static void cdns_mhdp_configure_video(struct
> > cdns_mhdp_device *mhdp,
> CDNS_DP_MSAV1_VDISP_WIDTH(mode->crtc_vdisplay);
> > if (mode->flags & DRM_MODE_FLAG_NVSYNC)
> > msa_vertical_1 |= CDNS_DP_MSAV1_VSYNC_POL_LOW;
> > - cdns_mhdp_reg_write(mhdp,
> CDNS_DP_MSA_VERTICAL_1(stream_id),
> > + cdns_mhdp_reg_write(&mhdp->base,
> > + CDNS_DP_MSA_VERTICAL_1(stream_id),
> > msa_vertical_1);
> >
> > if ((mode->flags & DRM_MODE_FLAG_INTERLACE) && @@
> -1902,14
> > +1632,14 @@ static void cdns_mhdp_configure_video(struct
> > cdns_mhdp_device *mhdp, if (pxlfmt == DRM_COLOR_FORMAT_YCBCR420)
> > misc1 = CDNS_DP_TEST_VSC_SDP;
> >
> > - cdns_mhdp_reg_write(mhdp, CDNS_DP_MSA_MISC(stream_id),
> > + cdns_mhdp_reg_write(&mhdp->base,
> CDNS_DP_MSA_MISC(stream_id),
> > misc0 | (misc1 << 8));
> >
> > - cdns_mhdp_reg_write(mhdp, CDNS_DP_HORIZONTAL(stream_id),
> > + cdns_mhdp_reg_write(&mhdp->base,
> CDNS_DP_HORIZONTAL(stream_id),
> > CDNS_DP_H_HSYNC_WIDTH(hsync) |
> >
> CDNS_DP_H_H_TOTAL(mode->crtc_hdisplay));
> >
> > - cdns_mhdp_reg_write(mhdp, CDNS_DP_VERTICAL_0(stream_id),
> > + cdns_mhdp_reg_write(&mhdp->base,
> CDNS_DP_VERTICAL_0(stream_id),
> >
> CDNS_DP_V0_VHEIGHT(mode->crtc_vdisplay) |
> > CDNS_DP_V0_VSTART(msa_v0));
> >
> > @@ -1918,13 +1648,13 @@ static void cdns_mhdp_configure_video(struct
> > cdns_mhdp_device *mhdp, mode->crtc_vtotal % 2 == 0)
> > dp_vertical_1 |= CDNS_DP_V1_VTOTAL_EVEN;
> >
> > - cdns_mhdp_reg_write(mhdp, CDNS_DP_VERTICAL_1(stream_id),
> dp_vertical_1);
> > + cdns_mhdp_reg_write(&mhdp->base,
> CDNS_DP_VERTICAL_1(stream_id),
> > dp_vertical_1);
> >
> > - cdns_mhdp_reg_write_bit(mhdp, CDNS_DP_VB_ID(stream_id), 2, 1,
> > - (mode->flags &
> DRM_MODE_FLAG_INTERLACE) ?
> > - CDNS_DP_VB_ID_INTERLACED : 0);
> > + cdns_mhdp_dp_reg_write_bit(&mhdp->base,
> > + CDNS_DP_VB_ID(stream_id), 2,
> 1,
> > + (mode->flags &
> DRM_MODE_FLAG_INTERLACE) ?
> > + CDNS_DP_VB_ID_INTERLACED :
> 0);
> >
> > - ret = cdns_mhdp_reg_read(mhdp,
> CDNS_DP_FRAMER_GLOBAL_CONFIG,
> &framer);
> > + ret = cdns_mhdp_reg_read(&mhdp->base,
> > + CDNS_DP_FRAMER_GLOBAL_CONFIG,
> > &framer); if (ret < 0) {
> > dev_err(mhdp->dev,
> > "Failed to read
> CDNS_DP_FRAMER_GLOBAL_CONFIG
> %d\n",
> > @@ -1933,7 +1663,7 @@ static void cdns_mhdp_configure_video(struct
> > cdns_mhdp_device *mhdp, }
> > framer |= CDNS_DP_FRAMER_EN;
> > framer &= ~CDNS_DP_NO_VIDEO_MODE;
> > - cdns_mhdp_reg_write(mhdp, CDNS_DP_FRAMER_GLOBAL_CONFIG,
> framer);
> > + cdns_mhdp_reg_write(&mhdp->base,
> CDNS_DP_FRAMER_GLOBAL_CONFIG,
> framer);
> > }
> >
> > static void cdns_mhdp_sst_enable(struct cdns_mhdp_device *mhdp, @@
> > -1966,15 +1696,15 @@ static void cdns_mhdp_sst_enable(struct
> > cdns_mhdp_device *mhdp,
> >
> > mhdp->stream_id = 0;
> >
> > - cdns_mhdp_reg_write(mhdp, CDNS_DP_FRAMER_TU,
> > + cdns_mhdp_reg_write(&mhdp->base, CDNS_DP_FRAMER_TU,
> > CDNS_DP_FRAMER_TU_VS(vs) |
> > CDNS_DP_FRAMER_TU_SIZE(tu_size) |
> > CDNS_DP_FRAMER_TU_CNT_RST_EN);
> >
> > - cdns_mhdp_reg_write(mhdp, CDNS_DP_LINE_THRESH(0),
> > + cdns_mhdp_reg_write(&mhdp->base, CDNS_DP_LINE_THRESH(0),
> > line_thresh & GENMASK(5, 0));
> >
> > - cdns_mhdp_reg_write(mhdp, CDNS_DP_STREAM_CONFIG_2(0),
> > + cdns_mhdp_reg_write(&mhdp->base,
> CDNS_DP_STREAM_CONFIG_2(0),
> > CDNS_DP_SC2_TU_VS_DIFF((tu_size - vs >
> 3) ?
> > 0 : tu_size -
> vs));
> >
> > @@ -2009,13 +1739,13 @@ static void cdns_mhdp_atomic_enable(struct
> > drm_bridge *bridge, mhdp->info->ops->enable(mhdp);
> >
> > /* Enable VIF clock for stream 0 */
> > - ret = cdns_mhdp_reg_read(mhdp, CDNS_DPTX_CAR, &resp);
> > + ret = cdns_mhdp_reg_read(&mhdp->base, CDNS_DPTX_CAR,
> &resp);
> > if (ret < 0) {
> > dev_err(mhdp->dev, "Failed to read
> CDNS_DPTX_CAR %d\n",
> ret);
> > goto out;
> > }
> >
> > - cdns_mhdp_reg_write(mhdp, CDNS_DPTX_CAR,
> > + cdns_mhdp_reg_write(&mhdp->base, CDNS_DPTX_CAR,
> > resp | CDNS_VIF_CLK_EN |
> CDNS_VIF_CLK_RSTN);
> >
> > connector = drm_atomic_get_new_connector_for_encoder(state,
> > @@ -2083,16 +1813,16 @@ static void cdns_mhdp_atomic_disable(struct
> > drm_bridge *bridge, cdns_mhdp_hdcp_disable(mhdp);
> >
> > mhdp->bridge_enabled = false;
> > - cdns_mhdp_reg_read(mhdp, CDNS_DP_FRAMER_GLOBAL_CONFIG,
> &resp);
> > + cdns_mhdp_reg_read(&mhdp->base,
> CDNS_DP_FRAMER_GLOBAL_CONFIG,
> &resp);
> > resp &= ~CDNS_DP_FRAMER_EN;
> > resp |= CDNS_DP_NO_VIDEO_MODE;
> > - cdns_mhdp_reg_write(mhdp, CDNS_DP_FRAMER_GLOBAL_CONFIG,
> resp);
> > + cdns_mhdp_reg_write(&mhdp->base,
> CDNS_DP_FRAMER_GLOBAL_CONFIG,
> resp);
> >
> > cdns_mhdp_link_down(mhdp);
> >
> > /* Disable VIF clock for stream 0 */
> > - cdns_mhdp_reg_read(mhdp, CDNS_DPTX_CAR, &resp);
> > - cdns_mhdp_reg_write(mhdp, CDNS_DPTX_CAR,
> > + cdns_mhdp_reg_read(&mhdp->base, CDNS_DPTX_CAR, &resp);
> > + cdns_mhdp_reg_write(&mhdp->base, CDNS_DPTX_CAR,
> > resp & ~(CDNS_VIF_CLK_EN |
> CDNS_VIF_CLK_RSTN));
> >
> > if (mhdp->info && mhdp->info->ops && mhdp->info->ops->disable)
> > @@ -2502,6 +2232,11 @@ static int cdns_mhdp_probe(struct
> > platform_device
> > *pdev)
> >
> > platform_set_drvdata(pdev, mhdp);
> >
> > + /* init base struct for access mailbox */
> > + mhdp->base.dev = mhdp->dev;
> > + mhdp->base.regs = mhdp->regs;
> > + mhdp->base.mbox_mutex = &mhdp->mbox_mutex;
> > +
> > mhdp->info = of_device_get_match_data(dev);
> >
> > clk_prepare_enable(clk);
> > diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h
> > b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h index
> > bad2fc0c73066..f08db38c82bbd 100644
> > --- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h
> > +++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.h
> > @@ -15,6 +15,7 @@
> > #include <linux/mutex.h>
> > #include <linux/spinlock.h>
> >
> > +#include <drm/bridge/cdns-mhdp-helper.h>
> > #include <drm/display/drm_dp_helper.h> #include <drm/drm_bridge.h>
> > #include <drm/drm_connector.h> @@ -27,10 +28,6 @@ struct phy;
> > #define CDNS_APB_CTRL 0x00000
> > #define CDNS_CPU_STALL BIT(3)
> >
> > -#define CDNS_MAILBOX_FULL 0x00008
> > -#define CDNS_MAILBOX_EMPTY 0x0000c
> > -#define CDNS_MAILBOX_TX_DATA 0x00010
> > -#define CDNS_MAILBOX_RX_DATA 0x00014
> > #define CDNS_KEEP_ALIVE 0x00018
> > #define CDNS_KEEP_ALIVE_MASK GENMASK(7, 0)
> >
> > @@ -198,45 +195,10 @@ struct phy;
> > #define CDNS_DP_BYTE_COUNT(s)
> (CDNS_DPTX_STREAM(s) + 0x7c)
> > #define CDNS_DP_BYTE_COUNT_BYTES_IN_CHUNK_SHIFT 16
> >
> > -/* mailbox */
> > -#define MAILBOX_RETRY_US 1000
> > -#define MAILBOX_TIMEOUT_US 2000000
> > -
> > -#define MB_OPCODE_ID 0
> > -#define MB_MODULE_ID 1
> > -#define MB_SIZE_MSB_ID 2
> > -#define MB_SIZE_LSB_ID 3
> > -#define MB_DATA_ID 4
> > -
> > -#define MB_MODULE_ID_DP_TX 0x01
> > -#define MB_MODULE_ID_HDCP_TX 0x07
> > -#define MB_MODULE_ID_HDCP_RX 0x08
> > -#define MB_MODULE_ID_HDCP_GENERAL 0x09
> > -#define MB_MODULE_ID_GENERAL 0x0a
> > -
> > -/* firmware and opcodes */
> > +/* firmware */
> > #define FW_NAME
> "cadence/
> mhdp8546.bin"
> > #define CDNS_MHDP_IMEM
> 0x10000
> >
> > -#define GENERAL_MAIN_CONTROL 0x01
> > -#define GENERAL_TEST_ECHO 0x02
> > -#define GENERAL_BUS_SETTINGS 0x03
> > -#define GENERAL_TEST_ACCESS 0x04
> > -#define GENERAL_REGISTER_READ 0x07
> > -
> > -#define DPTX_SET_POWER_MNG 0x00
> > -#define DPTX_GET_EDID 0x02
> > -#define DPTX_READ_DPCD 0x03
> > -#define DPTX_WRITE_DPCD 0x04
> > -#define DPTX_ENABLE_EVENT 0x05
> > -#define DPTX_WRITE_REGISTER 0x06
> > -#define DPTX_READ_REGISTER 0x07
> > -#define DPTX_WRITE_FIELD 0x08
> > -#define DPTX_READ_EVENT 0x0a
> > -#define DPTX_GET_LAST_AUX_STAUS 0x0e
> > -#define DPTX_HPD_STATE 0x11
> > -#define DPTX_ADJUST_LT 0x12
> > -
> > #define FW_STANDBY 0
> > #define FW_ACTIVE 1
> >
> > @@ -352,6 +314,8 @@ struct cdns_mhdp_hdcp { };
> >
> > struct cdns_mhdp_device {
> > + struct cdns_mhdp_base base;
> > +
> > void __iomem *regs;
> > void __iomem *sapb_regs;
> > void __iomem *j721e_regs;
> > diff --git a/include/drm/bridge/cdns-mhdp-helper.h
> > b/include/drm/bridge/cdns-mhdp-helper.h new file mode 100644 index
> > 0000000000000..477e67601ee5f
> > --- /dev/null
> > +++ b/include/drm/bridge/cdns-mhdp-helper.h
> > @@ -0,0 +1,94 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (C) 2023 NXP Semiconductor, Inc.
> > + */
> > +#ifndef __CDNS_MHDP_HELPER_H__
> > +#define __CDNS_MHDP_HELPER_H__
> > +
> > +#include <asm/unaligned.h>
> > +#include <linux/iopoll.h>
> > +
> > +/* mailbox regs offset */
> > +#define CDNS_MAILBOX_FULL 0x00008
> > +#define CDNS_MAILBOX_EMPTY 0x0000c
> > +#define CDNS_MAILBOX_TX_DATA 0x00010
> > +#define CDNS_MAILBOX_RX_DATA 0x00014
> > +
> > +#define MAILBOX_RETRY_US 1000
> > +#define MAILBOX_TIMEOUT_US 2000000
> > +
> > +/* Module ID Code */
> > +#define MB_MODULE_ID_DP_TX 0x01
> > +#define MB_MODULE_ID_HDMI_TX 0x03
> > +#define MB_MODULE_ID_HDCP_TX 0x07
> > +#define MB_MODULE_ID_HDCP_RX 0x08
> > +#define MB_MODULE_ID_HDCP_GENERAL 0x09
> > +#define MB_MODULE_ID_GENERAL 0x0A
> > +
> > +/* General Commands */
> > +#define GENERAL_MAIN_CONTROL 0x01
> > +#define GENERAL_TEST_ECHO 0x02
> > +#define GENERAL_BUS_SETTINGS 0x03
> > +#define GENERAL_TEST_ACCESS 0x04
> > +#define GENERAL_REGISTER_WRITE 0x05
> > +#define GENERAL_WRITE_FIELD 0x06
> > +#define GENERAL_REGISTER_READ 0x07
> > +#define GENERAL_GET_HPD_STATE 0x11
> > +
> > +/* DPTX Commands */
> > +#define DPTX_SET_POWER_MNG 0x00
> > +#define DPTX_SET_HOST_CAPABILITIES 0x01
> > +#define DPTX_GET_EDID 0x02
> > +#define DPTX_READ_DPCD 0x03
> > +#define DPTX_WRITE_DPCD 0x04
> > +#define DPTX_ENABLE_EVENT 0x05
> > +#define DPTX_WRITE_REGISTER 0x06
> > +#define DPTX_READ_REGISTER 0x07
> > +#define DPTX_WRITE_FIELD 0x08
> > +#define DPTX_TRAINING_CONTROL 0x09
> > +#define DPTX_READ_EVENT 0x0a
> > +#define DPTX_READ_LINK_STAT 0x0b
> > +#define DPTX_SET_VIDEO 0x0c
> > +#define DPTX_SET_AUDIO 0x0d
> > +#define DPTX_GET_LAST_AUX_STAUS 0x0e
> > +#define DPTX_SET_LINK_BREAK_POINT 0x0f
> > +#define DPTX_FORCE_LANES 0x10
> > +#define DPTX_HPD_STATE 0x11
> > +#define DPTX_ADJUST_LT 0x12
> > +
> > +/* HDMI TX Commands */
> > +#define HDMI_TX_READ 0x00
> > +#define HDMI_TX_WRITE 0x01
> > +#define HDMI_TX_UPDATE_READ 0x02
> > +#define HDMI_TX_EDID 0x03
> > +#define HDMI_TX_EVENTS 0x04
> > +#define HDMI_TX_HPD_STATUS 0x05
> > +
> > +struct cdns_mhdp_base {
> > + struct device *dev;
> > + void __iomem *regs;
> > + /* protect mailbox communications with the firmware */
> > + struct mutex *mbox_mutex;
> > +};
> > +
> > +/* Mailbox helper functions */
> > +int cdns_mhdp_mailbox_send(struct cdns_mhdp_base *base, u8
> module_id,
> > + u8 opcode, u16 size, u8 *message);
>
> Any reason to move the declaration for send before recv? It seems reasonable
> to have the in alphabetical order.
OK.
>
> > +int cdns_mhdp_mailbox_recv_header(struct cdns_mhdp_base *base,
> > + u8 module_id, u8 opcode, u16
> req_size);
> > +int cdns_mhdp_mailbox_recv_data(struct cdns_mhdp_base *base,
> > + u8 *buff, u16 buff_size);
>
> AFAICS while calling a sequence of these 3 functions mhdp->mbox_mutex is
> locked. This should be noted here.
OK, I will add notes in the next version.
Best regards,
Sandor
>
> Best regards,
> Alexander
>
> > +/* General commands helper functions */ int cdns_mhdp_reg_read(struct
> > +cdns_mhdp_base *base, u32 addr, u32 *value); int
> > +cdns_mhdp_reg_write(struct cdns_mhdp_base *base, u32 addr, u32 val);
> > +
> > +/* DPTX commands helper functions */
> > +int cdns_mhdp_dp_reg_write(struct cdns_mhdp_base *base, u16 addr,
> u32
> > +val); int cdns_mhdp_dp_reg_write_bit(struct cdns_mhdp_base *base, u16
> > +addr, +
>
> > u8 start_bit, u8 bits_no, u32 val);
> > +int cdns_mhdp_dpcd_read(struct cdns_mhdp_base *base,
> > + u32 addr, u8 *data, u16 len); int
> > +cdns_mhdp_dpcd_write(struct cdns_mhdp_base *base, u32 addr, u8
> > +value);
> > +
> > +#endif /* __CDNS_MHDP_HELPER_H__ */
>
>
> --
> TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
> Amtsgericht München, HRB 105018
> Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
> http://www.tq/
> -group.com%2F&data=05%7C01%7CSandor.yu%40nxp.com%7C7dae84b9c73
> 944b20c8308dbcef85e20%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7
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^ permalink raw reply
* Re: [PATCH 0/2] phy: qualcomm: eusb2-repeater: Some fixes after the regmap rework
From: Elliot Berman @ 2024-01-04 22:58 UTC (permalink / raw)
To: Abel Vesa, Bjorn Andersson, Konrad Dybcio, Vinod Koul,
Kishon Vijay Abraham I
Cc: linux-arm-msm, linux-phy, linux-kernel
In-Reply-To: <20240104-phy-qcom-eusb2-repeater-fixes-v1-0-047b7b6b8333@linaro.org>
On 1/4/2024 6:52 AM, Abel Vesa wrote:
> Found the first issue (from first patch) while adding support
> for X Elite (X1E80100) which comes with more than one repeaters.
> The second fix is just bonus.
>
Tested-by: Elliot Berman <quic_eberman@quicinc.com> # sm8650-qrd
> ---
> Abel Vesa (2):
> phy: qualcomm: eusb2-repeater: Fix the regfields for multiple instances
> phy: qualcomm: eusb2-repeater: Drop the redundant zeroing
>
> drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c | 23 ++++++++++-------------
> 1 file changed, 10 insertions(+), 13 deletions(-)
> ---
> base-commit: 0fef202ac2f8e6d9ad21aead648278f1226b9053
> change-id: 20240104-phy-qcom-eusb2-repeater-fixes-c9201113032c
>
> Best regards,
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