* Re: [PATCH] phy: socionext: usb2: Simplify with scoped for each OF child loop
From: Neil Armstrong @ 2026-01-05 15:31 UTC (permalink / raw)
To: Krzysztof Kozlowski, Vinod Koul, Kunihiko Hayashi,
Masami Hiramatsu, linux-phy, linux-arm-kernel, linux-kernel
In-Reply-To: <20260102124848.64474-2-krzysztof.kozlowski@oss.qualcomm.com>
On 1/2/26 13:48, Krzysztof Kozlowski wrote:
> Use scoped for-each loop when iterating over device nodes to make code a
> bit simpler.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
> ---
> drivers/phy/socionext/phy-uniphier-usb2.c | 28 ++++++++---------------
> 1 file changed, 10 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/phy/socionext/phy-uniphier-usb2.c b/drivers/phy/socionext/phy-uniphier-usb2.c
> index 21c201717d95..c49d432e526b 100644
> --- a/drivers/phy/socionext/phy-uniphier-usb2.c
> +++ b/drivers/phy/socionext/phy-uniphier-usb2.c
> @@ -106,7 +106,7 @@ static const struct phy_ops uniphier_u2phy_ops = {
> static int uniphier_u2phy_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> - struct device_node *parent, *child;
> + struct device_node *parent;
> struct uniphier_u2phy_priv *priv = NULL, *next = NULL;
> struct phy_provider *phy_provider;
> struct regmap *regmap;
> @@ -129,34 +129,31 @@ static int uniphier_u2phy_probe(struct platform_device *pdev)
> return PTR_ERR(regmap);
> }
>
> - for_each_child_of_node(dev->of_node, child) {
> + for_each_child_of_node_scoped(dev->of_node, child) {
> priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> - if (!priv) {
> - ret = -ENOMEM;
> - goto out_put_child;
> - }
> + if (!priv)
> + return -ENOMEM;
> +
> priv->regmap = regmap;
>
> priv->vbus = devm_regulator_get_optional(dev, "vbus");
> if (IS_ERR(priv->vbus)) {
> - if (PTR_ERR(priv->vbus) == -EPROBE_DEFER) {
> - ret = PTR_ERR(priv->vbus);
> - goto out_put_child;
> - }
> + if (PTR_ERR(priv->vbus) == -EPROBE_DEFER)
> + return PTR_ERR(priv->vbus);
> +
> priv->vbus = NULL;
> }
>
> priv->phy = devm_phy_create(dev, child, &uniphier_u2phy_ops);
> if (IS_ERR(priv->phy)) {
> dev_err(dev, "Failed to create phy\n");
> - ret = PTR_ERR(priv->phy);
> - goto out_put_child;
> + return PTR_ERR(priv->phy);
> }
>
> ret = of_property_read_u32(child, "reg", &data_idx);
> if (ret) {
> dev_err(dev, "Failed to get reg property\n");
> - goto out_put_child;
> + return ret;
> }
>
> if (data_idx < ndatas)
> @@ -174,11 +171,6 @@ static int uniphier_u2phy_probe(struct platform_device *pdev)
> phy_provider = devm_of_phy_provider_register(dev,
> uniphier_u2phy_xlate);
> return PTR_ERR_OR_ZERO(phy_provider);
> -
> -out_put_child:
> - of_node_put(child);
> -
> - return ret;
> }
>
> static const struct uniphier_u2phy_soc_data uniphier_pro4_data[] = {
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Thanks,
Neil
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* Re: [PATCH next v2] phy: apple: atc: Actually check return value of devm_apple_tunable_parse
From: Neil Armstrong @ 2026-01-05 15:28 UTC (permalink / raw)
To: Sven Peter, Janne Grunau, Neal Gompa, Vinod Koul
Cc: asahi, linux-arm-kernel, linux-phy, linux-kernel,
Thomas Glanzmann
In-Reply-To: <20260104-atcphy-tunable-fix-v2-1-84e5c2a57aaa@kernel.org>
On 1/4/26 22:56, Sven Peter wrote:
> Let's actually check the return value of devm_apple_tunable_parse
> instead of trying to check IS_ERR on a pointer to the return value which
> is always going to be valid. This prevent a oops when the tunables are
> invalid or when they don't exist:
>
> [ 57.664567] Unable to handle kernel paging request at virtual address fffffffffffffffe
> [ 57.664584] Mem abort info:
> [ 57.664589] ESR = 0x0000000096000007
> [ 57.664595] EC = 0x25: DABT (current EL), IL = 32 bits
> [ 57.664602] SET = 0, FnV = 0
> [ 57.664607] EA = 0, S1PTW = 0
> [ 57.664611] FSC = 0x07: level 3 translation fault
> [ 57.664617] Data abort info:
> [ 57.664621] ISV = 0, ISS = 0x00000007, ISS2 = 0x00000000
> [ 57.664626] CM = 0, WnR = 0, TnD = 0, TagAccess = 0
> [ 57.664631] GCS = 0, Overlay = 0, DirtyBit = 0, Xs = 0
> [ 57.664640] swapper pgtable: 16k pages, 47-bit VAs, pgdp=0000000b4391c000
> [ 57.664647] [fffffffffffffffe] pgd=0000000000000000, p4d=0000000000000000, pud=0000000b44188403, pmd=0000000b4418c403, pte=0000000000000000
> [ 57.664670] Internal error: Oops: 0000000096000007 [#1] SMP
> [ 57.665047] CPU: 1 UID: 0 PID: 23 Comm: kworker/1:0 Tainted: G S 6.18.2+ #2 PREEMPTLAZY
> [ 57.665061] Tainted: [S]=CPU_OUT_OF_SPEC
> [ 57.665066] Hardware name: Apple Mac mini (M1, 2020) (DT)
> [ 57.665072] Workqueue: events cd321x_update_work [tps6598x]
> [ 57.665100] pstate: 61400009 (nZCv daif +PAN -UAO -TCO +DIT -SSBS BTYPE=--)
> [ 57.665111] pc : apple_tunable_apply+0x8/0x80 [apple_tunable]
> [ 57.665121] lr : atcphy_mux_set+0x3e0/0x1138 [phy_apple_atc]
> [ 57.665133] sp : ffffc000802a7c00
> [ 57.665138] x29: ffffc000802a7c00 x28: 0000000000000003 x27: ffff800016c84080
> [ 57.665151] x26: 0000000000000002 x25: ffff800016c84090 x24: ffff800016c8408f
> [ 57.665163] x23: 0000000000020004 x22: 0000000000000001 x21: 0000000000000006
> [ 57.665175] x20: ffff80000d6da9b0 x19: ffff80000d6da880 x18: 0000000000000002
> [ 57.665188] x17: 0000000000000000 x16: ffffe22de59e0e38 x15: 0000000000000002
> [ 57.665199] x14: ffffe22de76ecff8 x13: 0000000000000001 x12: ffff9dd5f90bc000
> [ 57.665211] x11: 00000000000000c0 x10: 048abc15ceba0919 x9 : ffffe22dbc5fde10
> [ 57.665223] x8 : ffff80000175e0d8 x7 : 0000000000000004 x6 : 0000000000000000
> [ 57.665234] x5 : 0000000000000001 x4 : 0000000d6d132db7 x3 : 00000000000155db
> [ 57.665246] x2 : 0000000000000000 x1 : fffffffffffffffe x0 : ffffc00082b80000
> [ 57.665258] Call trace:
> [ 57.665265] apple_tunable_apply+0x8/0x80 [apple_tunable] (P)
> [ 57.665276] typec_mux_set+0x74/0xe0 [typec]
> [ 57.665315] cd321x_update_work+0x440/0x8c0 [tps6598x]
> [ 57.665332] process_one_work+0x178/0x3d0
> [ 57.665346] worker_thread+0x260/0x390
> [ 57.665354] kthread+0x150/0x250
> [ 57.665369] ret_from_fork+0x10/0x20
> [ 57.665386] Code: e69a0ae8 ffffe22d aa1e03e9 d503201f (f9400022)
> [ 57.665394] ---[ end trace 0000000000000000 ]---
>
> Reported-by: Thomas Glanzmann <thomas@glanzmann.de>
> Fixes: 8e98ca1e74db ("phy: apple: Add Apple Type-C PHY")
> Signed-off-by: Sven Peter <sven@kernel.org>
> ---
> Changes in v2:
> - Copy/paste error: Copied a WARN instead of the kernel oops this patch fixes
> - Link to v1: https://patch.msgid.link/20260104-atcphy-tunable-fix-v1-1-40bf00feaac0@kernel.org
> ---
> drivers/phy/apple/atc.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/phy/apple/atc.c b/drivers/phy/apple/atc.c
> index c8a58ee64b7aad3205df51cf16ae778471ad2c5d..716c1e70de38ca604803739fedaa543d91f7501b 100644
> --- a/drivers/phy/apple/atc.c
> +++ b/drivers/phy/apple/atc.c
> @@ -2178,10 +2178,10 @@ static int atcphy_load_tunables(struct apple_atcphy *atcphy)
> for (int i = 0; i < ARRAY_SIZE(tunables); i++) {
> *tunables[i].tunable = devm_apple_tunable_parse(
> atcphy->dev, atcphy->np, tunables[i].dt_name, tunables[i].res);
> - if (IS_ERR(tunables[i].tunable)) {
> + if (IS_ERR(*tunables[i].tunable)) {
> dev_err(atcphy->dev, "Failed to read tunable %s: %ld\n",
> - tunables[i].dt_name, PTR_ERR(tunables[i].tunable));
> - return PTR_ERR(tunables[i].tunable);
> + tunables[i].dt_name, PTR_ERR(*tunables[i].tunable));
> + return PTR_ERR(*tunables[i].tunable);
> }
> }
>
>
> ---
> base-commit: add66a6673bc4aacd0ef0f3c4a51271501770b17
> change-id: 20260104-atcphy-tunable-fix-517826d6fefd
>
> Best regards,
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Thanks,
Neil
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* Re: [PATCH v2 2/2] phy: cadence-torrent: Add PCIe + XAUI multilink configuration for 100MHz refclk
From: Siddharth Vadapalli @ 2026-01-05 15:17 UTC (permalink / raw)
To: Andrew Lunn
Cc: vkoul, neil.armstrong, robh, krzk+dt, conor+dt, sjakhade, rogerq,
krzk, linux-phy, linux-kernel, devicetree, linux-arm-kernel, srk,
s-vadapalli
In-Reply-To: <7fd42221-d602-4ce4-9f7f-6754ed91e7aa@lunn.ch>
On 05/01/26 3:27 AM, Andrew Lunn wrote:
> On Sun, Jan 04, 2026 at 05:14:18PM +0530, Siddharth Vadapalli wrote:
>> From: Swapnil Jakhade <sjakhade@cadence.com>
>>
>> Add register sequences for PCIe + XAUI multilink configuration for
>> 100MHz reference clock.
>>
>> Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
>> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
>> ---
>>
>> v1 of this patch is at:
>> https://lore.kernel.org/r/20251224054905.763399-3-s-vadapalli@ti.com/
>> No changes since v1.
>>
>> Regards,
>> Siddharth.
>>
>> drivers/phy/cadence/phy-cadence-torrent.c | 143 ++++++++++++++++++++--
>> 1 file changed, 136 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
>> index 37fa4bad6bd7..f0d870886cca 100644
>> --- a/drivers/phy/cadence/phy-cadence-torrent.c
>> +++ b/drivers/phy/cadence/phy-cadence-torrent.c
>> @@ -300,6 +300,7 @@ enum cdns_torrent_phy_type {
>> TYPE_USB,
>> TYPE_USXGMII,
>> TYPE_PCIE_ML,
>> + TYPE_XAUI,
>> };
>>
>> enum cdns_torrent_ref_clk {
>> @@ -320,14 +321,14 @@ enum cdns_torrent_ssc_mode {
>> /* Unique key id for vals table entry
>> * REFCLK0_RATE | REFCLK1_RATE | LINK0_TYPE | LINK1_TYPE | SSC_TYPE
>> */
>> -#define REFCLK0_SHIFT 12
>> -#define REFCLK0_MASK GENMASK(14, 12)
>> -#define REFCLK1_SHIFT 9
>> -#define REFCLK1_MASK GENMASK(11, 9)
>> -#define LINK0_SHIFT 6
>> -#define LINK0_MASK GENMASK(8, 6)
>> +#define REFCLK0_SHIFT 15
>> +#define REFCLK0_MASK GENMASK(18, 15)
>> +#define REFCLK1_SHIFT 11
>> +#define REFCLK1_MASK GENMASK(14, 11)
>> +#define LINK0_SHIFT 7
>> +#define LINK0_MASK GENMASK(10, 7)
>
> Why do these change? It would be good to add an explanation to the
> commit message about this, because it is not obvious why these need to
> change.
The 'key id' is supposed to be a unique value defined as the following
Bitwise OR:
REFCLK0_RATE | REFCLK1_RATE | LINK0_TYPE | LINK1_TYPE | SSC_TYPE
The 'LINK_TYPE' parameter corresponds to the protocol (PHY Type). In the
phy-cadence-torrent.c driver, the following enum describes the supported
'LINK_TYPE's:
enum cdns_torrent_phy_type {
TYPE_NONE,
TYPE_DP,
TYPE_PCIE,
TYPE_SGMII,
TYPE_QSGMII,
TYPE_USB,
TYPE_USXGMII,
TYPE_PCIE_ML,
};
The last entry which is TYPE_PCIE_ML has the value of '7' (TYPE_NONE is
'0'). Therefore, 'LINK_MASK' happened to be a 3-bit mask:
#define LINK0_MASK GENMASK(8, 6)
#define LINK1_MASK GENMASK(5, 3)
With the addition of TYPE_XAUI in the current patch, 'LINK_MASK' has to
be extended to a 4-bit mask.
The 'REFCLK_RATE' parameter corresponds to the reference clock rates
defined which are again described by the following enum in the driver:
enum cdns_torrent_ref_clk {
CLK_19_2_MHZ,
CLK_25_MHZ,
CLK_100_MHZ,
CLK_156_25_MHZ,
CLK_ANY,
};
The last entry which is CLK_ANY has the value of '4' (CLK_19_2_MHZ is
'0'). Although the existing macros defined as:
#define REFCLK0_MASK GENMASK(14, 12)
#define REFCLK1_MASK GENMASK(11, 9)
are 3-bit masks and can fit values until '7', for the sake of
future-proofing the driver (the SERDES Hardware supports more reference
clocks which are not yet enabled in the driver), 'REFCLK_MASK' has been
extended to a 4-bit mask as well.
The shifts associated with the masks have been updated accordingly.
I shall include a summary of the above in the commit message of the v3
series.
Thank you for reviewing the patch and providing feedback.
Regards,
Siddharth.
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* [PATCH V3 4/4] arm64: dts: qcom: hamoa-iot-evk: Enable UFS
From: Pradeep P V K @ 2026-01-05 14:46 UTC (permalink / raw)
To: vkoul, neil.armstrong, robh, krzk+dt, conor+dt, martin.petersen,
andersson, konradybcio, taniya.das, dmitry.baryshkov,
manivannan.sadhasivam
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
nitin.rawat, Pradeep P V K, Konrad Dybcio
In-Reply-To: <20260105144643.669344-1-pradeep.pragallapati@oss.qualcomm.com>
Enable UFS for HAMOA-IOT-EVK board.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts
index 88e3e7bed998..23cd913b05f5 100644
--- a/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts
+++ b/arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts
@@ -1253,6 +1253,24 @@ &uart21 {
status = "okay";
};
+&ufs_mem_phy {
+ vdda-phy-supply = <&vreg_l3i_0p8>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&ufs_mem_hc {
+ reset-gpios = <&tlmm 238 GPIO_ACTIVE_LOW>;
+
+ vcc-supply = <&vreg_l17b_2p5>;
+ vcc-max-microamp = <1300000>;
+ vccq-supply = <&vreg_l2i_1p2>;
+ vccq-max-microamp = <1200000>;
+
+ status = "okay";
+};
+
&usb_1_ss0_dwc3_hs {
remote-endpoint = <&pmic_glink_ss0_hs_in>;
};
--
2.34.1
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* [PATCH V3 3/4] arm64: dts: qcom: hamoa: Add UFS nodes for x1e80100 SoC
From: Pradeep P V K @ 2026-01-05 14:46 UTC (permalink / raw)
To: vkoul, neil.armstrong, robh, krzk+dt, conor+dt, martin.petersen,
andersson, konradybcio, taniya.das, dmitry.baryshkov,
manivannan.sadhasivam
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
nitin.rawat, Pradeep P V K, Konrad Dybcio, Abel Vesa
In-Reply-To: <20260105144643.669344-1-pradeep.pragallapati@oss.qualcomm.com>
Add UFS host controller and PHY nodes for x1e80100 SoC.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/hamoa.dtsi | 123 +++++++++++++++++++++++++++-
1 file changed, 120 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi
index f7d71793bc77..33899fa06aa4 100644
--- a/arch/arm64/boot/dts/qcom/hamoa.dtsi
+++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi
@@ -835,9 +835,9 @@ gcc: clock-controller@100000 {
<0>,
<0>,
<0>,
- <0>,
- <0>,
- <0>;
+ <&ufs_mem_phy 0>,
+ <&ufs_mem_phy 1>,
+ <&ufs_mem_phy 2>;
power-domains = <&rpmhpd RPMHPD_CX>;
#clock-cells = <1>;
@@ -3848,6 +3848,123 @@ pcie4_phy: phy@1c0e000 {
status = "disabled";
};
+ ufs_mem_phy: phy@1d80000 {
+ compatible = "qcom,x1e80100-qmp-ufs-phy",
+ "qcom,sm8550-qmp-ufs-phy";
+ reg = <0x0 0x01d80000 0x0 0x2000>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
+ <&tcsr TCSR_UFS_PHY_CLKREF_EN>;
+
+ clock-names = "ref",
+ "ref_aux",
+ "qref";
+ resets = <&ufs_mem_hc 0>;
+ reset-names = "ufsphy";
+
+ power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>;
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ ufs_mem_hc: ufs@1d84000 {
+ compatible = "qcom,x1e80100-ufshc",
+ "qcom,sm8550-ufshc",
+ "qcom,ufshc",
+ "jedec,ufs-2.0";
+ reg = <0x0 0x01d84000 0x0 0x3000>;
+
+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+ <&gcc GCC_UFS_PHY_AHB_CLK>,
+ <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+ <&rpmhcc RPMH_LN_BB_CLK3>,
+ <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+ <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
+ clock-names = "core_clk",
+ "bus_aggr_clk",
+ "iface_clk",
+ "core_clk_unipro",
+ "ref_clk",
+ "tx_lane0_sync_clk",
+ "rx_lane0_sync_clk",
+ "rx_lane1_sync_clk";
+
+ operating-points-v2 = <&ufs_opp_table>;
+
+ resets = <&gcc GCC_UFS_PHY_BCR>;
+ reset-names = "rst";
+
+ interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "ufs-ddr",
+ "cpu-ufs";
+
+ power-domains = <&gcc GCC_UFS_PHY_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
+
+ iommus = <&apps_smmu 0x1a0 0>;
+ dma-coherent;
+
+ lanes-per-direction = <2>;
+
+ phys = <&ufs_mem_phy>;
+ phy-names = "ufsphy";
+
+ #reset-cells = <1>;
+
+ status = "disabled";
+
+ ufs_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-75000000 {
+ opp-hz = /bits/ 64 <75000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <75000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-150000000 {
+ opp-hz = /bits/ 64 <150000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <150000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <300000000>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>,
+ /bits/ 64 <0>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
cryptobam: dma-controller@1dc4000 {
compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
reg = <0x0 0x01dc4000 0x0 0x28000>;
--
2.34.1
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* [PATCH V3 2/4] dt-bindings: ufs: qcom,sc7180-ufshc: Add UFSHC compatible for x1e80100
From: Pradeep P V K @ 2026-01-05 14:46 UTC (permalink / raw)
To: vkoul, neil.armstrong, robh, krzk+dt, conor+dt, martin.petersen,
andersson, konradybcio, taniya.das, dmitry.baryshkov,
manivannan.sadhasivam
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
nitin.rawat, Pradeep P V K
In-Reply-To: <20260105144643.669344-1-pradeep.pragallapati@oss.qualcomm.com>
Add UFS Host Controller (UFSHC) compatible for x1e80100 SoC. Use
SM8550 as a fallback since x1e80100 is fully compatible with it.
Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
---
.../bindings/ufs/qcom,sc7180-ufshc.yaml | 37 +++++++++++--------
1 file changed, 22 insertions(+), 15 deletions(-)
diff --git a/Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml b/Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml
index d94ef4e6b85a..c1085d178421 100644
--- a/Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml
+++ b/Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml
@@ -31,21 +31,28 @@ select:
properties:
compatible:
- items:
- - enum:
- - qcom,msm8998-ufshc
- - qcom,qcs8300-ufshc
- - qcom,sa8775p-ufshc
- - qcom,sc7180-ufshc
- - qcom,sc7280-ufshc
- - qcom,sc8180x-ufshc
- - qcom,sc8280xp-ufshc
- - qcom,sm8250-ufshc
- - qcom,sm8350-ufshc
- - qcom,sm8450-ufshc
- - qcom,sm8550-ufshc
- - const: qcom,ufshc
- - const: jedec,ufs-2.0
+ oneOf:
+ - items:
+ - enum:
+ - qcom,x1e80100-ufshc
+ - const: qcom,sm8550-ufshc
+ - const: qcom,ufshc
+ - const: jedec,ufs-2.0
+ - items:
+ - enum:
+ - qcom,msm8998-ufshc
+ - qcom,qcs8300-ufshc
+ - qcom,sa8775p-ufshc
+ - qcom,sc7180-ufshc
+ - qcom,sc7280-ufshc
+ - qcom,sc8180x-ufshc
+ - qcom,sc8280xp-ufshc
+ - qcom,sm8250-ufshc
+ - qcom,sm8350-ufshc
+ - qcom,sm8450-ufshc
+ - qcom,sm8550-ufshc
+ - const: qcom,ufshc
+ - const: jedec,ufs-2.0
reg:
maxItems: 1
--
2.34.1
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* [PATCH V3 1/4] dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Add QMP UFS PHY compatible
From: Pradeep P V K @ 2026-01-05 14:46 UTC (permalink / raw)
To: vkoul, neil.armstrong, robh, krzk+dt, conor+dt, martin.petersen,
andersson, konradybcio, taniya.das, dmitry.baryshkov,
manivannan.sadhasivam
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
nitin.rawat, Pradeep P V K
In-Reply-To: <20260105144643.669344-1-pradeep.pragallapati@oss.qualcomm.com>
Document QMP UFS PHY compatible for x1e80100 SoC. Use SM8550 as a
fallback since x1e80100 is fully compatible with it.
Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
---
.../devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
index fba7b2549dde..166e3787db58 100644
--- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
@@ -20,6 +20,10 @@ properties:
- enum:
- qcom,qcs615-qmp-ufs-phy
- const: qcom,sm6115-qmp-ufs-phy
+ - items:
+ - enum:
+ - qcom,x1e80100-qmp-ufs-phy
+ - const: qcom,sm8550-qmp-ufs-phy
- items:
- enum:
- qcom,qcs8300-qmp-ufs-phy
--
2.34.1
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* [PATCH V3 0/4] Add UFS support for x1e80100 SoC
From: Pradeep P V K @ 2026-01-05 14:46 UTC (permalink / raw)
To: vkoul, neil.armstrong, robh, krzk+dt, conor+dt, martin.petersen,
andersson, konradybcio, taniya.das, dmitry.baryshkov,
manivannan.sadhasivam
Cc: linux-arm-msm, linux-phy, devicetree, linux-kernel, linux-scsi,
nitin.rawat, Pradeep P V K
Add UFSPHY, UFSHC compatible binding names and UFS devicetree
enablement changes for Qualcomm x1e80100 SoC.
Changes in V3:
- Update all dt-bindings commit messages with concise and informative
statements [Krzysztof]
- keep the QMP UFS PHY order by last compatible in numerical ascending
order [Krzysztof]
- Remove qcom,x1e80100-ufshc from select: enum: list of
qcom,sc7180-ufshc.yaml file [Krzysztof]
- Update subject prefix for all dt-bindings [Krzysztof]
- Add RB-by for SoC dtsi [Konrad, Abel, Taniya]
- Add RB-by for board dts [Konrad]
- Link to V2:
https://lore.kernel.org/all/20251231101951.1026163-1-pradeep.pragallapati@oss.qualcomm.com
---
Pradeep P V K (4):
dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Add QMP UFS PHY
compatible
dt-bindings: ufs: qcom,sc7180-ufshc: Add UFSHC compatible for x1e80100
arm64: dts: qcom: hamoa: Add UFS nodes for x1e80100 SoC
arm64: dts: qcom: hamoa-iot-evk: Enable UFS
.../phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 4 +
.../bindings/ufs/qcom,sc7180-ufshc.yaml | 37 +++---
arch/arm64/boot/dts/qcom/hamoa-iot-evk.dts | 18 +++
arch/arm64/boot/dts/qcom/hamoa.dtsi | 123 +++++++++++++++++-
4 files changed, 164 insertions(+), 18 deletions(-)
--
2.34.1
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* Re: [PATCH v3 9/9] phy: ti: phy-j721e-wiz: convert from round_rate() to determine_rate()
From: Brian Masney @ 2026-01-05 12:14 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Vinod Koul, Kishon Vijay Abraham I, Chun-Kuang Hu, Philipp Zabel,
Chunfeng Yun, Matthias Brugger, AngeloGioacchino Del Regno,
Heiko Stuebner, Neil Armstrong, Stephen Boyd, Maxime Ripard,
linux-clk, linux-phy, linux-kernel, dri-devel, linux-mediatek,
linux-arm-kernel, linux-rockchip
In-Reply-To: <CAMuHMdXudWW3MPKqP0-d+DyMNRF-X62oyHRnj=MM_9MSpJw6sw@mail.gmail.com>
Hi Geert,
On Mon, Dec 29, 2025 at 11:18:52AM +0100, Geert Uytterhoeven wrote:
> Hi Brian,
>
> On Fri, 12 Dec 2025 at 00:21, Brian Masney <bmasney@redhat.com> wrote:
> > The round_rate() clk ops is deprecated, so migrate this driver from
> > round_rate() to determine_rate() using the Coccinelle semantic patch
> > on the cover letter of this series.
> >
> > Signed-off-by: Brian Masney <bmasney@redhat.com>
>
> Thanks for your patch, which is now commit 27287e3b52b5954b ("phy:
> ti: phy-j721e-wiz: convert from round_rate() to determine_rate()")
> in phy/next
>
> > --- a/drivers/phy/ti/phy-j721e-wiz.c
> > +++ b/drivers/phy/ti/phy-j721e-wiz.c
> > @@ -934,12 +934,15 @@ static unsigned long wiz_clk_div_recalc_rate(struct clk_hw *hw,
> > return divider_recalc_rate(hw, parent_rate, val, div->table, 0x0, 2);
> > }
> >
> > -static long wiz_clk_div_round_rate(struct clk_hw *hw, unsigned long rate,
> > - unsigned long *prate)
> > +static int wiz_clk_div_determine_rate(struct clk_hw *hw,
> > + struct clk_rate_request *req)
> > {
> > struct wiz_clk_divider *div = to_wiz_clk_div(hw);
> >
> > - return divider_round_rate(hw, rate, prate, div->table, 2, 0x0);
> > + req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate,
> > + div->table, 2, 0x0);
>
> Is this correct? divider_round_rate() can return a negative error code
> (from divider_ro_determine_rate()), which is not handled here?
>
> Looks like several other users of divider_round_rate() use this
> same logic, and thus are affected, too.
Thanks for the review! You are correct that this is a bug.
I had planned once round_rate is removed from the clk core to post a
series to remove divider_round_rate() and divider_ro_round_rate() (plus
the _parent functions) since they call the corresponding determine_rate
functions. I'll bump that up on my todo list this week.
Brian
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* Re: [PATCH 01/11] dt-bindings: phy: renesas: usb3-phy: add r8a77990 support
From: Krzysztof Kozlowski @ 2026-01-05 8:31 UTC (permalink / raw)
To: Marek Vasut
Cc: linux-arm-kernel, Conor Dooley, Geert Uytterhoeven,
Krzysztof Kozlowski, Magnus Damm, Neil Armstrong, Rob Herring,
Vinod Koul, Yoshihiro Shimoda, devicetree, linux-phy,
linux-renesas-soc
In-Reply-To: <20260101203938.159161-2-marek.vasut+renesas@mailbox.org>
On Thu, Jan 01, 2026 at 09:35:48PM +0100, Marek Vasut wrote:
> This patch adds support for r8a77990 (R-Car E3).
Please do not use "This commit/patch/change", but imperative mood. See
longer explanation here:
https://elixir.bootlin.com/linux/v6.16/source/Documentation/process/submitting-patches.rst#L94
Also, you cannot add support in bindings. You either document hardware
or you add bindings for or simply you add hardware.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
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* Re: [PATCH V2 2/4] scsi: ufs: qcom: dt-bindings: Document UFSHC compatible for x1e80100
From: Pradeep Pragallapati @ 2026-01-05 8:16 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: vkoul, neil.armstrong, robh, krzk+dt, conor+dt, martin.petersen,
andersson, konradybcio, taniya.das, dmitry.baryshkov,
manivannan.sadhasivam, linux-arm-msm, linux-phy, devicetree,
linux-kernel, linux-scsi, nitin.rawat
In-Reply-To: <20260102-logical-frigatebird-of-elegance-8abd82@quoll>
On 1/2/2026 4:56 PM, Krzysztof Kozlowski wrote:
> On Wed, Dec 31, 2025 at 03:49:49PM +0530, Pradeep P V K wrote:
>> Add the UFS Host Controller (UFSHC) compatible for Qualcomm x1e80100
>> SoC. Use SM8550 as a fallback since x1e80100 shares compatibility
>> with SM8550 UFSHC, enabling reuse of existing support.
>>
>
> Please use subject prefixes matching the subsystem. You can get them for
> example with 'git log --oneline -- DIRECTORY_OR_FILE' on the directory
> your patch is touching. For bindings, the preferred subjects are
> explained here:
> https://www.kernel.org/doc/html/latest/devicetree/bindings/submitting-patches.html#i-for-patch-submitters
>
sure, i will update the subject prefix to directory path in my next
patchset.
>
> Best regards,
> Krzysztof
>
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* Re: [PATCH V2 2/4] scsi: ufs: qcom: dt-bindings: Document UFSHC compatible for x1e80100
From: Pradeep Pragallapati @ 2026-01-05 8:14 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: vkoul, neil.armstrong, robh, krzk+dt, conor+dt, martin.petersen,
andersson, konradybcio, taniya.das, dmitry.baryshkov,
manivannan.sadhasivam, linux-arm-msm, linux-phy, devicetree,
linux-kernel, linux-scsi, nitin.rawat
In-Reply-To: <20260102-rapid-abiding-parakeet-d0735f@quoll>
On 1/2/2026 4:55 PM, Krzysztof Kozlowski wrote:
> On Wed, Dec 31, 2025 at 03:49:49PM +0530, Pradeep P V K wrote:
>> Add the UFS Host Controller (UFSHC) compatible for Qualcomm x1e80100
>> SoC. Use SM8550 as a fallback since x1e80100 shares compatibility
>> with SM8550 UFSHC, enabling reuse of existing support.
>
> Your last sentence is redundant. "Make devices compatible because they
> are compatible". Why are they compatible? Or just say that you add a new
> device fully compatible with SM8550. Write concise and informative
> statements, not long elaborted paragraphs where only few words are the
> actual information
>
ok, i will update in my next patchset.
>>
>> Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
>> ---
>> .../bindings/ufs/qcom,sc7180-ufshc.yaml | 38 +++++++++++--------
>> 1 file changed, 23 insertions(+), 15 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml b/Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml
>> index d94ef4e6b85a..0f6ea7ca06c8 100644
>> --- a/Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml
>> +++ b/Documentation/devicetree/bindings/ufs/qcom,sc7180-ufshc.yaml
>> @@ -26,26 +26,34 @@ select:
>> - qcom,sm8350-ufshc
>> - qcom,sm8450-ufshc
>> - qcom,sm8550-ufshc
>> + - qcom,x1e80100-ufshc
>
> You don't need this.
sure, i will update in my next patchset.
>
>> required:
>> - compatible
>
> Best regards,
> Krzysztof
>
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* Re: [PATCH V2 1/4] dt-bindings: phy: Add QMP UFS PHY compatible for x1e80100
From: Pradeep Pragallapati @ 2026-01-05 8:11 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: vkoul, neil.armstrong, robh, krzk+dt, conor+dt, martin.petersen,
andersson, konradybcio, taniya.das, dmitry.baryshkov,
manivannan.sadhasivam, linux-arm-msm, linux-phy, devicetree,
linux-kernel, linux-scsi, nitin.rawat
In-Reply-To: <20260102-heretic-angelic-narwhal-5d9d8c@quoll>
On 1/2/2026 4:53 PM, Krzysztof Kozlowski wrote:
> On Wed, Dec 31, 2025 at 03:49:48PM +0530, Pradeep P V K wrote:
>> Add the QMP UFS PHY compatible string for Qualcomm x1e80100 SoC to
>> support its physical layer functionality for UFS. Use SM8550 as a
>> fallback since x1e80100 UFS PHY shares the same tech node, allowing
>
> What is a "tech node"?
At brief - tech node represents a generation (e.g., 7nm, 5nm, 3nm) of
semiconductor fabrication technology.
>
>> reuse of existing UFS PHY support.
>>
>> Signed-off-by: Pradeep P V K <pradeep.pragallapati@oss.qualcomm.com>
>> ---
>> .../devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 4 ++++
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
>> index fba7b2549dde..552dd663b7c9 100644
>> --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
>> +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml
>> @@ -28,6 +28,10 @@ properties:
>> - enum:
>> - qcom,kaanapali-qmp-ufs-phy
>> - const: qcom,sm8750-qmp-ufs-phy
>> + - items:
>> + - enum:
>> + - qcom,x1e80100-qmp-ufs-phy
>> + - const: qcom,sm8550-qmp-ufs-phy
>
> 85 < 87, keep the order by last compatible. It was already screwed by
> Xin Liu in previous commit but you do not have to grow discouraged
> patterns.
>
sure, i will update in my next patchset.
> Best regards,
> Krzysztof
>
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* Re: [PATCH v4 09/25] scsi: ufs: mediatek: Rework the crypt-boost stuff
From: Nicolas Frattaroli @ 2026-01-05 8:05 UTC (permalink / raw)
To: chu.stanley@gmail.com, robh@kernel.org,
Chunfeng Yun (云春峰), kishon@kernel.org,
James.Bottomley@HansenPartnership.com, bvanassche@acm.org,
AngeloGioacchino Del Regno, neil.armstrong@linaro.org,
conor+dt@kernel.org, Chaotian Jing (井朝天),
lgirdwood@gmail.com, vkoul@kernel.org, krzk+dt@kernel.org,
p.zabel@pengutronix.de, alim.akhtar@samsung.com,
matthias.bgg@gmail.com, avri.altman@wdc.com,
martin.petersen@oracle.com, broonie@kernel.org,
Peter Wang (王信友)
Cc: linux-scsi@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-phy@lists.infradead.org, linux-mediatek@lists.infradead.org,
Louis-Alexis Eyraud, kernel@collabora.com
In-Reply-To: <a12f7ffe8448d205a7318219ea7a18f0f722727f.camel@mediatek.com>
On Wednesday, 24 December 2025 07:16:34 Central European Standard Time Peter Wang (王信友) wrote:
> On Thu, 2025-12-18 at 13:54 +0100, Nicolas Frattaroli wrote:
> > -
> > -static void ufs_mtk_init_boost_crypt(struct ufs_hba *hba)
> > +static int ufs_mtk_init_boost_crypt(struct ufs_hba *hba)
> >
>
> Hi Nicolas,
>
> Please do not change the return type if you are not checking the return
> value.
>
>
> > {
> > struct ufs_mtk_host *host = ufshcd_get_variant(hba);
> > struct ufs_mtk_crypt_cfg *cfg;
> > struct device *dev = hba->dev;
> > - struct regulator *reg;
> > - u32 volt;
> > + int ret;
> >
> > - host->crypt = devm_kzalloc(dev, sizeof(*(host->crypt)),
> > - GFP_KERNEL);
> > - if (!host->crypt)
> > - goto disable_caps;
> > + cfg = devm_kzalloc(dev, sizeof(*cfg), GFP_KERNEL);
> > + if (!cfg)
> > + return -ENOMEM;
> >
> > - reg = devm_regulator_get_optional(dev, "dvfsrc-vcore");
> > - if (IS_ERR(reg)) {
> > - dev_info(dev, "failed to get dvfsrc-vcore: %ld",
> > - PTR_ERR(reg));
> > - goto disable_caps;
> > + cfg->reg_vcore = devm_regulator_get_optional(dev, "dvfsrc-
> > vcore");
> > + if (IS_ERR(cfg->reg_vcore)) {
> > + dev_err(dev, "Failed to get dvfsrc-vcore: %pe", cfg-
> > >reg_vcore);
> >
>
> Should free the cfg memory?
It's a devres alloc. It'll get freed on driver removal automatically.
Freeing it manually would be a double-free once the driver unloads.
>
> > + return PTR_ERR(cfg->reg_vcore);
> > }
> >
> > - if (of_property_read_u32(dev->of_node, "boost-crypt-vcore-
> > min",
> > - &volt)) {
> > - dev_info(dev, "failed to get boost-crypt-vcore-min");
> > - goto disable_caps;
> > + ret = of_property_read_u32(dev->of_node, "mediatek,boost-
> > crypt-vcore-min",
> > + &cfg->vcore_volt);
> > + if (ret) {
> > + dev_err(dev, "Failed to get mediatek,boost-crypt-
> > vcore-min: %pe\n",
> > + ERR_PTR(ret));
> > + return ret;
> > }
> >
> > - cfg = host->crypt;
> > - if (ufs_mtk_init_host_clk(hba, "crypt_mux",
> > - &cfg->clk_crypt_mux))
> > - goto disable_caps;
> > + cfg->clk_crypt_mux = devm_clk_get(dev, "crypt_mux");
> > + if (IS_ERR(cfg->clk_crypt_mux)) {
> > + dev_err(dev, "Failed to get clock crypt_mux: %pe\n",
> > cfg->clk_crypt_mux);
> > + return PTR_ERR(cfg->clk_crypt_mux);
> > + }
> >
> > - if (ufs_mtk_init_host_clk(hba, "crypt_lp",
> > - &cfg->clk_crypt_lp))
> > - goto disable_caps;
> > + cfg->clk_crypt_lp = devm_clk_get(dev, "crypt_lp");
> > + if (IS_ERR(cfg->clk_crypt_lp)) {
> > + dev_err(dev, "Failed to get clock crypt_lp: %pe\n",
> > cfg->clk_crypt_lp);
> > + return PTR_ERR(cfg->clk_crypt_lp);
> > + }
> >
> > - if (ufs_mtk_init_host_clk(hba, "crypt_perf",
> > - &cfg->clk_crypt_perf))
> > - goto disable_caps;
> > + cfg->clk_crypt_perf = devm_clk_get(dev, "crypt_perf");
> > + if (IS_ERR(cfg->clk_crypt_perf)) {
> > + dev_err(dev, "Failed to get clock crypt_perf: %pe\n",
> > cfg->clk_crypt_perf);
> > + return PTR_ERR(cfg->clk_crypt_perf);
> > + }
> >
> > - cfg->reg_vcore = reg;
> > - cfg->vcore_volt = volt;
> > + host->crypt = cfg;
> > host->caps |= UFS_MTK_CAP_BOOST_CRYPT_ENGINE;
> >
> > -disable_caps:
> > - return;
> > + return 0;
> > }
> >
> > static void ufs_mtk_init_host_caps(struct ufs_hba *hba)
> >
> > --
> > 2.52.0
> >
>
>
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* Re: [PATCH v4 02/25] dt-bindings: ufs: mediatek,ufs: Complete the binding
From: Nicolas Frattaroli @ 2026-01-05 8:00 UTC (permalink / raw)
To: Peter Wang (王信友),
Chunfeng Yun (云春峰), kishon@kernel.org,
avri.altman@wdc.com, bvanassche@acm.org,
martin.petersen@oracle.com, broonie@kernel.org,
alim.akhtar@samsung.com, chu.stanley@gmail.com,
conor+dt@kernel.org, p.zabel@pengutronix.de, robh@kernel.org,
James.Bottomley@HansenPartnership.com, lgirdwood@gmail.com,
vkoul@kernel.org, matthias.bgg@gmail.com,
neil.armstrong@linaro.org, krzk+dt@kernel.org,
AngeloGioacchino Del Regno,
Chaotian Jing (井朝天)
Cc: linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
devicetree@vger.kernel.org, kernel@collabora.com,
Louis-Alexis Eyraud, linux-scsi@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-phy@lists.infradead.org
In-Reply-To: <e30abc4cbda3d655d9e0ef2beeac1456b93febb5.camel@mediatek.com>
On Wednesday, 24 December 2025 06:33:42 Central European Standard Time Chaotian Jing (井朝天) wrote:
> On Thu, 2025-12-18 at 13:54 +0100, Nicolas Frattaroli wrote:
> > External email : Please do not click links or open attachments until
> > you have verified the sender or the content.
> >
> >
> > As it stands, the mediatek,ufs.yaml binding is startlingly
> > incomplete.
> > Its one example, which is the only real "user" of this binding in
> > mainline, uses the deprecated freq-table-hz property.
> >
> > The resets, of which there are three optional ones, are completely
> > absent.
> >
> > The clock description for MT8195 is incomplete, as is the one for
> > MT8192. It's not known if the one clock binding for MT8183 is even
> > correct, but I do not have access to the necessary code and
> > documentation to find this out myself.
> >
> > The power supply situation is not much better; the binding describes
> > one
> > required power supply, but it's the UFS card supply, not any of the
> > supplies feeding the controller silicon.
> >
> > No second example is present in the binding, making verification
> > difficult.
> >
> > Disallow freq-table-hz and move to operating-points-v2. It's fine to
> > break compatibility here, as the binding is currently unused and
> > would
> > be impossible to correctly use in its current state.
> >
> > Add the three resets and the corresponding reset-names property.
> > These
> > resets appear to be optional, i.e. not required for the functioning
> > of
> > the device.
> >
> > Move the list of clock names out of the if condition, and expand it
> > for
> > the confirmed clocks I could find by cross-referencing several clock
> > drivers. For MT8195, increase the minimum number of clocks to include
> > the crypt and rx_symbol ones, as they're internal to the SoC and
> > should
> > always be present, and should therefore not be omitted.
> >
> > MT8192 gets to have at least 3 clocks, as these were the ones I could
> > quickly confirm from a glance at various trees. I can't say this was
> > an
> > exhaustive search though, but it's better than the current situation.
> >
> > Properly document all supplies, with which pin name on the SoCs they
> > supply. Complete the example with them.
> >
> > Also add a MT8195 example to the binding, using supply labels that I
> > am
> > pretty sure would be the right ones for e.g. the Radxa NIO 12L.
> >
> > Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
> > ---
> > .../devicetree/bindings/ufs/mediatek,ufs.yaml | 117
> > ++++++++++++++++++---
> > 1 file changed, 100 insertions(+), 17 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml
> > b/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml
> > index 15c347f5e660..e0aef3e5f56b 100644
> > --- a/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml
> > +++ b/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml
> > @@ -19,11 +19,28 @@ properties:
> >
> > clocks:
> > minItems: 1
> > - maxItems: 8
> > + maxItems: 13
> >
> > clock-names:
> > minItems: 1
> > - maxItems: 8
> > + items:
> > + - const: ufs
> > + - const: ufs_aes
> > + - const: ufs_tick
> > + - const: unipro_sysclk
> > + - const: unipro_tick
> > + - const: unipro_mp_bclk
> > + - const: ufs_tx_symbol
> > + - const: ufs_mem_sub
> > + - const: crypt_mux
> > + - const: crypt_lp
> > + - const: crypt_perf
> > + - const: ufs_rx_symbol0
> > + - const: ufs_rx_symbol1
> > +
> > + operating-points-v2: true
> > +
> > + freq-table-hz: false
> >
> > phys:
> > maxItems: 1
> > @@ -31,8 +48,36 @@ properties:
> > reg:
> > maxItems: 1
> >
> > + resets:
> > + items:
> > + - description: reset for the UniPro layer
> > + - description: reset for the cryptography engine
> > + - description: reset for the host controller
> > +
> > + reset-names:
> > + items:
> > + - const: unipro
> > + - const: crypto
> > + - const: hci
> > +
> > + avdd09-supply:
> > + description: Phandle to the 0.9V supply powering the AVDD09_UFS
> > pin
> > +
> > + avdd12-supply:
> > + description: Phandle to the 1.2V supply powering the AVDD12_UFS
> > pin
> > +
> > + avdd12-ckbuf-supply:
> > + description: Phandle to the 1.2V supply powering the
> > AVDD12_CKBUF_UFS pin
> > +
> > + avdd18-supply:
> > + description: Phandle to the 1.8V supply powering the AVDD18_UFS
> > pin
> > +
> > vcc-supply: true
> >
> > + vccq-supply: true
> > +
> > + vccq2-supply: true
> > +
> > mediatek,ufs-disable-mcq:
> > $ref: /schemas/types.yaml#/definitions/flag
> > description: The mask to disable MCQ (Multi-Circular Queue) for
> > UFS host.
> > @@ -54,29 +99,41 @@ allOf:
> > properties:
> > compatible:
> > contains:
> > - enum:
> > - - mediatek,mt8195-ufshci
> > + const: mediatek,mt8183-ufshci
> > then:
> > properties:
> > clocks:
> > - minItems: 8
> > + maxItems: 1
> > clock-names:
> > items:
> > - const: ufs
> > - - const: ufs_aes
> > - - const: ufs_tick
> > - - const: unipro_sysclk
> > - - const: unipro_tick
> > - - const: unipro_mp_bclk
> > - - const: ufs_tx_symbol
> > - - const: ufs_mem_sub
> > - else:
> > + avdd12-ckbuf-supply: false
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + const: mediatek,mt8192-ufshci
> > + then:
> > properties:
> > clocks:
> > - maxItems: 1
> > + minItems: 3
> > + maxItems: 3
> > + clocks-names:
> > + minItems: 3
> > + maxItems: 3
> > + avdd09-supply: false
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + const: mediatek,mt8195-ufshci
> > + then:
> > + properties:
> > + clocks:
> > + minItems: 13
> > clock-names:
> > - items:
> > - - const: ufs
> > + minItems: 13
> > + avdd09-supply: false
> >
> > examples:
> > - |
> > @@ -95,8 +152,34 @@ examples:
> >
> > clocks = <&infracfg_ao CLK_INFRA_UFS>;
> > clock-names = "ufs";
> > - freq-table-hz = <0 0>;
> >
> > vcc-supply = <&mt_pmic_vemc_ldo_reg>;
> > };
> > };
> > + - |
> > + ufshci@11270000 {
> > + compatible = "mediatek,mt8195-ufshci";
> > + reg = <0x11270000 0x2300>;
> > + interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
> > + phys = <&ufsphy>;
> > + clocks = <&infracfg_ao 63>, <&infracfg_ao 64>, <&infracfg_ao
> > 65>,
> > + <&infracfg_ao 54>, <&infracfg_ao 55>,
> > + <&infracfg_ao 56>, <&infracfg_ao 90>,
> > + <&infracfg_ao 93>, <&topckgen 60>, <&topckgen 152>,
> > + <&topckgen 125>, <&topckgen 212>, <&topckgen 215>;
> > + clock-names = "ufs", "ufs_aes", "ufs_tick",
> > + "unipro_sysclk", "unipro_tick",
> > + "unipro_mp_bclk", "ufs_tx_symbol",
> > + "ufs_mem_sub", "crypt_mux", "crypt_lp",
> > + "crypt_perf", "ufs_rx_symbol0",
> > "ufs_rx_symbol1";
> > +
> > + operating-points-v2 = <&ufs_opp_table>;
> > +
> > + avdd12-supply = <&mt6359_vrf12_ldo_reg>;
> > + avdd12-ckbuf-supply = <&mt6359_vbbck_ldo_reg>;
> > + avdd18-supply = <&mt6359_vio18_ldo_reg>;
> Do not add the avdd12/avdd12-clkbuf/avdd18! these analog power cannot
> be power off. even that the system is in suspend state!
That does not matter. If a supply cannot be powered off, it should
have the regulator-always-on property in the DTS. The relationship
still needs to be properly described in the binding. If you want the
driver to not do those calls, then please comment this on the driver
series.
> > + vcc-supply = <&mt6359_vemc_1_ldo_reg>;
> > + vccq2-supply = <&mt6359_vufs_ldo_reg>;
> > +
> > + mediatek,ufs-disable-mcq;
> > + };
> >
> > --
> > 2.52.0
> >
>
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* Re: [PATCH v2 2/2] phy: cadence-torrent: Add PCIe + XAUI multilink configuration for 100MHz refclk
From: Andrew Lunn @ 2026-01-04 21:57 UTC (permalink / raw)
To: Siddharth Vadapalli
Cc: vkoul, neil.armstrong, robh, krzk+dt, conor+dt, sjakhade, rogerq,
krzk, linux-phy, linux-kernel, devicetree, linux-arm-kernel, srk
In-Reply-To: <20260104114422.2868321-3-s-vadapalli@ti.com>
On Sun, Jan 04, 2026 at 05:14:18PM +0530, Siddharth Vadapalli wrote:
> From: Swapnil Jakhade <sjakhade@cadence.com>
>
> Add register sequences for PCIe + XAUI multilink configuration for
> 100MHz reference clock.
>
> Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> ---
>
> v1 of this patch is at:
> https://lore.kernel.org/r/20251224054905.763399-3-s-vadapalli@ti.com/
> No changes since v1.
>
> Regards,
> Siddharth.
>
> drivers/phy/cadence/phy-cadence-torrent.c | 143 ++++++++++++++++++++--
> 1 file changed, 136 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
> index 37fa4bad6bd7..f0d870886cca 100644
> --- a/drivers/phy/cadence/phy-cadence-torrent.c
> +++ b/drivers/phy/cadence/phy-cadence-torrent.c
> @@ -300,6 +300,7 @@ enum cdns_torrent_phy_type {
> TYPE_USB,
> TYPE_USXGMII,
> TYPE_PCIE_ML,
> + TYPE_XAUI,
> };
>
> enum cdns_torrent_ref_clk {
> @@ -320,14 +321,14 @@ enum cdns_torrent_ssc_mode {
> /* Unique key id for vals table entry
> * REFCLK0_RATE | REFCLK1_RATE | LINK0_TYPE | LINK1_TYPE | SSC_TYPE
> */
> -#define REFCLK0_SHIFT 12
> -#define REFCLK0_MASK GENMASK(14, 12)
> -#define REFCLK1_SHIFT 9
> -#define REFCLK1_MASK GENMASK(11, 9)
> -#define LINK0_SHIFT 6
> -#define LINK0_MASK GENMASK(8, 6)
> +#define REFCLK0_SHIFT 15
> +#define REFCLK0_MASK GENMASK(18, 15)
> +#define REFCLK1_SHIFT 11
> +#define REFCLK1_MASK GENMASK(14, 11)
> +#define LINK0_SHIFT 7
> +#define LINK0_MASK GENMASK(10, 7)
Why do these change? It would be good to add an explanation to the
commit message about this, because it is not obvious why these need to
change.
Andrew
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* [PATCH next v2] phy: apple: atc: Actually check return value of devm_apple_tunable_parse
From: Sven Peter @ 2026-01-04 21:56 UTC (permalink / raw)
To: Janne Grunau, Neal Gompa, Vinod Koul, Neil Armstrong
Cc: asahi, linux-arm-kernel, linux-phy, linux-kernel,
Thomas Glanzmann, Sven Peter
Let's actually check the return value of devm_apple_tunable_parse
instead of trying to check IS_ERR on a pointer to the return value which
is always going to be valid. This prevent a oops when the tunables are
invalid or when they don't exist:
[ 57.664567] Unable to handle kernel paging request at virtual address fffffffffffffffe
[ 57.664584] Mem abort info:
[ 57.664589] ESR = 0x0000000096000007
[ 57.664595] EC = 0x25: DABT (current EL), IL = 32 bits
[ 57.664602] SET = 0, FnV = 0
[ 57.664607] EA = 0, S1PTW = 0
[ 57.664611] FSC = 0x07: level 3 translation fault
[ 57.664617] Data abort info:
[ 57.664621] ISV = 0, ISS = 0x00000007, ISS2 = 0x00000000
[ 57.664626] CM = 0, WnR = 0, TnD = 0, TagAccess = 0
[ 57.664631] GCS = 0, Overlay = 0, DirtyBit = 0, Xs = 0
[ 57.664640] swapper pgtable: 16k pages, 47-bit VAs, pgdp=0000000b4391c000
[ 57.664647] [fffffffffffffffe] pgd=0000000000000000, p4d=0000000000000000, pud=0000000b44188403, pmd=0000000b4418c403, pte=0000000000000000
[ 57.664670] Internal error: Oops: 0000000096000007 [#1] SMP
[ 57.665047] CPU: 1 UID: 0 PID: 23 Comm: kworker/1:0 Tainted: G S 6.18.2+ #2 PREEMPTLAZY
[ 57.665061] Tainted: [S]=CPU_OUT_OF_SPEC
[ 57.665066] Hardware name: Apple Mac mini (M1, 2020) (DT)
[ 57.665072] Workqueue: events cd321x_update_work [tps6598x]
[ 57.665100] pstate: 61400009 (nZCv daif +PAN -UAO -TCO +DIT -SSBS BTYPE=--)
[ 57.665111] pc : apple_tunable_apply+0x8/0x80 [apple_tunable]
[ 57.665121] lr : atcphy_mux_set+0x3e0/0x1138 [phy_apple_atc]
[ 57.665133] sp : ffffc000802a7c00
[ 57.665138] x29: ffffc000802a7c00 x28: 0000000000000003 x27: ffff800016c84080
[ 57.665151] x26: 0000000000000002 x25: ffff800016c84090 x24: ffff800016c8408f
[ 57.665163] x23: 0000000000020004 x22: 0000000000000001 x21: 0000000000000006
[ 57.665175] x20: ffff80000d6da9b0 x19: ffff80000d6da880 x18: 0000000000000002
[ 57.665188] x17: 0000000000000000 x16: ffffe22de59e0e38 x15: 0000000000000002
[ 57.665199] x14: ffffe22de76ecff8 x13: 0000000000000001 x12: ffff9dd5f90bc000
[ 57.665211] x11: 00000000000000c0 x10: 048abc15ceba0919 x9 : ffffe22dbc5fde10
[ 57.665223] x8 : ffff80000175e0d8 x7 : 0000000000000004 x6 : 0000000000000000
[ 57.665234] x5 : 0000000000000001 x4 : 0000000d6d132db7 x3 : 00000000000155db
[ 57.665246] x2 : 0000000000000000 x1 : fffffffffffffffe x0 : ffffc00082b80000
[ 57.665258] Call trace:
[ 57.665265] apple_tunable_apply+0x8/0x80 [apple_tunable] (P)
[ 57.665276] typec_mux_set+0x74/0xe0 [typec]
[ 57.665315] cd321x_update_work+0x440/0x8c0 [tps6598x]
[ 57.665332] process_one_work+0x178/0x3d0
[ 57.665346] worker_thread+0x260/0x390
[ 57.665354] kthread+0x150/0x250
[ 57.665369] ret_from_fork+0x10/0x20
[ 57.665386] Code: e69a0ae8 ffffe22d aa1e03e9 d503201f (f9400022)
[ 57.665394] ---[ end trace 0000000000000000 ]---
Reported-by: Thomas Glanzmann <thomas@glanzmann.de>
Fixes: 8e98ca1e74db ("phy: apple: Add Apple Type-C PHY")
Signed-off-by: Sven Peter <sven@kernel.org>
---
Changes in v2:
- Copy/paste error: Copied a WARN instead of the kernel oops this patch fixes
- Link to v1: https://patch.msgid.link/20260104-atcphy-tunable-fix-v1-1-40bf00feaac0@kernel.org
---
drivers/phy/apple/atc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/apple/atc.c b/drivers/phy/apple/atc.c
index c8a58ee64b7aad3205df51cf16ae778471ad2c5d..716c1e70de38ca604803739fedaa543d91f7501b 100644
--- a/drivers/phy/apple/atc.c
+++ b/drivers/phy/apple/atc.c
@@ -2178,10 +2178,10 @@ static int atcphy_load_tunables(struct apple_atcphy *atcphy)
for (int i = 0; i < ARRAY_SIZE(tunables); i++) {
*tunables[i].tunable = devm_apple_tunable_parse(
atcphy->dev, atcphy->np, tunables[i].dt_name, tunables[i].res);
- if (IS_ERR(tunables[i].tunable)) {
+ if (IS_ERR(*tunables[i].tunable)) {
dev_err(atcphy->dev, "Failed to read tunable %s: %ld\n",
- tunables[i].dt_name, PTR_ERR(tunables[i].tunable));
- return PTR_ERR(tunables[i].tunable);
+ tunables[i].dt_name, PTR_ERR(*tunables[i].tunable));
+ return PTR_ERR(*tunables[i].tunable);
}
}
---
base-commit: add66a6673bc4aacd0ef0f3c4a51271501770b17
change-id: 20260104-atcphy-tunable-fix-517826d6fefd
Best regards,
--
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^ permalink raw reply related
* [PATCH next] phy: apple: atc: Actually check return value of devm_apple_tunable_parse
From: Sven Peter @ 2026-01-04 21:18 UTC (permalink / raw)
To: Janne Grunau, Neal Gompa, Vinod Koul, Neil Armstrong
Cc: asahi, linux-arm-kernel, linux-phy, linux-kernel,
Thomas Glanzmann, Sven Peter
Let's actually check the return value of devm_apple_tunable_parse
instead of trying to check IS_ERR on a pointer to the return value which
is always going to be valid. This prevent a oops when the tunables are
invalid or when they don't exist:
[ 42.819119] ------------[ cut here ]------------
[ 42.819121] WARNING: CPU: 6 PID: 88 at drivers/phy/apple/atc.c:2145 atcphy_mux_set+0xf60/0x1128 [phy_apple_atc]
[ 42.819302] CPU: 6 UID: 0 PID: 88 Comm: kworker/6:1 Tainted: G S 6.18+unreleased-asahi #1 PREEMPTLAZY Debian 6.18.2-0-1~exp1
[ 42.819311] Tainted: [S]=CPU_OUT_OF_SPEC
[ 42.819314] Hardware name: Apple Mac mini (M1, 2020) (DT)
[ 42.819316] Workqueue: events cd321x_update_work [tps6598x]
[ 42.819332] pstate: 81400009 (Nzcv daif +PAN -UAO -TCO +DIT -SSBS BTYPE=--)
[ 42.819338] pc : atcphy_mux_set+0xf60/0x1128 [phy_apple_atc]
[ 42.819344] lr : atcphy_mux_set+0x30/0x1128 [phy_apple_atc]
[ 42.819348] sp : ffffc000813c7c00
[ 42.819350] x29: ffffc000813c7c00 x28: ffff800016babeb8 x27: ffff800016babc80
[ 42.819357] x26: 0000000000000001 x25: 0000000000000001 x24: 0000000000000000
[ 42.819364] x23: ffff800016babec0 x22: 00000000ffffffa1 x21: 0000000000000003
[ 42.819371] x20: ffff80000c1b3680 x19: ffff80000dcdd080 x18: 0000000000000000
[ 42.819376] x17: 0000000000000000 x16: ffffd42e6ede6e08 x15: 0000000000000000
[ 42.819382] x14: ffffd42e707b6980 x13: 0000000000025c68 x12: 726f703d54524f50
[ 42.819388] x11: 0000000000000040 x10: 0000000000000000 x9 : ffffd42e555ed9c0
[ 42.819394] x8 : 0000000000000006 x7 : ffff80000a000dd8 x6 : 0000000000000002
[ 42.819399] x5 : 0000000000000000 x4 : 0000000000000000 x3 : 0000000000000001
[ 42.819404] x2 : 0000000000000005 x1 : 000000000000ff01 x0 : 0000000000000001
[ 42.819410] Call trace:
[ 42.819412] atcphy_mux_set+0xf60/0x1128 [phy_apple_atc] (P)
[ 42.819419] typec_mux_set+0x74/0xd8 [typec]
[ 42.819444] cd321x_update_work+0x440/0x8a8 [tps6598x]
[ 42.819453] process_one_work+0x170/0x3e0
[ 42.819466] worker_thread+0x25c/0x390
[ 42.819473] kthread+0x148/0x240
[ 42.819479] ret_from_fork+0x10/0x20
[ 42.819488] ---[ end trace 0000000000000000 ]---
Reported-by: Thomas Glanzmann <thomas@glanzmann.de>
Fixes: 8e98ca1e74db ("phy: apple: Add Apple Type-C PHY")
Signed-off-by: Sven Peter <sven@kernel.org>
---
drivers/phy/apple/atc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/apple/atc.c b/drivers/phy/apple/atc.c
index c8a58ee64b7aad3205df51cf16ae778471ad2c5d..716c1e70de38ca604803739fedaa543d91f7501b 100644
--- a/drivers/phy/apple/atc.c
+++ b/drivers/phy/apple/atc.c
@@ -2178,10 +2178,10 @@ static int atcphy_load_tunables(struct apple_atcphy *atcphy)
for (int i = 0; i < ARRAY_SIZE(tunables); i++) {
*tunables[i].tunable = devm_apple_tunable_parse(
atcphy->dev, atcphy->np, tunables[i].dt_name, tunables[i].res);
- if (IS_ERR(tunables[i].tunable)) {
+ if (IS_ERR(*tunables[i].tunable)) {
dev_err(atcphy->dev, "Failed to read tunable %s: %ld\n",
- tunables[i].dt_name, PTR_ERR(tunables[i].tunable));
- return PTR_ERR(tunables[i].tunable);
+ tunables[i].dt_name, PTR_ERR(*tunables[i].tunable));
+ return PTR_ERR(*tunables[i].tunable);
}
}
---
base-commit: add66a6673bc4aacd0ef0f3c4a51271501770b17
change-id: 20260104-atcphy-tunable-fix-517826d6fefd
Best regards,
--
Sven Peter <sven@kernel.org>
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* Re: [PATCH 1/2] dt-bindings: phy: Add PHY_TYPE_XAUI definition
From: Siddharth Vadapalli @ 2026-01-04 11:46 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: vkoul, neil.armstrong, robh, krzk+dt, conor+dt, sjakhade, rogerq,
linux-phy, linux-kernel, devicetree, linux-arm-kernel, srk,
s-vadapalli
In-Reply-To: <20251227-airborne-energetic-kingfisher-adc4fb@quoll>
On 27/12/25 6:33 PM, Krzysztof Kozlowski wrote:
> On Wed, Dec 24, 2025 at 11:18:58AM +0530, Siddharth Vadapalli wrote:
>> From: Swapnil Jakhade <sjakhade@cadence.com>
>>
>> Add definition for XAUI phy type.
>
> What is XAUI?
>
> Your commit msg duplicates subject and is obvious - repeats what is
> in the diff. Pretty pointless.
I have posted the v2 series at:
https://lore.kernel.org/r/20260104114422.2868321-1-s-vadapalli@ti.com/
providing a detailed description of XAUI in the commit message.
Thank you for the feedback.
Regards,
Siddharth.
--
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linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply
* [PATCH v2 2/2] phy: cadence-torrent: Add PCIe + XAUI multilink configuration for 100MHz refclk
From: Siddharth Vadapalli @ 2026-01-04 11:44 UTC (permalink / raw)
To: vkoul, neil.armstrong, robh, krzk+dt, conor+dt, sjakhade, rogerq
Cc: krzk, linux-phy, linux-kernel, devicetree, linux-arm-kernel, srk,
s-vadapalli
In-Reply-To: <20260104114422.2868321-1-s-vadapalli@ti.com>
From: Swapnil Jakhade <sjakhade@cadence.com>
Add register sequences for PCIe + XAUI multilink configuration for
100MHz reference clock.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
v1 of this patch is at:
https://lore.kernel.org/r/20251224054905.763399-3-s-vadapalli@ti.com/
No changes since v1.
Regards,
Siddharth.
drivers/phy/cadence/phy-cadence-torrent.c | 143 ++++++++++++++++++++--
1 file changed, 136 insertions(+), 7 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
index 37fa4bad6bd7..f0d870886cca 100644
--- a/drivers/phy/cadence/phy-cadence-torrent.c
+++ b/drivers/phy/cadence/phy-cadence-torrent.c
@@ -300,6 +300,7 @@ enum cdns_torrent_phy_type {
TYPE_USB,
TYPE_USXGMII,
TYPE_PCIE_ML,
+ TYPE_XAUI,
};
enum cdns_torrent_ref_clk {
@@ -320,14 +321,14 @@ enum cdns_torrent_ssc_mode {
/* Unique key id for vals table entry
* REFCLK0_RATE | REFCLK1_RATE | LINK0_TYPE | LINK1_TYPE | SSC_TYPE
*/
-#define REFCLK0_SHIFT 12
-#define REFCLK0_MASK GENMASK(14, 12)
-#define REFCLK1_SHIFT 9
-#define REFCLK1_MASK GENMASK(11, 9)
-#define LINK0_SHIFT 6
-#define LINK0_MASK GENMASK(8, 6)
+#define REFCLK0_SHIFT 15
+#define REFCLK0_MASK GENMASK(18, 15)
+#define REFCLK1_SHIFT 11
+#define REFCLK1_MASK GENMASK(14, 11)
+#define LINK0_SHIFT 7
+#define LINK0_MASK GENMASK(10, 7)
#define LINK1_SHIFT 3
-#define LINK1_MASK GENMASK(5, 3)
+#define LINK1_MASK GENMASK(6, 3)
#define SSC_SHIFT 0
#define SSC_MASK GENMASK(2, 0)
@@ -708,6 +709,8 @@ static const char *cdns_torrent_get_phy_type(enum cdns_torrent_phy_type phy_type
return "USB";
case TYPE_USXGMII:
return "USXGMII";
+ case TYPE_XAUI:
+ return "XAUI";
default:
return "None";
}
@@ -3020,6 +3023,9 @@ static int cdns_torrent_phy_probe(struct platform_device *pdev)
case PHY_TYPE_USXGMII:
cdns_phy->phys[node].phy_type = TYPE_USXGMII;
break;
+ case PHY_TYPE_XAUI:
+ cdns_phy->phys[node].phy_type = TYPE_XAUI;
+ break;
default:
dev_err(dev, "Unsupported protocol\n");
ret = -EINVAL;
@@ -3382,6 +3388,95 @@ static DEFINE_NOIRQ_DEV_PM_OPS(cdns_torrent_phy_pm_ops,
cdns_torrent_phy_suspend_noirq,
cdns_torrent_phy_resume_noirq);
+/* PCIe and XAUI link configuration */
+static const struct cdns_reg_pairs pcie_xaui_link_cmn_regs[] = {
+ {0x0003, PHY_PLL_CFG},
+ {0x0600, CMN_PDIAG_PLL1_CLK_SEL_M0}
+};
+
+static const struct cdns_reg_pairs xaui_pcie_xcvr_diag_ln_regs[] = {
+ {0x0011, XCVR_DIAG_HSCLK_SEL},
+ {0x0089, XCVR_DIAG_PLLDRC_CTRL}
+};
+
+static const struct cdns_torrent_vals pcie_xaui_link_cmn_vals = {
+ .reg_pairs = pcie_xaui_link_cmn_regs,
+ .num_regs = ARRAY_SIZE(pcie_xaui_link_cmn_regs),
+};
+
+static const struct cdns_torrent_vals xaui_pcie_xcvr_diag_ln_vals = {
+ .reg_pairs = xaui_pcie_xcvr_diag_ln_regs,
+ .num_regs = ARRAY_SIZE(xaui_pcie_xcvr_diag_ln_regs),
+};
+
+/* XAUI 100 MHz Ref clk, no SSC */
+static const struct cdns_reg_pairs xaui_100_no_ssc_cmn_regs[] = {
+ {0x0004, CMN_PLL1_DSM_DIAG_M0},
+ {0x0B17, CMN_PDIAG_PLL1_CP_PADJ_M0},
+ {0x0E01, CMN_PDIAG_PLL1_CP_IADJ_M0},
+ {0x0D05, CMN_PDIAG_PLL1_FILT_PADJ_M0},
+ {0x003E, CMN_PLL1_INTDIV_M0},
+ {0x8000, CMN_PLL1_FRACDIVL_M0},
+ {0x0002, CMN_PLL1_FRACDIVH_M0},
+ {0x002A, CMN_PLL1_HIGH_THR_M0},
+ {0x3102, CMN_PDIAG_PLL1_CTRL_M0},
+ {0x007F, CMN_TXPUCAL_TUNE},
+ {0x007F, CMN_TXPDCAL_TUNE}
+};
+
+static const struct cdns_reg_pairs xaui_100_no_ssc_tx_ln_regs[] = {
+ {0x00F3, TX_PSC_A0},
+ {0x04A2, TX_PSC_A2},
+ {0x04A2, TX_PSC_A3 },
+ {0x0000, TX_TXCC_CPOST_MULT_00}
+};
+
+static const struct cdns_reg_pairs ti_xaui_100_no_ssc_tx_ln_regs[] = {
+ {0x00F3, TX_PSC_A0},
+ {0x04A2, TX_PSC_A2},
+ {0x04A2, TX_PSC_A3 },
+ {0x0000, TX_TXCC_CPOST_MULT_00},
+ {0x4000, XCVR_DIAG_RXCLK_CTRL}
+};
+
+static const struct cdns_reg_pairs xaui_100_no_ssc_rx_ln_regs[] = {
+ {0x091D, RX_PSC_A0},
+ {0x0900, RX_PSC_A2},
+ {0x0100, RX_PSC_A3},
+ {0x03C7, RX_REE_GCSM1_EQENM_PH1},
+ {0x01C7, RX_REE_GCSM1_EQENM_PH2},
+ {0x0000, RX_DIAG_DFE_CTRL},
+ {0x0019, RX_REE_TAP1_CLIP},
+ {0x0019, RX_REE_TAP2TON_CLIP},
+ {0x0098, RX_DIAG_NQST_CTRL},
+ {0x0C01, RX_DIAG_DFE_AMP_TUNE_2},
+ {0x0000, RX_DIAG_DFE_AMP_TUNE_3},
+ {0x0000, RX_DIAG_PI_CAP},
+ {0x0031, RX_DIAG_PI_RATE},
+ {0x0001, RX_DIAG_ACYA},
+ {0x018C, RX_CDRLF_CNFG},
+};
+
+static const struct cdns_torrent_vals xaui_100_no_ssc_cmn_vals = {
+ .reg_pairs = xaui_100_no_ssc_cmn_regs,
+ .num_regs = ARRAY_SIZE(xaui_100_no_ssc_cmn_regs),
+};
+
+static const struct cdns_torrent_vals xaui_100_no_ssc_tx_ln_vals = {
+ .reg_pairs = xaui_100_no_ssc_tx_ln_regs,
+ .num_regs = ARRAY_SIZE(xaui_100_no_ssc_tx_ln_regs),
+};
+
+static const struct cdns_torrent_vals ti_xaui_100_no_ssc_tx_ln_vals = {
+ .reg_pairs = ti_xaui_100_no_ssc_tx_ln_regs,
+ .num_regs = ARRAY_SIZE(ti_xaui_100_no_ssc_tx_ln_regs),
+};
+
+static const struct cdns_torrent_vals xaui_100_no_ssc_rx_ln_vals = {
+ .reg_pairs = xaui_100_no_ssc_rx_ln_regs,
+ .num_regs = ARRAY_SIZE(xaui_100_no_ssc_rx_ln_regs),
+};
+
/* USB and DP link configuration */
static const struct cdns_reg_pairs usb_dp_link_cmn_regs[] = {
{0x0002, PHY_PLL_CFG},
@@ -4853,6 +4948,7 @@ static const struct cdns_torrent_vals_entry link_cmn_vals_entries[] = {
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_USB), &pcie_usb_link_cmn_vals},
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_DP), &pcie_dp_link_cmn_vals},
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_USXGMII), &pcie_usxgmii_link_cmn_vals},
+ {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_XAUI), &pcie_xaui_link_cmn_vals},
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE_ML, TYPE_USB), &ml_pcie_usb_link_cmn_vals},
@@ -4879,6 +4975,8 @@ static const struct cdns_torrent_vals_entry link_cmn_vals_entries[] = {
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_PCIE), &pcie_usxgmii_link_cmn_vals},
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_SGMII), &usxgmii_sgmii_link_cmn_vals},
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_QSGMII), &usxgmii_sgmii_link_cmn_vals},
+
+ {CDNS_TORRENT_KEY_ANYCLK(TYPE_XAUI, TYPE_PCIE), &pcie_xaui_link_cmn_vals},
};
static const struct cdns_torrent_vals_entry xcvr_diag_vals_entries[] = {
@@ -4893,6 +4991,7 @@ static const struct cdns_torrent_vals_entry xcvr_diag_vals_entries[] = {
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_USB), &pcie_usb_xcvr_diag_ln_vals},
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_DP), &pcie_dp_xcvr_diag_ln_vals},
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_USXGMII), &pcie_usxgmii_xcvr_diag_ln_vals},
+ {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_XAUI), NULL},
{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE_ML, TYPE_USB), &ml_pcie_usb_xcvr_diag_ln_vals},
@@ -4919,6 +5018,8 @@ static const struct cdns_torrent_vals_entry xcvr_diag_vals_entries[] = {
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_PCIE), &usxgmii_pcie_xcvr_diag_ln_vals},
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_SGMII), &usxgmii_sgmii_xcvr_diag_ln_vals},
{CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_QSGMII), &usxgmii_sgmii_xcvr_diag_ln_vals},
+
+ {CDNS_TORRENT_KEY_ANYCLK(TYPE_XAUI, TYPE_PCIE), &xaui_pcie_xcvr_diag_ln_vals},
};
static const struct cdns_torrent_vals_entry pcs_cmn_vals_entries[] = {
@@ -4960,6 +5061,8 @@ static const struct cdns_torrent_vals_entry cmn_vals_entries[] = {
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), NULL},
+ {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_XAUI, NO_SSC), NULL},
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, NO_SSC), &ml_pcie_100_no_ssc_cmn_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, EXTERNAL_SSC), &ml_pcie_100_no_ssc_cmn_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, INTERNAL_SSC), &ml_pcie_100_int_ssc_cmn_vals},
@@ -5010,6 +5113,8 @@ static const struct cdns_torrent_vals_entry cmn_vals_entries[] = {
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_DP, NO_SSC), &usb_100_no_ssc_cmn_vals},
+ {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_XAUI, TYPE_PCIE, NO_SSC), &xaui_100_no_ssc_cmn_vals},
+
{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_156_25_MHZ, TYPE_USXGMII, TYPE_NONE, NO_SSC), &sl_usxgmii_156_25_no_ssc_cmn_vals},
/* Dual refclk */
@@ -5054,6 +5159,8 @@ static const struct cdns_torrent_vals_entry cdns_tx_ln_vals_entries[] = {
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), NULL},
+ {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_XAUI, NO_SSC), NULL},
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, NO_SSC), NULL},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, EXTERNAL_SSC), NULL},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, INTERNAL_SSC), NULL},
@@ -5104,6 +5211,8 @@ static const struct cdns_torrent_vals_entry cdns_tx_ln_vals_entries[] = {
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_DP, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
+ {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_XAUI, TYPE_PCIE, NO_SSC), &xaui_100_no_ssc_tx_ln_vals},
+
{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_156_25_MHZ, TYPE_USXGMII, TYPE_NONE, NO_SSC), &usxgmii_156_25_no_ssc_tx_ln_vals},
/* Dual refclk */
@@ -5148,6 +5257,8 @@ static const struct cdns_torrent_vals_entry cdns_rx_ln_vals_entries[] = {
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
+ {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_XAUI, NO_SSC), &ml_pcie_100_no_ssc_rx_ln_vals},
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, NO_SSC), &ml_pcie_100_no_ssc_rx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, EXTERNAL_SSC), &ml_pcie_100_no_ssc_rx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, INTERNAL_SSC), &ml_pcie_100_no_ssc_rx_ln_vals},
@@ -5198,6 +5309,8 @@ static const struct cdns_torrent_vals_entry cdns_rx_ln_vals_entries[] = {
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_DP, NO_SSC), &usb_100_no_ssc_rx_ln_vals},
+ {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_XAUI, TYPE_PCIE, NO_SSC), &xaui_100_no_ssc_rx_ln_vals},
+
{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_156_25_MHZ, TYPE_USXGMII, TYPE_NONE, NO_SSC), &usxgmii_156_25_no_ssc_rx_ln_vals},
/* Dual refclk */
@@ -5278,6 +5391,8 @@ static const struct cdns_torrent_vals_entry ti_tx_ln_vals_entries[] = {
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), NULL},
+ {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_XAUI, NO_SSC), NULL},
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, NO_SSC), NULL},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, EXTERNAL_SSC), NULL},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, INTERNAL_SSC), NULL},
@@ -5328,6 +5443,8 @@ static const struct cdns_torrent_vals_entry ti_tx_ln_vals_entries[] = {
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_DP, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
+ {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_XAUI, TYPE_PCIE, NO_SSC), &ti_xaui_100_no_ssc_tx_ln_vals},
+
{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_156_25_MHZ, TYPE_USXGMII, TYPE_NONE, NO_SSC), &usxgmii_156_25_no_ssc_tx_ln_vals},
/* Dual refclk */
@@ -5406,6 +5523,8 @@ static const struct cdns_torrent_vals_entry ti_j7200_cmn_vals_entries[] = {
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), NULL},
+ {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_XAUI, NO_SSC), NULL},
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, NO_SSC), &ml_pcie_100_no_ssc_cmn_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, EXTERNAL_SSC), &ml_pcie_100_no_ssc_cmn_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, INTERNAL_SSC), &ml_pcie_100_int_ssc_cmn_vals},
@@ -5456,6 +5575,8 @@ static const struct cdns_torrent_vals_entry ti_j7200_cmn_vals_entries[] = {
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_DP, NO_SSC), &usb_100_no_ssc_cmn_vals},
+ {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_XAUI, TYPE_PCIE, NO_SSC), &xaui_100_no_ssc_cmn_vals},
+
{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_156_25_MHZ, TYPE_USXGMII, TYPE_NONE, NO_SSC), &sl_usxgmii_156_25_no_ssc_cmn_vals},
/* Dual refclk */
@@ -5500,6 +5621,8 @@ static const struct cdns_torrent_vals_entry ti_j7200_tx_ln_vals_entries[] = {
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), NULL},
+ {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_XAUI, NO_SSC), NULL},
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, NO_SSC), NULL},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, EXTERNAL_SSC), NULL},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, INTERNAL_SSC), NULL},
@@ -5550,6 +5673,8 @@ static const struct cdns_torrent_vals_entry ti_j7200_tx_ln_vals_entries[] = {
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_DP, NO_SSC), &usb_100_no_ssc_tx_ln_vals},
+ {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_XAUI, TYPE_PCIE, NO_SSC), &ti_xaui_100_no_ssc_tx_ln_vals},
+
{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_156_25_MHZ, TYPE_USXGMII, TYPE_NONE, NO_SSC), &usxgmii_156_25_no_ssc_tx_ln_vals},
/* Dual refclk */
@@ -5594,6 +5719,8 @@ static const struct cdns_torrent_vals_entry ti_j7200_rx_ln_vals_entries[] = {
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
+ {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_XAUI, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
+
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},
@@ -5644,6 +5771,8 @@ static const struct cdns_torrent_vals_entry ti_j7200_rx_ln_vals_entries[] = {
{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_DP, NO_SSC), &usb_100_no_ssc_rx_ln_vals},
+ {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_XAUI, TYPE_PCIE, NO_SSC), &xaui_100_no_ssc_rx_ln_vals},
+
{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_156_25_MHZ, TYPE_USXGMII, TYPE_NONE, NO_SSC), &usxgmii_156_25_no_ssc_rx_ln_vals},
/* Dual refclk */
--
2.51.1
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* [PATCH v2 1/2] dt-bindings: phy: Add PHY_TYPE_XAUI definition
From: Siddharth Vadapalli @ 2026-01-04 11:44 UTC (permalink / raw)
To: vkoul, neil.armstrong, robh, krzk+dt, conor+dt, sjakhade, rogerq
Cc: krzk, linux-phy, linux-kernel, devicetree, linux-arm-kernel, srk,
s-vadapalli
In-Reply-To: <20260104114422.2868321-1-s-vadapalli@ti.com>
From: Swapnil Jakhade <sjakhade@cadence.com>
XAUI (eXtended Attachment Unit Interface) is a high-speed serial interface
standard for 10 Gigabit Ethernet (10GbE). It uses four lanes with each
lane operating at 3.125 Gbps (totaling 10 Gbps), to extend the XGMII
interface across circuit boards, commonly used in backplanes for
networking switches and high-performance computing. XAUI is defined as a
standardized instantiation of XGMII Extender in the IEEE 802.3
specification.
Add definition for XAUI PHY type.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
[s-vadapalli: added detailed description of XAUI in the commit message]
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
v1 of this patch is at:
https://lore.kernel.org/r/20251224054905.763399-2-s-vadapalli@ti.com/
Changes since v1:
- The commit message has been updated to provide a detailed description of
XAUI based on feedback from Krzysztof at:
https://lore.kernel.org/r/20251227-airborne-energetic-kingfisher-adc4fb@quoll/
Regards,
Siddharth.
include/dt-bindings/phy/phy.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/phy/phy.h b/include/dt-bindings/phy/phy.h
index 6b901b342348..d77b372d302f 100644
--- a/include/dt-bindings/phy/phy.h
+++ b/include/dt-bindings/phy/phy.h
@@ -23,5 +23,6 @@
#define PHY_TYPE_DPHY 10
#define PHY_TYPE_CPHY 11
#define PHY_TYPE_USXGMII 12
+#define PHY_TYPE_XAUI 13
#endif /* _DT_BINDINGS_PHY */
--
2.51.1
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* [PATCH v2 0/2] Cadence: Torrent: Enable PCIe + XAUI multilink configuration
From: Siddharth Vadapalli @ 2026-01-04 11:44 UTC (permalink / raw)
To: vkoul, neil.armstrong, robh, krzk+dt, conor+dt, sjakhade, rogerq
Cc: krzk, linux-phy, linux-kernel, devicetree, linux-arm-kernel, srk,
s-vadapalli
Hello,
This patch series adds the dt-binding for PHY_TYPE_XAUI and adds the
driver support for enabling PCIe + XAUI multilink configuration.
Patch series is based on linux-next tagged next-20251219 and it also
applies cleanly on the latest Mainline Linux commit
aacb0a6d604a Merge tag 'pmdomain-v6.19-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm
v1 of this patch series is at:
https://lore.kernel.org/r/20251224054905.763399-1-s-vadapalli@ti.com/
Changes since v1:
- The commit message in the first patch has been updated to provide a
detailed description of XAUI based on feedback from Krzysztof at:
https://lore.kernel.org/r/20251227-airborne-energetic-kingfisher-adc4fb@quoll/
Regards,
Siddharth.
Swapnil Jakhade (2):
dt-bindings: phy: Add PHY_TYPE_XAUI definition
phy: cadence-torrent: Add PCIe + XAUI multilink configuration for
100MHz refclk
drivers/phy/cadence/phy-cadence-torrent.c | 143 ++++++++++++++++++++--
include/dt-bindings/phy/phy.h | 1 +
2 files changed, 137 insertions(+), 7 deletions(-)
--
2.51.1
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* Re: [PATCH 2/5] dt-bindings: soc: canaan: Add top syscon for Canaan K230 SoC
From: Jiayu Du @ 2026-01-04 1:40 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: conor, vkoul, gregkh, pjw, palmer, aou, alex, neil.armstrong,
krzk+dt, linux-riscv, devicetree, linux-kernel, linux-phy,
linux-usb
In-Reply-To: <572407e8-bac7-4277-bfbd-ed42327b0ff4@kernel.org>
On Tue, Dec 30, 2025 at 03:00:26PM +0100, Krzysztof Kozlowski wrote:
> On 30/12/2025 14:14, Jiayu Du wrote:
> > On Tue, Dec 30, 2025 at 08:39:19AM +0100, Krzysztof Kozlowski wrote:
> >> On Tue, Dec 30, 2025 at 10:37:21AM +0800, Jiayu Du wrote:
> > This hisys memory area not only includes the usbphy registers,
> > but also contains the registers of sd/mmc phy. Therefore, the
> > hisys node is necessary and cannot be folded.
>
> Can be. There is absolutely nothing stopping it.
>
> Anyway, define all nodes.
I will fold the child into the parent in v2, thanks for your guidance.
> >
> >
> > If what I said above is accepted by you, do I still need to
> > merge the two usb phy nodes by defining one phy with phy-cells=2?
>
> You should read your datasheet, not exactly rely on me guessing. In
> current form of the binding, you must fold the child into the parent.
>
> Best regards,
> Krzysztof
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
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* Re: [PATCH 4/5] phy: usb: Add driver for Canaan K230 USB 2.0 PHY
From: Jiayu Du @ 2026-01-04 1:37 UTC (permalink / raw)
To: Vinod Koul
Cc: conor, gregkh, pjw, palmer, aou, alex, neil.armstrong, krzk+dt,
linux-riscv, devicetree, linux-kernel, linux-phy, linux-usb
In-Reply-To: <aVZQ4YVXGryHz0ds@vaman>
On Thu, Jan 01, 2026 at 04:18:01PM +0530, Vinod Koul wrote:
> On 30-12-25, 10:37, Jiayu Du wrote:
> > Add driver for the USB 2.0 PHY in Canaan K230 SoC, which supports PHY
> > initialization, power management and USB mode switching.
> >
> > Add Kconfig/Makefile under drivers/phy/canaan/.
> >
> > Signed-off-by: Jiayu Du <jiayu.riscv@isrc.iscas.ac.cn>
...
> > +#define TEST_CTL3_OFFSET 0x0C
>
> Lowercase hex values please.. do you need a test register :-)
Sorry, I will convert the hex to lowercase.
In the TRM manual, the registers are named TEST_CTL and they are
used to describe the otg0 phy port control. The TRM manual is here[1].
The description of this register is located on page 1015.
Therefore, I have retained the names as stated in the TRM manual.
Link:
https://kendryte-download.canaan-creative.com/developer/k230/HDK/K230%E7%A1%AC%E4%BB%B6%E6%96%87%E6%A1%A3/K230_Technical_Reference_Manual_V0.3.1_20241118.pdf
[1]
> > + FIELD_PREP(USB_CTL0_PLLPTUNE_MASK, 0xC) | \
>
> lower hex here and rest
I will fix it in v2.
>
> > + ret = regmap_update_bits(phy->regmap, phy->reg_test_offset +
> > + TEST_CTL3_OFFSET, val, val);
>
> so we are writing to a test register..?
As I mentioned above, this is actually otg0 phy port control
register.
> > + int ret;
> > + u32 offset;
> > + struct regmap *regmap;
> > + struct phy *generic_phy;
> > + struct k230_usb_phy *phy;
> > + struct phy_provider *provider;
> > + struct device *dev = &pdev->dev;
>
> reverse christmas tree order would look better...
I will fix it in v2.
> > +
> > +
>
> why two lines...?
I will fix it in v2.
>
> > +MODULE_LICENSE("GPL");
> > --
> > 2.52.0
>
> --
> ~Vinod
Regards,
Jiayu Du
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* [PATCH v2 net-next 10/10] net: pcs: pcs-mtk-lynxi: deprecate "mediatek,pnswap"
From: Vladimir Oltean @ 2026-01-03 21:04 UTC (permalink / raw)
To: netdev, devicetree, linux-phy
Cc: linux-kernel, linux-arm-kernel, linux-mediatek, Daniel Golle,
Horatiu Vultur, Bjørn Mork, Andrew Lunn, Heiner Kallweit,
Russell King, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Vinod Koul, Neil Armstrong, Matthias Brugger,
AngeloGioacchino Del Regno, Eric Woudstra, Marek Behún,
Lee Jones, Patrice Chotard
In-Reply-To: <20260103210403.438687-1-vladimir.oltean@nxp.com>
Prefer the new "rx-polarity" and "tx-polarity" properties, which in this
case have the advantage that polarity inversion can be specified per
direction (and per protocol, although this isn't useful here).
We use the vendor specific ones as fallback if the standard description
doesn't exist.
Daniel, referring to the Mediatek SDK, clarifies that the combined
SGMII_PN_SWAP_TX_RX register field should be split like this: bit 0 is
TX and bit 1 is RX:
https://lore.kernel.org/linux-phy/aSW--slbJWpXK0nv@makrotopia.org/
Suggested-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
v1->v2: patch is new
drivers/net/pcs/Kconfig | 1 +
drivers/net/pcs/pcs-mtk-lynxi.c | 50 +++++++++++++++++++++++++++++----
2 files changed, 45 insertions(+), 6 deletions(-)
diff --git a/drivers/net/pcs/Kconfig b/drivers/net/pcs/Kconfig
index ecbc3530e780..5f94a11f6332 100644
--- a/drivers/net/pcs/Kconfig
+++ b/drivers/net/pcs/Kconfig
@@ -20,6 +20,7 @@ config PCS_LYNX
config PCS_MTK_LYNXI
tristate
+ select GENERIC_PHY_COMMON_PROPS
select REGMAP
help
This module provides helpers to phylink for managing the LynxI PCS
diff --git a/drivers/net/pcs/pcs-mtk-lynxi.c b/drivers/net/pcs/pcs-mtk-lynxi.c
index 7f719da5812e..74dbce205f71 100644
--- a/drivers/net/pcs/pcs-mtk-lynxi.c
+++ b/drivers/net/pcs/pcs-mtk-lynxi.c
@@ -11,6 +11,7 @@
#include <linux/mdio.h>
#include <linux/of.h>
#include <linux/pcs/pcs-mtk-lynxi.h>
+#include <linux/phy/phy-common-props.h>
#include <linux/phylink.h>
#include <linux/regmap.h>
@@ -62,8 +63,9 @@
/* Register to QPHY wrapper control */
#define SGMSYS_QPHY_WRAP_CTRL 0xec
-#define SGMII_PN_SWAP_MASK GENMASK(1, 0)
-#define SGMII_PN_SWAP_TX_RX (BIT(0) | BIT(1))
+#define SGMII_PN_SWAP_RX BIT(1)
+#define SGMII_PN_SWAP_TX BIT(0)
+
/* struct mtk_pcs_lynxi - This structure holds each sgmii regmap andassociated
* data
@@ -121,6 +123,42 @@ static void mtk_pcs_lynxi_get_state(struct phylink_pcs *pcs,
FIELD_GET(SGMII_LPA, adv));
}
+static int mtk_pcs_config_polarity(struct mtk_pcs_lynxi *mpcs,
+ phy_interface_t interface)
+{
+ struct fwnode_handle *fwnode = mpcs->fwnode, *pcs_fwnode;
+ unsigned int pol, default_pol = PHY_POL_NORMAL;
+ unsigned int val = 0;
+ int ret;
+
+ if (fwnode_property_read_bool(fwnode, "mediatek,pnswap"))
+ default_pol = PHY_POL_INVERT;
+
+ pcs_fwnode = fwnode_get_named_child_node(fwnode, "pcs");
+
+ ret = phy_get_rx_polarity(pcs_fwnode, phy_modes(interface),
+ BIT(PHY_POL_NORMAL) | BIT(PHY_POL_INVERT),
+ default_pol, &pol);
+ if (ret) {
+ fwnode_handle_put(pcs_fwnode);
+ return ret;
+ }
+ if (pol == PHY_POL_INVERT)
+ val |= SGMII_PN_SWAP_RX;
+
+ ret = phy_get_tx_polarity(pcs_fwnode, phy_modes(interface),
+ BIT(PHY_POL_NORMAL) | BIT(PHY_POL_INVERT),
+ default_pol, &pol);
+ fwnode_handle_put(pcs_fwnode);
+ if (ret)
+ return ret;
+ if (pol == PHY_POL_INVERT)
+ val |= SGMII_PN_SWAP_TX;
+
+ return regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_WRAP_CTRL,
+ SGMII_PN_SWAP_RX | SGMII_PN_SWAP_TX, val);
+}
+
static int mtk_pcs_lynxi_config(struct phylink_pcs *pcs, unsigned int neg_mode,
phy_interface_t interface,
const unsigned long *advertising,
@@ -130,6 +168,7 @@ static int mtk_pcs_lynxi_config(struct phylink_pcs *pcs, unsigned int neg_mode,
bool mode_changed = false, changed;
unsigned int rgc3, sgm_mode, bmcr;
int advertise, link_timer;
+ int ret;
advertise = phylink_mii_c22_pcs_encode_advertisement(interface,
advertising);
@@ -169,10 +208,9 @@ static int mtk_pcs_lynxi_config(struct phylink_pcs *pcs, unsigned int neg_mode,
regmap_set_bits(mpcs->regmap, SGMSYS_RESERVED_0,
SGMII_SW_RESET);
- if (fwnode_property_read_bool(mpcs->fwnode, "mediatek,pnswap"))
- regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_WRAP_CTRL,
- SGMII_PN_SWAP_MASK,
- SGMII_PN_SWAP_TX_RX);
+ ret = mtk_pcs_config_polarity(mpcs, interface);
+ if (ret)
+ return ret;
if (interface == PHY_INTERFACE_MODE_2500BASEX)
rgc3 = SGMII_PHY_SPEED_3_125G;
--
2.34.1
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