* Re: [PATCH v2 9/9] arm64: dts: renesas: ebisu: Describe PCIe/USB3.0 clock generator
From: Marek Vasut @ 2026-01-22 10:56 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Mark Brown, linux-arm-kernel, Conor Dooley, Krzysztof Kozlowski,
Magnus Damm, Neil Armstrong, Rob Herring, Vinod Koul,
Yoshihiro Shimoda, devicetree, linux-phy, linux-renesas-soc
In-Reply-To: <CAMuHMdX0iuyUhGRPFf4x==e_ZEMjaB_dP6mrM81F+yxqwam0FA@mail.gmail.com>
On 1/22/26 11:24 AM, Geert Uytterhoeven wrote:
Hello Geert,
>> This piece of code in drivers/usb/phy/phy-generic.c [1] shouldn't fail
>> the probe if "vbus-supply" property is not present in DT. If
>> "vbus-supply" property is not present in DT, then
>> PTR_ERR(nop->vbus_draw) == -ENODEV is true, nop->vbus_draw will be set
>> to NULL, but won't encode error, so the dev_err_probe() won't trigger.
>>
>> "
>> 259 nop->vbus_draw = devm_regulator_get_exclusive(dev, "vbus");
>> 260 if (PTR_ERR(nop->vbus_draw) == -ENODEV)
>> 261 nop->vbus_draw = NULL;
>> 262 if (IS_ERR(nop->vbus_draw))
>> 263 return dev_err_probe(dev, PTR_ERR(nop->vbus_draw),
>> 264 "could not get vbus regulator\n");
>> "
>>
>> [1]
>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/usb/phy/phy-generic.c#n259
>
> Sorry, you are right. I missed the PHY driver ignores the error and
> probes successfully, and thus didn't bother doing "echo ee000000.usb >
> /sys/bus/platform/drivers/xhci-renesas-hcd/bind" after /lib/firmware
> became available.
Is any change needed to this series then ?
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply
* Re: [PATCH v2 1/6] phy: qcom: qmp-combo: Prevent unnecessary PM runtime suspend at boot
From: Konrad Dybcio @ 2026-01-22 14:52 UTC (permalink / raw)
To: Loic Poulain, vkoul, kishon
Cc: linux-arm-msm, linux-phy, dmitry.baryshkov, neil.armstrong
In-Reply-To: <20260121142827.2583-2-loic.poulain@oss.qualcomm.com>
On 1/21/26 3:28 PM, Loic Poulain wrote:
> There is a small window where the device can suspend after
> pm_runtime_enable() and before pm_runtime_forbid(), causing an
> unnecessary suspend/resume cycle while the PHY is not yet registered.
>
> Move pm_runtime_forbid() before pm_runtime_enable() to eliminate
> this race.
>
> Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply
* Re: [PATCH v2 3/6] phy: qcom: qmp-usbc: Prevent unnecessary PM runtime suspend at boot
From: Konrad Dybcio @ 2026-01-22 14:53 UTC (permalink / raw)
To: Loic Poulain, vkoul, kishon
Cc: linux-arm-msm, linux-phy, dmitry.baryshkov, neil.armstrong
In-Reply-To: <20260121142827.2583-4-loic.poulain@oss.qualcomm.com>
On 1/21/26 3:28 PM, Loic Poulain wrote:
> There is a small window where the device can suspend after
> pm_runtime_enable() and before pm_runtime_forbid(), causing an
> unnecessary suspend/resume cycle while the PHY is not yet registered.
>
> Move pm_runtime_forbid() before pm_runtime_enable() to eliminate
> this race.
>
> Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply
* Re: [PATCH v2 5/6] phy: qcom: qmp-usb-legacy: Prevent unnecessary PM runtime suspend at boot
From: Konrad Dybcio @ 2026-01-22 14:53 UTC (permalink / raw)
To: Loic Poulain, vkoul, kishon
Cc: linux-arm-msm, linux-phy, dmitry.baryshkov, neil.armstrong
In-Reply-To: <20260121142827.2583-6-loic.poulain@oss.qualcomm.com>
On 1/21/26 3:28 PM, Loic Poulain wrote:
> There is a small window where the device can suspend after
> pm_runtime_enable() and before pm_runtime_forbid(), causing an
> unnecessary suspend/resume cycle while the PHY is not yet registered.
>
> Move pm_runtime_forbid() before pm_runtime_enable() to eliminate
> this race.
>
> Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply
* Re: [PATCH v2 6/6] phy: qcom: snps-femto-v2: Fix possible NULL-deref on early runtime suspend
From: Konrad Dybcio @ 2026-01-22 14:53 UTC (permalink / raw)
To: Loic Poulain, vkoul, kishon
Cc: linux-arm-msm, linux-phy, dmitry.baryshkov, neil.armstrong
In-Reply-To: <20260121142827.2583-7-loic.poulain@oss.qualcomm.com>
On 1/21/26 3:28 PM, Loic Poulain wrote:
> Enabling runtime PM before attaching the hsphy instance as driver data
> can lead to a NULL pointer dereference in runtime PM callbacks that
> expect valid driver data. There is a small window where the suspend
> callback may run after PM runtime enabling and before runtime forbid.
>
> Attach the hsphy instance as driver data before enabling runtime PM to
> prevent NULL pointer dereference in runtime PM callbacks.
>
> Reorder pm_runtime_enable() and pm_runtime_forbid() to prevent a
> short window where an unnecessary runtime suspend can occur.
>
> Use the devres-managed version to ensure PM runtime is symmetrically
> disabled during driver removal for proper cleanup.
>
> Fixes: 0d75f508a9d5 ("phy: qcom-snps: Add runtime suspend and resume handlers")
> Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply
* Re: [PATCH v2 2/6] phy: qcom: qmp-usbc: Fix possible NULL-deref on early runtime suspend
From: Konrad Dybcio @ 2026-01-22 15:00 UTC (permalink / raw)
To: Loic Poulain, vkoul, kishon
Cc: linux-arm-msm, linux-phy, dmitry.baryshkov, neil.armstrong
In-Reply-To: <20260121142827.2583-3-loic.poulain@oss.qualcomm.com>
On 1/21/26 3:28 PM, Loic Poulain wrote:
> There is a small window where the runtime suspend callback may run
> after pm_runtime_enable() and before pm_runtime_forbid(). In this
> case, a crash occurs because runtime suspend/resume dereferences
> qmp->phy pointer, which is not yet initialized:
> `if (!qmp->phy->init_count) {`
>
> This can also occur if user re-enables runtime-pm via the sysfs
> attribute before qmp phy is initialized.
>
> Use qmp->usb_init_count instead of qmp->phy->init_count to avoid
> depending on the possibly uninitialized phy pointer.
>
> Fixes: 19281571a4d5 ("phy: qcom: qmp-usb: split USB-C PHY driver")
> Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
> index 5e7fcb26744a..edfaa14db967 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
> @@ -690,7 +690,7 @@ static int __maybe_unused qmp_usbc_runtime_suspend(struct device *dev)
>
> dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode);
>
> - if (!qmp->phy->init_count) {
> + if (!qmp->usb_init_count) {
This function changed a month ago, please rebase against next
Although I believe this patch becomes unnecessary with 3 in the picture.
I suppose the case that you mention in the commit message, however
improbable, could be fixed by moving the pm call to after devm_phy_create
Although we'd then rely on devlink to make sure a consumer doesn't snatch
the reference halfway through .probe...
Konrad
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply
* [PATCH v3 0/3] dt-bindings: phy: Convert TI OMAP control and PIPE3 PHY to DT schema
From: Charan Pedumuru @ 2026-01-22 17:52 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Kishon Vijay Abraham I, Aaro Koskinen,
Andreas Kemnade, Kevin Hilman, Roger Quadros, Tony Lindgren,
Roger Quadros
Cc: linux-phy, devicetree, linux-kernel, linux-omap, Charan Pedumuru
This series converts the old text-based DeviceTree bindings for TI OMAP
Control PHY and TI PIPE3 PHY to modern JSON-schema (YAML) format.
Signed-off-by: Charan Pedumuru <charan.pedumuru@gmail.com>
---
Changes in v3:
- Change maintainer to "Roger Quadros" for both YAML files.
- dts: Split node pattern updates into a separate patch and align node
naming with standard conventions.
- ti,phy-usb3: Update node pattern to follow standard conventions.
- ti,phy-usb3: Refine the reg-names property and add constraints for
optional phandle-array properties.
- ti,phy-usb3: Redefine "syscon-pllreset" dependency on the compatible
"ti,phy-pipe3-sata" in a correct format.
- ti,control-phy-otghs: Update node pattern and adjust maxItems for reg
and reg-names.
- ti,control-phy-otghs: Fix the conditional handling for the
ti,control-phy-pcie compatible.
- Link to v2: https://lore.kernel.org/r/20260107-ti-phy-v2-0-a1ec27401fff@gmail.com
Changes in v2:
- ti,control-phy-otghs: Update commit message to reflect the latest
binding changes.
- ti,phy-usb3: Drop the obsolete "id" property from the schema.
- Both bindings: Update maintainers list, modify node pattern and improve
node descriptions for clarity.
- ti,phy-usb3: Introduce new YAML schema with properly defined optional
properties for the PIPE3 PHY.
- Link to v1: https://lore.kernel.org/r/20260103-ti-phy-v1-1-8c3f5e2cbd63@gmail.com
---
Charan Pedumuru (3):
arm: dts: ti: omap: align node patterns with established convention
dt-bindings: phy: ti,phy-usb3: convert to DT schema
dt-bindings: phy: ti,control-phy-otghs: convert to DT schema
.../bindings/phy/ti,control-phy-otghs.yaml | 99 +++++++++++++++
.../devicetree/bindings/phy/ti,phy-usb3.yaml | 135 +++++++++++++++++++++
Documentation/devicetree/bindings/phy/ti-phy.txt | 98 ---------------
arch/arm/boot/dts/ti/omap/dra7-l4.dtsi | 4 +-
arch/arm/boot/dts/ti/omap/omap4-l4.dtsi | 4 +-
arch/arm/boot/dts/ti/omap/omap5-l4.dtsi | 2 +-
6 files changed, 239 insertions(+), 103 deletions(-)
---
base-commit: cc3aa43b44bdb43dfbac0fcb51c56594a11338a8
change-id: 20251231-ti-phy-58bb9e38cfc9
Best regards,
--
Charan Pedumuru <charan.pedumuru@gmail.com>
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply
* [PATCH v3 1/3] arm: dts: ti: omap: align node patterns with established convention
From: Charan Pedumuru @ 2026-01-22 17:52 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Kishon Vijay Abraham I, Aaro Koskinen,
Andreas Kemnade, Kevin Hilman, Roger Quadros, Tony Lindgren,
Roger Quadros
Cc: linux-phy, devicetree, linux-kernel, linux-omap, Charan Pedumuru
In-Reply-To: <20260122-ti-phy-v3-0-751619729433@gmail.com>
Update OMAP DTS node patterns to match established conventions.
Signed-off-by: Charan Pedumuru <charan.pedumuru@gmail.com>
---
arch/arm/boot/dts/ti/omap/dra7-l4.dtsi | 4 ++--
arch/arm/boot/dts/ti/omap/omap4-l4.dtsi | 4 ++--
arch/arm/boot/dts/ti/omap/omap5-l4.dtsi | 2 +-
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi b/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi
index c9282f57ffa5..ed206eb84d02 100644
--- a/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi
+++ b/arch/arm/boot/dts/ti/omap/dra7-l4.dtsi
@@ -328,7 +328,7 @@ ocp2scp@0 {
ranges = <0 0 0x8000>;
reg = <0x0 0x20>;
- pcie1_phy: pciephy@4000 {
+ pcie1_phy: pcie-phy@4000 {
compatible = "ti,phy-pipe3-pcie";
reg = <0x4000 0x80>, /* phy_rx */
<0x4400 0x64>; /* phy_tx */
@@ -348,7 +348,7 @@ pcie1_phy: pciephy@4000 {
#phy-cells = <0>;
};
- pcie2_phy: pciephy@5000 {
+ pcie2_phy: pcie-phy@5000 {
compatible = "ti,phy-pipe3-pcie";
reg = <0x5000 0x80>, /* phy_rx */
<0x5400 0x64>; /* phy_tx */
diff --git a/arch/arm/boot/dts/ti/omap/omap4-l4.dtsi b/arch/arm/boot/dts/ti/omap/omap4-l4.dtsi
index 4ee53dfb71b4..d8b16cbe6c35 100644
--- a/arch/arm/boot/dts/ti/omap/omap4-l4.dtsi
+++ b/arch/arm/boot/dts/ti/omap/omap4-l4.dtsi
@@ -72,13 +72,13 @@ scm_conf: scm_conf@0 {
#size-cells = <1>;
};
- omap_control_usb2phy: control-phy@300 {
+ omap_control_usb2phy: phy@300 {
compatible = "ti,control-phy-usb2";
reg = <0x300 0x4>;
reg-names = "power";
};
- omap_control_usbotg: control-phy@33c {
+ omap_control_usbotg: phy@33c {
compatible = "ti,control-phy-otghs";
reg = <0x33c 0x4>;
reg-names = "otghs_control";
diff --git a/arch/arm/boot/dts/ti/omap/omap5-l4.dtsi b/arch/arm/boot/dts/ti/omap/omap5-l4.dtsi
index 9f6100c7c34d..5c94db589dd1 100644
--- a/arch/arm/boot/dts/ti/omap/omap5-l4.dtsi
+++ b/arch/arm/boot/dts/ti/omap/omap5-l4.dtsi
@@ -472,7 +472,7 @@ usb2_phy: usb2phy@4000 {
#phy-cells = <0>;
};
- usb3_phy: usb3phy@4400 {
+ usb3_phy: usb3-phy@4400 {
compatible = "ti,omap-usb3";
reg = <0x4400 0x80>,
<0x4800 0x64>,
--
2.52.0
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH v3 2/3] dt-bindings: phy: ti,phy-usb3: convert to DT schema
From: Charan Pedumuru @ 2026-01-22 17:52 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Kishon Vijay Abraham I, Aaro Koskinen,
Andreas Kemnade, Kevin Hilman, Roger Quadros, Tony Lindgren,
Roger Quadros
Cc: linux-phy, devicetree, linux-kernel, linux-omap, Charan Pedumuru
In-Reply-To: <20260122-ti-phy-v3-0-751619729433@gmail.com>
Convert TI PIPE3 PHY binding to DT schema.
Changes during conversion:
- Define a new pattern 'pcie-phy' to match nodes defined in DT.
- Drop obsolete "id" property from the schema.
Signed-off-by: Charan Pedumuru <charan.pedumuru@gmail.com>
---
.../devicetree/bindings/phy/ti,phy-usb3.yaml | 135 +++++++++++++++++++++
1 file changed, 135 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml b/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml
new file mode 100644
index 000000000000..605f12f0f79a
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml
@@ -0,0 +1,135 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/ti,phy-usb3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI PIPE3 PHY Module
+
+maintainers:
+ - Roger Quadros <rogerq@ti.com>
+
+description:
+ The TI PIPE3 PHY is a high-speed SerDes (Serializer/Deserializer)
+ transceiver integrated in OMAP5, DRA7xx/AM57xx, and similar SoCs.
+ It supports multiple protocols (USB3, SATA, PCIe) using the PIPE3
+ interface standard, which defines a common physical layer for
+ high-speed serial interfaces.
+
+properties:
+ $nodename:
+ pattern: "^(pcie-phy|usb3-phy|phy)@[0-9a-f]+$"
+
+ compatible:
+ enum:
+ - ti,omap-usb3
+ - ti,phy-pipe3-pcie
+ - ti,phy-pipe3-sata
+ - ti,phy-usb3
+
+ reg:
+ minItems: 2
+ maxItems: 3
+
+ reg-names:
+ minItems: 2
+ items:
+ - const: phy_rx
+ - const: phy_tx
+ - const: pll_ctrl
+
+ "#phy-cells":
+ const: 0
+
+ clocks:
+ minItems: 2
+ maxItems: 7
+
+ clock-names:
+ minItems: 2
+ maxItems: 7
+ items:
+ enum: [wkupclk, sysclk, refclk, dpll_ref,
+ dpll_ref_m2, phy-div, div-clk]
+
+ syscon-phy-power:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ items:
+ - description: Phandle to the system control module
+ - description: Register offset controlling PHY power
+
+ syscon-pllreset:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ items:
+ - description: Phandle to the system control module
+ - description: Register offset of CTRL_CORE_SMA_SW_0
+
+ syscon-pcs:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ items:
+ - description: Phandle to the system control module
+ - description: Register offset for PCS delay programming
+
+ ctrl-module:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle of control module for PHY power on.
+ deprecated: true
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: ti,phy-pipe3-sata
+ then:
+ properties:
+ syscon-pllreset: true
+ else:
+ properties:
+ syscon-pllreset: false
+
+required:
+ - reg
+ - compatible
+ - reg-names
+ - "#phy-cells"
+ - clocks
+ - clock-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ /* TI PIPE3 USB3 PHY */
+ usb3-phy@4a084400 {
+ compatible = "ti,phy-usb3";
+ reg = <0x4a084400 0x80>,
+ <0x4a084800 0x64>,
+ <0x4a084c00 0x40>;
+ reg-names = "phy_rx", "phy_tx", "pll_ctrl";
+ #phy-cells = <0>;
+ clocks = <&usb_phy_cm_clk32k>,
+ <&sys_clkin>,
+ <&usb_otg_ss_refclk960m>;
+ clock-names = "wkupclk", "sysclk", "refclk";
+ ctrl-module = <&omap_control_usb>;
+ };
+
+ - |
+ /* TI PIPE3 SATA PHY */
+ phy@4a096000 {
+ compatible = "ti,phy-pipe3-sata";
+ reg = <0x4A096000 0x80>, /* phy_rx */
+ <0x4A096400 0x64>, /* phy_tx */
+ <0x4A096800 0x40>; /* pll_ctrl */
+ reg-names = "phy_rx", "phy_tx", "pll_ctrl";
+ clocks = <&sys_clkin1>, <&sata_ref_clk>;
+ clock-names = "sysclk", "refclk";
+ syscon-pllreset = <&scm_conf 0x3fc>;
+ #phy-cells = <0>;
+ };
+...
--
2.52.0
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH v3 3/3] dt-bindings: phy: ti,control-phy-otghs: convert to DT schema
From: Charan Pedumuru @ 2026-01-22 17:52 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Kishon Vijay Abraham I, Aaro Koskinen,
Andreas Kemnade, Kevin Hilman, Roger Quadros, Tony Lindgren,
Roger Quadros
Cc: linux-phy, devicetree, linux-kernel, linux-omap, Charan Pedumuru
In-Reply-To: <20260122-ti-phy-v3-0-751619729433@gmail.com>
Convert TI OMAP Control PHY binding to DT schema.
Signed-off-by: Charan Pedumuru <charan.pedumuru@gmail.com>
---
.../bindings/phy/ti,control-phy-otghs.yaml | 99 ++++++++++++++++++++++
Documentation/devicetree/bindings/phy/ti-phy.txt | 98 ---------------------
2 files changed, 99 insertions(+), 98 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/ti,control-phy-otghs.yaml b/Documentation/devicetree/bindings/phy/ti,control-phy-otghs.yaml
new file mode 100644
index 000000000000..4ecb1611ee65
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/ti,control-phy-otghs.yaml
@@ -0,0 +1,99 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/ti,control-phy-otghs.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI OMAP Control PHY Module
+
+maintainers:
+ - Roger Quadros <rogerq@ti.com>
+
+description:
+ The TI OMAP Control PHY module is a hardware block within the system
+ control module (SCM) of Texas Instruments OMAP SoCs. It provides
+ centralized control over power, configuration, and auxiliary features
+ for multiple on-chip PHYs. This module is essential for proper PHY
+ operation in power-constrained embedded systems.
+
+properties:
+ $nodename:
+ pattern: "^phy@[0-9a-f]+$"
+
+ compatible:
+ enum:
+ - ti,control-phy-otghs
+ - ti,control-phy-pcie
+ - ti,control-phy-pipe3
+ - ti,control-phy-usb2
+ - ti,control-phy-usb2-am437
+ - ti,control-phy-usb2-dra7
+
+ reg:
+ minItems: 1
+ maxItems: 3
+
+ reg-names:
+ minItems: 1
+ maxItems: 3
+ items:
+ enum: [otghs_control, power, pcie_pcs, control_sma]
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - ti,control-phy-otghs
+ then:
+ properties:
+ reg-names:
+ const: otghs_control
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - ti,control-phy-pcie
+ then:
+ properties:
+ reg:
+ minItems: 3
+
+ reg-names:
+ items:
+ - const: power
+ - const: pcie_pcs
+ - const: control_sma
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - ti,control-phy-usb2
+ - ti,control-phy-usb2-dra7
+ - ti,control-phy-usb2-am437
+ - ti,control-phy-pipe3
+ then:
+ properties:
+ reg-names:
+ const: power
+
+required:
+ - reg
+ - compatible
+ - reg-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ phy@4a00233c {
+ compatible = "ti,control-phy-otghs";
+ reg = <0x4a00233c 0x4>;
+ reg-names = "otghs_control";
+ };
+...
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt b/Documentation/devicetree/bindings/phy/ti-phy.txt
deleted file mode 100644
index 7c7936b89f2c..000000000000
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ /dev/null
@@ -1,98 +0,0 @@
-TI PHY: DT DOCUMENTATION FOR PHYs in TI PLATFORMs
-
-OMAP CONTROL PHY
-
-Required properties:
- - compatible: Should be one of
- "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
- "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
- e.g. USB2_PHY on OMAP5.
- "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
- e.g. USB3 PHY and SATA PHY on OMAP5.
- "ti,control-phy-pcie" - for pcie to support external clock for pcie and to
- set PCS delay value.
- e.g. PCIE PHY in DRA7x
- "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on
- DRA7 platform.
- "ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on
- AM437 platform.
- - reg : register ranges as listed in the reg-names property
- - reg-names: "otghs_control" for control-phy-otghs
- "power", "pcie_pcs" and "control_sma" for control-phy-pcie
- "power" for all other types
-
-omap_control_usb: omap-control-usb@4a002300 {
- compatible = "ti,control-phy-otghs";
- reg = <0x4a00233c 0x4>;
- reg-names = "otghs_control";
-};
-
-TI PIPE3 PHY
-
-Required properties:
- - compatible: Should be "ti,phy-usb3", "ti,phy-pipe3-sata" or
- "ti,phy-pipe3-pcie. "ti,omap-usb3" is deprecated.
- - reg : Address and length of the register set for the device.
- - reg-names: The names of the register addresses corresponding to the registers
- filled in "reg".
- - #phy-cells: determine the number of cells that should be given in the
- phandle while referencing this phy.
- - clocks: a list of phandles and clock-specifier pairs, one for each entry in
- clock-names.
- - clock-names: should include:
- * "wkupclk" - wakeup clock.
- * "sysclk" - system clock.
- * "refclk" - reference clock.
- * "dpll_ref" - external dpll ref clk
- * "dpll_ref_m2" - external dpll ref clk
- * "phy-div" - divider for apll
- * "div-clk" - apll clock
-
-Optional properties:
- - id: If there are multiple instance of the same type, in order to
- differentiate between each instance "id" can be used (e.g., multi-lane PCIe
- PHY). If "id" is not provided, it is set to default value of '1'.
- - syscon-pllreset: Handle to system control region that contains the
- CTRL_CORE_SMA_SW_0 register and register offset to the CTRL_CORE_SMA_SW_0
- register that contains the SATA_PLL_SOFT_RESET bit. Only valid for sata_phy.
- - syscon-pcs : phandle/offset pair. Phandle to the system control module and the
- register offset to write the PCS delay value.
-
-Deprecated properties:
- - ctrl-module : phandle of the control module used by PHY driver to power on
- the PHY.
-
-Recommended properties:
- - syscon-phy-power : phandle/offset pair. Phandle to the system control
- module and the register offset to power on/off the PHY.
-
-This is usually a subnode of ocp2scp to which it is connected.
-
-usb3phy@4a084400 {
- compatible = "ti,phy-usb3";
- reg = <0x4a084400 0x80>,
- <0x4a084800 0x64>,
- <0x4a084c00 0x40>;
- reg-names = "phy_rx", "phy_tx", "pll_ctrl";
- ctrl-module = <&omap_control_usb>;
- #phy-cells = <0>;
- clocks = <&usb_phy_cm_clk32k>,
- <&sys_clkin>,
- <&usb_otg_ss_refclk960m>;
- clock-names = "wkupclk",
- "sysclk",
- "refclk";
-};
-
-sata_phy: phy@4a096000 {
- compatible = "ti,phy-pipe3-sata";
- reg = <0x4A096000 0x80>, /* phy_rx */
- <0x4A096400 0x64>, /* phy_tx */
- <0x4A096800 0x40>; /* pll_ctrl */
- reg-names = "phy_rx", "phy_tx", "pll_ctrl";
- ctrl-module = <&omap_control_sata>;
- clocks = <&sys_clkin1>, <&sata_ref_clk>;
- clock-names = "sysclk", "refclk";
- syscon-pllreset = <&scm_conf 0x3fc>;
- #phy-cells = <0>;
-};
--
2.52.0
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* Re: [PATCH next] phy: google: fix build dependency for Google Tensor USB PHY
From: Roy Luo @ 2026-01-22 19:00 UTC (permalink / raw)
To: André Draszik
Cc: Vinod Koul, Neil Armstrong, Peter Griffin, Tudor Ambarus,
Joy Chakraborty, Naveen Kumar, linux-phy, linux-kernel,
linux-arm-kernel, linux-samsung-soc, kernel test robot
In-Reply-To: <7c78f9da40022e7bbf850ae8989c617bdc30cc95.camel@linaro.org>
On Thu, Jan 22, 2026 at 2:39 AM André Draszik <andre.draszik@linaro.org> wrote:
>
> Hi Roy,
>
> On Wed, 2026-01-21 at 22:21 +0000, Roy Luo wrote:
> > The Google Tensor USB PHY driver uses the Type-C switch framework to
> > handle orientation changes. However, the Kconfig did not specify a
> > dependency on the TYPEC framework, leading to undefined reference
> > errors when building for architectures or configurations where
> > CONFIG_TYPEC is disabled or configured as a module.
> >
> > Add 'depends on TYPEC' to the PHY_GOOGLE_USB entry to ensure all
> > required symbols are available during linking.
> >
> > Fixes: cbce66669c82 ("phy: Add Google Tensor SoC USB PHY driver")
> > Reported-by: kernel test robot <lkp@intel.com>
> > Closes: https://lore.kernel.org/oe-kbuild-all/202601210825.ELrpQeED-lkp@intel.com/
> > Signed-off-by: Roy Luo <royluo@google.com>
> > ---
> > drivers/phy/Kconfig | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> > index 142e7b0ef2efb9209781800ee47b820a91b115ae..5531ff31d8156cb164c32e3e52d4a57b26a62d8d 100644
> > --- a/drivers/phy/Kconfig
> > +++ b/drivers/phy/Kconfig
> > @@ -49,6 +49,7 @@ config GENERIC_PHY_MIPI_DPHY
> >
> > config PHY_GOOGLE_USB
> > tristate "Google Tensor SoC USB PHY driver"
> > + depends on TYPEC
>
> Can you make this
>
> depends on TYPEC || COMPILE_TEST
>
> to allow some better test coverage?
>
> Cheers,
> Andre
Hi Andre,
Whether to add COMPILE_TEST for build coverage was discussed in
another thread [1]. My takeaway from that discussion is that
COMPILE_TEST is intended to substitute for ARCH_XXX in build
testing and should not be used without it. Once ARCH_GOOGLE is
present, we can add "depends on (ARCH_GOOGLE || COMPILTE_TEST)".
[1] https://lore.kernel.org/all/CA+zupgwgfKwPYqj8G2tNf4pEXNEWA+vL2WYJPhJ16xExgko7Dw@mail.gmail.com/
Regards,
Roy
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply
* Re: [PATCH v3 2/3] dt-bindings: phy: ti,phy-usb3: convert to DT schema
From: Rob Herring @ 2026-01-22 23:33 UTC (permalink / raw)
To: Charan Pedumuru
Cc: Vinod Koul, Neil Armstrong, Krzysztof Kozlowski, Conor Dooley,
Kishon Vijay Abraham I, Aaro Koskinen, Andreas Kemnade,
Kevin Hilman, Roger Quadros, Tony Lindgren, Roger Quadros,
linux-phy, devicetree, linux-kernel, linux-omap
In-Reply-To: <20260122-ti-phy-v3-2-751619729433@gmail.com>
On Thu, Jan 22, 2026 at 05:52:58PM +0000, Charan Pedumuru wrote:
> Convert TI PIPE3 PHY binding to DT schema.
> Changes during conversion:
> - Define a new pattern 'pcie-phy' to match nodes defined in DT.
> - Drop obsolete "id" property from the schema.
>
> Signed-off-by: Charan Pedumuru <charan.pedumuru@gmail.com>
> ---
> .../devicetree/bindings/phy/ti,phy-usb3.yaml | 135 +++++++++++++++++++++
> 1 file changed, 135 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml b/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml
> new file mode 100644
> index 000000000000..605f12f0f79a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/ti,phy-usb3.yaml
> @@ -0,0 +1,135 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/ti,phy-usb3.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: TI PIPE3 PHY Module
> +
> +maintainers:
> + - Roger Quadros <rogerq@ti.com>
> +
> +description:
> + The TI PIPE3 PHY is a high-speed SerDes (Serializer/Deserializer)
> + transceiver integrated in OMAP5, DRA7xx/AM57xx, and similar SoCs.
> + It supports multiple protocols (USB3, SATA, PCIe) using the PIPE3
> + interface standard, which defines a common physical layer for
> + high-speed serial interfaces.
> +
> +properties:
> + $nodename:
> + pattern: "^(pcie-phy|usb3-phy|phy)@[0-9a-f]+$"
> +
> + compatible:
> + enum:
> + - ti,omap-usb3
> + - ti,phy-pipe3-pcie
> + - ti,phy-pipe3-sata
> + - ti,phy-usb3
> +
> + reg:
> + minItems: 2
> + maxItems: 3
> +
> + reg-names:
> + minItems: 2
> + items:
> + - const: phy_rx
> + - const: phy_tx
> + - const: pll_ctrl
> +
> + "#phy-cells":
> + const: 0
> +
> + clocks:
> + minItems: 2
> + maxItems: 7
> +
> + clock-names:
> + minItems: 2
> + maxItems: 7
> + items:
> + enum: [wkupclk, sysclk, refclk, dpll_ref,
> + dpll_ref_m2, phy-div, div-clk]
> +
> + syscon-phy-power:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + items:
> + items:
> + - description: Phandle to the system control module
> + - description: Register offset controlling PHY power
This allows N entries of 2 cells each. You need either:
items:
- items:
- description: ...
- description: ...
(the hyphen is important!)
Or:
maxItems: 1
items:
items:
- description: ...
- description: ...
> +
> + syscon-pllreset:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + items:
> + items:
> + - description: Phandle to the system control module
> + - description: Register offset of CTRL_CORE_SMA_SW_0
> +
> + syscon-pcs:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + items:
> + items:
> + - description: Phandle to the system control module
> + - description: Register offset for PCS delay programming
> +
> + ctrl-module:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + Phandle of control module for PHY power on.
> + deprecated: true
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: ti,phy-pipe3-sata
> + then:
> + properties:
> + syscon-pllreset: true
> + else:
> + properties:
> + syscon-pllreset: false
> +
> +required:
> + - reg
> + - compatible
> + - reg-names
> + - "#phy-cells"
> + - clocks
> + - clock-names
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + /* TI PIPE3 USB3 PHY */
> + usb3-phy@4a084400 {
> + compatible = "ti,phy-usb3";
> + reg = <0x4a084400 0x80>,
> + <0x4a084800 0x64>,
> + <0x4a084c00 0x40>;
> + reg-names = "phy_rx", "phy_tx", "pll_ctrl";
> + #phy-cells = <0>;
> + clocks = <&usb_phy_cm_clk32k>,
> + <&sys_clkin>,
> + <&usb_otg_ss_refclk960m>;
> + clock-names = "wkupclk", "sysclk", "refclk";
> + ctrl-module = <&omap_control_usb>;
> + };
> +
> + - |
> + /* TI PIPE3 SATA PHY */
> + phy@4a096000 {
> + compatible = "ti,phy-pipe3-sata";
> + reg = <0x4A096000 0x80>, /* phy_rx */
> + <0x4A096400 0x64>, /* phy_tx */
> + <0x4A096800 0x40>; /* pll_ctrl */
Use lowercase hex.
> + reg-names = "phy_rx", "phy_tx", "pll_ctrl";
> + clocks = <&sys_clkin1>, <&sata_ref_clk>;
> + clock-names = "sysclk", "refclk";
> + syscon-pllreset = <&scm_conf 0x3fc>;
> + #phy-cells = <0>;
> + };
> +...
>
> --
> 2.52.0
>
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply
* Re: [PATCH v3 3/3] dt-bindings: phy: ti,control-phy-otghs: convert to DT schema
From: Rob Herring (Arm) @ 2026-01-22 23:34 UTC (permalink / raw)
To: Charan Pedumuru
Cc: Kishon Vijay Abraham I, linux-kernel, Kevin Hilman,
Andreas Kemnade, Aaro Koskinen, Roger Quadros, Tony Lindgren,
Krzysztof Kozlowski, linux-phy, devicetree, Conor Dooley,
linux-omap, Vinod Koul, Neil Armstrong, Roger Quadros
In-Reply-To: <20260122-ti-phy-v3-3-751619729433@gmail.com>
On Thu, 22 Jan 2026 17:52:59 +0000, Charan Pedumuru wrote:
> Convert TI OMAP Control PHY binding to DT schema.
>
> Signed-off-by: Charan Pedumuru <charan.pedumuru@gmail.com>
> ---
> .../bindings/phy/ti,control-phy-otghs.yaml | 99 ++++++++++++++++++++++
> Documentation/devicetree/bindings/phy/ti-phy.txt | 98 ---------------------
> 2 files changed, 99 insertions(+), 98 deletions(-)
>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply
* [PATCH v8 0/2] Add driver support for Eswin EIC7700 SoC SATA PHY
From: Yulin Lu @ 2026-01-23 2:48 UTC (permalink / raw)
To: vkoul, neil.armstrong, robh, krzk+dt, conor+dt, p.zabel,
linux-phy, devicetree, linux-kernel
Cc: ningyu, linmin, fenglin, Yulin Lu
Updates:
v8 -> v7:
- eswin,eic7700-sata-phy.yaml
- Add "eswin,tx-amplitude-tuning" and "eswin,tx-preemph-tuning"
properties, because these parameters may vary across different
circuit boards.
- Delete reviewed-by tag of Krzysztof Kozlowski, because the tuning
properties are introduced.
- phy-eic7700-sata.c
- Try to get SATA PHY transmitter amplitude and pre-emphasis signal
eye diagram tuning parameters from dts instead of hardcoded values
in the code. Because, these parameters may vary across different
circuit boards. Define default tuning parameters and use it when
these properties are not declared in dts.
- Add a comment to explain the reason for mapping I/O resources with
platform_get_resource and devm_ioremap instead of using the
devm_platform_ioremap_resource API.
- Link to v7: https://lore.kernel.org/lkml/20260106062944.1529-1-luyulin@eswincomputing.com/
v7 -> v6:
- phy-eic7700-sata.c
- Rename PHY_READY_TIMEOUT to PLL_LOCK_TIMEOUT_US with value 1000.
- Add macro PLL_LOCK_SLEEP_US set to 10.
- Add "goto disable_clk" in the eic7700_sata_phy_init function.
- Modify Copyright year from 2024 to 2026.
- Link to v6: https://lore.kernel.org/lkml/20251201060737.868-1-luyulin@eswincomputing.com/
v6 -> v5:
- eswin,eic7700-ahci.yaml
- Delete this file and it has already been applied in reply[1].
- eswin,eic7700-sata-phy.yaml
- Add clock and reset related properties.
- phy-eic7700-sata.c
- Map the io resource with platform_get_resource and devm_ioremap
instead of devm_platform_ioremap_resource API. Because the address
region of sata-phy falls into the region of hsp clock&reset which
has been got by hsp clock&reset driver.
- Use regmap_read_poll_timeout in wait_for_phy_ready to replace the
while loop check.
- Use devm_regmap_init_mmio and regmap_write to replace writel.
- Adapt to the clock and reset driver framework, replacing the
original readl and writel.
Because we are implementing the HSP layer clock and reset drivers,
the corresponding clock and reset registers can be registered into
the driver framework. And I have tested on the Sifive HiFive
Premier P550 board.
- Link to v5: https://lore.kernel.org/lkml/20250930083754.15-1-luyulin@eswincomputing.com/
v5 -> v4:
- eswin,eic7700-ahci.yaml
- Add "dt-bindings: ata:" prefix to the subject.
- Wrap at 80 characters in the YAML description field.
- Link to v4: https://lore.kernel.org/lkml/20250915125902.375-1-luyulin@eswincomputing.com/
v4 -> v3:
- eswin,eic7700-ahci.yaml
- Fix grammatical errors in patch subject and commit message
- Add an explanation in the commit message of patch 1 for retaining
the "ports-implemented" field, which Rob Herring suggested to
remove in the review comments on v2.
Link to Rob Herring's review:
https://lore.kernel.org/lkml/CAL_JsqKFotNLZZXwiy7S6K8qXLdGRAnsa-1zvZRDQBE39Gf5kg@mail.gmail.com/
Link to my question and Niklas Cassel's reply:
https://lore.kernel.org/lkml/aLBUC116MdJqDGIJ@flawful.org/
In this reply, Niklas Cassel mentioned his view:
If the ports-implemented register gets reset from
ahci_platform_assert_rsts(), then it seems acceptable to
retain the ports-implemented property in the device tree.
This aligns with our design.
Link to my reply:
https://lore.kernel.org/lkml/4ab70c6a.8be.198f47da494.Coremail.luyulin@eswincomputing.com/
Link to Niklas Cassel's question and my further explanation:
https://lore.kernel.org/lkml/aLlYkZWBaI5Yz6fo@ryzen/
https://lore.kernel.org/lkml/7206383a.d98.19918c22570.Coremail.luyulin@eswincomputing.com/
- eswin,eic7700-sata-phy.yaml
- Fix grammatical errors in patch subject and commit message
- Adjust the position of reg in the properties and required arrays
- Add reviewed-by tag of Krzysztof Kozlowski
- phy-eic7700-sata.c
- Correct the loop condition in wait_for_phy_ready() to use the
current jiffies instead of the fixed start time.
- Change the return value from -EFAULT to -ETIMEDOUT to correctly
indicate a timeout condition.
- Remove redundant clock disable handling in probe error path, as
SATA_SYS_CLK_EN is managed in phy_init() and phy_exit().
- Use dev_err_probe return in probe.
- Reorder local variables to follow reverse Xmas tree order.
- Wrap each line in the extended comments to 80 columns before
splitting lines.
- Adjust the position of `#include <linux/io.h>` for proper ordering.
- Link to v3: https://lore.kernel.org/lkml/20250904063427.1954-1-luyulin@eswincomputing.com/
v2 -> v3:
- Use full name in "From" and "Signed-off-by" fields information
- eswin,eic7700-ahci.yaml
- Remove the introduction to the reg, interrupts, phys, and
phy-names fields.
- Modify the usage of the clocks field in the examples.
- Correct the order of dt properties.
- phy-eic7700-sata.c
- Register operations use the GENMASK macro and FIELD_PREP instead
of the original bit offset method, and add
"#include <linux/bitfield.h>".
- Modify some macro definition names.
- Remove the redundant initialization assignments for "ret" and
"val".
- Delete ".suppress_bind_attrs = true".
- Modify the driver name.
- Add "#include <linux/io.h>" to fix the robot test issue.
- Link to v2: https://lore.kernel.org/lkml/20250819134722.220-1-luyulin@eswincomputing.com/
v2 -> v1:
- Delete the original controller driver and use ahci_dwc.c instead.
- Add eswin,eic7700-ahci.yaml
- Correct the descriptions of reset, interrupt and other hardware
resources for the sata controller on EIC7700 SoC.
- The clocks for both sata controller and sata PHY are controlled
via a register bit in the HSP bus and are not registered in the
clock tree. Clock are managed within the PHY driver, therefore it
is not described in this document.
- Add $ref: snps,dwc-ahci-common.yaml#.
- Add eswin,eic7700-sata-phy.yaml
- Add this file to include the description of the PHY on EIC7700 SoC.
- Add an eswin directory under the PHY driver path, and include the
SATA PHY driver code for EIC7700 SoC.
- Link to v1: https://lore.kernel.org/all/20250515085114.1692-1-hehuan1@eswincomputing.com/
Yulin Lu (2):
dt-bindings: phy: eswin: Document the EIC7700 SoC SATA PHY
phy: eswin: Create eswin directory and add EIC7700 SATA PHY driver
.../bindings/phy/eswin,eic7700-sata-phy.yaml | 96 ++++++
drivers/phy/Kconfig | 1 +
drivers/phy/Makefile | 1 +
drivers/phy/eswin/Kconfig | 14 +
drivers/phy/eswin/Makefile | 2 +
drivers/phy/eswin/phy-eic7700-sata.c | 273 ++++++++++++++++++
6 files changed, 387 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/eswin,eic7700-sata-phy.yaml
create mode 100644 drivers/phy/eswin/Kconfig
create mode 100644 drivers/phy/eswin/Makefile
create mode 100644 drivers/phy/eswin/phy-eic7700-sata.c
--
2.25.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply
* [PATCH v8 1/2] dt-bindings: phy: eswin: Document the EIC7700 SoC SATA PHY
From: Yulin Lu @ 2026-01-23 2:49 UTC (permalink / raw)
To: vkoul, neil.armstrong, robh, krzk+dt, conor+dt, p.zabel,
linux-phy, devicetree, linux-kernel
Cc: ningyu, linmin, fenglin, Yulin Lu
In-Reply-To: <20260123024823.1612-1-luyulin@eswincomputing.com>
Document the SATA PHY on the EIC7700 SoC platform,
describing its usage.
Signed-off-by: Yulin Lu <luyulin@eswincomputing.com>
---
.../bindings/phy/eswin,eic7700-sata-phy.yaml | 96 +++++++++++++++++++
1 file changed, 96 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/eswin,eic7700-sata-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/eswin,eic7700-sata-phy.yaml b/Documentation/devicetree/bindings/phy/eswin,eic7700-sata-phy.yaml
new file mode 100644
index 000000000000..4bb2d7a53761
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/eswin,eic7700-sata-phy.yaml
@@ -0,0 +1,96 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/eswin,eic7700-sata-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Eswin EIC7700 SoC SATA PHY
+
+maintainers:
+ - Yulin Lu <luyulin@eswincomputing.com>
+ - Huan He <hehuan1@eswincomputing.com>
+
+properties:
+ compatible:
+ const: eswin,eic7700-sata-phy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: phy
+
+ resets:
+ maxItems: 2
+
+ reset-names:
+ items:
+ - const: port
+ - const: phy
+
+ eswin,tx-amplitude-tuning:
+ description: This adjusts the transmitter amplitude signal, and its value
+ is derived from eye diagram tuning. The three values correspond to Gen1,
+ Gen2, and Gen3 parameters respectively.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ items:
+ - description: Gen1 parameter.
+ minimum: 0
+ maximum: 0x7f
+ default: 0
+ - description: Gen2 parameter.
+ minimum: 0
+ maximum: 0x7f
+ default: 0
+ - description: Gen3 parameter.
+ minimum: 0
+ maximum: 0x7f
+ default: 0
+
+ eswin,tx-preemph-tuning:
+ description: This adjusts the transmitter de-emphasis signal, and its value
+ is derived from eye diagram tuning. The three values correspond to Gen1,
+ Gen2, and Gen3 parameters respectively.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ items:
+ - description: Gen1 parameter.
+ minimum: 0
+ maximum: 0x3f
+ default: 0
+ - description: Gen2 parameter.
+ minimum: 0
+ maximum: 0x3f
+ default: 0
+ - description: Gen3 parameter.
+ minimum: 0
+ maximum: 0x3f
+ default: 0
+
+ "#phy-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ sata-phy@50440300 {
+ compatible = "eswin,eic7700-sata-phy";
+ reg = <0x50440300 0x40>;
+ clocks = <&hspcrg 17>;
+ clock-names = "phy";
+ resets = <&hspcrg 0>, <&hspcrg 1>;
+ reset-names = "port", "phy";
+ #phy-cells = <0>;
+ };
--
2.25.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH v8 2/2] phy: eswin: Create eswin directory and add EIC7700 SATA PHY driver
From: Yulin Lu @ 2026-01-23 3:09 UTC (permalink / raw)
To: vkoul, neil.armstrong, robh, krzk+dt, conor+dt, p.zabel,
linux-phy, devicetree, linux-kernel
Cc: ningyu, linmin, fenglin, Yulin Lu
In-Reply-To: <20260123024823.1612-1-luyulin@eswincomputing.com>
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset=y, Size: 10758 bytes --]
Create the eswin phy driver directory and add support for the
SATA PHY driver on the EIC7700 SoC platform.
Signed-off-by: Yulin Lu <luyulin@eswincomputing.com>
---
drivers/phy/Kconfig | 1 +
drivers/phy/Makefile | 1 +
drivers/phy/eswin/Kconfig | 14 ++
drivers/phy/eswin/Makefile | 2 +
drivers/phy/eswin/phy-eic7700-sata.c | 273 +++++++++++++++++++++++++++
5 files changed, 291 insertions(+)
create mode 100644 drivers/phy/eswin/Kconfig
create mode 100644 drivers/phy/eswin/Makefile
create mode 100644 drivers/phy/eswin/phy-eic7700-sata.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 678dd0452f0a..6d50704917f0 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -105,6 +105,7 @@ source "drivers/phy/allwinner/Kconfig"
source "drivers/phy/amlogic/Kconfig"
source "drivers/phy/broadcom/Kconfig"
source "drivers/phy/cadence/Kconfig"
+source "drivers/phy/eswin/Kconfig"
source "drivers/phy/freescale/Kconfig"
source "drivers/phy/hisilicon/Kconfig"
source "drivers/phy/ingenic/Kconfig"
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index bfb27fb5a494..482a143d3417 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -17,6 +17,7 @@ obj-y += allwinner/ \
amlogic/ \
broadcom/ \
cadence/ \
+ eswin/ \
freescale/ \
hisilicon/ \
ingenic/ \
diff --git a/drivers/phy/eswin/Kconfig b/drivers/phy/eswin/Kconfig
new file mode 100644
index 000000000000..37447cc3af63
--- /dev/null
+++ b/drivers/phy/eswin/Kconfig
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Phy drivers for ESWIN platforms
+#
+config PHY_EIC7700_SATA
+ tristate "eic7700 Sata SerDes/PHY driver"
+ depends on ARCH_ESWIN || COMPILE_TEST
+ depends on HAS_IOMEM
+ select GENERIC_PHY
+ help
+ Enable this to support SerDes/Phy found on ESWIN's
+ EIC7700 SoC.This Phy supports SATA 1.5 Gb/s,
+ SATA 3.0 Gb/s, SATA 6.0 Gb/s speeds.
+ It supports one SATA host port to accept one SATA device.
diff --git a/drivers/phy/eswin/Makefile b/drivers/phy/eswin/Makefile
new file mode 100644
index 000000000000..db08c66be812
--- /dev/null
+++ b/drivers/phy/eswin/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_PHY_EIC7700_SATA) += phy-eic7700-sata.o
diff --git a/drivers/phy/eswin/phy-eic7700-sata.c b/drivers/phy/eswin/phy-eic7700-sata.c
new file mode 100644
index 000000000000..4de8dfe18182
--- /dev/null
+++ b/drivers/phy/eswin/phy-eic7700-sata.c
@@ -0,0 +1,273 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ESWIN SATA PHY driver
+ *
+ * Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd..
+ * All rights reserved.
+ *
+ * Authors: Yulin Lu <luyulin@eswincomputing.com>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+
+#define SATA_AXI_LP_CTRL 0x08
+#define SATA_MPLL_CTRL 0x20
+#define SATA_P0_PHY_STAT 0x24
+#define SATA_PHY_CTRL0 0x28
+#define SATA_PHY_CTRL1 0x2c
+#define SATA_REF_CTRL 0x34
+#define SATA_REF_CTRL1 0x38
+#define SATA_LOS_IDEN 0x3c
+
+#define SATA_CLK_RST_SOURCE_PHY BIT(0)
+#define SATA_P0_PHY_TX_AMPLITUDE_GEN1_MASK GENMASK(6, 0)
+#define SATA_P0_PHY_TX_AMPLITUDE_GEN1_DEFAULT 0x42
+#define SATA_P0_PHY_TX_AMPLITUDE_GEN2_MASK GENMASK(14, 8)
+#define SATA_P0_PHY_TX_AMPLITUDE_GEN2_DEFAULT 0x46
+#define SATA_P0_PHY_TX_AMPLITUDE_GEN3_MASK GENMASK(22, 16)
+#define SATA_P0_PHY_TX_AMPLITUDE_GEN3_DEFAULT 0x73
+#define SATA_P0_PHY_TX_PREEMPH_GEN1_MASK GENMASK(5, 0)
+#define SATA_P0_PHY_TX_PREEMPH_GEN1_DEFAULT 0x5
+#define SATA_P0_PHY_TX_PREEMPH_GEN2_MASK GENMASK(13, 8)
+#define SATA_P0_PHY_TX_PREEMPH_GEN2_DEFAULT 0x5
+#define SATA_P0_PHY_TX_PREEMPH_GEN3_MASK GENMASK(21, 16)
+#define SATA_P0_PHY_TX_PREEMPH_GEN3_DEFAULT 0x23
+#define SATA_LOS_LEVEL_MASK GENMASK(4, 0)
+#define SATA_LOS_BIAS_MASK GENMASK(18, 16)
+#define SATA_M_CSYSREQ BIT(0)
+#define SATA_S_CSYSREQ BIT(16)
+#define SATA_REF_REPEATCLK_EN BIT(0)
+#define SATA_REF_USE_PAD BIT(20)
+#define SATA_MPLL_MULTIPLIER_MASK GENMASK(22, 16)
+#define SATA_P0_PHY_READY BIT(0)
+
+#define PLL_LOCK_SLEEP_US 10
+#define PLL_LOCK_TIMEOUT_US 1000
+
+struct eic7700_sata_phy {
+ u32 tx_amplitude_tuning_val[3];
+ u32 tx_preemph_tuning_val[3];
+ struct reset_control *rst;
+ struct regmap *regmap;
+ struct clk *clk;
+ struct phy *phy;
+};
+
+static const struct regmap_config eic7700_sata_phy_regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = SATA_LOS_IDEN,
+};
+
+static int wait_for_phy_ready(struct regmap *regmap, u32 reg, u32 checkbit,
+ u32 status)
+{
+ u32 val;
+ int ret;
+
+ ret = regmap_read_poll_timeout(regmap, reg, val,
+ (val & checkbit) == status,
+ PLL_LOCK_SLEEP_US, PLL_LOCK_TIMEOUT_US);
+
+ return ret;
+}
+
+static int eic7700_sata_phy_init(struct phy *phy)
+{
+ struct eic7700_sata_phy *sata_phy = phy_get_drvdata(phy);
+ u32 val;
+ int ret;
+
+ ret = clk_prepare_enable(sata_phy->clk);
+ if (ret)
+ return ret;
+
+ regmap_write(sata_phy->regmap, SATA_REF_CTRL1, SATA_CLK_RST_SOURCE_PHY);
+
+ val = FIELD_PREP(SATA_P0_PHY_TX_AMPLITUDE_GEN1_MASK,
+ sata_phy->tx_amplitude_tuning_val[0]) |
+ FIELD_PREP(SATA_P0_PHY_TX_AMPLITUDE_GEN2_MASK,
+ sata_phy->tx_amplitude_tuning_val[1]) |
+ FIELD_PREP(SATA_P0_PHY_TX_AMPLITUDE_GEN3_MASK,
+ sata_phy->tx_amplitude_tuning_val[2]);
+ regmap_write(sata_phy->regmap, SATA_PHY_CTRL0, val);
+
+ val = FIELD_PREP(SATA_P0_PHY_TX_PREEMPH_GEN1_MASK,
+ sata_phy->tx_preemph_tuning_val[0]) |
+ FIELD_PREP(SATA_P0_PHY_TX_PREEMPH_GEN2_MASK,
+ sata_phy->tx_preemph_tuning_val[1]) |
+ FIELD_PREP(SATA_P0_PHY_TX_PREEMPH_GEN3_MASK,
+ sata_phy->tx_preemph_tuning_val[2]);
+ regmap_write(sata_phy->regmap, SATA_PHY_CTRL1, val);
+
+ val = FIELD_PREP(SATA_LOS_LEVEL_MASK, 0x9) |
+ FIELD_PREP(SATA_LOS_BIAS_MASK, 0x2);
+ regmap_write(sata_phy->regmap, SATA_LOS_IDEN, val);
+
+ val = SATA_M_CSYSREQ | SATA_S_CSYSREQ;
+ regmap_write(sata_phy->regmap, SATA_AXI_LP_CTRL, val);
+
+ val = SATA_REF_REPEATCLK_EN | SATA_REF_USE_PAD;
+ regmap_write(sata_phy->regmap, SATA_REF_CTRL, val);
+
+ val = FIELD_PREP(SATA_MPLL_MULTIPLIER_MASK, 0x3c);
+ regmap_write(sata_phy->regmap, SATA_MPLL_CTRL, val);
+
+ usleep_range(15, 20);
+
+ ret = reset_control_deassert(sata_phy->rst);
+ if (ret)
+ goto disable_clk;
+
+ ret = wait_for_phy_ready(sata_phy->regmap, SATA_P0_PHY_STAT,
+ SATA_P0_PHY_READY, 1);
+ if (ret < 0) {
+ dev_err(&sata_phy->phy->dev, "PHY READY check failed\n");
+ goto disable_clk;
+ }
+
+ return 0;
+
+disable_clk:
+ clk_disable_unprepare(sata_phy->clk);
+ return ret;
+}
+
+static int eic7700_sata_phy_exit(struct phy *phy)
+{
+ struct eic7700_sata_phy *sata_phy = phy_get_drvdata(phy);
+ int ret;
+
+ ret = reset_control_assert(sata_phy->rst);
+ if (ret)
+ return ret;
+
+ clk_disable_unprepare(sata_phy->clk);
+
+ return 0;
+}
+
+static const struct phy_ops eic7700_sata_phy_ops = {
+ .init = eic7700_sata_phy_init,
+ .exit = eic7700_sata_phy_exit,
+ .owner = THIS_MODULE,
+};
+
+static void eic7700_get_tuning_param(struct device_node *np,
+ struct eic7700_sata_phy *sata_phy)
+{
+ if (of_property_read_u32_array
+ (np, "eswin,tx-amplitude-tuning",
+ sata_phy->tx_amplitude_tuning_val,
+ ARRAY_SIZE(sata_phy->tx_amplitude_tuning_val))) {
+ sata_phy->tx_amplitude_tuning_val[0] =
+ SATA_P0_PHY_TX_AMPLITUDE_GEN1_DEFAULT;
+ sata_phy->tx_amplitude_tuning_val[1] =
+ SATA_P0_PHY_TX_AMPLITUDE_GEN2_DEFAULT;
+ sata_phy->tx_amplitude_tuning_val[2] =
+ SATA_P0_PHY_TX_AMPLITUDE_GEN3_DEFAULT;
+ }
+
+ if (of_property_read_u32_array
+ (np, "eswin,tx-preemph-tuning",
+ sata_phy->tx_preemph_tuning_val,
+ ARRAY_SIZE(sata_phy->tx_preemph_tuning_val))) {
+ sata_phy->tx_preemph_tuning_val[0] =
+ SATA_P0_PHY_TX_PREEMPH_GEN1_DEFAULT;
+ sata_phy->tx_preemph_tuning_val[1] =
+ SATA_P0_PHY_TX_PREEMPH_GEN2_DEFAULT;
+ sata_phy->tx_preemph_tuning_val[2] =
+ SATA_P0_PHY_TX_PREEMPH_GEN3_DEFAULT;
+ }
+}
+
+static int eic7700_sata_phy_probe(struct platform_device *pdev)
+{
+ struct eic7700_sata_phy *sata_phy;
+ struct phy_provider *phy_provider;
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct resource *res;
+ void __iomem *regs;
+
+ sata_phy = devm_kzalloc(dev, sizeof(*sata_phy), GFP_KERNEL);
+ if (!sata_phy)
+ return -ENOMEM;
+
+ /*
+ * Map the I/O resource with platform_get_resource and devm_ioremap
+ * instead of the devm_platform_ioremap_resource API, because the
+ * address region of the SATA‑PHY falls into the region of the HSP
+ * clock & reset that has already been obtained by the HSP
+ * clock‑and‑reset driver.
+ */
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res)
+ return -ENOENT;
+
+ regs = devm_ioremap(dev, res->start, resource_size(res));
+ if (IS_ERR(regs))
+ return PTR_ERR(regs);
+
+ sata_phy->regmap = devm_regmap_init_mmio
+ (dev, regs, &eic7700_sata_phy_regmap_config);
+ if (IS_ERR(sata_phy->regmap))
+ return dev_err_probe(dev, PTR_ERR(sata_phy->regmap),
+ "failed to init regmap\n");
+
+ dev_set_drvdata(dev, sata_phy);
+
+ eic7700_get_tuning_param(np, sata_phy);
+
+ sata_phy->clk = devm_clk_get(dev, "phy");
+ if (IS_ERR(sata_phy->clk))
+ return PTR_ERR(sata_phy->clk);
+
+ sata_phy->rst = devm_reset_control_array_get_exclusive(dev);
+ if (IS_ERR(sata_phy->rst))
+ return dev_err_probe(dev, PTR_ERR(sata_phy->rst),
+ "failed to get reset control\n");
+
+ sata_phy->phy = devm_phy_create(dev, NULL, &eic7700_sata_phy_ops);
+ if (IS_ERR(sata_phy->phy))
+ return dev_err_probe(dev, PTR_ERR(sata_phy->phy),
+ "failed to create PHY\n");
+
+ phy_set_drvdata(sata_phy->phy, sata_phy);
+
+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+ if (IS_ERR(phy_provider))
+ return dev_err_probe(dev, PTR_ERR(phy_provider),
+ "failed to register PHY provider\n");
+
+ return 0;
+}
+
+static const struct of_device_id eic7700_sata_phy_of_match[] = {
+ { .compatible = "eswin,eic7700-sata-phy" },
+ { },
+};
+MODULE_DEVICE_TABLE(of, eic7700_sata_phy_of_match);
+
+static struct platform_driver eic7700_sata_phy_driver = {
+ .probe = eic7700_sata_phy_probe,
+ .driver = {
+ .of_match_table = eic7700_sata_phy_of_match,
+ .name = "eic7700-sata-phy",
+ }
+};
+module_platform_driver(eic7700_sata_phy_driver);
+
+MODULE_DESCRIPTION("SATA PHY driver for the ESWIN EIC7700 SoC");
+MODULE_AUTHOR("Yulin Lu <luyulin@eswincomputing.com>");
+MODULE_LICENSE("GPL");
--
2.25.1
[-- Attachment #2: Type: text/plain, Size: 112 bytes --]
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* Re: [PATCH next] phy: google: fix build dependency for Google Tensor USB PHY
From: André Draszik @ 2026-01-23 6:28 UTC (permalink / raw)
To: Roy Luo
Cc: Vinod Koul, Neil Armstrong, Peter Griffin, Tudor Ambarus,
Joy Chakraborty, Naveen Kumar, linux-phy, linux-kernel,
linux-arm-kernel, linux-samsung-soc, kernel test robot
In-Reply-To: <CA+zupgw5H5rumo+DxaTfA_=bcvjbBOivm6R+Pw31jgE-sMyEtw@mail.gmail.com>
Hi Roy,
On Thu, 2026-01-22 at 11:00 -0800, Roy Luo wrote:
> On Thu, Jan 22, 2026 at 2:39 AM André Draszik <andre.draszik@linaro.org> wrote:
> >
> > Hi Roy,
> >
> > On Wed, 2026-01-21 at 22:21 +0000, Roy Luo wrote:
> > > The Google Tensor USB PHY driver uses the Type-C switch framework to
> > > handle orientation changes. However, the Kconfig did not specify a
> > > dependency on the TYPEC framework, leading to undefined reference
> > > errors when building for architectures or configurations where
> > > CONFIG_TYPEC is disabled or configured as a module.
> > >
> > > Add 'depends on TYPEC' to the PHY_GOOGLE_USB entry to ensure all
> > > required symbols are available during linking.
> > >
> > > Fixes: cbce66669c82 ("phy: Add Google Tensor SoC USB PHY driver")
> > > Reported-by: kernel test robot <lkp@intel.com>
> > > Closes: https://lore.kernel.org/oe-kbuild-all/202601210825.ELrpQeED-lkp@intel.com/
> > > Signed-off-by: Roy Luo <royluo@google.com>
> > > ---
> > > drivers/phy/Kconfig | 1 +
> > > 1 file changed, 1 insertion(+)
> > >
> > > diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> > > index 142e7b0ef2efb9209781800ee47b820a91b115ae..5531ff31d8156cb164c32e3e52d4a57b26a62d8d 100644
> > > --- a/drivers/phy/Kconfig
> > > +++ b/drivers/phy/Kconfig
> > > @@ -49,6 +49,7 @@ config GENERIC_PHY_MIPI_DPHY
> > >
> > > config PHY_GOOGLE_USB
> > > tristate "Google Tensor SoC USB PHY driver"
> > > + depends on TYPEC
> >
> > Can you make this
> >
> > depends on TYPEC || COMPILE_TEST
> >
> > to allow some better test coverage?
> >
> > Cheers,
> > Andre
>
> Hi Andre,
>
> Whether to add COMPILE_TEST for build coverage was discussed in
> another thread [1]. My takeaway from that discussion is that
> COMPILE_TEST is intended to substitute for ARCH_XXX in build
> testing and should not be used without it. Once ARCH_GOOGLE is
> present, we can add "depends on (ARCH_GOOGLE || COMPILTE_TEST)".
COMPILE_TEST is not limited to ARCH_xxx. It allows drivers to be
compile tested even if the current build doesn't enable whatever
option (like TYPEC).
See also https://www.kernel.org/doc/html/latest/kbuild/kconfig-language.html#compile-testing
Cheers,
Andre'
>
> [1] https://lore.kernel.org/all/CA+zupgwgfKwPYqj8G2tNf4pEXNEWA+vL2WYJPhJ16xExgko7Dw@mail.gmail.com/
>
> Regards,
> Roy
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply
* Re: [PATCH v3] phy: fsl-imx8mq-usb: add debugfs to access control register
From: Xu Yang @ 2026-01-23 8:05 UTC (permalink / raw)
To: Andrew Lunn
Cc: Frank Li, vkoul, neil.armstrong, shawnguo, kernel, festevam,
jun.li, linux-phy, imx, linux-arm-kernel, linux-kernel
In-Reply-To: <06ae1272-9874-4ce7-9e4f-01d521a5f27f@lunn.ch>
On Tue, Jan 20, 2026 at 02:32:30PM +0100, Andrew Lunn wrote:
> > > Rather than reinvent the wheel, could you use regmap?
> > >
> > > https://elixir.bootlin.com/linux/v6.12.1/source/drivers/base/regmap/regmap-debugfs.c#L546
> > >
> > > Regmap should be able to provide a debugfs interface for you, no
> > > driver code needed.
> > >
> > > This will also help you with the abstraction between the core generic
> > > part of the PHY driver and the SoC integration glue. You pass the
> > > regmap to the core driver, and the funny muxing through two registers
> > > is hidden away from the core. If the next SoC integrated uses plan
> > > MMIO, that SoC glue driver can instantiate an MMIO regmap.
> > >
> > > Using regmap is a good idea for core generic drivers which can be
> > > integrated into SoCs in different ways. It hides the SoC details
> > > behind a well known API.
> >
> > Thanks for your suggestion.
> >
> > Using regmap is generally a good fit for reusable driver and I aggre it
> > helps abstract Soc-specific details.
> >
> > However, the regmap defbugfs has its own limitations:
> > 1. By default the register is read-only, add write operation require rebuild
> > the kernel which make it inconvenient to debug the issue on the spot.
>
> That is somewhat deliberate. We don't want a nice API which can be
> used for user space binary blob drivers. In networking, which is my
> more normal area, we pretty much reject any sort of write interface,
> other than official kernel APIs.
OK.
>
> > Refer to: "09c6ecd39410 regmap: Add support for writing to regmap registers
> > via debugfs"
> >
> > # ls /sys/kernel/debug/regmap/2-0050/ -l
> > total 0
> > -r-------- 1 root root 0 Jan 20 07:45 access
> > -r-------- 1 root root 0 Jan 20 07:45 name
> > -r-------- 1 root root 0 Jan 20 07:45 range
> > -r-------- 1 root root 0 Jan 20 07:45 registers
> >
> > 2. It can't randomly read specific one register with common linux commands. Besides,
> > the read operation is inefficient especially when the range is a bit large because
> > when you cat the register it always read and output all the registers.
>
> You are debugging. Do you need efficient output?
>
> If you have a specific debug tasks in mind, maybe you should be
> thinking of an official kernel API? In the past, there has been
> interest in getting SERDES eye information out of PHYs, and being able
> to change the configuration parameters of the eye. Could a generic API
> be added for that? Some of these PHYs also support pseudo random bit
> sequence generators, and there has been interest in adding APIs for
> configuring them.
After an internal discussion, we prefer to simply export Soc specific control
register access regmap in debugfs and let usespace read or write internal
registers according to CR port accessing sequence. With this, no needs for
a generic API for now.
Thanks for your comments.
Best Regards,
Xu Yang
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply
* Re: [PATCH v8 1/2] dt-bindings: phy: eswin: Document the EIC7700 SoC SATA PHY
From: Krzysztof Kozlowski @ 2026-01-23 8:18 UTC (permalink / raw)
To: Yulin Lu
Cc: vkoul, neil.armstrong, robh, krzk+dt, conor+dt, p.zabel,
linux-phy, devicetree, linux-kernel, ningyu, linmin, fenglin
In-Reply-To: <20260123024936.386-1-luyulin@eswincomputing.com>
On Fri, Jan 23, 2026 at 10:49:36AM +0800, Yulin Lu wrote:
> + eswin,tx-amplitude-tuning:
> + description: This adjusts the transmitter amplitude signal, and its value
> + is derived from eye diagram tuning. The three values correspond to Gen1,
> + Gen2, and Gen3 parameters respectively.
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> + items:
> + - description: Gen1 parameter.
> + minimum: 0
> + maximum: 0x7f
> + default: 0
> + - description: Gen2 parameter.
> + minimum: 0
> + maximum: 0x7f
> + default: 0
> + - description: Gen3 parameter.
> + minimum: 0
> + maximum: 0x7f
> + default: 0
I think defaults should be specified like this:
https://elixir.bootlin.com/linux/v6.19-rc5/source/Documentation/devicetree/bindings/sound/adi,adau7118.yaml#L54
> +
> + eswin,tx-preemph-tuning:
> + description: This adjusts the transmitter de-emphasis signal, and its value
> + is derived from eye diagram tuning. The three values correspond to Gen1,
> + Gen2, and Gen3 parameters respectively.
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> + items:
> + - description: Gen1 parameter.
> + minimum: 0
> + maximum: 0x3f
> + default: 0
> + - description: Gen2 parameter.
> + minimum: 0
> + maximum: 0x3f
> + default: 0
> + - description: Gen3 parameter.
> + minimum: 0
> + maximum: 0x3f
> + default: 0
Same here
Best regards,
Krzysztof
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply
* [PATCH net-next v2 00/14] net: stmmac: SerDes, PCS, BASE-X, and inband goodies
From: Russell King (Oracle) @ 2026-01-23 9:52 UTC (permalink / raw)
To: Andrew Lunn, Heiner Kallweit
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Konrad Dybcio, linux-arm-kernel, linux-arm-msm,
linux-phy, linux-stm32, Maxime Coquelin, Mohd Ayaan Anwar,
Neil Armstrong, netdev, Paolo Abeni, Vinod Koul
This is the v1 submission: if it doesn't get tested but review goes
well, it'll end up in net-next and mainline without testing on the
affected hardware!
Mentioned previously, I've been trying to sort out the PCS support in
stmmac, and this series represents the current state of play.
Previous posted patches centred around merely getting autonegotiation
to be configured correctly, to a point where the manual configuration
can be removed from the qcom-ethqos driver. The qcom-ethqos driver
uses both SGMII and 2500BASE-X, manually configuring the dwmac's
integrated PCS appropriately.
This *untested* series attempts to take this further. The patches:
- clean up qcom-ethqos only-written mac_base member.
- convert qcom-ethqos to use the set_clk_tx_rate() method for setting
the link clock rate.
- add support for phy_set_mode_ext() to the qcom "SGMII" ethernet
SerDes driver (which is really only what it needs. Note that
phy_set_mode_ext() is an expected call to be made, where as
phy_set_speed() is optional and not. See PHY documentation.)
- add platform-glue independent SerDes support to the stmmac core
driver. Currently, only qcom-ethqos will make use of this, and
I suspect as we haven't had this, it's going to be difficult to
convert other platform glue to use this - but had this existed
earlier, we could've pushed people to use PHY to abstract some
of the platform glue differences. Adding it now makes it available
for future platform glue.
- convert qcom-ethqos to use this core SerDes support.
- arrange for stmmac_pcs.c to supply the phy_intf_sel field value
if the integrated PCS will be used. (PHY_INTF_SEL_SGMII requires
the integrated PCS rather than an external PCS.)
- add BASE-X support to the integrated PCS driver, and use it for
BASE-X modes. This fully supports in-band mode, including reading
the link partner advertisement.
- add in-band support for SGMII, reading the state from the RGSMII
status field.
As we leave qcom-ethqos' manual configuration of the PCS in place at
the moment, the last patch adds reporting of any changes in its
configuration that the qcom-ethqos driver does beyond what phylink
requested, thus providing a path to debug and eventually remove
qcom-ethqos' manual configuration.
One patch is not included in this set - which adds a phy_intf_sel
value for external PCS (using PHY_INTF_SEL_GMII_MII). I believe all
external PCS use this mode when connected to a MAC capable of up to
2.5G. However, no platform glue that provides the mac_select_pcs()
method also provide the set_phy_intf_sel() method, so we can safely
ignore this for now.
I would like to get this into net-next before the next merge window,
so testing would be appreciated. If there are issues with these patches
applied, please check whether the issue exists without these patches
and only report regressions caused by this patch set. For example,
I'm aware that qcom-ethqos has issues with 10Mbps mode due to an AQR
PHY being insanely provisioned to use SGMII in 1000M mode but with
rate matching with 10M media. This is not an issue that is relevant
to this patch series, but a problem with the PHY provisioning.
rfc->v1:
- fix SGMII link status
- avoid calling phy_get_mode() if PHY is null
v2:
- fix further AI review bot dribble that could've been raised on
the rfc version but wasn't.
drivers/net/ethernet/stmicro/stmmac/Makefile | 2 +-
drivers/net/ethernet/stmicro/stmmac/common.h | 1 -
.../ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 74 ++-----
drivers/net/ethernet/stmicro/stmmac/dwmac1000.h | 12 +-
.../net/ethernet/stmicro/stmmac/dwmac1000_core.c | 11 +-
drivers/net/ethernet/stmicro/stmmac/dwmac4.h | 10 +-
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c | 10 +-
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 69 +++++--
drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c | 222 +++++++++++++++++++--
drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h | 53 ++---
.../net/ethernet/stmicro/stmmac/stmmac_serdes.c | 111 +++++++++++
.../net/ethernet/stmicro/stmmac/stmmac_serdes.h | 16 ++
drivers/phy/qualcomm/phy-qcom-sgmii-eth.c | 43 ++++
include/linux/stmmac.h | 2 +
14 files changed, 491 insertions(+), 145 deletions(-)
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply
* [PATCH net-next v2 01/14] net: stmmac: qcom-ethqos: remove mac_base
From: Russell King (Oracle) @ 2026-01-23 9:53 UTC (permalink / raw)
To: Andrew Lunn, Heiner Kallweit
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, linux-arm-kernel, linux-arm-msm, linux-phy,
linux-stm32, Maxime Chevallier, Maxime Coquelin, Mohd Ayaan Anwar,
Neil Armstrong, netdev, Paolo Abeni, Vinod Koul
In-Reply-To: <aXNEwBW3OA1xLEUj@shell.armlinux.org.uk>
In commit 9b443e58a896 ("net: stmmac: qcom-ethqos: remove MAC_CTRL_REG
modification"), ethqos->mac_base is only written, never read. Let's
remove it.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
index 0826a7bd32ff..869f924f3cde 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
@@ -100,7 +100,6 @@ struct ethqos_emac_driver_data {
struct qcom_ethqos {
struct platform_device *pdev;
void __iomem *rgmii_base;
- void __iomem *mac_base;
int (*configure_func)(struct qcom_ethqos *ethqos, int speed);
unsigned int link_clk_rate;
@@ -772,8 +771,6 @@ static int qcom_ethqos_probe(struct platform_device *pdev)
return dev_err_probe(dev, PTR_ERR(ethqos->rgmii_base),
"Failed to map rgmii resource\n");
- ethqos->mac_base = stmmac_res.addr;
-
data = of_device_get_match_data(dev);
ethqos->por = data->por;
ethqos->num_por = data->num_por;
--
2.47.3
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH net-next v2 02/14] net: stmmac: qcom-ethqos: convert to set_clk_tx_rate() method
From: Russell King (Oracle) @ 2026-01-23 9:53 UTC (permalink / raw)
To: Andrew Lunn, Heiner Kallweit
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, linux-arm-kernel, linux-arm-msm, linux-phy,
linux-stm32, Maxime Chevallier, Maxime Coquelin, Mohd Ayaan Anwar,
Neil Armstrong, netdev, Paolo Abeni, Vinod Koul
In-Reply-To: <aXNEwBW3OA1xLEUj@shell.armlinux.org.uk>
Set the RGMII link clock using the set_clk_tx_rate() method rather than
coding it into the .fix_mac_speed() method. This simplifies ethqos's
ethqos_fix_mac_speed().
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
.../stmicro/stmmac/dwmac-qcom-ethqos.c | 21 ++++++++++---------
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
index 869f924f3cde..80ea69fc8ee5 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
@@ -102,7 +102,6 @@ struct qcom_ethqos {
void __iomem *rgmii_base;
int (*configure_func)(struct qcom_ethqos *ethqos, int speed);
- unsigned int link_clk_rate;
struct clk *link_clk;
struct phy *serdes_phy;
int serdes_speed;
@@ -174,19 +173,20 @@ static void rgmii_dump(void *priv)
rgmii_readl(ethqos, EMAC_SYSTEM_LOW_POWER_DEBUG));
}
-static void
-ethqos_update_link_clk(struct qcom_ethqos *ethqos, int speed)
+static int ethqos_set_clk_tx_rate(void *bsp_priv, struct clk *clk_tx_i,
+ phy_interface_t interface, int speed)
{
+ struct qcom_ethqos *ethqos = bsp_priv;
long rate;
- if (!phy_interface_mode_is_rgmii(ethqos->phy_mode))
- return;
+ if (!phy_interface_mode_is_rgmii(interface))
+ return 0;
rate = rgmii_clock(speed);
- if (rate > 0)
- ethqos->link_clk_rate = rate * 2;
+ if (rate < 0)
+ return rate;
- clk_set_rate(ethqos->link_clk, ethqos->link_clk_rate);
+ return clk_set_rate(ethqos->link_clk, rate * 2);
}
static void
@@ -645,7 +645,6 @@ static void ethqos_fix_mac_speed(void *priv, int speed, unsigned int mode)
struct qcom_ethqos *ethqos = priv;
qcom_ethqos_set_sgmii_loopback(ethqos, false);
- ethqos_update_link_clk(ethqos, speed);
ethqos_configure(ethqos, speed);
}
@@ -797,10 +796,12 @@ static int qcom_ethqos_probe(struct platform_device *pdev)
"Failed to get serdes phy\n");
ethqos->serdes_speed = SPEED_1000;
- ethqos_update_link_clk(ethqos, SPEED_1000);
+ ethqos_set_clk_tx_rate(ethqos, NULL, plat_dat->phy_interface,
+ SPEED_1000);
ethqos_set_func_clk_en(ethqos);
plat_dat->bsp_priv = ethqos;
+ plat_dat->set_clk_tx_rate = ethqos_set_clk_tx_rate;
plat_dat->fix_mac_speed = ethqos_fix_mac_speed;
plat_dat->dump_debug_regs = rgmii_dump;
plat_dat->ptp_clk_freq_config = ethqos_ptp_clk_freq_config;
--
2.47.3
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH net-next v2 03/14] phy: qcom-sgmii-eth: add .set_mode() and .validate() methods
From: Russell King (Oracle) @ 2026-01-23 9:53 UTC (permalink / raw)
To: Andrew Lunn, Heiner Kallweit
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, linux-arm-kernel, linux-arm-msm, linux-phy,
linux-stm32, Maxime Chevallier, Maxime Coquelin, Mohd Ayaan Anwar,
Neil Armstrong, netdev, Paolo Abeni, Vinod Koul
In-Reply-To: <aXNEwBW3OA1xLEUj@shell.armlinux.org.uk>
qcom-sgmii-eth is an Ethernet SerDes supporting only Ethernet mode
using SGMII, 1000BASE-X and 2500BASE-X.
Add an implementation of the .set_mode() method, which can be used
instead of or as well as the .set_speed() method. The Ethernet
interface modes mentioned above all have a fixed data rate, so
setting the mode is sufficient to fully specify the operating
parameters.
Add an implementation of the .validate() method, which will be
necessary to allow discovery of the SerDes capabilities for platform
independent SerDes support in the stmmac network driver.
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Acked-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
drivers/phy/qualcomm/phy-qcom-sgmii-eth.c | 43 +++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-sgmii-eth.c b/drivers/phy/qualcomm/phy-qcom-sgmii-eth.c
index 5b1c82459c12..4ea3dce7719f 100644
--- a/drivers/phy/qualcomm/phy-qcom-sgmii-eth.c
+++ b/drivers/phy/qualcomm/phy-qcom-sgmii-eth.c
@@ -7,6 +7,7 @@
#include <linux/ethtool.h>
#include <linux/module.h>
#include <linux/of.h>
+#include <linux/phy.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
@@ -286,6 +287,37 @@ static int qcom_dwmac_sgmii_phy_power_off(struct phy *phy)
return 0;
}
+static int qcom_dwmac_sgmii_phy_speed(enum phy_mode mode, int submode)
+{
+ if (mode != PHY_MODE_ETHERNET)
+ return -EINVAL;
+
+ if (submode == PHY_INTERFACE_MODE_SGMII ||
+ submode == PHY_INTERFACE_MODE_1000BASEX)
+ return SPEED_1000;
+
+ if (submode == PHY_INTERFACE_MODE_2500BASEX)
+ return SPEED_2500;
+
+ return -EINVAL;
+}
+
+static int qcom_dwmac_sgmii_phy_set_mode(struct phy *phy, enum phy_mode mode,
+ int submode)
+{
+ struct qcom_dwmac_sgmii_phy_data *data = phy_get_drvdata(phy);
+ int speed;
+
+ speed = qcom_dwmac_sgmii_phy_speed(mode, submode);
+ if (speed < 0)
+ return speed;
+
+ if (speed != data->speed)
+ data->speed = speed;
+
+ return qcom_dwmac_sgmii_phy_calibrate(phy);
+}
+
static int qcom_dwmac_sgmii_phy_set_speed(struct phy *phy, int speed)
{
struct qcom_dwmac_sgmii_phy_data *data = phy_get_drvdata(phy);
@@ -296,10 +328,21 @@ static int qcom_dwmac_sgmii_phy_set_speed(struct phy *phy, int speed)
return qcom_dwmac_sgmii_phy_calibrate(phy);
}
+static int qcom_dwmac_sgmii_phy_validate(struct phy *phy, enum phy_mode mode,
+ int submode,
+ union phy_configure_opts *opts)
+{
+ int ret = qcom_dwmac_sgmii_phy_speed(mode, submode);
+
+ return ret < 0 ? ret : 0;
+}
+
static const struct phy_ops qcom_dwmac_sgmii_phy_ops = {
.power_on = qcom_dwmac_sgmii_phy_power_on,
.power_off = qcom_dwmac_sgmii_phy_power_off,
+ .set_mode = qcom_dwmac_sgmii_phy_set_mode,
.set_speed = qcom_dwmac_sgmii_phy_set_speed,
+ .validate = qcom_dwmac_sgmii_phy_validate,
.calibrate = qcom_dwmac_sgmii_phy_calibrate,
.owner = THIS_MODULE,
};
--
2.47.3
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH net-next v2 04/14] net: stmmac: wrap phylink's rx_clk_stop functions
From: Russell King (Oracle) @ 2026-01-23 9:53 UTC (permalink / raw)
To: Andrew Lunn, Heiner Kallweit
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, linux-arm-kernel, linux-arm-msm, linux-phy,
linux-stm32, Maxime Chevallier, Maxime Coquelin, Mohd Ayaan Anwar,
Neil Armstrong, netdev, Paolo Abeni, Vinod Koul
In-Reply-To: <aXNEwBW3OA1xLEUj@shell.armlinux.org.uk>
With generic SerDes support, stmmac will need to do more work to ensure
that clk_rx_i is running in all configurations. Rather than turn each
site that calls phylink_rx_clk_stop_xxx() into a list of functions,
move these to their own pair of functions so that they can be
augmented at a single location.
Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
.../net/ethernet/stmicro/stmmac/stmmac_main.c | 32 ++++++++++++-------
1 file changed, 21 insertions(+), 11 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index c2589f02ff7e..24a2555ca329 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -3547,6 +3547,16 @@ static void stmmac_safety_feat_configuration(struct stmmac_priv *priv)
}
}
+static void stmmac_clk_rx_i_require(struct stmmac_priv *priv)
+{
+ phylink_rx_clk_stop_block(priv->phylink);
+}
+
+static void stmmac_clk_rx_i_release(struct stmmac_priv *priv)
+{
+ phylink_rx_clk_stop_unblock(priv->phylink);
+}
+
/**
* stmmac_hw_setup - setup mac in a usable state.
* @dev : pointer to the device structure.
@@ -3578,12 +3588,12 @@ static int stmmac_hw_setup(struct net_device *dev)
* Block the receive clock stop for LPI mode at the PHY in case
* the link is established with EEE mode active.
*/
- phylink_rx_clk_stop_block(priv->phylink);
+ stmmac_clk_rx_i_require(priv);
/* DMA initialization and SW reset */
ret = stmmac_init_dma_engine(priv);
if (ret < 0) {
- phylink_rx_clk_stop_unblock(priv->phylink);
+ stmmac_clk_rx_i_release(priv);
netdev_err(priv->dev, "%s: DMA engine initialization failed\n",
__func__);
return ret;
@@ -3591,7 +3601,7 @@ static int stmmac_hw_setup(struct net_device *dev)
/* Copy the MAC addr into the HW */
stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0);
- phylink_rx_clk_stop_unblock(priv->phylink);
+ stmmac_clk_rx_i_release(priv);
/* Initialize the MAC Core */
stmmac_core_init(priv, priv->hw, dev);
@@ -3670,9 +3680,9 @@ static int stmmac_hw_setup(struct net_device *dev)
/* Start the ball rolling... */
stmmac_start_all_dma(priv);
- phylink_rx_clk_stop_block(priv->phylink);
+ stmmac_clk_rx_i_require(priv);
stmmac_set_hw_vlan_mode(priv, priv->hw);
- phylink_rx_clk_stop_unblock(priv->phylink);
+ stmmac_clk_rx_i_release(priv);
return 0;
}
@@ -6107,9 +6117,9 @@ static int stmmac_set_features(struct net_device *netdev,
else
priv->hw->hw_vlan_en = false;
- phylink_rx_clk_stop_block(priv->phylink);
+ stmmac_clk_rx_i_require(priv);
stmmac_set_hw_vlan_mode(priv, priv->hw);
- phylink_rx_clk_stop_unblock(priv->phylink);
+ stmmac_clk_rx_i_release(priv);
return 0;
}
@@ -6378,9 +6388,9 @@ static int stmmac_set_mac_address(struct net_device *ndev, void *addr)
if (ret)
goto set_mac_error;
- phylink_rx_clk_stop_block(priv->phylink);
+ stmmac_clk_rx_i_require(priv);
stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0);
- phylink_rx_clk_stop_unblock(priv->phylink);
+ stmmac_clk_rx_i_release(priv);
set_mac_error:
pm_runtime_put(priv->device);
@@ -8192,11 +8202,11 @@ int stmmac_resume(struct device *dev)
stmmac_init_timestamping(priv);
stmmac_init_coalesce(priv);
- phylink_rx_clk_stop_block(priv->phylink);
+ stmmac_clk_rx_i_require(priv);
stmmac_set_rx_mode(ndev);
stmmac_restore_hw_vlan_rx_fltr(priv, ndev, priv->hw);
- phylink_rx_clk_stop_unblock(priv->phylink);
+ stmmac_clk_rx_i_release(priv);
stmmac_enable_all_queues(priv);
stmmac_enable_all_dma_irq(priv);
--
2.47.3
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH net-next v2 05/14] net: stmmac: add stmmac core serdes support
From: Russell King (Oracle) @ 2026-01-23 9:53 UTC (permalink / raw)
To: Andrew Lunn, Heiner Kallweit
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, linux-arm-kernel, linux-arm-msm, linux-phy,
linux-stm32, Maxime Chevallier, Maxime Coquelin, Mohd Ayaan Anwar,
Neil Armstrong, netdev, Paolo Abeni, Vinod Koul
In-Reply-To: <aXNEwBW3OA1xLEUj@shell.armlinux.org.uk>
Rather than having platform glue implement SerDes PHY support, add it
to the core driver, specifically to the stmmac integrated PCS driver
as the SerDes is connected to the integrated PCS.
Platforms using external PCS can also populate plat->serdes, and the
core driver will call phy_init() and phy_exit() when the administrative
state of the interface changes, but the other phy methods will not be
called.
Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
--
rfc->v1: avoid calling phy_get_mode() with NULL serdes PHY
v2: add cleanup when dwmac_serdes_set_mode() fails, because AI allegedly
knows better than the author and phylink maintainer, even though this
will result in dwmac_serdes_power_off() being called multiple times
and producing a kernel warning. But if it makes AI happy, then it must
be a good thing. It'll also make Vladimir happy.
---
drivers/net/ethernet/stmicro/stmmac/Makefile | 2 +-
.../net/ethernet/stmicro/stmmac/stmmac_main.c | 14 ++-
.../net/ethernet/stmicro/stmmac/stmmac_pcs.c | 40 ++++++-
.../net/ethernet/stmicro/stmmac/stmmac_pcs.h | 1 +
.../ethernet/stmicro/stmmac/stmmac_serdes.c | 111 ++++++++++++++++++
.../ethernet/stmicro/stmmac/stmmac_serdes.h | 16 +++
include/linux/stmmac.h | 2 +
7 files changed, 182 insertions(+), 4 deletions(-)
create mode 100644 drivers/net/ethernet/stmicro/stmmac/stmmac_serdes.c
create mode 100644 drivers/net/ethernet/stmicro/stmmac/stmmac_serdes.h
diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile
index c9263987ef8d..a3c2cd5d0c91 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Makefile
+++ b/drivers/net/ethernet/stmicro/stmmac/Makefile
@@ -7,7 +7,7 @@ stmmac-objs:= stmmac_main.o stmmac_ethtool.o stmmac_mdio.o ring_mode.o \
dwmac4_dma.o dwmac4_lib.o dwmac4_core.o dwmac5.o hwif.o \
stmmac_tc.o dwxgmac2_core.o dwxgmac2_dma.o dwxgmac2_descs.o \
stmmac_xdp.o stmmac_est.o stmmac_fpe.o stmmac_vlan.o \
- stmmac_pcs.o $(stmmac-y)
+ stmmac_pcs.o stmmac_serdes.o $(stmmac-y)
stmmac-$(CONFIG_STMMAC_SELFTESTS) += stmmac_selftests.o
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 24a2555ca329..6c515f9efbe7 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -48,6 +48,7 @@
#include "stmmac_fpe.h"
#include "stmmac.h"
#include "stmmac_pcs.h"
+#include "stmmac_serdes.h"
#include "stmmac_xdp.h"
#include <linux/reset.h>
#include <linux/of_mdio.h>
@@ -3549,12 +3550,16 @@ static void stmmac_safety_feat_configuration(struct stmmac_priv *priv)
static void stmmac_clk_rx_i_require(struct stmmac_priv *priv)
{
+ dwmac_serdes_power_on(priv);
+ /* Only sets the SerDes mode if it wasn't already configured. */
+ dwmac_serdes_init_mode(priv, priv->plat->phy_interface);
phylink_rx_clk_stop_block(priv->phylink);
}
static void stmmac_clk_rx_i_release(struct stmmac_priv *priv)
{
phylink_rx_clk_stop_unblock(priv->phylink);
+ dwmac_serdes_power_off(priv);
}
/**
@@ -4152,10 +4157,14 @@ static int stmmac_open(struct net_device *dev)
if (ret)
goto err_runtime_pm;
- ret = __stmmac_open(dev, dma_conf);
+ ret = dwmac_serdes_init(priv);
if (ret)
goto err_disconnect_phy;
+ ret = __stmmac_open(dev, dma_conf);
+ if (ret)
+ goto err_serdes;
+
kfree(dma_conf);
/* We may have called phylink_speed_down before */
@@ -4163,6 +4172,8 @@ static int stmmac_open(struct net_device *dev)
return ret;
+err_serdes:
+ dwmac_serdes_exit(priv);
err_disconnect_phy:
phylink_disconnect_phy(priv->phylink);
err_runtime_pm:
@@ -4226,6 +4237,7 @@ static int stmmac_release(struct net_device *dev)
__stmmac_release(dev);
+ dwmac_serdes_exit(priv);
phylink_disconnect_phy(priv->phylink);
pm_runtime_put(priv->device);
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
index 2f826fe7229b..10a2eb903d2a 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
@@ -1,12 +1,27 @@
// SPDX-License-Identifier: GPL-2.0-only
#include "stmmac.h"
#include "stmmac_pcs.h"
+#include "stmmac_serdes.h"
static int dwmac_integrated_pcs_enable(struct phylink_pcs *pcs)
{
struct stmmac_pcs *spcs = phylink_pcs_to_stmmac_pcs(pcs);
+ struct stmmac_priv *priv = spcs->priv;
+ int ret;
+
+ ret = dwmac_serdes_power_on(priv);
+ if (ret)
+ return ret;
+
+ if (spcs->interface != PHY_INTERFACE_MODE_NA) {
+ ret = dwmac_serdes_set_mode(priv, spcs->interface);
+ if (ret) {
+ dwmac_serdes_power_off(priv);
+ return ret;
+ }
+ }
- stmmac_mac_irq_modify(spcs->priv, 0, spcs->int_mask);
+ stmmac_mac_irq_modify(priv, 0, spcs->int_mask);
return 0;
}
@@ -14,8 +29,11 @@ static int dwmac_integrated_pcs_enable(struct phylink_pcs *pcs)
static void dwmac_integrated_pcs_disable(struct phylink_pcs *pcs)
{
struct stmmac_pcs *spcs = phylink_pcs_to_stmmac_pcs(pcs);
+ struct stmmac_priv *priv = spcs->priv;
+
+ stmmac_mac_irq_modify(priv, spcs->int_mask, 0);
- stmmac_mac_irq_modify(spcs->priv, spcs->int_mask, 0);
+ dwmac_serdes_power_off(priv);
}
static void dwmac_integrated_pcs_get_state(struct phylink_pcs *pcs,
@@ -32,6 +50,15 @@ static int dwmac_integrated_pcs_config(struct phylink_pcs *pcs,
bool permit_pause_to_mac)
{
struct stmmac_pcs *spcs = phylink_pcs_to_stmmac_pcs(pcs);
+ int ret;
+
+ if (spcs->interface != interface) {
+ ret = dwmac_serdes_set_mode(spcs->priv, interface);
+ if (ret)
+ return ret;
+
+ spcs->interface = interface;
+ }
dwmac_ctrl_ane(spcs->base, 0, 1, spcs->priv->hw->reverse_sgmii_enable);
@@ -71,6 +98,7 @@ int stmmac_integrated_pcs_init(struct stmmac_priv *priv, unsigned int offset,
u32 int_mask)
{
struct stmmac_pcs *spcs;
+ int ret;
spcs = devm_kzalloc(priv->device, sizeof(*spcs), GFP_KERNEL);
if (!spcs)
@@ -81,6 +109,14 @@ int stmmac_integrated_pcs_init(struct stmmac_priv *priv, unsigned int offset,
spcs->int_mask = int_mask;
spcs->pcs.ops = &dwmac_integrated_pcs_ops;
+ if (priv->plat->serdes) {
+ ret = dwmac_serdes_validate(priv, PHY_INTERFACE_MODE_SGMII);
+ if (ret)
+ dev_warn(priv->device,
+ "serdes does not support SGMII: %pe\n",
+ ERR_PTR(ret));
+ }
+
__set_bit(PHY_INTERFACE_MODE_SGMII, spcs->pcs.supported_interfaces);
priv->integrated_pcs = spcs;
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h
index c4e6b242d390..36bf75fdf478 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h
@@ -53,6 +53,7 @@ struct stmmac_pcs {
struct stmmac_priv *priv;
void __iomem *base;
u32 int_mask;
+ phy_interface_t interface;
struct phylink_pcs pcs;
};
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_serdes.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_serdes.c
new file mode 100644
index 000000000000..d46a071bc383
--- /dev/null
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_serdes.c
@@ -0,0 +1,111 @@
+#include <linux/phy/phy.h>
+
+#include "stmmac.h"
+#include "stmmac_serdes.h"
+
+static phy_interface_t dwmac_serdes_phy_modes[] = {
+ PHY_INTERFACE_MODE_SGMII,
+ PHY_INTERFACE_MODE_1000BASEX,
+ PHY_INTERFACE_MODE_2500BASEX
+};
+
+int dwmac_serdes_validate(struct stmmac_priv *priv, phy_interface_t interface)
+{
+ return phy_validate(priv->plat->serdes, PHY_MODE_ETHERNET, interface,
+ NULL);
+}
+
+int dwmac_serdes_init(struct stmmac_priv *priv)
+{
+ size_t i;
+ int ret;
+
+ if (!priv->plat->serdes)
+ return 0;
+
+ /* Encourage good implementation of the SerDes PHY driver, so that
+ * we can discover which Ethernet modes the SerDes supports.
+ * Unfortunately, some implementations are noisy (bad), others
+ * require phy_set_speed() to select the correct speed first
+ * (which then reprograms the SerDes, negating the whole point of
+ * phy_validate().) Weed out these incompatible implementations.
+ */
+ for (i = 0; i < ARRAY_SIZE(dwmac_serdes_phy_modes); i++) {
+ ret = phy_validate(priv->plat->serdes, PHY_MODE_ETHERNET,
+ dwmac_serdes_phy_modes[i], NULL);
+ if (ret == 0 || ret == -EOPNOTSUPP)
+ break;
+ }
+
+ if (ret == -EOPNOTSUPP)
+ dev_warn(priv->device,
+ "SerDes driver does not implement phy_validate()\n");
+ if (ret) {
+ /* The SerDes PHY failed validation, refuse to use it. */
+ dev_warn(priv->device,
+ "SerDes driver fails to validate SGMII, 1000BASE-X nor 2500BASE-X\n");
+ return -EINVAL;
+ }
+
+ ret = phy_init(priv->plat->serdes);
+ if (ret)
+ dev_err(priv->device, "failed to initialize SerDes: %pe\n",
+ ERR_PTR(ret));
+
+ return ret;
+}
+
+int dwmac_serdes_power_on(struct stmmac_priv *priv)
+{
+ int ret;
+
+ ret = phy_power_on(priv->plat->serdes);
+ if (ret)
+ dev_err(priv->device, "failed to power on SerDes: %pe\n",
+ ERR_PTR(ret));
+
+ return ret;
+}
+
+int dwmac_serdes_init_mode(struct stmmac_priv *priv, phy_interface_t interface)
+{
+ struct phy *serdes = priv->plat->serdes;
+
+ if (!serdes || phy_get_mode(serdes) == PHY_MODE_ETHERNET)
+ return 0;
+
+ return dwmac_serdes_set_mode(priv, interface);
+}
+
+int dwmac_serdes_set_mode(struct stmmac_priv *priv, phy_interface_t interface)
+{
+ struct phy *serdes = priv->plat->serdes;
+ int ret;
+
+ ret = phy_set_mode_ext(serdes, PHY_MODE_ETHERNET, interface);
+ if (ret)
+ dev_err(priv->device,
+ "failed to set SerDes mode %s: %pe\n",
+ phy_modes(interface), ERR_PTR(ret));
+
+ return ret;
+}
+
+void dwmac_serdes_power_off(struct stmmac_priv *priv)
+{
+ int ret;
+
+ ret = phy_power_off(priv->plat->serdes);
+ if (ret)
+ dev_err(priv->device, "failed to power off SerDes: %pe\n",
+ ERR_PTR(ret));
+}
+
+void dwmac_serdes_exit(struct stmmac_priv *priv)
+{
+ int ret = phy_exit(priv->plat->serdes);
+
+ if (ret)
+ dev_err(priv->device, "failed to shutdown SerDes: %pe\n",
+ ERR_PTR(ret));
+}
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_serdes.h b/drivers/net/ethernet/stmicro/stmmac/stmmac_serdes.h
new file mode 100644
index 000000000000..a31e6c9e0570
--- /dev/null
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_serdes.h
@@ -0,0 +1,16 @@
+#ifndef STMMAC_SERDES_H
+#define STMMAC_SERDES_H
+
+#include <linux/phy.h>
+
+struct stmmac_priv;
+
+int dwmac_serdes_validate(struct stmmac_priv *priv, phy_interface_t interface);
+int dwmac_serdes_init(struct stmmac_priv *priv);
+int dwmac_serdes_power_on(struct stmmac_priv *priv);
+int dwmac_serdes_init_mode(struct stmmac_priv *priv, phy_interface_t interface);
+int dwmac_serdes_set_mode(struct stmmac_priv *priv, phy_interface_t interface);
+void dwmac_serdes_power_off(struct stmmac_priv *priv);
+void dwmac_serdes_exit(struct stmmac_priv *priv);
+
+#endif
diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
index f1054b9c2d8a..4db506e5cf13 100644
--- a/include/linux/stmmac.h
+++ b/include/linux/stmmac.h
@@ -193,6 +193,7 @@ enum dwmac_core_type {
#define STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY BIT(13)
struct mac_device_info;
+struct phy;
struct plat_stmmacenet_data {
enum dwmac_core_type core_type;
@@ -222,6 +223,7 @@ struct plat_stmmacenet_data {
* that phylink uses.
*/
phy_interface_t phy_interface;
+ struct phy *serdes;
struct stmmac_mdio_bus_data *mdio_bus_data;
struct device_node *phy_node;
struct fwnode_handle *port_node;
--
2.47.3
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox