* [PATCH v8 1/2] dt-bindings: phy: eswin: Document the EIC7700 SoC SATA PHY
From: Yulin Lu @ 2026-01-23 2:49 UTC (permalink / raw)
To: vkoul, neil.armstrong, robh, krzk+dt, conor+dt, p.zabel,
linux-phy, devicetree, linux-kernel
Cc: ningyu, linmin, fenglin, Yulin Lu
In-Reply-To: <20260123024823.1612-1-luyulin@eswincomputing.com>
Document the SATA PHY on the EIC7700 SoC platform,
describing its usage.
Signed-off-by: Yulin Lu <luyulin@eswincomputing.com>
---
.../bindings/phy/eswin,eic7700-sata-phy.yaml | 96 +++++++++++++++++++
1 file changed, 96 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/eswin,eic7700-sata-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/eswin,eic7700-sata-phy.yaml b/Documentation/devicetree/bindings/phy/eswin,eic7700-sata-phy.yaml
new file mode 100644
index 000000000000..4bb2d7a53761
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/eswin,eic7700-sata-phy.yaml
@@ -0,0 +1,96 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/eswin,eic7700-sata-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Eswin EIC7700 SoC SATA PHY
+
+maintainers:
+ - Yulin Lu <luyulin@eswincomputing.com>
+ - Huan He <hehuan1@eswincomputing.com>
+
+properties:
+ compatible:
+ const: eswin,eic7700-sata-phy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: phy
+
+ resets:
+ maxItems: 2
+
+ reset-names:
+ items:
+ - const: port
+ - const: phy
+
+ eswin,tx-amplitude-tuning:
+ description: This adjusts the transmitter amplitude signal, and its value
+ is derived from eye diagram tuning. The three values correspond to Gen1,
+ Gen2, and Gen3 parameters respectively.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ items:
+ - description: Gen1 parameter.
+ minimum: 0
+ maximum: 0x7f
+ default: 0
+ - description: Gen2 parameter.
+ minimum: 0
+ maximum: 0x7f
+ default: 0
+ - description: Gen3 parameter.
+ minimum: 0
+ maximum: 0x7f
+ default: 0
+
+ eswin,tx-preemph-tuning:
+ description: This adjusts the transmitter de-emphasis signal, and its value
+ is derived from eye diagram tuning. The three values correspond to Gen1,
+ Gen2, and Gen3 parameters respectively.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ items:
+ - description: Gen1 parameter.
+ minimum: 0
+ maximum: 0x3f
+ default: 0
+ - description: Gen2 parameter.
+ minimum: 0
+ maximum: 0x3f
+ default: 0
+ - description: Gen3 parameter.
+ minimum: 0
+ maximum: 0x3f
+ default: 0
+
+ "#phy-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ sata-phy@50440300 {
+ compatible = "eswin,eic7700-sata-phy";
+ reg = <0x50440300 0x40>;
+ clocks = <&hspcrg 17>;
+ clock-names = "phy";
+ resets = <&hspcrg 0>, <&hspcrg 1>;
+ reset-names = "port", "phy";
+ #phy-cells = <0>;
+ };
--
2.25.1
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^ permalink raw reply related
* [PATCH v8 2/2] phy: eswin: Create eswin directory and add EIC7700 SATA PHY driver
From: Yulin Lu @ 2026-01-23 3:09 UTC (permalink / raw)
To: vkoul, neil.armstrong, robh, krzk+dt, conor+dt, p.zabel,
linux-phy, devicetree, linux-kernel
Cc: ningyu, linmin, fenglin, Yulin Lu
In-Reply-To: <20260123024823.1612-1-luyulin@eswincomputing.com>
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset=y, Size: 10758 bytes --]
Create the eswin phy driver directory and add support for the
SATA PHY driver on the EIC7700 SoC platform.
Signed-off-by: Yulin Lu <luyulin@eswincomputing.com>
---
drivers/phy/Kconfig | 1 +
drivers/phy/Makefile | 1 +
drivers/phy/eswin/Kconfig | 14 ++
drivers/phy/eswin/Makefile | 2 +
drivers/phy/eswin/phy-eic7700-sata.c | 273 +++++++++++++++++++++++++++
5 files changed, 291 insertions(+)
create mode 100644 drivers/phy/eswin/Kconfig
create mode 100644 drivers/phy/eswin/Makefile
create mode 100644 drivers/phy/eswin/phy-eic7700-sata.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 678dd0452f0a..6d50704917f0 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -105,6 +105,7 @@ source "drivers/phy/allwinner/Kconfig"
source "drivers/phy/amlogic/Kconfig"
source "drivers/phy/broadcom/Kconfig"
source "drivers/phy/cadence/Kconfig"
+source "drivers/phy/eswin/Kconfig"
source "drivers/phy/freescale/Kconfig"
source "drivers/phy/hisilicon/Kconfig"
source "drivers/phy/ingenic/Kconfig"
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index bfb27fb5a494..482a143d3417 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -17,6 +17,7 @@ obj-y += allwinner/ \
amlogic/ \
broadcom/ \
cadence/ \
+ eswin/ \
freescale/ \
hisilicon/ \
ingenic/ \
diff --git a/drivers/phy/eswin/Kconfig b/drivers/phy/eswin/Kconfig
new file mode 100644
index 000000000000..37447cc3af63
--- /dev/null
+++ b/drivers/phy/eswin/Kconfig
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Phy drivers for ESWIN platforms
+#
+config PHY_EIC7700_SATA
+ tristate "eic7700 Sata SerDes/PHY driver"
+ depends on ARCH_ESWIN || COMPILE_TEST
+ depends on HAS_IOMEM
+ select GENERIC_PHY
+ help
+ Enable this to support SerDes/Phy found on ESWIN's
+ EIC7700 SoC.This Phy supports SATA 1.5 Gb/s,
+ SATA 3.0 Gb/s, SATA 6.0 Gb/s speeds.
+ It supports one SATA host port to accept one SATA device.
diff --git a/drivers/phy/eswin/Makefile b/drivers/phy/eswin/Makefile
new file mode 100644
index 000000000000..db08c66be812
--- /dev/null
+++ b/drivers/phy/eswin/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_PHY_EIC7700_SATA) += phy-eic7700-sata.o
diff --git a/drivers/phy/eswin/phy-eic7700-sata.c b/drivers/phy/eswin/phy-eic7700-sata.c
new file mode 100644
index 000000000000..4de8dfe18182
--- /dev/null
+++ b/drivers/phy/eswin/phy-eic7700-sata.c
@@ -0,0 +1,273 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ESWIN SATA PHY driver
+ *
+ * Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd..
+ * All rights reserved.
+ *
+ * Authors: Yulin Lu <luyulin@eswincomputing.com>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+
+#define SATA_AXI_LP_CTRL 0x08
+#define SATA_MPLL_CTRL 0x20
+#define SATA_P0_PHY_STAT 0x24
+#define SATA_PHY_CTRL0 0x28
+#define SATA_PHY_CTRL1 0x2c
+#define SATA_REF_CTRL 0x34
+#define SATA_REF_CTRL1 0x38
+#define SATA_LOS_IDEN 0x3c
+
+#define SATA_CLK_RST_SOURCE_PHY BIT(0)
+#define SATA_P0_PHY_TX_AMPLITUDE_GEN1_MASK GENMASK(6, 0)
+#define SATA_P0_PHY_TX_AMPLITUDE_GEN1_DEFAULT 0x42
+#define SATA_P0_PHY_TX_AMPLITUDE_GEN2_MASK GENMASK(14, 8)
+#define SATA_P0_PHY_TX_AMPLITUDE_GEN2_DEFAULT 0x46
+#define SATA_P0_PHY_TX_AMPLITUDE_GEN3_MASK GENMASK(22, 16)
+#define SATA_P0_PHY_TX_AMPLITUDE_GEN3_DEFAULT 0x73
+#define SATA_P0_PHY_TX_PREEMPH_GEN1_MASK GENMASK(5, 0)
+#define SATA_P0_PHY_TX_PREEMPH_GEN1_DEFAULT 0x5
+#define SATA_P0_PHY_TX_PREEMPH_GEN2_MASK GENMASK(13, 8)
+#define SATA_P0_PHY_TX_PREEMPH_GEN2_DEFAULT 0x5
+#define SATA_P0_PHY_TX_PREEMPH_GEN3_MASK GENMASK(21, 16)
+#define SATA_P0_PHY_TX_PREEMPH_GEN3_DEFAULT 0x23
+#define SATA_LOS_LEVEL_MASK GENMASK(4, 0)
+#define SATA_LOS_BIAS_MASK GENMASK(18, 16)
+#define SATA_M_CSYSREQ BIT(0)
+#define SATA_S_CSYSREQ BIT(16)
+#define SATA_REF_REPEATCLK_EN BIT(0)
+#define SATA_REF_USE_PAD BIT(20)
+#define SATA_MPLL_MULTIPLIER_MASK GENMASK(22, 16)
+#define SATA_P0_PHY_READY BIT(0)
+
+#define PLL_LOCK_SLEEP_US 10
+#define PLL_LOCK_TIMEOUT_US 1000
+
+struct eic7700_sata_phy {
+ u32 tx_amplitude_tuning_val[3];
+ u32 tx_preemph_tuning_val[3];
+ struct reset_control *rst;
+ struct regmap *regmap;
+ struct clk *clk;
+ struct phy *phy;
+};
+
+static const struct regmap_config eic7700_sata_phy_regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = SATA_LOS_IDEN,
+};
+
+static int wait_for_phy_ready(struct regmap *regmap, u32 reg, u32 checkbit,
+ u32 status)
+{
+ u32 val;
+ int ret;
+
+ ret = regmap_read_poll_timeout(regmap, reg, val,
+ (val & checkbit) == status,
+ PLL_LOCK_SLEEP_US, PLL_LOCK_TIMEOUT_US);
+
+ return ret;
+}
+
+static int eic7700_sata_phy_init(struct phy *phy)
+{
+ struct eic7700_sata_phy *sata_phy = phy_get_drvdata(phy);
+ u32 val;
+ int ret;
+
+ ret = clk_prepare_enable(sata_phy->clk);
+ if (ret)
+ return ret;
+
+ regmap_write(sata_phy->regmap, SATA_REF_CTRL1, SATA_CLK_RST_SOURCE_PHY);
+
+ val = FIELD_PREP(SATA_P0_PHY_TX_AMPLITUDE_GEN1_MASK,
+ sata_phy->tx_amplitude_tuning_val[0]) |
+ FIELD_PREP(SATA_P0_PHY_TX_AMPLITUDE_GEN2_MASK,
+ sata_phy->tx_amplitude_tuning_val[1]) |
+ FIELD_PREP(SATA_P0_PHY_TX_AMPLITUDE_GEN3_MASK,
+ sata_phy->tx_amplitude_tuning_val[2]);
+ regmap_write(sata_phy->regmap, SATA_PHY_CTRL0, val);
+
+ val = FIELD_PREP(SATA_P0_PHY_TX_PREEMPH_GEN1_MASK,
+ sata_phy->tx_preemph_tuning_val[0]) |
+ FIELD_PREP(SATA_P0_PHY_TX_PREEMPH_GEN2_MASK,
+ sata_phy->tx_preemph_tuning_val[1]) |
+ FIELD_PREP(SATA_P0_PHY_TX_PREEMPH_GEN3_MASK,
+ sata_phy->tx_preemph_tuning_val[2]);
+ regmap_write(sata_phy->regmap, SATA_PHY_CTRL1, val);
+
+ val = FIELD_PREP(SATA_LOS_LEVEL_MASK, 0x9) |
+ FIELD_PREP(SATA_LOS_BIAS_MASK, 0x2);
+ regmap_write(sata_phy->regmap, SATA_LOS_IDEN, val);
+
+ val = SATA_M_CSYSREQ | SATA_S_CSYSREQ;
+ regmap_write(sata_phy->regmap, SATA_AXI_LP_CTRL, val);
+
+ val = SATA_REF_REPEATCLK_EN | SATA_REF_USE_PAD;
+ regmap_write(sata_phy->regmap, SATA_REF_CTRL, val);
+
+ val = FIELD_PREP(SATA_MPLL_MULTIPLIER_MASK, 0x3c);
+ regmap_write(sata_phy->regmap, SATA_MPLL_CTRL, val);
+
+ usleep_range(15, 20);
+
+ ret = reset_control_deassert(sata_phy->rst);
+ if (ret)
+ goto disable_clk;
+
+ ret = wait_for_phy_ready(sata_phy->regmap, SATA_P0_PHY_STAT,
+ SATA_P0_PHY_READY, 1);
+ if (ret < 0) {
+ dev_err(&sata_phy->phy->dev, "PHY READY check failed\n");
+ goto disable_clk;
+ }
+
+ return 0;
+
+disable_clk:
+ clk_disable_unprepare(sata_phy->clk);
+ return ret;
+}
+
+static int eic7700_sata_phy_exit(struct phy *phy)
+{
+ struct eic7700_sata_phy *sata_phy = phy_get_drvdata(phy);
+ int ret;
+
+ ret = reset_control_assert(sata_phy->rst);
+ if (ret)
+ return ret;
+
+ clk_disable_unprepare(sata_phy->clk);
+
+ return 0;
+}
+
+static const struct phy_ops eic7700_sata_phy_ops = {
+ .init = eic7700_sata_phy_init,
+ .exit = eic7700_sata_phy_exit,
+ .owner = THIS_MODULE,
+};
+
+static void eic7700_get_tuning_param(struct device_node *np,
+ struct eic7700_sata_phy *sata_phy)
+{
+ if (of_property_read_u32_array
+ (np, "eswin,tx-amplitude-tuning",
+ sata_phy->tx_amplitude_tuning_val,
+ ARRAY_SIZE(sata_phy->tx_amplitude_tuning_val))) {
+ sata_phy->tx_amplitude_tuning_val[0] =
+ SATA_P0_PHY_TX_AMPLITUDE_GEN1_DEFAULT;
+ sata_phy->tx_amplitude_tuning_val[1] =
+ SATA_P0_PHY_TX_AMPLITUDE_GEN2_DEFAULT;
+ sata_phy->tx_amplitude_tuning_val[2] =
+ SATA_P0_PHY_TX_AMPLITUDE_GEN3_DEFAULT;
+ }
+
+ if (of_property_read_u32_array
+ (np, "eswin,tx-preemph-tuning",
+ sata_phy->tx_preemph_tuning_val,
+ ARRAY_SIZE(sata_phy->tx_preemph_tuning_val))) {
+ sata_phy->tx_preemph_tuning_val[0] =
+ SATA_P0_PHY_TX_PREEMPH_GEN1_DEFAULT;
+ sata_phy->tx_preemph_tuning_val[1] =
+ SATA_P0_PHY_TX_PREEMPH_GEN2_DEFAULT;
+ sata_phy->tx_preemph_tuning_val[2] =
+ SATA_P0_PHY_TX_PREEMPH_GEN3_DEFAULT;
+ }
+}
+
+static int eic7700_sata_phy_probe(struct platform_device *pdev)
+{
+ struct eic7700_sata_phy *sata_phy;
+ struct phy_provider *phy_provider;
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct resource *res;
+ void __iomem *regs;
+
+ sata_phy = devm_kzalloc(dev, sizeof(*sata_phy), GFP_KERNEL);
+ if (!sata_phy)
+ return -ENOMEM;
+
+ /*
+ * Map the I/O resource with platform_get_resource and devm_ioremap
+ * instead of the devm_platform_ioremap_resource API, because the
+ * address region of the SATA‑PHY falls into the region of the HSP
+ * clock & reset that has already been obtained by the HSP
+ * clock‑and‑reset driver.
+ */
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res)
+ return -ENOENT;
+
+ regs = devm_ioremap(dev, res->start, resource_size(res));
+ if (IS_ERR(regs))
+ return PTR_ERR(regs);
+
+ sata_phy->regmap = devm_regmap_init_mmio
+ (dev, regs, &eic7700_sata_phy_regmap_config);
+ if (IS_ERR(sata_phy->regmap))
+ return dev_err_probe(dev, PTR_ERR(sata_phy->regmap),
+ "failed to init regmap\n");
+
+ dev_set_drvdata(dev, sata_phy);
+
+ eic7700_get_tuning_param(np, sata_phy);
+
+ sata_phy->clk = devm_clk_get(dev, "phy");
+ if (IS_ERR(sata_phy->clk))
+ return PTR_ERR(sata_phy->clk);
+
+ sata_phy->rst = devm_reset_control_array_get_exclusive(dev);
+ if (IS_ERR(sata_phy->rst))
+ return dev_err_probe(dev, PTR_ERR(sata_phy->rst),
+ "failed to get reset control\n");
+
+ sata_phy->phy = devm_phy_create(dev, NULL, &eic7700_sata_phy_ops);
+ if (IS_ERR(sata_phy->phy))
+ return dev_err_probe(dev, PTR_ERR(sata_phy->phy),
+ "failed to create PHY\n");
+
+ phy_set_drvdata(sata_phy->phy, sata_phy);
+
+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+ if (IS_ERR(phy_provider))
+ return dev_err_probe(dev, PTR_ERR(phy_provider),
+ "failed to register PHY provider\n");
+
+ return 0;
+}
+
+static const struct of_device_id eic7700_sata_phy_of_match[] = {
+ { .compatible = "eswin,eic7700-sata-phy" },
+ { },
+};
+MODULE_DEVICE_TABLE(of, eic7700_sata_phy_of_match);
+
+static struct platform_driver eic7700_sata_phy_driver = {
+ .probe = eic7700_sata_phy_probe,
+ .driver = {
+ .of_match_table = eic7700_sata_phy_of_match,
+ .name = "eic7700-sata-phy",
+ }
+};
+module_platform_driver(eic7700_sata_phy_driver);
+
+MODULE_DESCRIPTION("SATA PHY driver for the ESWIN EIC7700 SoC");
+MODULE_AUTHOR("Yulin Lu <luyulin@eswincomputing.com>");
+MODULE_LICENSE("GPL");
--
2.25.1
[-- Attachment #2: Type: text/plain, Size: 112 bytes --]
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^ permalink raw reply related
* Re: [PATCH next] phy: google: fix build dependency for Google Tensor USB PHY
From: André Draszik @ 2026-01-23 6:28 UTC (permalink / raw)
To: Roy Luo
Cc: Vinod Koul, Neil Armstrong, Peter Griffin, Tudor Ambarus,
Joy Chakraborty, Naveen Kumar, linux-phy, linux-kernel,
linux-arm-kernel, linux-samsung-soc, kernel test robot
In-Reply-To: <CA+zupgw5H5rumo+DxaTfA_=bcvjbBOivm6R+Pw31jgE-sMyEtw@mail.gmail.com>
Hi Roy,
On Thu, 2026-01-22 at 11:00 -0800, Roy Luo wrote:
> On Thu, Jan 22, 2026 at 2:39 AM André Draszik <andre.draszik@linaro.org> wrote:
> >
> > Hi Roy,
> >
> > On Wed, 2026-01-21 at 22:21 +0000, Roy Luo wrote:
> > > The Google Tensor USB PHY driver uses the Type-C switch framework to
> > > handle orientation changes. However, the Kconfig did not specify a
> > > dependency on the TYPEC framework, leading to undefined reference
> > > errors when building for architectures or configurations where
> > > CONFIG_TYPEC is disabled or configured as a module.
> > >
> > > Add 'depends on TYPEC' to the PHY_GOOGLE_USB entry to ensure all
> > > required symbols are available during linking.
> > >
> > > Fixes: cbce66669c82 ("phy: Add Google Tensor SoC USB PHY driver")
> > > Reported-by: kernel test robot <lkp@intel.com>
> > > Closes: https://lore.kernel.org/oe-kbuild-all/202601210825.ELrpQeED-lkp@intel.com/
> > > Signed-off-by: Roy Luo <royluo@google.com>
> > > ---
> > > drivers/phy/Kconfig | 1 +
> > > 1 file changed, 1 insertion(+)
> > >
> > > diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> > > index 142e7b0ef2efb9209781800ee47b820a91b115ae..5531ff31d8156cb164c32e3e52d4a57b26a62d8d 100644
> > > --- a/drivers/phy/Kconfig
> > > +++ b/drivers/phy/Kconfig
> > > @@ -49,6 +49,7 @@ config GENERIC_PHY_MIPI_DPHY
> > >
> > > config PHY_GOOGLE_USB
> > > tristate "Google Tensor SoC USB PHY driver"
> > > + depends on TYPEC
> >
> > Can you make this
> >
> > depends on TYPEC || COMPILE_TEST
> >
> > to allow some better test coverage?
> >
> > Cheers,
> > Andre
>
> Hi Andre,
>
> Whether to add COMPILE_TEST for build coverage was discussed in
> another thread [1]. My takeaway from that discussion is that
> COMPILE_TEST is intended to substitute for ARCH_XXX in build
> testing and should not be used without it. Once ARCH_GOOGLE is
> present, we can add "depends on (ARCH_GOOGLE || COMPILTE_TEST)".
COMPILE_TEST is not limited to ARCH_xxx. It allows drivers to be
compile tested even if the current build doesn't enable whatever
option (like TYPEC).
See also https://www.kernel.org/doc/html/latest/kbuild/kconfig-language.html#compile-testing
Cheers,
Andre'
>
> [1] https://lore.kernel.org/all/CA+zupgwgfKwPYqj8G2tNf4pEXNEWA+vL2WYJPhJ16xExgko7Dw@mail.gmail.com/
>
> Regards,
> Roy
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^ permalink raw reply
* Re: [PATCH v3] phy: fsl-imx8mq-usb: add debugfs to access control register
From: Xu Yang @ 2026-01-23 8:05 UTC (permalink / raw)
To: Andrew Lunn
Cc: Frank Li, vkoul, neil.armstrong, shawnguo, kernel, festevam,
jun.li, linux-phy, imx, linux-arm-kernel, linux-kernel
In-Reply-To: <06ae1272-9874-4ce7-9e4f-01d521a5f27f@lunn.ch>
On Tue, Jan 20, 2026 at 02:32:30PM +0100, Andrew Lunn wrote:
> > > Rather than reinvent the wheel, could you use regmap?
> > >
> > > https://elixir.bootlin.com/linux/v6.12.1/source/drivers/base/regmap/regmap-debugfs.c#L546
> > >
> > > Regmap should be able to provide a debugfs interface for you, no
> > > driver code needed.
> > >
> > > This will also help you with the abstraction between the core generic
> > > part of the PHY driver and the SoC integration glue. You pass the
> > > regmap to the core driver, and the funny muxing through two registers
> > > is hidden away from the core. If the next SoC integrated uses plan
> > > MMIO, that SoC glue driver can instantiate an MMIO regmap.
> > >
> > > Using regmap is a good idea for core generic drivers which can be
> > > integrated into SoCs in different ways. It hides the SoC details
> > > behind a well known API.
> >
> > Thanks for your suggestion.
> >
> > Using regmap is generally a good fit for reusable driver and I aggre it
> > helps abstract Soc-specific details.
> >
> > However, the regmap defbugfs has its own limitations:
> > 1. By default the register is read-only, add write operation require rebuild
> > the kernel which make it inconvenient to debug the issue on the spot.
>
> That is somewhat deliberate. We don't want a nice API which can be
> used for user space binary blob drivers. In networking, which is my
> more normal area, we pretty much reject any sort of write interface,
> other than official kernel APIs.
OK.
>
> > Refer to: "09c6ecd39410 regmap: Add support for writing to regmap registers
> > via debugfs"
> >
> > # ls /sys/kernel/debug/regmap/2-0050/ -l
> > total 0
> > -r-------- 1 root root 0 Jan 20 07:45 access
> > -r-------- 1 root root 0 Jan 20 07:45 name
> > -r-------- 1 root root 0 Jan 20 07:45 range
> > -r-------- 1 root root 0 Jan 20 07:45 registers
> >
> > 2. It can't randomly read specific one register with common linux commands. Besides,
> > the read operation is inefficient especially when the range is a bit large because
> > when you cat the register it always read and output all the registers.
>
> You are debugging. Do you need efficient output?
>
> If you have a specific debug tasks in mind, maybe you should be
> thinking of an official kernel API? In the past, there has been
> interest in getting SERDES eye information out of PHYs, and being able
> to change the configuration parameters of the eye. Could a generic API
> be added for that? Some of these PHYs also support pseudo random bit
> sequence generators, and there has been interest in adding APIs for
> configuring them.
After an internal discussion, we prefer to simply export Soc specific control
register access regmap in debugfs and let usespace read or write internal
registers according to CR port accessing sequence. With this, no needs for
a generic API for now.
Thanks for your comments.
Best Regards,
Xu Yang
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^ permalink raw reply
* Re: [PATCH v8 1/2] dt-bindings: phy: eswin: Document the EIC7700 SoC SATA PHY
From: Krzysztof Kozlowski @ 2026-01-23 8:18 UTC (permalink / raw)
To: Yulin Lu
Cc: vkoul, neil.armstrong, robh, krzk+dt, conor+dt, p.zabel,
linux-phy, devicetree, linux-kernel, ningyu, linmin, fenglin
In-Reply-To: <20260123024936.386-1-luyulin@eswincomputing.com>
On Fri, Jan 23, 2026 at 10:49:36AM +0800, Yulin Lu wrote:
> + eswin,tx-amplitude-tuning:
> + description: This adjusts the transmitter amplitude signal, and its value
> + is derived from eye diagram tuning. The three values correspond to Gen1,
> + Gen2, and Gen3 parameters respectively.
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> + items:
> + - description: Gen1 parameter.
> + minimum: 0
> + maximum: 0x7f
> + default: 0
> + - description: Gen2 parameter.
> + minimum: 0
> + maximum: 0x7f
> + default: 0
> + - description: Gen3 parameter.
> + minimum: 0
> + maximum: 0x7f
> + default: 0
I think defaults should be specified like this:
https://elixir.bootlin.com/linux/v6.19-rc5/source/Documentation/devicetree/bindings/sound/adi,adau7118.yaml#L54
> +
> + eswin,tx-preemph-tuning:
> + description: This adjusts the transmitter de-emphasis signal, and its value
> + is derived from eye diagram tuning. The three values correspond to Gen1,
> + Gen2, and Gen3 parameters respectively.
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> + items:
> + - description: Gen1 parameter.
> + minimum: 0
> + maximum: 0x3f
> + default: 0
> + - description: Gen2 parameter.
> + minimum: 0
> + maximum: 0x3f
> + default: 0
> + - description: Gen3 parameter.
> + minimum: 0
> + maximum: 0x3f
> + default: 0
Same here
Best regards,
Krzysztof
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^ permalink raw reply
* [PATCH net-next v2 00/14] net: stmmac: SerDes, PCS, BASE-X, and inband goodies
From: Russell King (Oracle) @ 2026-01-23 9:52 UTC (permalink / raw)
To: Andrew Lunn, Heiner Kallweit
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Konrad Dybcio, linux-arm-kernel, linux-arm-msm,
linux-phy, linux-stm32, Maxime Coquelin, Mohd Ayaan Anwar,
Neil Armstrong, netdev, Paolo Abeni, Vinod Koul
This is the v1 submission: if it doesn't get tested but review goes
well, it'll end up in net-next and mainline without testing on the
affected hardware!
Mentioned previously, I've been trying to sort out the PCS support in
stmmac, and this series represents the current state of play.
Previous posted patches centred around merely getting autonegotiation
to be configured correctly, to a point where the manual configuration
can be removed from the qcom-ethqos driver. The qcom-ethqos driver
uses both SGMII and 2500BASE-X, manually configuring the dwmac's
integrated PCS appropriately.
This *untested* series attempts to take this further. The patches:
- clean up qcom-ethqos only-written mac_base member.
- convert qcom-ethqos to use the set_clk_tx_rate() method for setting
the link clock rate.
- add support for phy_set_mode_ext() to the qcom "SGMII" ethernet
SerDes driver (which is really only what it needs. Note that
phy_set_mode_ext() is an expected call to be made, where as
phy_set_speed() is optional and not. See PHY documentation.)
- add platform-glue independent SerDes support to the stmmac core
driver. Currently, only qcom-ethqos will make use of this, and
I suspect as we haven't had this, it's going to be difficult to
convert other platform glue to use this - but had this existed
earlier, we could've pushed people to use PHY to abstract some
of the platform glue differences. Adding it now makes it available
for future platform glue.
- convert qcom-ethqos to use this core SerDes support.
- arrange for stmmac_pcs.c to supply the phy_intf_sel field value
if the integrated PCS will be used. (PHY_INTF_SEL_SGMII requires
the integrated PCS rather than an external PCS.)
- add BASE-X support to the integrated PCS driver, and use it for
BASE-X modes. This fully supports in-band mode, including reading
the link partner advertisement.
- add in-band support for SGMII, reading the state from the RGSMII
status field.
As we leave qcom-ethqos' manual configuration of the PCS in place at
the moment, the last patch adds reporting of any changes in its
configuration that the qcom-ethqos driver does beyond what phylink
requested, thus providing a path to debug and eventually remove
qcom-ethqos' manual configuration.
One patch is not included in this set - which adds a phy_intf_sel
value for external PCS (using PHY_INTF_SEL_GMII_MII). I believe all
external PCS use this mode when connected to a MAC capable of up to
2.5G. However, no platform glue that provides the mac_select_pcs()
method also provide the set_phy_intf_sel() method, so we can safely
ignore this for now.
I would like to get this into net-next before the next merge window,
so testing would be appreciated. If there are issues with these patches
applied, please check whether the issue exists without these patches
and only report regressions caused by this patch set. For example,
I'm aware that qcom-ethqos has issues with 10Mbps mode due to an AQR
PHY being insanely provisioned to use SGMII in 1000M mode but with
rate matching with 10M media. This is not an issue that is relevant
to this patch series, but a problem with the PHY provisioning.
rfc->v1:
- fix SGMII link status
- avoid calling phy_get_mode() if PHY is null
v2:
- fix further AI review bot dribble that could've been raised on
the rfc version but wasn't.
drivers/net/ethernet/stmicro/stmmac/Makefile | 2 +-
drivers/net/ethernet/stmicro/stmmac/common.h | 1 -
.../ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 74 ++-----
drivers/net/ethernet/stmicro/stmmac/dwmac1000.h | 12 +-
.../net/ethernet/stmicro/stmmac/dwmac1000_core.c | 11 +-
drivers/net/ethernet/stmicro/stmmac/dwmac4.h | 10 +-
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c | 10 +-
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 69 +++++--
drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c | 222 +++++++++++++++++++--
drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h | 53 ++---
.../net/ethernet/stmicro/stmmac/stmmac_serdes.c | 111 +++++++++++
.../net/ethernet/stmicro/stmmac/stmmac_serdes.h | 16 ++
drivers/phy/qualcomm/phy-qcom-sgmii-eth.c | 43 ++++
include/linux/stmmac.h | 2 +
14 files changed, 491 insertions(+), 145 deletions(-)
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
--
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^ permalink raw reply
* [PATCH net-next v2 01/14] net: stmmac: qcom-ethqos: remove mac_base
From: Russell King (Oracle) @ 2026-01-23 9:53 UTC (permalink / raw)
To: Andrew Lunn, Heiner Kallweit
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, linux-arm-kernel, linux-arm-msm, linux-phy,
linux-stm32, Maxime Chevallier, Maxime Coquelin, Mohd Ayaan Anwar,
Neil Armstrong, netdev, Paolo Abeni, Vinod Koul
In-Reply-To: <aXNEwBW3OA1xLEUj@shell.armlinux.org.uk>
In commit 9b443e58a896 ("net: stmmac: qcom-ethqos: remove MAC_CTRL_REG
modification"), ethqos->mac_base is only written, never read. Let's
remove it.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
index 0826a7bd32ff..869f924f3cde 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
@@ -100,7 +100,6 @@ struct ethqos_emac_driver_data {
struct qcom_ethqos {
struct platform_device *pdev;
void __iomem *rgmii_base;
- void __iomem *mac_base;
int (*configure_func)(struct qcom_ethqos *ethqos, int speed);
unsigned int link_clk_rate;
@@ -772,8 +771,6 @@ static int qcom_ethqos_probe(struct platform_device *pdev)
return dev_err_probe(dev, PTR_ERR(ethqos->rgmii_base),
"Failed to map rgmii resource\n");
- ethqos->mac_base = stmmac_res.addr;
-
data = of_device_get_match_data(dev);
ethqos->por = data->por;
ethqos->num_por = data->num_por;
--
2.47.3
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^ permalink raw reply related
* [PATCH net-next v2 02/14] net: stmmac: qcom-ethqos: convert to set_clk_tx_rate() method
From: Russell King (Oracle) @ 2026-01-23 9:53 UTC (permalink / raw)
To: Andrew Lunn, Heiner Kallweit
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, linux-arm-kernel, linux-arm-msm, linux-phy,
linux-stm32, Maxime Chevallier, Maxime Coquelin, Mohd Ayaan Anwar,
Neil Armstrong, netdev, Paolo Abeni, Vinod Koul
In-Reply-To: <aXNEwBW3OA1xLEUj@shell.armlinux.org.uk>
Set the RGMII link clock using the set_clk_tx_rate() method rather than
coding it into the .fix_mac_speed() method. This simplifies ethqos's
ethqos_fix_mac_speed().
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
.../stmicro/stmmac/dwmac-qcom-ethqos.c | 21 ++++++++++---------
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
index 869f924f3cde..80ea69fc8ee5 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
@@ -102,7 +102,6 @@ struct qcom_ethqos {
void __iomem *rgmii_base;
int (*configure_func)(struct qcom_ethqos *ethqos, int speed);
- unsigned int link_clk_rate;
struct clk *link_clk;
struct phy *serdes_phy;
int serdes_speed;
@@ -174,19 +173,20 @@ static void rgmii_dump(void *priv)
rgmii_readl(ethqos, EMAC_SYSTEM_LOW_POWER_DEBUG));
}
-static void
-ethqos_update_link_clk(struct qcom_ethqos *ethqos, int speed)
+static int ethqos_set_clk_tx_rate(void *bsp_priv, struct clk *clk_tx_i,
+ phy_interface_t interface, int speed)
{
+ struct qcom_ethqos *ethqos = bsp_priv;
long rate;
- if (!phy_interface_mode_is_rgmii(ethqos->phy_mode))
- return;
+ if (!phy_interface_mode_is_rgmii(interface))
+ return 0;
rate = rgmii_clock(speed);
- if (rate > 0)
- ethqos->link_clk_rate = rate * 2;
+ if (rate < 0)
+ return rate;
- clk_set_rate(ethqos->link_clk, ethqos->link_clk_rate);
+ return clk_set_rate(ethqos->link_clk, rate * 2);
}
static void
@@ -645,7 +645,6 @@ static void ethqos_fix_mac_speed(void *priv, int speed, unsigned int mode)
struct qcom_ethqos *ethqos = priv;
qcom_ethqos_set_sgmii_loopback(ethqos, false);
- ethqos_update_link_clk(ethqos, speed);
ethqos_configure(ethqos, speed);
}
@@ -797,10 +796,12 @@ static int qcom_ethqos_probe(struct platform_device *pdev)
"Failed to get serdes phy\n");
ethqos->serdes_speed = SPEED_1000;
- ethqos_update_link_clk(ethqos, SPEED_1000);
+ ethqos_set_clk_tx_rate(ethqos, NULL, plat_dat->phy_interface,
+ SPEED_1000);
ethqos_set_func_clk_en(ethqos);
plat_dat->bsp_priv = ethqos;
+ plat_dat->set_clk_tx_rate = ethqos_set_clk_tx_rate;
plat_dat->fix_mac_speed = ethqos_fix_mac_speed;
plat_dat->dump_debug_regs = rgmii_dump;
plat_dat->ptp_clk_freq_config = ethqos_ptp_clk_freq_config;
--
2.47.3
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* [PATCH net-next v2 03/14] phy: qcom-sgmii-eth: add .set_mode() and .validate() methods
From: Russell King (Oracle) @ 2026-01-23 9:53 UTC (permalink / raw)
To: Andrew Lunn, Heiner Kallweit
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, linux-arm-kernel, linux-arm-msm, linux-phy,
linux-stm32, Maxime Chevallier, Maxime Coquelin, Mohd Ayaan Anwar,
Neil Armstrong, netdev, Paolo Abeni, Vinod Koul
In-Reply-To: <aXNEwBW3OA1xLEUj@shell.armlinux.org.uk>
qcom-sgmii-eth is an Ethernet SerDes supporting only Ethernet mode
using SGMII, 1000BASE-X and 2500BASE-X.
Add an implementation of the .set_mode() method, which can be used
instead of or as well as the .set_speed() method. The Ethernet
interface modes mentioned above all have a fixed data rate, so
setting the mode is sufficient to fully specify the operating
parameters.
Add an implementation of the .validate() method, which will be
necessary to allow discovery of the SerDes capabilities for platform
independent SerDes support in the stmmac network driver.
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Acked-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
drivers/phy/qualcomm/phy-qcom-sgmii-eth.c | 43 +++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-sgmii-eth.c b/drivers/phy/qualcomm/phy-qcom-sgmii-eth.c
index 5b1c82459c12..4ea3dce7719f 100644
--- a/drivers/phy/qualcomm/phy-qcom-sgmii-eth.c
+++ b/drivers/phy/qualcomm/phy-qcom-sgmii-eth.c
@@ -7,6 +7,7 @@
#include <linux/ethtool.h>
#include <linux/module.h>
#include <linux/of.h>
+#include <linux/phy.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
@@ -286,6 +287,37 @@ static int qcom_dwmac_sgmii_phy_power_off(struct phy *phy)
return 0;
}
+static int qcom_dwmac_sgmii_phy_speed(enum phy_mode mode, int submode)
+{
+ if (mode != PHY_MODE_ETHERNET)
+ return -EINVAL;
+
+ if (submode == PHY_INTERFACE_MODE_SGMII ||
+ submode == PHY_INTERFACE_MODE_1000BASEX)
+ return SPEED_1000;
+
+ if (submode == PHY_INTERFACE_MODE_2500BASEX)
+ return SPEED_2500;
+
+ return -EINVAL;
+}
+
+static int qcom_dwmac_sgmii_phy_set_mode(struct phy *phy, enum phy_mode mode,
+ int submode)
+{
+ struct qcom_dwmac_sgmii_phy_data *data = phy_get_drvdata(phy);
+ int speed;
+
+ speed = qcom_dwmac_sgmii_phy_speed(mode, submode);
+ if (speed < 0)
+ return speed;
+
+ if (speed != data->speed)
+ data->speed = speed;
+
+ return qcom_dwmac_sgmii_phy_calibrate(phy);
+}
+
static int qcom_dwmac_sgmii_phy_set_speed(struct phy *phy, int speed)
{
struct qcom_dwmac_sgmii_phy_data *data = phy_get_drvdata(phy);
@@ -296,10 +328,21 @@ static int qcom_dwmac_sgmii_phy_set_speed(struct phy *phy, int speed)
return qcom_dwmac_sgmii_phy_calibrate(phy);
}
+static int qcom_dwmac_sgmii_phy_validate(struct phy *phy, enum phy_mode mode,
+ int submode,
+ union phy_configure_opts *opts)
+{
+ int ret = qcom_dwmac_sgmii_phy_speed(mode, submode);
+
+ return ret < 0 ? ret : 0;
+}
+
static const struct phy_ops qcom_dwmac_sgmii_phy_ops = {
.power_on = qcom_dwmac_sgmii_phy_power_on,
.power_off = qcom_dwmac_sgmii_phy_power_off,
+ .set_mode = qcom_dwmac_sgmii_phy_set_mode,
.set_speed = qcom_dwmac_sgmii_phy_set_speed,
+ .validate = qcom_dwmac_sgmii_phy_validate,
.calibrate = qcom_dwmac_sgmii_phy_calibrate,
.owner = THIS_MODULE,
};
--
2.47.3
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* [PATCH net-next v2 04/14] net: stmmac: wrap phylink's rx_clk_stop functions
From: Russell King (Oracle) @ 2026-01-23 9:53 UTC (permalink / raw)
To: Andrew Lunn, Heiner Kallweit
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, linux-arm-kernel, linux-arm-msm, linux-phy,
linux-stm32, Maxime Chevallier, Maxime Coquelin, Mohd Ayaan Anwar,
Neil Armstrong, netdev, Paolo Abeni, Vinod Koul
In-Reply-To: <aXNEwBW3OA1xLEUj@shell.armlinux.org.uk>
With generic SerDes support, stmmac will need to do more work to ensure
that clk_rx_i is running in all configurations. Rather than turn each
site that calls phylink_rx_clk_stop_xxx() into a list of functions,
move these to their own pair of functions so that they can be
augmented at a single location.
Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
.../net/ethernet/stmicro/stmmac/stmmac_main.c | 32 ++++++++++++-------
1 file changed, 21 insertions(+), 11 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index c2589f02ff7e..24a2555ca329 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -3547,6 +3547,16 @@ static void stmmac_safety_feat_configuration(struct stmmac_priv *priv)
}
}
+static void stmmac_clk_rx_i_require(struct stmmac_priv *priv)
+{
+ phylink_rx_clk_stop_block(priv->phylink);
+}
+
+static void stmmac_clk_rx_i_release(struct stmmac_priv *priv)
+{
+ phylink_rx_clk_stop_unblock(priv->phylink);
+}
+
/**
* stmmac_hw_setup - setup mac in a usable state.
* @dev : pointer to the device structure.
@@ -3578,12 +3588,12 @@ static int stmmac_hw_setup(struct net_device *dev)
* Block the receive clock stop for LPI mode at the PHY in case
* the link is established with EEE mode active.
*/
- phylink_rx_clk_stop_block(priv->phylink);
+ stmmac_clk_rx_i_require(priv);
/* DMA initialization and SW reset */
ret = stmmac_init_dma_engine(priv);
if (ret < 0) {
- phylink_rx_clk_stop_unblock(priv->phylink);
+ stmmac_clk_rx_i_release(priv);
netdev_err(priv->dev, "%s: DMA engine initialization failed\n",
__func__);
return ret;
@@ -3591,7 +3601,7 @@ static int stmmac_hw_setup(struct net_device *dev)
/* Copy the MAC addr into the HW */
stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0);
- phylink_rx_clk_stop_unblock(priv->phylink);
+ stmmac_clk_rx_i_release(priv);
/* Initialize the MAC Core */
stmmac_core_init(priv, priv->hw, dev);
@@ -3670,9 +3680,9 @@ static int stmmac_hw_setup(struct net_device *dev)
/* Start the ball rolling... */
stmmac_start_all_dma(priv);
- phylink_rx_clk_stop_block(priv->phylink);
+ stmmac_clk_rx_i_require(priv);
stmmac_set_hw_vlan_mode(priv, priv->hw);
- phylink_rx_clk_stop_unblock(priv->phylink);
+ stmmac_clk_rx_i_release(priv);
return 0;
}
@@ -6107,9 +6117,9 @@ static int stmmac_set_features(struct net_device *netdev,
else
priv->hw->hw_vlan_en = false;
- phylink_rx_clk_stop_block(priv->phylink);
+ stmmac_clk_rx_i_require(priv);
stmmac_set_hw_vlan_mode(priv, priv->hw);
- phylink_rx_clk_stop_unblock(priv->phylink);
+ stmmac_clk_rx_i_release(priv);
return 0;
}
@@ -6378,9 +6388,9 @@ static int stmmac_set_mac_address(struct net_device *ndev, void *addr)
if (ret)
goto set_mac_error;
- phylink_rx_clk_stop_block(priv->phylink);
+ stmmac_clk_rx_i_require(priv);
stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0);
- phylink_rx_clk_stop_unblock(priv->phylink);
+ stmmac_clk_rx_i_release(priv);
set_mac_error:
pm_runtime_put(priv->device);
@@ -8192,11 +8202,11 @@ int stmmac_resume(struct device *dev)
stmmac_init_timestamping(priv);
stmmac_init_coalesce(priv);
- phylink_rx_clk_stop_block(priv->phylink);
+ stmmac_clk_rx_i_require(priv);
stmmac_set_rx_mode(ndev);
stmmac_restore_hw_vlan_rx_fltr(priv, ndev, priv->hw);
- phylink_rx_clk_stop_unblock(priv->phylink);
+ stmmac_clk_rx_i_release(priv);
stmmac_enable_all_queues(priv);
stmmac_enable_all_dma_irq(priv);
--
2.47.3
--
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https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH net-next v2 05/14] net: stmmac: add stmmac core serdes support
From: Russell King (Oracle) @ 2026-01-23 9:53 UTC (permalink / raw)
To: Andrew Lunn, Heiner Kallweit
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, linux-arm-kernel, linux-arm-msm, linux-phy,
linux-stm32, Maxime Chevallier, Maxime Coquelin, Mohd Ayaan Anwar,
Neil Armstrong, netdev, Paolo Abeni, Vinod Koul
In-Reply-To: <aXNEwBW3OA1xLEUj@shell.armlinux.org.uk>
Rather than having platform glue implement SerDes PHY support, add it
to the core driver, specifically to the stmmac integrated PCS driver
as the SerDes is connected to the integrated PCS.
Platforms using external PCS can also populate plat->serdes, and the
core driver will call phy_init() and phy_exit() when the administrative
state of the interface changes, but the other phy methods will not be
called.
Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
--
rfc->v1: avoid calling phy_get_mode() with NULL serdes PHY
v2: add cleanup when dwmac_serdes_set_mode() fails, because AI allegedly
knows better than the author and phylink maintainer, even though this
will result in dwmac_serdes_power_off() being called multiple times
and producing a kernel warning. But if it makes AI happy, then it must
be a good thing. It'll also make Vladimir happy.
---
drivers/net/ethernet/stmicro/stmmac/Makefile | 2 +-
.../net/ethernet/stmicro/stmmac/stmmac_main.c | 14 ++-
.../net/ethernet/stmicro/stmmac/stmmac_pcs.c | 40 ++++++-
.../net/ethernet/stmicro/stmmac/stmmac_pcs.h | 1 +
.../ethernet/stmicro/stmmac/stmmac_serdes.c | 111 ++++++++++++++++++
.../ethernet/stmicro/stmmac/stmmac_serdes.h | 16 +++
include/linux/stmmac.h | 2 +
7 files changed, 182 insertions(+), 4 deletions(-)
create mode 100644 drivers/net/ethernet/stmicro/stmmac/stmmac_serdes.c
create mode 100644 drivers/net/ethernet/stmicro/stmmac/stmmac_serdes.h
diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile
index c9263987ef8d..a3c2cd5d0c91 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Makefile
+++ b/drivers/net/ethernet/stmicro/stmmac/Makefile
@@ -7,7 +7,7 @@ stmmac-objs:= stmmac_main.o stmmac_ethtool.o stmmac_mdio.o ring_mode.o \
dwmac4_dma.o dwmac4_lib.o dwmac4_core.o dwmac5.o hwif.o \
stmmac_tc.o dwxgmac2_core.o dwxgmac2_dma.o dwxgmac2_descs.o \
stmmac_xdp.o stmmac_est.o stmmac_fpe.o stmmac_vlan.o \
- stmmac_pcs.o $(stmmac-y)
+ stmmac_pcs.o stmmac_serdes.o $(stmmac-y)
stmmac-$(CONFIG_STMMAC_SELFTESTS) += stmmac_selftests.o
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 24a2555ca329..6c515f9efbe7 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -48,6 +48,7 @@
#include "stmmac_fpe.h"
#include "stmmac.h"
#include "stmmac_pcs.h"
+#include "stmmac_serdes.h"
#include "stmmac_xdp.h"
#include <linux/reset.h>
#include <linux/of_mdio.h>
@@ -3549,12 +3550,16 @@ static void stmmac_safety_feat_configuration(struct stmmac_priv *priv)
static void stmmac_clk_rx_i_require(struct stmmac_priv *priv)
{
+ dwmac_serdes_power_on(priv);
+ /* Only sets the SerDes mode if it wasn't already configured. */
+ dwmac_serdes_init_mode(priv, priv->plat->phy_interface);
phylink_rx_clk_stop_block(priv->phylink);
}
static void stmmac_clk_rx_i_release(struct stmmac_priv *priv)
{
phylink_rx_clk_stop_unblock(priv->phylink);
+ dwmac_serdes_power_off(priv);
}
/**
@@ -4152,10 +4157,14 @@ static int stmmac_open(struct net_device *dev)
if (ret)
goto err_runtime_pm;
- ret = __stmmac_open(dev, dma_conf);
+ ret = dwmac_serdes_init(priv);
if (ret)
goto err_disconnect_phy;
+ ret = __stmmac_open(dev, dma_conf);
+ if (ret)
+ goto err_serdes;
+
kfree(dma_conf);
/* We may have called phylink_speed_down before */
@@ -4163,6 +4172,8 @@ static int stmmac_open(struct net_device *dev)
return ret;
+err_serdes:
+ dwmac_serdes_exit(priv);
err_disconnect_phy:
phylink_disconnect_phy(priv->phylink);
err_runtime_pm:
@@ -4226,6 +4237,7 @@ static int stmmac_release(struct net_device *dev)
__stmmac_release(dev);
+ dwmac_serdes_exit(priv);
phylink_disconnect_phy(priv->phylink);
pm_runtime_put(priv->device);
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
index 2f826fe7229b..10a2eb903d2a 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
@@ -1,12 +1,27 @@
// SPDX-License-Identifier: GPL-2.0-only
#include "stmmac.h"
#include "stmmac_pcs.h"
+#include "stmmac_serdes.h"
static int dwmac_integrated_pcs_enable(struct phylink_pcs *pcs)
{
struct stmmac_pcs *spcs = phylink_pcs_to_stmmac_pcs(pcs);
+ struct stmmac_priv *priv = spcs->priv;
+ int ret;
+
+ ret = dwmac_serdes_power_on(priv);
+ if (ret)
+ return ret;
+
+ if (spcs->interface != PHY_INTERFACE_MODE_NA) {
+ ret = dwmac_serdes_set_mode(priv, spcs->interface);
+ if (ret) {
+ dwmac_serdes_power_off(priv);
+ return ret;
+ }
+ }
- stmmac_mac_irq_modify(spcs->priv, 0, spcs->int_mask);
+ stmmac_mac_irq_modify(priv, 0, spcs->int_mask);
return 0;
}
@@ -14,8 +29,11 @@ static int dwmac_integrated_pcs_enable(struct phylink_pcs *pcs)
static void dwmac_integrated_pcs_disable(struct phylink_pcs *pcs)
{
struct stmmac_pcs *spcs = phylink_pcs_to_stmmac_pcs(pcs);
+ struct stmmac_priv *priv = spcs->priv;
+
+ stmmac_mac_irq_modify(priv, spcs->int_mask, 0);
- stmmac_mac_irq_modify(spcs->priv, spcs->int_mask, 0);
+ dwmac_serdes_power_off(priv);
}
static void dwmac_integrated_pcs_get_state(struct phylink_pcs *pcs,
@@ -32,6 +50,15 @@ static int dwmac_integrated_pcs_config(struct phylink_pcs *pcs,
bool permit_pause_to_mac)
{
struct stmmac_pcs *spcs = phylink_pcs_to_stmmac_pcs(pcs);
+ int ret;
+
+ if (spcs->interface != interface) {
+ ret = dwmac_serdes_set_mode(spcs->priv, interface);
+ if (ret)
+ return ret;
+
+ spcs->interface = interface;
+ }
dwmac_ctrl_ane(spcs->base, 0, 1, spcs->priv->hw->reverse_sgmii_enable);
@@ -71,6 +98,7 @@ int stmmac_integrated_pcs_init(struct stmmac_priv *priv, unsigned int offset,
u32 int_mask)
{
struct stmmac_pcs *spcs;
+ int ret;
spcs = devm_kzalloc(priv->device, sizeof(*spcs), GFP_KERNEL);
if (!spcs)
@@ -81,6 +109,14 @@ int stmmac_integrated_pcs_init(struct stmmac_priv *priv, unsigned int offset,
spcs->int_mask = int_mask;
spcs->pcs.ops = &dwmac_integrated_pcs_ops;
+ if (priv->plat->serdes) {
+ ret = dwmac_serdes_validate(priv, PHY_INTERFACE_MODE_SGMII);
+ if (ret)
+ dev_warn(priv->device,
+ "serdes does not support SGMII: %pe\n",
+ ERR_PTR(ret));
+ }
+
__set_bit(PHY_INTERFACE_MODE_SGMII, spcs->pcs.supported_interfaces);
priv->integrated_pcs = spcs;
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h
index c4e6b242d390..36bf75fdf478 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h
@@ -53,6 +53,7 @@ struct stmmac_pcs {
struct stmmac_priv *priv;
void __iomem *base;
u32 int_mask;
+ phy_interface_t interface;
struct phylink_pcs pcs;
};
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_serdes.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_serdes.c
new file mode 100644
index 000000000000..d46a071bc383
--- /dev/null
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_serdes.c
@@ -0,0 +1,111 @@
+#include <linux/phy/phy.h>
+
+#include "stmmac.h"
+#include "stmmac_serdes.h"
+
+static phy_interface_t dwmac_serdes_phy_modes[] = {
+ PHY_INTERFACE_MODE_SGMII,
+ PHY_INTERFACE_MODE_1000BASEX,
+ PHY_INTERFACE_MODE_2500BASEX
+};
+
+int dwmac_serdes_validate(struct stmmac_priv *priv, phy_interface_t interface)
+{
+ return phy_validate(priv->plat->serdes, PHY_MODE_ETHERNET, interface,
+ NULL);
+}
+
+int dwmac_serdes_init(struct stmmac_priv *priv)
+{
+ size_t i;
+ int ret;
+
+ if (!priv->plat->serdes)
+ return 0;
+
+ /* Encourage good implementation of the SerDes PHY driver, so that
+ * we can discover which Ethernet modes the SerDes supports.
+ * Unfortunately, some implementations are noisy (bad), others
+ * require phy_set_speed() to select the correct speed first
+ * (which then reprograms the SerDes, negating the whole point of
+ * phy_validate().) Weed out these incompatible implementations.
+ */
+ for (i = 0; i < ARRAY_SIZE(dwmac_serdes_phy_modes); i++) {
+ ret = phy_validate(priv->plat->serdes, PHY_MODE_ETHERNET,
+ dwmac_serdes_phy_modes[i], NULL);
+ if (ret == 0 || ret == -EOPNOTSUPP)
+ break;
+ }
+
+ if (ret == -EOPNOTSUPP)
+ dev_warn(priv->device,
+ "SerDes driver does not implement phy_validate()\n");
+ if (ret) {
+ /* The SerDes PHY failed validation, refuse to use it. */
+ dev_warn(priv->device,
+ "SerDes driver fails to validate SGMII, 1000BASE-X nor 2500BASE-X\n");
+ return -EINVAL;
+ }
+
+ ret = phy_init(priv->plat->serdes);
+ if (ret)
+ dev_err(priv->device, "failed to initialize SerDes: %pe\n",
+ ERR_PTR(ret));
+
+ return ret;
+}
+
+int dwmac_serdes_power_on(struct stmmac_priv *priv)
+{
+ int ret;
+
+ ret = phy_power_on(priv->plat->serdes);
+ if (ret)
+ dev_err(priv->device, "failed to power on SerDes: %pe\n",
+ ERR_PTR(ret));
+
+ return ret;
+}
+
+int dwmac_serdes_init_mode(struct stmmac_priv *priv, phy_interface_t interface)
+{
+ struct phy *serdes = priv->plat->serdes;
+
+ if (!serdes || phy_get_mode(serdes) == PHY_MODE_ETHERNET)
+ return 0;
+
+ return dwmac_serdes_set_mode(priv, interface);
+}
+
+int dwmac_serdes_set_mode(struct stmmac_priv *priv, phy_interface_t interface)
+{
+ struct phy *serdes = priv->plat->serdes;
+ int ret;
+
+ ret = phy_set_mode_ext(serdes, PHY_MODE_ETHERNET, interface);
+ if (ret)
+ dev_err(priv->device,
+ "failed to set SerDes mode %s: %pe\n",
+ phy_modes(interface), ERR_PTR(ret));
+
+ return ret;
+}
+
+void dwmac_serdes_power_off(struct stmmac_priv *priv)
+{
+ int ret;
+
+ ret = phy_power_off(priv->plat->serdes);
+ if (ret)
+ dev_err(priv->device, "failed to power off SerDes: %pe\n",
+ ERR_PTR(ret));
+}
+
+void dwmac_serdes_exit(struct stmmac_priv *priv)
+{
+ int ret = phy_exit(priv->plat->serdes);
+
+ if (ret)
+ dev_err(priv->device, "failed to shutdown SerDes: %pe\n",
+ ERR_PTR(ret));
+}
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_serdes.h b/drivers/net/ethernet/stmicro/stmmac/stmmac_serdes.h
new file mode 100644
index 000000000000..a31e6c9e0570
--- /dev/null
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_serdes.h
@@ -0,0 +1,16 @@
+#ifndef STMMAC_SERDES_H
+#define STMMAC_SERDES_H
+
+#include <linux/phy.h>
+
+struct stmmac_priv;
+
+int dwmac_serdes_validate(struct stmmac_priv *priv, phy_interface_t interface);
+int dwmac_serdes_init(struct stmmac_priv *priv);
+int dwmac_serdes_power_on(struct stmmac_priv *priv);
+int dwmac_serdes_init_mode(struct stmmac_priv *priv, phy_interface_t interface);
+int dwmac_serdes_set_mode(struct stmmac_priv *priv, phy_interface_t interface);
+void dwmac_serdes_power_off(struct stmmac_priv *priv);
+void dwmac_serdes_exit(struct stmmac_priv *priv);
+
+#endif
diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
index f1054b9c2d8a..4db506e5cf13 100644
--- a/include/linux/stmmac.h
+++ b/include/linux/stmmac.h
@@ -193,6 +193,7 @@ enum dwmac_core_type {
#define STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY BIT(13)
struct mac_device_info;
+struct phy;
struct plat_stmmacenet_data {
enum dwmac_core_type core_type;
@@ -222,6 +223,7 @@ struct plat_stmmacenet_data {
* that phylink uses.
*/
phy_interface_t phy_interface;
+ struct phy *serdes;
struct stmmac_mdio_bus_data *mdio_bus_data;
struct device_node *phy_node;
struct fwnode_handle *port_node;
--
2.47.3
--
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^ permalink raw reply related
* [PATCH net-next v2 06/14] net: stmmac: qcom-ethqos: convert to dwmac generic SerDes support
From: Russell King (Oracle) @ 2026-01-23 9:53 UTC (permalink / raw)
To: Andrew Lunn, Heiner Kallweit
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, linux-arm-kernel, linux-arm-msm, linux-phy,
linux-stm32, Maxime Chevallier, Maxime Coquelin, Mohd Ayaan Anwar,
Neil Armstrong, netdev, Paolo Abeni, Vinod Koul
In-Reply-To: <aXNEwBW3OA1xLEUj@shell.armlinux.org.uk>
Convert qcom-ethqos to use the dwmac core's generic SerDes support,
which will handle SerDes initialisation, powering, and mode setting.
Note that generic support requires the SerDes to support phy_validate()
in order to probe which PHY interface modes are supported, and
phy_set_mode_ext() to configure the appropriate PHY interface mode
(and thus the speed.)
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
.../stmicro/stmmac/dwmac-qcom-ethqos.c | 50 ++-----------------
1 file changed, 3 insertions(+), 47 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
index 80ea69fc8ee5..a0b893d3fbd4 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
@@ -103,8 +103,6 @@ struct qcom_ethqos {
int (*configure_func)(struct qcom_ethqos *ethqos, int speed);
struct clk *link_clk;
- struct phy *serdes_phy;
- int serdes_speed;
phy_interface_t phy_mode;
const struct ethqos_emac_por *por;
@@ -584,14 +582,6 @@ static int ethqos_configure_rgmii(struct qcom_ethqos *ethqos, int speed)
return 0;
}
-static void ethqos_set_serdes_speed(struct qcom_ethqos *ethqos, int speed)
-{
- if (ethqos->serdes_speed != speed) {
- phy_set_speed(ethqos->serdes_phy, speed);
- ethqos->serdes_speed = speed;
- }
-}
-
static void ethqos_pcs_set_inband(struct stmmac_priv *priv, bool enable)
{
stmmac_pcs_ctrl_ane(priv, enable, 0);
@@ -609,17 +599,14 @@ static int ethqos_configure_sgmii(struct qcom_ethqos *ethqos, int speed)
case SPEED_2500:
rgmii_setmask(ethqos, RGMII_CONFIG2_RGMII_CLK_SEL_CFG,
RGMII_IO_MACRO_CONFIG2);
- ethqos_set_serdes_speed(ethqos, SPEED_2500);
ethqos_pcs_set_inband(priv, false);
break;
case SPEED_1000:
rgmii_setmask(ethqos, RGMII_CONFIG2_RGMII_CLK_SEL_CFG,
RGMII_IO_MACRO_CONFIG2);
- ethqos_set_serdes_speed(ethqos, SPEED_1000);
ethqos_pcs_set_inband(priv, true);
break;
case SPEED_100:
- ethqos_set_serdes_speed(ethqos, SPEED_1000);
ethqos_pcs_set_inband(priv, true);
break;
case SPEED_10:
@@ -627,7 +614,6 @@ static int ethqos_configure_sgmii(struct qcom_ethqos *ethqos, int speed)
FIELD_PREP(RGMII_CONFIG_SGMII_CLK_DVDR,
SGMII_10M_RX_CLK_DVDR),
RGMII_IO_MACRO_CONFIG);
- ethqos_set_serdes_speed(ethqos, SPEED_1000);
ethqos_pcs_set_inband(priv, true);
break;
}
@@ -648,30 +634,6 @@ static void ethqos_fix_mac_speed(void *priv, int speed, unsigned int mode)
ethqos_configure(ethqos, speed);
}
-static int qcom_ethqos_serdes_powerup(struct net_device *ndev, void *priv)
-{
- struct qcom_ethqos *ethqos = priv;
- int ret;
-
- ret = phy_init(ethqos->serdes_phy);
- if (ret)
- return ret;
-
- ret = phy_power_on(ethqos->serdes_phy);
- if (ret)
- return ret;
-
- return phy_set_speed(ethqos->serdes_phy, ethqos->serdes_speed);
-}
-
-static void qcom_ethqos_serdes_powerdown(struct net_device *ndev, void *priv)
-{
- struct qcom_ethqos *ethqos = priv;
-
- phy_power_off(ethqos->serdes_phy);
- phy_exit(ethqos->serdes_phy);
-}
-
static int ethqos_clks_config(void *priv, bool enabled)
{
struct qcom_ethqos *ethqos = priv;
@@ -790,12 +752,11 @@ static int qcom_ethqos_probe(struct platform_device *pdev)
if (ret)
return ret;
- ethqos->serdes_phy = devm_phy_optional_get(dev, "serdes");
- if (IS_ERR(ethqos->serdes_phy))
- return dev_err_probe(dev, PTR_ERR(ethqos->serdes_phy),
+ plat_dat->serdes = devm_phy_optional_get(dev, "serdes");
+ if (IS_ERR(plat_dat->serdes))
+ return dev_err_probe(dev, PTR_ERR(plat_dat->serdes),
"Failed to get serdes phy\n");
- ethqos->serdes_speed = SPEED_1000;
ethqos_set_clk_tx_rate(ethqos, NULL, plat_dat->phy_interface,
SPEED_1000);
ethqos_set_func_clk_en(ethqos);
@@ -816,11 +777,6 @@ static int qcom_ethqos_probe(struct platform_device *pdev)
if (data->dma_addr_width)
plat_dat->host_dma_width = data->dma_addr_width;
- if (ethqos->serdes_phy) {
- plat_dat->serdes_powerup = qcom_ethqos_serdes_powerup;
- plat_dat->serdes_powerdown = qcom_ethqos_serdes_powerdown;
- }
-
/* Enable TSO on queue0 and enable TBS on rest of the queues */
for (i = 1; i < plat_dat->tx_queues_to_use; i++)
plat_dat->tx_queues_cfg[i].tbs_en = 1;
--
2.47.3
--
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https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH net-next v2 07/14] net: stmmac: move most PCS register definitions to stmmac_pcs.c
From: Russell King (Oracle) @ 2026-01-23 9:53 UTC (permalink / raw)
To: Andrew Lunn, Heiner Kallweit
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, linux-arm-kernel, linux-arm-msm, linux-phy,
linux-stm32, Maxime Chevallier, Maxime Coquelin, Mohd Ayaan Anwar,
Neil Armstrong, netdev, Paolo Abeni, Vinod Koul
In-Reply-To: <aXNEwBW3OA1xLEUj@shell.armlinux.org.uk>
Move most of the PCS register offset definitions to stmmac_pcs.c.
Since stmmac_pcs.c only ever passes zero into the register offset
macros, remove that ability, making them simple constant integer
definitions.
Add appropriate descriptions of the registers, pointing out their
similarity with their IEEE 802.3 counterparts. Make use of the
BMSR definitions for the GMAC_AN_STATUS register and remove the
driver private versions.
Note that BMSR_LSTATUS is non-low-latching, unlike it's 802.3z
counterpart.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
.../net/ethernet/stmicro/stmmac/stmmac_pcs.c | 22 +++++++++++++++----
.../net/ethernet/stmicro/stmmac/stmmac_pcs.h | 22 -------------------
2 files changed, 18 insertions(+), 26 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
index 10a2eb903d2a..ac588756e450 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
@@ -3,6 +3,20 @@
#include "stmmac_pcs.h"
#include "stmmac_serdes.h"
+/*
+ * GMAC_AN_STATUS is equivalent to MII_BMSR
+ * GMAC_ANE_ADV is equivalent to 802.3z MII_ADVERTISE
+ * GMAC_ANE_LPA is equivalent to 802.3z MII_LPA
+ * GMAC_ANE_EXP is equivalent to MII_EXPANSION
+ * GMAC_TBI is equivalent to MII_ESTATUS
+ *
+ * ADV, LPA and EXP are only available for the TBI and RTBI modes.
+ */
+#define GMAC_AN_STATUS 0x04 /* AN status */
+#define GMAC_ANE_ADV 0x08 /* ANE Advertisement */
+#define GMAC_ANE_LPA 0x0c /* ANE link partener ability */
+#define GMAC_TBI 0x14 /* TBI extend status */
+
static int dwmac_integrated_pcs_enable(struct phylink_pcs *pcs)
{
struct stmmac_pcs *spcs = phylink_pcs_to_stmmac_pcs(pcs);
@@ -76,11 +90,11 @@ void stmmac_integrated_pcs_irq(struct stmmac_priv *priv, u32 status,
struct stmmac_extra_stats *x)
{
struct stmmac_pcs *spcs = priv->integrated_pcs;
- u32 val = readl(spcs->base + GMAC_AN_STATUS(0));
+ u32 val = readl(spcs->base + GMAC_AN_STATUS);
if (status & PCS_ANE_IRQ) {
x->irq_pcs_ane_n++;
- if (val & GMAC_AN_STATUS_ANC)
+ if (val & BMSR_ANEGCOMPLETE)
dev_info(priv->device,
"PCS ANE process completed\n");
}
@@ -88,9 +102,9 @@ void stmmac_integrated_pcs_irq(struct stmmac_priv *priv, u32 status,
if (status & PCS_LINK_IRQ) {
x->irq_pcs_link_n++;
dev_info(priv->device, "PCS Link %s\n",
- val & GMAC_AN_STATUS_LS ? "Up" : "Down");
+ val & BMSR_LSTATUS ? "Up" : "Down");
- phylink_pcs_change(&spcs->pcs, val & GMAC_AN_STATUS_LS);
+ phylink_pcs_change(&spcs->pcs, val & BMSR_LSTATUS);
}
}
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h
index 36bf75fdf478..887c4ff302aa 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h
@@ -16,13 +16,6 @@
/* PCS registers (AN/TBI/SGMII/RGMII) offsets */
#define GMAC_AN_CTRL(x) (x) /* AN control */
-#define GMAC_AN_STATUS(x) (x + 0x4) /* AN status */
-
-/* ADV, LPA and EXP are only available for the TBI and RTBI interfaces */
-#define GMAC_ANE_ADV(x) (x + 0x8) /* ANE Advertisement */
-#define GMAC_ANE_LPA(x) (x + 0xc) /* ANE link partener ability */
-#define GMAC_ANE_EXP(x) (x + 0x10) /* ANE expansion */
-#define GMAC_TBI(x) (x + 0x14) /* TBI extend status */
/* AN Configuration defines */
#define GMAC_AN_CTRL_RAN BIT_U32(9) /* Restart Auto-Negotiation */
@@ -32,21 +25,6 @@
#define GMAC_AN_CTRL_LR BIT_U32(17) /* Lock to Reference */
#define GMAC_AN_CTRL_SGMRAL BIT_U32(18) /* SGMII RAL Control */
-/* AN Status defines */
-#define GMAC_AN_STATUS_LS BIT_U32(2) /* Link Status 0:down 1:up */
-#define GMAC_AN_STATUS_ANA BIT_U32(3) /* Auto-Negotiation Ability */
-#define GMAC_AN_STATUS_ANC BIT_U32(5) /* Auto-Negotiation Complete */
-#define GMAC_AN_STATUS_ES BIT_U32(8) /* Extended Status */
-
-/* ADV and LPA defines */
-#define GMAC_ANE_FD BIT_U32(5)
-#define GMAC_ANE_HD BIT_U32(6)
-#define GMAC_ANE_PSE GENMASK_U32(8, 7)
-#define GMAC_ANE_PSE_SHIFT 7
-#define GMAC_ANE_RFE GENMASK_U32(13, 12)
-#define GMAC_ANE_RFE_SHIFT 12
-#define GMAC_ANE_ACK BIT_U32(14)
-
struct stmmac_priv;
struct stmmac_pcs {
--
2.47.3
--
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^ permalink raw reply related
* [PATCH net-next v2 08/14] net: stmmac: handle integrated PCS phy_intf_sel separately
From: Russell King (Oracle) @ 2026-01-23 9:53 UTC (permalink / raw)
To: Andrew Lunn, Heiner Kallweit
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, linux-arm-kernel, linux-arm-msm, linux-phy,
linux-stm32, Maxime Chevallier, Maxime Coquelin, Mohd Ayaan Anwar,
Neil Armstrong, netdev, Paolo Abeni, Vinod Koul
In-Reply-To: <aXNEwBW3OA1xLEUj@shell.armlinux.org.uk>
The dwmac core has no support for SGMII without using its integrated
PCS. Thus, PHY_INTF_SEL_SGMII is only supported when this block is
present, and it makes no sense for stmmac_get_phy_intf_sel() to decode
this.
None of the platform glue users that use stmmac_get_phy_intf_sel()
directly accept PHY_INTF_SEL_SGMII as a valid mode.
Check whether a PCS will be used by the driver for the interface mode,
and if it is the integrated PCS, query the integrated PCS for the
phy_intf_sel_i value to use.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 15 ++++++++++++---
drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c | 9 +++++++++
drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h | 2 ++
3 files changed, 23 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 6c515f9efbe7..5254d9d19ffe 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -3135,8 +3135,6 @@ int stmmac_get_phy_intf_sel(phy_interface_t interface)
phy_intf_sel = PHY_INTF_SEL_GMII_MII;
else if (phy_interface_mode_is_rgmii(interface))
phy_intf_sel = PHY_INTF_SEL_RGMII;
- else if (interface == PHY_INTERFACE_MODE_SGMII)
- phy_intf_sel = PHY_INTF_SEL_SGMII;
else if (interface == PHY_INTERFACE_MODE_RMII)
phy_intf_sel = PHY_INTF_SEL_RMII;
else if (interface == PHY_INTERFACE_MODE_REVMII)
@@ -3150,13 +3148,24 @@ static int stmmac_prereset_configure(struct stmmac_priv *priv)
{
struct plat_stmmacenet_data *plat_dat = priv->plat;
phy_interface_t interface;
+ struct phylink_pcs *pcs;
int phy_intf_sel, ret;
if (!plat_dat->set_phy_intf_sel)
return 0;
interface = plat_dat->phy_interface;
- phy_intf_sel = stmmac_get_phy_intf_sel(interface);
+
+ /* Check whether this mode uses a PCS */
+ pcs = stmmac_mac_select_pcs(&priv->phylink_config, interface);
+ if (priv->integrated_pcs && pcs == &priv->integrated_pcs->pcs) {
+ /* Request the phy_intf_sel from the integrated PCS */
+ phy_intf_sel = stmmac_integrated_pcs_get_phy_intf_sel(priv,
+ interface);
+ } else {
+ phy_intf_sel = stmmac_get_phy_intf_sel(interface);
+ }
+
if (phy_intf_sel < 0) {
netdev_err(priv->dev,
"failed to get phy_intf_sel for %s: %pe\n",
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
index ac588756e450..1644e045cfb3 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
@@ -108,6 +108,15 @@ void stmmac_integrated_pcs_irq(struct stmmac_priv *priv, u32 status,
}
}
+int stmmac_integrated_pcs_get_phy_intf_sel(struct stmmac_priv *priv,
+ phy_interface_t interface)
+{
+ if (interface == PHY_INTERFACE_MODE_SGMII)
+ return PHY_INTF_SEL_SGMII;
+
+ return -EINVAL;
+}
+
int stmmac_integrated_pcs_init(struct stmmac_priv *priv, unsigned int offset,
u32 int_mask)
{
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h
index 887c4ff302aa..845bcad9d0f7 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h
@@ -43,6 +43,8 @@ phylink_pcs_to_stmmac_pcs(struct phylink_pcs *pcs)
void stmmac_integrated_pcs_irq(struct stmmac_priv *priv, u32 status,
struct stmmac_extra_stats *x);
+int stmmac_integrated_pcs_get_phy_intf_sel(struct stmmac_priv *priv,
+ phy_interface_t interface);
int stmmac_integrated_pcs_init(struct stmmac_priv *priv, unsigned int offset,
u32 int_mask);
--
2.47.3
--
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^ permalink raw reply related
* [PATCH net-next v2 09/14] net: stmmac: add BASE-X support to integrated PCS
From: Russell King (Oracle) @ 2026-01-23 9:54 UTC (permalink / raw)
To: Andrew Lunn, Heiner Kallweit
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, linux-arm-kernel, linux-arm-msm, linux-phy,
linux-stm32, Maxime Chevallier, Maxime Coquelin, Mohd Ayaan Anwar,
Neil Armstrong, netdev, Paolo Abeni, Vinod Koul
In-Reply-To: <aXNEwBW3OA1xLEUj@shell.armlinux.org.uk>
The integrated PCS supports 802.3z (BASE-X) modes when the Synopsys
IP is coupled with an appropriate SerDes to provide the electrical
interface. The PCS presents a TBI interface to the SerDes for this.
Thus, the BASE-X related registers are only present when TBI mode is
supported.
dwmac-qcom-ethqos added support for using 2.5G with the integrated PCS
by calling dwmac_ctrl_ane() directly.
Add support for 1000BASE-X mode to the integrated PCS support if the
PCS supports TBI, and 2500BASE-X if we have a SerDes that supports
this mode.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
.../net/ethernet/stmicro/stmmac/stmmac_pcs.c | 95 ++++++++++++++++++-
1 file changed, 92 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
index 1644e045cfb3..aae4d6ad9f9b 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
@@ -17,6 +17,50 @@
#define GMAC_ANE_LPA 0x0c /* ANE link partener ability */
#define GMAC_TBI 0x14 /* TBI extend status */
+static enum ethtool_link_mode_bit_indices dwmac_hd_mode_bits[] = {
+ ETHTOOL_LINK_MODE_10baseT_Half_BIT,
+ ETHTOOL_LINK_MODE_100baseT_Half_BIT,
+ ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
+ ETHTOOL_LINK_MODE_100baseFX_Half_BIT,
+ ETHTOOL_LINK_MODE_10baseT1S_Half_BIT,
+ ETHTOOL_LINK_MODE_10baseT1S_P2MP_Half_BIT,
+};
+
+static int dwmac_integrated_pcs_validate(struct phylink_pcs *pcs,
+ unsigned long *supported,
+ const struct phylink_link_state *state)
+{
+ struct stmmac_pcs *spcs = phylink_pcs_to_stmmac_pcs(pcs);
+ size_t i;
+ u32 val;
+
+ if (phy_interface_mode_is_8023z(state->interface)) {
+ /* ESTATUS_1000_XFULL is always set, so full duplex is
+ * supported. ESTATUS_1000_XHALF depends on core configuration.
+ */
+ val = readl(spcs->base + GMAC_TBI);
+ if (~val & ESTATUS_1000_XHALF)
+ for (i = 0; i < ARRAY_SIZE(dwmac_hd_mode_bits); i++)
+ linkmode_clear_bit(dwmac_hd_mode_bits[i],
+ supported);
+
+ return 0;
+ } else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+static unsigned int dwmac_integrated_pcs_inband_caps(struct phylink_pcs *pcs,
+ phy_interface_t interface)
+{
+ if (phy_interface_mode_is_8023z(interface))
+ return LINK_INBAND_ENABLE | LINK_INBAND_DISABLE;
+
+ return 0;
+}
+
static int dwmac_integrated_pcs_enable(struct phylink_pcs *pcs)
{
struct stmmac_pcs *spcs = phylink_pcs_to_stmmac_pcs(pcs);
@@ -54,7 +98,23 @@ static void dwmac_integrated_pcs_get_state(struct phylink_pcs *pcs,
unsigned int neg_mode,
struct phylink_link_state *state)
{
- state->link = false;
+ struct stmmac_pcs *spcs = phylink_pcs_to_stmmac_pcs(pcs);
+ u32 status, lpa;
+
+ status = readl(spcs->base + GMAC_AN_STATUS);
+
+ if (phy_interface_mode_is_8023z(state->interface)) {
+ /* For 802.3z modes, the PCS block supports the advertisement
+ * and link partner advertisement registers using standard
+ * 802.3 format. The status register also has the link status
+ * and AN complete bits in the same bit location.
+ */
+ lpa = readl(spcs->base + GMAC_ANE_LPA);
+
+ phylink_mii_c22_pcs_decode_state(state, neg_mode, status, lpa);
+ } else {
+ state->link = false;
+ }
}
static int dwmac_integrated_pcs_config(struct phylink_pcs *pcs,
@@ -64,6 +124,8 @@ static int dwmac_integrated_pcs_config(struct phylink_pcs *pcs,
bool permit_pause_to_mac)
{
struct stmmac_pcs *spcs = phylink_pcs_to_stmmac_pcs(pcs);
+ bool changed = false, ane = true;
+ u32 adv;
int ret;
if (spcs->interface != interface) {
@@ -74,12 +136,25 @@ static int dwmac_integrated_pcs_config(struct phylink_pcs *pcs,
spcs->interface = interface;
}
- dwmac_ctrl_ane(spcs->base, 0, 1, spcs->priv->hw->reverse_sgmii_enable);
+ if (phy_interface_mode_is_8023z(interface)) {
+ adv = phylink_mii_c22_pcs_encode_advertisement(interface,
+ advertising);
+ if (readl(spcs->base + GMAC_ANE_ADV) != adv)
+ changed = true;
+ writel(adv, spcs->base + GMAC_ANE_ADV);
- return 0;
+ ane = neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED;
+ }
+
+ dwmac_ctrl_ane(spcs->base, 0, ane,
+ spcs->priv->hw->reverse_sgmii_enable);
+
+ return changed;
}
static const struct phylink_pcs_ops dwmac_integrated_pcs_ops = {
+ .pcs_validate = dwmac_integrated_pcs_validate,
+ .pcs_inband_caps = dwmac_integrated_pcs_inband_caps,
.pcs_enable = dwmac_integrated_pcs_enable,
.pcs_disable = dwmac_integrated_pcs_disable,
.pcs_get_state = dwmac_integrated_pcs_get_state,
@@ -114,6 +189,9 @@ int stmmac_integrated_pcs_get_phy_intf_sel(struct stmmac_priv *priv,
if (interface == PHY_INTERFACE_MODE_SGMII)
return PHY_INTF_SEL_SGMII;
+ if (phy_interface_mode_is_8023z(interface))
+ return PHY_INTF_SEL_TBI;
+
return -EINVAL;
}
@@ -142,6 +220,17 @@ int stmmac_integrated_pcs_init(struct stmmac_priv *priv, unsigned int offset,
__set_bit(PHY_INTERFACE_MODE_SGMII, spcs->pcs.supported_interfaces);
+ if (readl(spcs->base + GMAC_AN_STATUS) & BMSR_ESTATEN) {
+ __set_bit(PHY_INTERFACE_MODE_1000BASEX,
+ spcs->pcs.supported_interfaces);
+
+ /* Only allow 2500Base-X if the SerDes has support. */
+ ret = dwmac_serdes_validate(priv, PHY_INTERFACE_MODE_2500BASEX);
+ if (ret == 0)
+ __set_bit(PHY_INTERFACE_MODE_2500BASEX,
+ spcs->pcs.supported_interfaces);
+ }
+
priv->integrated_pcs = spcs;
return 0;
--
2.47.3
--
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^ permalink raw reply related
* [PATCH net-next v2 10/14] net: stmmac: use integrated PCS for BASE-X modes
From: Russell King (Oracle) @ 2026-01-23 9:54 UTC (permalink / raw)
To: Andrew Lunn, Heiner Kallweit
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, linux-arm-kernel, linux-arm-msm, linux-phy,
linux-stm32, Maxime Chevallier, Maxime Coquelin, Mohd Ayaan Anwar,
Neil Armstrong, netdev, Paolo Abeni, Vinod Koul
In-Reply-To: <aXNEwBW3OA1xLEUj@shell.armlinux.org.uk>
dwmac-qcom-ethqos supports SGMII and 2500BASE-X using the integrated
PCS, so we need to expand the PCS support to include support for
BASE-X modes.
Add support to the prereset configuration to detect 2500BASE-X, and
arrange for stmmac_mac_select_pcs() to return the integrated PCS if
its supported_interfaces bitmap reports support for the interface mode.
This results in priv->hw->pcs now being write-only, so remove it.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
drivers/net/ethernet/stmicro/stmmac/common.h | 1 -
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 8 ++------
2 files changed, 2 insertions(+), 7 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h
index 49df46be3669..8ef54f6e78f6 100644
--- a/drivers/net/ethernet/stmicro/stmmac/common.h
+++ b/drivers/net/ethernet/stmicro/stmmac/common.h
@@ -629,7 +629,6 @@ struct mac_device_info {
unsigned int unicast_filter_entries;
unsigned int mcast_bits_log2;
unsigned int rx_csum;
- unsigned int pcs;
unsigned int xlgmac;
unsigned int num_vlan;
u32 vlan_filter[32];
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 5254d9d19ffe..a63ae6c4bc8a 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -911,11 +911,8 @@ static struct phylink_pcs *stmmac_mac_select_pcs(struct phylink_config *config,
return pcs;
}
- /* The PCS control register is only relevant for SGMII, TBI and RTBI
- * modes. We no longer support TBI or RTBI, so only configure this
- * register when operating in SGMII mode with the integrated PCS.
- */
- if (priv->hw->pcs & STMMAC_PCS_SGMII && priv->integrated_pcs)
+ if (priv->integrated_pcs &&
+ test_bit(interface, priv->integrated_pcs->pcs.supported_interfaces))
return &priv->integrated_pcs->pcs;
return NULL;
@@ -1173,7 +1170,6 @@ static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
if (priv->dma_cap.pcs && interface == PHY_INTERFACE_MODE_SGMII) {
netdev_dbg(priv->dev, "PCS SGMII support enabled\n");
- priv->hw->pcs = STMMAC_PCS_SGMII;
switch (speed) {
case SPEED_10:
--
2.47.3
--
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^ permalink raw reply related
* Re: [PATCH net-next v2 00/14] net: stmmac: SerDes, PCS, BASE-X, and inband goodies
From: Russell King (Oracle) @ 2026-01-23 9:56 UTC (permalink / raw)
To: Andrew Lunn, Heiner Kallweit
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Konrad Dybcio, linux-arm-kernel, linux-arm-msm,
linux-phy, linux-stm32, Maxime Coquelin, Mohd Ayaan Anwar,
Neil Armstrong, netdev, Paolo Abeni, Vinod Koul
In-Reply-To: <aXNEwBW3OA1xLEUj@shell.armlinux.org.uk>
Please note that gmail is now rejecting this patch series because it's
spam. From now on, I will be dropping all gmail.com email addresses from
patch series that are sent out.
If you care about Linux, stop using gmail and giving Google an excessive
amount of power over email.
On Fri, Jan 23, 2026 at 09:52:00AM +0000, Russell King (Oracle) wrote:
> This is the v1 submission: if it doesn't get tested but review goes
> well, it'll end up in net-next and mainline without testing on the
> affected hardware!
>
> Mentioned previously, I've been trying to sort out the PCS support in
> stmmac, and this series represents the current state of play.
>
> Previous posted patches centred around merely getting autonegotiation
> to be configured correctly, to a point where the manual configuration
> can be removed from the qcom-ethqos driver. The qcom-ethqos driver
> uses both SGMII and 2500BASE-X, manually configuring the dwmac's
> integrated PCS appropriately.
>
> This *untested* series attempts to take this further. The patches:
>
> - clean up qcom-ethqos only-written mac_base member.
> - convert qcom-ethqos to use the set_clk_tx_rate() method for setting
> the link clock rate.
> - add support for phy_set_mode_ext() to the qcom "SGMII" ethernet
> SerDes driver (which is really only what it needs. Note that
> phy_set_mode_ext() is an expected call to be made, where as
> phy_set_speed() is optional and not. See PHY documentation.)
> - add platform-glue independent SerDes support to the stmmac core
> driver. Currently, only qcom-ethqos will make use of this, and
> I suspect as we haven't had this, it's going to be difficult to
> convert other platform glue to use this - but had this existed
> earlier, we could've pushed people to use PHY to abstract some
> of the platform glue differences. Adding it now makes it available
> for future platform glue.
> - convert qcom-ethqos to use this core SerDes support.
> - arrange for stmmac_pcs.c to supply the phy_intf_sel field value
> if the integrated PCS will be used. (PHY_INTF_SEL_SGMII requires
> the integrated PCS rather than an external PCS.)
> - add BASE-X support to the integrated PCS driver, and use it for
> BASE-X modes. This fully supports in-band mode, including reading
> the link partner advertisement.
> - add in-band support for SGMII, reading the state from the RGSMII
> status field.
>
> As we leave qcom-ethqos' manual configuration of the PCS in place at
> the moment, the last patch adds reporting of any changes in its
> configuration that the qcom-ethqos driver does beyond what phylink
> requested, thus providing a path to debug and eventually remove
> qcom-ethqos' manual configuration.
>
> One patch is not included in this set - which adds a phy_intf_sel
> value for external PCS (using PHY_INTF_SEL_GMII_MII). I believe all
> external PCS use this mode when connected to a MAC capable of up to
> 2.5G. However, no platform glue that provides the mac_select_pcs()
> method also provide the set_phy_intf_sel() method, so we can safely
> ignore this for now.
>
> I would like to get this into net-next before the next merge window,
> so testing would be appreciated. If there are issues with these patches
> applied, please check whether the issue exists without these patches
> and only report regressions caused by this patch set. For example,
> I'm aware that qcom-ethqos has issues with 10Mbps mode due to an AQR
> PHY being insanely provisioned to use SGMII in 1000M mode but with
> rate matching with 10M media. This is not an issue that is relevant
> to this patch series, but a problem with the PHY provisioning.
>
> rfc->v1:
> - fix SGMII link status
> - avoid calling phy_get_mode() if PHY is null
> v2:
> - fix further AI review bot dribble that could've been raised on
> the rfc version but wasn't.
>
> drivers/net/ethernet/stmicro/stmmac/Makefile | 2 +-
> drivers/net/ethernet/stmicro/stmmac/common.h | 1 -
> .../ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 74 ++-----
> drivers/net/ethernet/stmicro/stmmac/dwmac1000.h | 12 +-
> .../net/ethernet/stmicro/stmmac/dwmac1000_core.c | 11 +-
> drivers/net/ethernet/stmicro/stmmac/dwmac4.h | 10 +-
> drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c | 10 +-
> drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 69 +++++--
> drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c | 222 +++++++++++++++++++--
> drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h | 53 ++---
> .../net/ethernet/stmicro/stmmac/stmmac_serdes.c | 111 +++++++++++
> .../net/ethernet/stmicro/stmmac/stmmac_serdes.h | 16 ++
> drivers/phy/qualcomm/phy-qcom-sgmii-eth.c | 43 ++++
> include/linux/stmmac.h | 2 +
> 14 files changed, 491 insertions(+), 145 deletions(-)
>
> --
> RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
> FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
>
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
--
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^ permalink raw reply
* [PATCH net-next v2 11/14] net: stmmac: add struct stmmac_pcs_info
From: Russell King (Oracle) @ 2026-01-23 9:54 UTC (permalink / raw)
To: Andrew Lunn, Heiner Kallweit
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, linux-arm-kernel, linux-arm-msm, linux-phy,
linux-stm32, Maxime Chevallier, Maxime Coquelin, Mohd Ayaan Anwar,
Neil Armstrong, netdev, Paolo Abeni, Vinod Koul
In-Reply-To: <aXNEwBW3OA1xLEUj@shell.armlinux.org.uk>
We need to describe one more register (offset and field bitmask) to
the PCS code. Move the existing PCS offset and interrupt enable bits
to a new struct and pass that in to stmmac_integrated_pcs_init().
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c | 9 ++++++---
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c | 8 ++++++--
drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c | 8 ++++----
drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h | 9 +++++++--
4 files changed, 23 insertions(+), 11 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
index af566636fad9..a3ef237de1b8 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
@@ -22,14 +22,17 @@
#include "stmmac_ptp.h"
#include "dwmac1000.h"
+static const struct stmmac_pcs_info dwmac1000_pcs_info = {
+ .pcs_offset = GMAC_PCS_BASE,
+ .int_mask = GMAC_INT_DISABLE_PCSLINK | GMAC_INT_DISABLE_PCSAN,
+};
+
static int dwmac1000_pcs_init(struct stmmac_priv *priv)
{
if (!priv->dma_cap.pcs)
return 0;
- return stmmac_integrated_pcs_init(priv, GMAC_PCS_BASE,
- GMAC_INT_DISABLE_PCSLINK |
- GMAC_INT_DISABLE_PCSAN);
+ return stmmac_integrated_pcs_init(priv, &dwmac1000_pcs_info);
}
static void dwmac1000_core_init(struct mac_device_info *hw,
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
index 623868afe93d..7f4949229288 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
@@ -22,13 +22,17 @@
#include "dwmac4.h"
#include "dwmac5.h"
+static const struct stmmac_pcs_info dwmac4_pcs_info = {
+ .pcs_offset = GMAC_PCS_BASE,
+ .int_mask = GMAC_INT_PCS_LINK | GMAC_INT_PCS_ANE,
+};
+
static int dwmac4_pcs_init(struct stmmac_priv *priv)
{
if (!priv->dma_cap.pcs)
return 0;
- return stmmac_integrated_pcs_init(priv, GMAC_PCS_BASE,
- GMAC_INT_PCS_LINK | GMAC_INT_PCS_ANE);
+ return stmmac_integrated_pcs_init(priv, &dwmac4_pcs_info);
}
static void dwmac4_core_init(struct mac_device_info *hw,
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
index aae4d6ad9f9b..c67041c49d9b 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
@@ -195,8 +195,8 @@ int stmmac_integrated_pcs_get_phy_intf_sel(struct stmmac_priv *priv,
return -EINVAL;
}
-int stmmac_integrated_pcs_init(struct stmmac_priv *priv, unsigned int offset,
- u32 int_mask)
+int stmmac_integrated_pcs_init(struct stmmac_priv *priv,
+ const struct stmmac_pcs_info *pcs_info)
{
struct stmmac_pcs *spcs;
int ret;
@@ -206,8 +206,8 @@ int stmmac_integrated_pcs_init(struct stmmac_priv *priv, unsigned int offset,
return -ENOMEM;
spcs->priv = priv;
- spcs->base = priv->ioaddr + offset;
- spcs->int_mask = int_mask;
+ spcs->base = priv->ioaddr + pcs_info->pcs_offset;
+ spcs->int_mask = pcs_info->int_mask;
spcs->pcs.ops = &dwmac_integrated_pcs_ops;
if (priv->plat->serdes) {
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h
index 845bcad9d0f7..a7c71f40f952 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h
@@ -27,6 +27,11 @@
struct stmmac_priv;
+struct stmmac_pcs_info {
+ unsigned int pcs_offset;
+ u32 int_mask;
+};
+
struct stmmac_pcs {
struct stmmac_priv *priv;
void __iomem *base;
@@ -45,8 +50,8 @@ void stmmac_integrated_pcs_irq(struct stmmac_priv *priv, u32 status,
struct stmmac_extra_stats *x);
int stmmac_integrated_pcs_get_phy_intf_sel(struct stmmac_priv *priv,
phy_interface_t interface);
-int stmmac_integrated_pcs_init(struct stmmac_priv *priv, unsigned int offset,
- u32 int_mask);
+int stmmac_integrated_pcs_init(struct stmmac_priv *priv,
+ const struct stmmac_pcs_info *pcs_info);
/**
* dwmac_ctrl_ane - To program the AN Control Register.
--
2.47.3
--
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^ permalink raw reply related
* [PATCH net-next v2 13/14] net: stmmac: configure SGMII AN control according to phylink
From: Russell King (Oracle) @ 2026-01-23 9:54 UTC (permalink / raw)
To: Andrew Lunn, Heiner Kallweit
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, linux-arm-kernel, linux-arm-msm, linux-phy,
linux-stm32, Maxime Chevallier, Maxime Coquelin, Mohd Ayaan Anwar,
Neil Armstrong, netdev, Paolo Abeni, Vinod Koul
In-Reply-To: <aXNEwBW3OA1xLEUj@shell.armlinux.org.uk>
Provide phylink with the integrated PCS autonegotiation capabilities,
and configure the PCS's AN settings according to phylink's requested
requirements.
This may cause regressions.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
.../ethernet/stmicro/stmmac/dwmac1000_core.c | 4 ++--
.../net/ethernet/stmicro/stmmac/dwmac4_core.c | 4 ++--
.../net/ethernet/stmicro/stmmac/stmmac_pcs.c | 20 ++++++++++++-------
3 files changed, 17 insertions(+), 11 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
index 18a0b678295d..31f6ac5432f2 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
@@ -24,8 +24,8 @@
static const struct stmmac_pcs_info dwmac1000_pcs_info = {
.pcs_offset = GMAC_PCS_BASE,
- .rsgmii_offset = GMAC_RGSMIIIS,
- .rsgmii_status_mask = GMAC_RSGMIIIS_MASK,
+ .rgsmii_offset = GMAC_RGSMIIIS,
+ .rgsmii_status_mask = GMAC_RSGMIIIS_MASK,
.int_mask = GMAC_INT_DISABLE_PCSLINK | GMAC_INT_DISABLE_PCSAN,
};
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
index e7836bb27a9b..ced2cd98cc54 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
@@ -24,8 +24,8 @@
static const struct stmmac_pcs_info dwmac4_pcs_info = {
.pcs_offset = GMAC_PCS_BASE,
- .rsgmii_offset = GMAC_PHYIF_CONTROL_STATUS,
- .rsgmii_status_mask = GMAC_PHYIF_CTRLSTATUS_RSGMII_MASK,
+ .rgsmii_offset = GMAC_PHYIF_CONTROL_STATUS,
+ .rgsmii_status_mask = GMAC_PHYIF_CTRLSTATUS_RSGMII_MASK,
.int_mask = GMAC_INT_PCS_LINK | GMAC_INT_PCS_ANE,
};
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
index 3b450e7f794c..978f66ea51f3 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
@@ -65,7 +65,8 @@ static int dwmac_integrated_pcs_validate(struct phylink_pcs *pcs,
static unsigned int dwmac_integrated_pcs_inband_caps(struct phylink_pcs *pcs,
phy_interface_t interface)
{
- if (phy_interface_mode_is_8023z(interface))
+ if (phy_interface_mode_is_8023z(interface) ||
+ interface == PHY_INTERFACE_MODE_SGMII)
return LINK_INBAND_ENABLE | LINK_INBAND_DISABLE;
return 0;
@@ -164,8 +165,9 @@ static int dwmac_integrated_pcs_config(struct phylink_pcs *pcs,
bool permit_pause_to_mac)
{
struct stmmac_pcs *spcs = phylink_pcs_to_stmmac_pcs(pcs);
- bool changed = false, ane = true;
- u32 adv;
+ void __iomem *an_control = spcs->base + GMAC_AN_CTRL(0);
+ bool changed = false;
+ u32 adv, ctrl;
int ret;
if (spcs->interface != interface) {
@@ -182,12 +184,16 @@ static int dwmac_integrated_pcs_config(struct phylink_pcs *pcs,
if (readl(spcs->base + GMAC_ANE_ADV) != adv)
changed = true;
writel(adv, spcs->base + GMAC_ANE_ADV);
-
- ane = neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED;
}
- dwmac_ctrl_ane(spcs->base, 0, ane,
- spcs->priv->hw->reverse_sgmii_enable);
+ ctrl = readl(an_control) & ~(GMAC_AN_CTRL_ANE | GMAC_AN_CTRL_SGMRAL);
+ if (spcs->priv->hw->reverse_sgmii_enable)
+ ctrl |= GMAC_AN_CTRL_SGMRAL | GMAC_AN_CTRL_ANE;
+ else if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
+ ctrl |= GMAC_AN_CTRL_ANE;
+ else
+ ctrl |= GMAC_AN_CTRL_SGMRAL;
+ writel(ctrl, an_control);
return changed;
}
--
2.47.3
--
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^ permalink raw reply related
* [PATCH net-next v2 12/14] net: stmmac: add support for reading inband SGMII status
From: Russell King (Oracle) @ 2026-01-23 9:54 UTC (permalink / raw)
To: Andrew Lunn, Heiner Kallweit
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, linux-arm-kernel, linux-arm-msm, linux-phy,
linux-stm32, Maxime Chevallier, Maxime Coquelin, Mohd Ayaan Anwar,
Neil Armstrong, netdev, Paolo Abeni, Vinod Koul
In-Reply-To: <aXNEwBW3OA1xLEUj@shell.armlinux.org.uk>
Report the link, speed and duplex for SGMII links, read from the
SGMII, RGMII and SMII status and control register.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
rfc->v1: fix setting SGMII's link status - depend on both link status.
v2:
- fill in rsgmii offset and status fields in dwmac cores
- rename new GMAC_RGSMIII_xxx constants to GMAC_RGSMII_xxx
---
.../net/ethernet/stmicro/stmmac/dwmac1000.h | 12 +----
.../ethernet/stmicro/stmmac/dwmac1000_core.c | 2 +
drivers/net/ethernet/stmicro/stmmac/dwmac4.h | 10 +---
.../net/ethernet/stmicro/stmmac/dwmac4_core.c | 2 +
.../net/ethernet/stmicro/stmmac/stmmac_pcs.c | 46 ++++++++++++++++++-
.../net/ethernet/stmicro/stmmac/stmmac_pcs.h | 4 ++
6 files changed, 54 insertions(+), 22 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h b/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h
index b3135df0a359..03e8c2534673 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000.h
@@ -70,18 +70,8 @@ enum power_event {
#define GMAC_RGSMIIIS 0x000000d8 /* RGMII/SMII status */
/* SGMII/RGMII status register */
-#define GMAC_RGSMIIIS_LNKMODE BIT(0)
-#define GMAC_RGSMIIIS_SPEED GENMASK(2, 1)
-#define GMAC_RGSMIIIS_LNKSTS BIT(3)
-#define GMAC_RGSMIIIS_JABTO BIT(4)
-#define GMAC_RGSMIIIS_FALSECARDET BIT(5)
+#define GMAC_RSGMIIIS_MASK GENMASK(15, 0)
#define GMAC_RGSMIIIS_SMIDRXS BIT(16)
-/* LNKMOD */
-#define GMAC_RGSMIIIS_LNKMOD_MASK 0x1
-/* LNKSPEED */
-#define GMAC_RGSMIIIS_SPEED_125 0x2
-#define GMAC_RGSMIIIS_SPEED_25 0x1
-#define GMAC_RGSMIIIS_SPEED_2_5 0x0
/* GMAC Configuration defines */
#define GMAC_CONTROL_2K 0x08000000 /* IEEE 802.3as 2K packets */
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
index a3ef237de1b8..18a0b678295d 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
@@ -24,6 +24,8 @@
static const struct stmmac_pcs_info dwmac1000_pcs_info = {
.pcs_offset = GMAC_PCS_BASE,
+ .rsgmii_offset = GMAC_RGSMIIIS,
+ .rsgmii_status_mask = GMAC_RSGMIIIS_MASK,
.int_mask = GMAC_INT_DISABLE_PCSLINK | GMAC_INT_DISABLE_PCSAN,
};
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
index d797d936aee1..ffcd036d4c02 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4.h
@@ -470,15 +470,7 @@ static inline u32 mtl_low_credx_base_addr(const struct dwmac4_addrs *addrs,
#define GMAC_PHYIF_CTRLSTATUS_TC BIT(0)
#define GMAC_PHYIF_CTRLSTATUS_LUD BIT(1)
#define GMAC_PHYIF_CTRLSTATUS_SMIDRXS BIT(4)
-#define GMAC_PHYIF_CTRLSTATUS_LNKMOD BIT(16)
-#define GMAC_PHYIF_CTRLSTATUS_SPEED GENMASK(18, 17)
-#define GMAC_PHYIF_CTRLSTATUS_LNKSTS BIT(19)
-#define GMAC_PHYIF_CTRLSTATUS_JABTO BIT(20)
-#define GMAC_PHYIF_CTRLSTATUS_FALSECARDET BIT(21)
-/* LNKSPEED */
-#define GMAC_PHYIF_CTRLSTATUS_SPEED_125 0x2
-#define GMAC_PHYIF_CTRLSTATUS_SPEED_25 0x1
-#define GMAC_PHYIF_CTRLSTATUS_SPEED_2_5 0x0
+#define GMAC_PHYIF_CTRLSTATUS_RSGMII_MASK GENMASK(31, 16)
extern const struct stmmac_dma_ops dwmac4_dma_ops;
extern const struct stmmac_dma_ops dwmac410_dma_ops;
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
index 7f4949229288..e7836bb27a9b 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
@@ -24,6 +24,8 @@
static const struct stmmac_pcs_info dwmac4_pcs_info = {
.pcs_offset = GMAC_PCS_BASE,
+ .rsgmii_offset = GMAC_PHYIF_CONTROL_STATUS,
+ .rsgmii_status_mask = GMAC_PHYIF_CTRLSTATUS_RSGMII_MASK,
.int_mask = GMAC_INT_PCS_LINK | GMAC_INT_PCS_ANE,
};
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
index c67041c49d9b..3b450e7f794c 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
@@ -17,6 +17,16 @@
#define GMAC_ANE_LPA 0x0c /* ANE link partener ability */
#define GMAC_TBI 0x14 /* TBI extend status */
+/*
+ * RGSMII status bitfield definitions.
+ */
+#define GMAC_RGSMII_LNKMOD BIT(0)
+#define GMAC_RGSMII_SPEED_MASK GENMASK(2, 1)
+#define GMAC_RGSMII_SPEED_125 2
+#define GMAC_RGSMII_SPEED_25 1
+#define GMAC_RGSMII_SPEED_2_5 0
+#define GMAC_RGSMII_LNKSTS BIT(3)
+
static enum ethtool_link_mode_bit_indices dwmac_hd_mode_bits[] = {
ETHTOOL_LINK_MODE_10baseT_Half_BIT,
ETHTOOL_LINK_MODE_100baseT_Half_BIT,
@@ -99,7 +109,7 @@ static void dwmac_integrated_pcs_get_state(struct phylink_pcs *pcs,
struct phylink_link_state *state)
{
struct stmmac_pcs *spcs = phylink_pcs_to_stmmac_pcs(pcs);
- u32 status, lpa;
+ u32 status, lpa, rgsmii;
status = readl(spcs->base + GMAC_AN_STATUS);
@@ -113,7 +123,37 @@ static void dwmac_integrated_pcs_get_state(struct phylink_pcs *pcs,
phylink_mii_c22_pcs_decode_state(state, neg_mode, status, lpa);
} else {
- state->link = false;
+ rgsmii = field_get(spcs->rgsmii_status_mask,
+ readl(spcs->rgsmii));
+
+ state->link = status & BMSR_LSTATUS &&
+ rgsmii & GMAC_RGSMII_LNKSTS;
+
+ if (state->link && neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
+ /* FIXME: fill in speed and duplex. This requires the
+ * contents of the dwmac1000 GMAC_RGSMIIS or dwmac4
+ * GMAC_PHYIF_CONTROL_STATUS register.
+ */
+ state->duplex = rgsmii & GMAC_RGSMII_LNKMOD ?
+ DUPLEX_FULL : DUPLEX_HALF;
+ switch (FIELD_GET(GMAC_RGSMII_SPEED_MASK, rgsmii)) {
+ case GMAC_RGSMII_SPEED_2_5:
+ state->speed = SPEED_10;
+ break;
+
+ case GMAC_RGSMII_SPEED_25:
+ state->speed = SPEED_100;
+ break;
+
+ case GMAC_RGSMII_SPEED_125:
+ state->speed = SPEED_1000;
+ break;
+
+ default:
+ state->link = false;
+ break;
+ }
+ }
}
}
@@ -207,6 +247,8 @@ int stmmac_integrated_pcs_init(struct stmmac_priv *priv,
spcs->priv = priv;
spcs->base = priv->ioaddr + pcs_info->pcs_offset;
+ spcs->rgsmii = priv->ioaddr + pcs_info->rgsmii_offset;
+ spcs->rgsmii_status_mask = pcs_info->rgsmii_status_mask;
spcs->int_mask = pcs_info->int_mask;
spcs->pcs.ops = &dwmac_integrated_pcs_ops;
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h
index a7c71f40f952..f9e7a7ed840b 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h
@@ -29,12 +29,16 @@ struct stmmac_priv;
struct stmmac_pcs_info {
unsigned int pcs_offset;
+ unsigned int rgsmii_offset;
+ u32 rgsmii_status_mask;
u32 int_mask;
};
struct stmmac_pcs {
struct stmmac_priv *priv;
void __iomem *base;
+ void __iomem *rgsmii;
+ u32 rgsmii_status_mask;
u32 int_mask;
phy_interface_t interface;
struct phylink_pcs pcs;
--
2.47.3
--
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^ permalink raw reply related
* [PATCH net-next v2 14/14] net: stmmac: report PCS configuration changes
From: Russell King (Oracle) @ 2026-01-23 9:54 UTC (permalink / raw)
To: Andrew Lunn, Heiner Kallweit
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, linux-arm-kernel, linux-arm-msm, linux-phy,
linux-stm32, Maxime Chevallier, Maxime Coquelin, Mohd Ayaan Anwar,
Neil Armstrong, netdev, Paolo Abeni, Vinod Koul
In-Reply-To: <aXNEwBW3OA1xLEUj@shell.armlinux.org.uk>
Report if/when qcom-ethqos changes the PCS configuration. With phylink
now setting the PCS configuration, there should be no need for drivers
to change this.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h
index f9e7a7ed840b..6a1e30b10740 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h
@@ -71,6 +71,7 @@ static inline void dwmac_ctrl_ane(void __iomem *ioaddr, u32 reg, bool ane,
bool srgmi_ral)
{
u32 value = readl(ioaddr + GMAC_AN_CTRL(reg));
+ u32 old = value, diff;
/* Enable and restart the Auto-Negotiation */
if (ane)
@@ -84,6 +85,20 @@ static inline void dwmac_ctrl_ane(void __iomem *ioaddr, u32 reg, bool ane,
if (srgmi_ral)
value |= GMAC_AN_CTRL_SGMRAL;
+ diff = old ^ value;
+ if (diff & ~GMAC_AN_CTRL_RAN) {
+ pr_warn("dwmac: PCS configuration changed from phylink by glue, please report: 0x%08x -> 0x%08x\n",
+ old & ~GMAC_AN_CTRL_RAN, value & ~GMAC_AN_CTRL_RAN);
+#define REPORT_BIT(x) \
+ if (diff & GMAC_AN_CTRL_##x) \
+ pr_warn("dwmac: %8s %u -> %u\n", #x, \
+ !!(old & GMAC_AN_CTRL_##x), \
+ !!(value & GMAC_AN_CTRL_##x))
+ REPORT_BIT(ANE);
+ REPORT_BIT(SGMRAL);
+#undef REPORT_BIT
+ }
+
writel(value, ioaddr + GMAC_AN_CTRL(reg));
}
#endif /* __STMMAC_PCS_H__ */
--
2.47.3
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* Re: [next-20260122] Build failure on IBM Power Server
From: Vladimir Oltean @ 2026-01-23 10:39 UTC (permalink / raw)
To: Christophe Leroy (CS GROUP)
Cc: Venkat Rao Bagalkote, Randy Dunlap, Madhavan Srinivasan, broonie,
Linux Next Mailing List, Maxime Chevallier, Jakub Kicinski, LKML,
linuxppc-dev, netdev@vger.kernel.org, Vinod Koul, linux-phy
In-Reply-To: <fa330d98-653c-4643-aee9-9697068e734a@kernel.org>
On Fri, Jan 23, 2026 at 10:52:49AM +0100, Christophe Leroy (CS GROUP) wrote:
> +Vladimir, Maxime, Jakub and netdev
>
> Le 23/01/2026 à 10:11, Venkat Rao Bagalkote a écrit :
> >
> > On 23/01/26 1:17 pm, Randy Dunlap wrote:
> > >
> > > On 1/22/26 8:15 PM, Venkat Rao Bagalkote wrote:
> > > > Greetings!!
> > > >
> > > > IBM CI has reported build failure of 20260122 on IBM Power server.
> > > >
> > > >
> > > > Error:
> > > >
> > > >
> > > > ERROR: modpost: "phy_get_rx_polarity" [drivers/net/phy/
> > > > air_en8811h.ko] undefined!
> > > > ERROR: modpost: "phy_get_tx_polarity" [drivers/net/phy/
> > > > air_en8811h.ko] undefined!
> > > > make[2]: *** [scripts/Makefile.modpost:147: Module.symvers] Error 1
> > > > make[1]: *** [/home/upstreamci/linux/Makefile:2040: modpost] Error 2
> > > > make: *** [Makefile:248: __sub-make] Error 2
>
> Thanks for the config file.
>
> The probleme is because allthough CONFIG_PHY_COMMON_PROPS is selected,
> drivers/phy/phy-common-props.o is not built because CONFIG_GENERIC_PHY
> is not selected.
>
> Likely comes from commit 66d8a334b57e ("net: phy: air_en8811h: deprecate
> "airoha,pnswap-rx" and "airoha,pnswap-tx"")
>
> Christophe
The intention was for drivers/phy/phy-common-props.o to be
buildable/usable without CONFIG_GENERIC_PHY.
Does this help?
diff --git a/drivers/Makefile b/drivers/Makefile
index ccc05f1eae3e..53fbd2e0acdd 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -10,7 +10,7 @@ obj-y += cache/
obj-y += irqchip/
obj-y += bus/
-obj-$(CONFIG_GENERIC_PHY) += phy/
+obj-y += phy/
# GPIO must come after pinctrl as gpios may need to mux pins etc
obj-$(CONFIG_PINCTRL) += pinctrl/
>
>
> > > >
> > > >
> > > > IBM CI has bisected this issue and below is the bisection log.
> > > >
> > > >
> > > > git bisect log
> > > > git bisect log
> > > > git bisect start
> > > > # status: waiting for both good and bad commits
> > > > # good: [24d479d26b25bce5faea3ddd9fa8f3a6c3129ea7] Linux 6.19-rc6
> > > > git bisect good 24d479d26b25bce5faea3ddd9fa8f3a6c3129ea7
> > > > # status: waiting for bad commit, 1 good commit known
> > > > # bad: [a0c666c25aeefd16f4b088c6549a6fb6b65a8a1d] Add linux-next
> > > > specific files for 20260122
> > > > git bisect bad a0c666c25aeefd16f4b088c6549a6fb6b65a8a1d
> > > > # good: [2574bcf1765ec13bf3ef469aa5b15cce293aebb6] Merge branch
> > > > 'master' of Warning: Removed corrupted safelink.
> > > > url=https%3A%2F%2Fgit.kernel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Fbluetooth%2Fbluetooth-next.git&data=05%7C02%7Cchristophe.leroy2%40cs-soprasteria.com%7C441b227c282845cf2a3308de5a5f8110%7C8b87af7d86474dc78df45f69a2011bb5%7C0%7C0%7C639047563441808471%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=FlVDfg3VVHplFxnQpG4oQNlr5Mm3ZzaCve19hnomYNo%3D&reserved=0
> > > > git bisect good 2574bcf1765ec13bf3ef469aa5b15cce293aebb6
> > > > # good: [2ad38467d20c16f38d0cffad711ef4f4acdb8b29] Merge branch 'for-
> > > > next' of Warning: Removed corrupted safelink.
> > > > url=https%3A%2F%2Fgit.kernel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Faxboe%2Flinux.git&data=05%7C02%7Cchristophe.leroy2%40cs-soprasteria.com%7C441b227c282845cf2a3308de5a5f8110%7C8b87af7d86474dc78df45f69a2011bb5%7C0%7C0%7C639047563441834557%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=ez4lgXXDn95PjgZNSAjwp%2BWbvJvQYLeHApGrODqs%2Fmc%3D&reserved=0
> > > > git bisect good 2ad38467d20c16f38d0cffad711ef4f4acdb8b29
> > > > # good: [a954370fea56ee1bf995524255a34da7a1ddb524] Merge branch 'for-
> > > > next' of Warning: Removed corrupted safelink.
> > > > url=https%3A%2F%2Fgit.kernel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Fpdx86%2Fplatform-drivers-x86.git&data=05%7C02%7Cchristophe.leroy2%40cs-soprasteria.com%7C441b227c282845cf2a3308de5a5f8110%7C8b87af7d86474dc78df45f69a2011bb5%7C0%7C0%7C639047563441853661%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=c4Fim5nuBV9O%2BfFTUltpoLTV19%2Fdy394PvzzGBxh8I4%3D&reserved=0
> > > > git bisect good a954370fea56ee1bf995524255a34da7a1ddb524
> > > > # good: [c7ec480f05dd0185a26f190471905ddf1215bc52] Merge branch
> > > > 'staging-next' of Warning: Removed corrupted safelink.
> > > > url=https%3A%2F%2Fgit.kernel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Fgregkh%2Fstaging.git&data=05%7C02%7Cchristophe.leroy2%40cs-soprasteria.com%7C441b227c282845cf2a3308de5a5f8110%7C8b87af7d86474dc78df45f69a2011bb5%7C0%7C0%7C639047563441870081%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=xgtRCeDKj7BL1EXx%2BSEtCzR5gaN6wKfihyiwh0AFsRM%3D&reserved=0
> > > > git bisect good c7ec480f05dd0185a26f190471905ddf1215bc52
> > > > # good: [4427398fed2b8e07a62fd4f3f6fcf9ffcf56829a] Merge branch 'for-
> > > > next' of Warning: Removed corrupted safelink.
> > > > url=https%3A%2F%2Fgit.kernel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Flinusw%2Flinux-pinctrl.git&data=05%7C02%7Cchristophe.leroy2%40cs-soprasteria.com%7C441b227c282845cf2a3308de5a5f8110%7C8b87af7d86474dc78df45f69a2011bb5%7C0%7C0%7C639047563441887814%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=AzoGH2fuDhFyYqK9JxlVZEsx3V7P5x8Yc8%2BuVE%2BBHJ4%3D&reserved=0
> > > > git bisect good 4427398fed2b8e07a62fd4f3f6fcf9ffcf56829a
> > > > # good: [852ccea1ca3144beb7003976d4fa04dbf81b307b] Merge branch
> > > > 'next' of Warning: Removed corrupted safelink.
> > > > url=https%3A%2F%2Fgit.kernel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Fmic%2Flinux.git&data=05%7C02%7Cchristophe.leroy2%40cs-soprasteria.com%7C441b227c282845cf2a3308de5a5f8110%7C8b87af7d86474dc78df45f69a2011bb5%7C0%7C0%7C639047563441903764%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=%2BTtdFgkDy9QevJOIHlzjk7Jjd1390L6g0Nr5RpSTYp8%3D&reserved=0
> > > > git bisect good 852ccea1ca3144beb7003976d4fa04dbf81b307b
> > > > # good: [f174dabd307dfd92edacb34e8bee0384daa1bd2e] Merge branch
> > > > 'next' of Warning: Removed corrupted safelink.
> > > > url=https%3A%2F%2Fgit.kernel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Flenb%2Flinux.git&data=05%7C02%7Cchristophe.leroy2%40cs-soprasteria.com%7C441b227c282845cf2a3308de5a5f8110%7C8b87af7d86474dc78df45f69a2011bb5%7C0%7C0%7C639047563441919983%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=%2BaVHILI%2FJcj%2BedPEPrJ1zFeSRGwuXUKb0VHFpZ%2Bp95s%3D&reserved=0
> > > > git bisect good f174dabd307dfd92edacb34e8bee0384daa1bd2e
> > > > # good: [e31f3c967c66cf03eecdf50fe138d05f635e3698] doc: Add
> > > > housekeeping documentation
> > > > git bisect good e31f3c967c66cf03eecdf50fe138d05f635e3698
> > > > # good: [0cc83fc23debf3e2df19c4510a77fe2d60ab2693] gpu: nova-core:
> > > > don't print raw PMU table entries
> > > > git bisect good 0cc83fc23debf3e2df19c4510a77fe2d60ab2693
> > > > # good: [75df6953fed6b7274f9c5080925ae4c8d3e424e6] Merge branch 'for-
> > > > next' of Warning: Removed corrupted safelink.
> > > > url=https%3A%2F%2Fgit.kernel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Ffrederic%2Flinux-dynticks.git&data=05%7C02%7Cchristophe.leroy2%40cs-soprasteria.com%7C441b227c282845cf2a3308de5a5f8110%7C8b87af7d86474dc78df45f69a2011bb5%7C0%7C0%7C639047563441936107%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=beNKxNQCA6SYkfbETF9eJYQ7mBFWwCKUFce6cwNbHUA%3D&reserved=0
> > > > git bisect good 75df6953fed6b7274f9c5080925ae4c8d3e424e6
> > > > # good: [086714bbb96f63785da251e1f8d1ce3e716a6e42] Merge tag 'v6.19-
> > > > rc5' into drm-rust-next
> > > > git bisect good 086714bbb96f63785da251e1f8d1ce3e716a6e42
> > > > # good: [6ea52b6d8f33ae627f4dcf43b12b6e713a8b9331] drm/tyr: use
> > > > read_poll_timeout
> > > > git bisect good 6ea52b6d8f33ae627f4dcf43b12b6e713a8b9331
> > > > # good: [b956937ce78fae5fa785f6a95f291e2137502c5e] drm: tyr: Mark BROKEN
> > > > git bisect good b956937ce78fae5fa785f6a95f291e2137502c5e
> > > > # first bad commit: [a0c666c25aeefd16f4b088c6549a6fb6b65a8a1d] Add
> > > > linux-next specific files for 20260122
> > > >
> > > >
> > > > If you happen to fix, this please add below tag.
> > > >
> > > >
> > > > Reported-by: Venkat Rao Bagalkote <venkat88@linux.ibm.com>
> > > I don't think that bisection helps very much.
> > >
> > > Can you post the kernel config file?
> > >
> >
> > Attached is the .config file.
> >
> >
> > GCC: gcc version 11.5.0 20240719 (Red Hat 11.5.0-2) (GCC)
> >
> > ld: GNU ld version 2.35.2-54.el9
> >
> >
> > Regards,
> >
> > Venkat.
>
--
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^ permalink raw reply related
* Re: [next-20260122] Build failure on IBM Power Server
From: Christophe Leroy (CS GROUP) @ 2026-01-23 10:52 UTC (permalink / raw)
To: Vladimir Oltean
Cc: Venkat Rao Bagalkote, Randy Dunlap, Madhavan Srinivasan, broonie,
Linux Next Mailing List, Maxime Chevallier, Jakub Kicinski, LKML,
linuxppc-dev, netdev@vger.kernel.org, Vinod Koul, linux-phy
In-Reply-To: <20260123103922.sr7m7py7d4afvc2f@skbuf>
Le 23/01/2026 à 11:39, Vladimir Oltean a écrit :
> On Fri, Jan 23, 2026 at 10:52:49AM +0100, Christophe Leroy (CS GROUP) wrote:
>> +Vladimir, Maxime, Jakub and netdev
>>
>> Le 23/01/2026 à 10:11, Venkat Rao Bagalkote a écrit :
>>>
>>> On 23/01/26 1:17 pm, Randy Dunlap wrote:
>>>>
>>>> On 1/22/26 8:15 PM, Venkat Rao Bagalkote wrote:
>>>>> Greetings!!
>>>>>
>>>>> IBM CI has reported build failure of 20260122 on IBM Power server.
>>>>>
>>>>>
>>>>> Error:
>>>>>
>>>>>
>>>>> ERROR: modpost: "phy_get_rx_polarity" [drivers/net/phy/
>>>>> air_en8811h.ko] undefined!
>>>>> ERROR: modpost: "phy_get_tx_polarity" [drivers/net/phy/
>>>>> air_en8811h.ko] undefined!
>>>>> make[2]: *** [scripts/Makefile.modpost:147: Module.symvers] Error 1
>>>>> make[1]: *** [/home/upstreamci/linux/Makefile:2040: modpost] Error 2
>>>>> make: *** [Makefile:248: __sub-make] Error 2
>>
>> Thanks for the config file.
>>
>> The probleme is because allthough CONFIG_PHY_COMMON_PROPS is selected,
>> drivers/phy/phy-common-props.o is not built because CONFIG_GENERIC_PHY
>> is not selected.
>>
>> Likely comes from commit 66d8a334b57e ("net: phy: air_en8811h: deprecate
>> "airoha,pnswap-rx" and "airoha,pnswap-tx"")
>>
>> Christophe
>
> The intention was for drivers/phy/phy-common-props.o to be
> buildable/usable without CONFIG_GENERIC_PHY.
>
> Does this help?
Yes it fixes the build for me.
Christophe
>
> diff --git a/drivers/Makefile b/drivers/Makefile
> index ccc05f1eae3e..53fbd2e0acdd 100644
> --- a/drivers/Makefile
> +++ b/drivers/Makefile
> @@ -10,7 +10,7 @@ obj-y += cache/
> obj-y += irqchip/
> obj-y += bus/
>
> -obj-$(CONFIG_GENERIC_PHY) += phy/
> +obj-y += phy/
>
> # GPIO must come after pinctrl as gpios may need to mux pins etc
> obj-$(CONFIG_PINCTRL) += pinctrl/
>
>>
>>
>>>>>
>>>>>
>>>>> IBM CI has bisected this issue and below is the bisection log.
>>>>>
>>>>>
>>>>> git bisect log
>>>>> git bisect log
>>>>> git bisect start
>>>>> # status: waiting for both good and bad commits
>>>>> # good: [24d479d26b25bce5faea3ddd9fa8f3a6c3129ea7] Linux 6.19-rc6
>>>>> git bisect good 24d479d26b25bce5faea3ddd9fa8f3a6c3129ea7
>>>>> # status: waiting for bad commit, 1 good commit known
>>>>> # bad: [a0c666c25aeefd16f4b088c6549a6fb6b65a8a1d] Add linux-next
>>>>> specific files for 20260122
>>>>> git bisect bad a0c666c25aeefd16f4b088c6549a6fb6b65a8a1d
>>>>> # good: [2574bcf1765ec13bf3ef469aa5b15cce293aebb6] Merge branch
>>>>> 'master' of Warning: Removed corrupted safelink.
>>>>> url=https%3A%2F%2Fgit.kernel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Fbluetooth%2Fbluetooth-next.git&data=05%7C02%7Cchristophe.leroy2%40cs-soprasteria.com%7C441b227c282845cf2a3308de5a5f8110%7C8b87af7d86474dc78df45f69a2011bb5%7C0%7C0%7C639047563441808471%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=FlVDfg3VVHplFxnQpG4oQNlr5Mm3ZzaCve19hnomYNo%3D&reserved=0
>>>>> git bisect good 2574bcf1765ec13bf3ef469aa5b15cce293aebb6
>>>>> # good: [2ad38467d20c16f38d0cffad711ef4f4acdb8b29] Merge branch 'for-
>>>>> next' of Warning: Removed corrupted safelink.
>>>>> url=https%3A%2F%2Fgit.kernel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Faxboe%2Flinux.git&data=05%7C02%7Cchristophe.leroy2%40cs-soprasteria.com%7C441b227c282845cf2a3308de5a5f8110%7C8b87af7d86474dc78df45f69a2011bb5%7C0%7C0%7C639047563441834557%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=ez4lgXXDn95PjgZNSAjwp%2BWbvJvQYLeHApGrODqs%2Fmc%3D&reserved=0
>>>>> git bisect good 2ad38467d20c16f38d0cffad711ef4f4acdb8b29
>>>>> # good: [a954370fea56ee1bf995524255a34da7a1ddb524] Merge branch 'for-
>>>>> next' of Warning: Removed corrupted safelink.
>>>>> url=https%3A%2F%2Fgit.kernel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Fpdx86%2Fplatform-drivers-x86.git&data=05%7C02%7Cchristophe.leroy2%40cs-soprasteria.com%7C441b227c282845cf2a3308de5a5f8110%7C8b87af7d86474dc78df45f69a2011bb5%7C0%7C0%7C639047563441853661%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=c4Fim5nuBV9O%2BfFTUltpoLTV19%2Fdy394PvzzGBxh8I4%3D&reserved=0
>>>>> git bisect good a954370fea56ee1bf995524255a34da7a1ddb524
>>>>> # good: [c7ec480f05dd0185a26f190471905ddf1215bc52] Merge branch
>>>>> 'staging-next' of Warning: Removed corrupted safelink.
>>>>> url=https%3A%2F%2Fgit.kernel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Fgregkh%2Fstaging.git&data=05%7C02%7Cchristophe.leroy2%40cs-soprasteria.com%7C441b227c282845cf2a3308de5a5f8110%7C8b87af7d86474dc78df45f69a2011bb5%7C0%7C0%7C639047563441870081%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=xgtRCeDKj7BL1EXx%2BSEtCzR5gaN6wKfihyiwh0AFsRM%3D&reserved=0
>>>>> git bisect good c7ec480f05dd0185a26f190471905ddf1215bc52
>>>>> # good: [4427398fed2b8e07a62fd4f3f6fcf9ffcf56829a] Merge branch 'for-
>>>>> next' of Warning: Removed corrupted safelink.
>>>>> url=https%3A%2F%2Fgit.kernel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Flinusw%2Flinux-pinctrl.git&data=05%7C02%7Cchristophe.leroy2%40cs-soprasteria.com%7C441b227c282845cf2a3308de5a5f8110%7C8b87af7d86474dc78df45f69a2011bb5%7C0%7C0%7C639047563441887814%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=AzoGH2fuDhFyYqK9JxlVZEsx3V7P5x8Yc8%2BuVE%2BBHJ4%3D&reserved=0
>>>>> git bisect good 4427398fed2b8e07a62fd4f3f6fcf9ffcf56829a
>>>>> # good: [852ccea1ca3144beb7003976d4fa04dbf81b307b] Merge branch
>>>>> 'next' of Warning: Removed corrupted safelink.
>>>>> url=https%3A%2F%2Fgit.kernel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Fmic%2Flinux.git&data=05%7C02%7Cchristophe.leroy2%40cs-soprasteria.com%7C441b227c282845cf2a3308de5a5f8110%7C8b87af7d86474dc78df45f69a2011bb5%7C0%7C0%7C639047563441903764%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=%2BTtdFgkDy9QevJOIHlzjk7Jjd1390L6g0Nr5RpSTYp8%3D&reserved=0
>>>>> git bisect good 852ccea1ca3144beb7003976d4fa04dbf81b307b
>>>>> # good: [f174dabd307dfd92edacb34e8bee0384daa1bd2e] Merge branch
>>>>> 'next' of Warning: Removed corrupted safelink.
>>>>> url=https%3A%2F%2Fgit.kernel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Flenb%2Flinux.git&data=05%7C02%7Cchristophe.leroy2%40cs-soprasteria.com%7C441b227c282845cf2a3308de5a5f8110%7C8b87af7d86474dc78df45f69a2011bb5%7C0%7C0%7C639047563441919983%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=%2BaVHILI%2FJcj%2BedPEPrJ1zFeSRGwuXUKb0VHFpZ%2Bp95s%3D&reserved=0
>>>>> git bisect good f174dabd307dfd92edacb34e8bee0384daa1bd2e
>>>>> # good: [e31f3c967c66cf03eecdf50fe138d05f635e3698] doc: Add
>>>>> housekeeping documentation
>>>>> git bisect good e31f3c967c66cf03eecdf50fe138d05f635e3698
>>>>> # good: [0cc83fc23debf3e2df19c4510a77fe2d60ab2693] gpu: nova-core:
>>>>> don't print raw PMU table entries
>>>>> git bisect good 0cc83fc23debf3e2df19c4510a77fe2d60ab2693
>>>>> # good: [75df6953fed6b7274f9c5080925ae4c8d3e424e6] Merge branch 'for-
>>>>> next' of Warning: Removed corrupted safelink.
>>>>> url=https%3A%2F%2Fgit.kernel.org%2Fpub%2Fscm%2Flinux%2Fkernel%2Fgit%2Ffrederic%2Flinux-dynticks.git&data=05%7C02%7Cchristophe.leroy2%40cs-soprasteria.com%7C441b227c282845cf2a3308de5a5f8110%7C8b87af7d86474dc78df45f69a2011bb5%7C0%7C0%7C639047563441936107%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=beNKxNQCA6SYkfbETF9eJYQ7mBFWwCKUFce6cwNbHUA%3D&reserved=0
>>>>> git bisect good 75df6953fed6b7274f9c5080925ae4c8d3e424e6
>>>>> # good: [086714bbb96f63785da251e1f8d1ce3e716a6e42] Merge tag 'v6.19-
>>>>> rc5' into drm-rust-next
>>>>> git bisect good 086714bbb96f63785da251e1f8d1ce3e716a6e42
>>>>> # good: [6ea52b6d8f33ae627f4dcf43b12b6e713a8b9331] drm/tyr: use
>>>>> read_poll_timeout
>>>>> git bisect good 6ea52b6d8f33ae627f4dcf43b12b6e713a8b9331
>>>>> # good: [b956937ce78fae5fa785f6a95f291e2137502c5e] drm: tyr: Mark BROKEN
>>>>> git bisect good b956937ce78fae5fa785f6a95f291e2137502c5e
>>>>> # first bad commit: [a0c666c25aeefd16f4b088c6549a6fb6b65a8a1d] Add
>>>>> linux-next specific files for 20260122
>>>>>
>>>>>
>>>>> If you happen to fix, this please add below tag.
>>>>>
>>>>>
>>>>> Reported-by: Venkat Rao Bagalkote <venkat88@linux.ibm.com>
>>>> I don't think that bisection helps very much.
>>>>
>>>> Can you post the kernel config file?
>>>>
>>>
>>> Attached is the .config file.
>>>
>>>
>>> GCC: gcc version 11.5.0 20240719 (Red Hat 11.5.0-2) (GCC)
>>>
>>> ld: GNU ld version 2.35.2-54.el9
>>>
>>>
>>> Regards,
>>>
>>> Venkat.
>>
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^ permalink raw reply
* [PATCH phy] phy: enter drivers/phy/Makefile even without CONFIG_GENERIC_PHY
From: Vladimir Oltean @ 2026-01-23 11:06 UTC (permalink / raw)
To: linux-phy, Vinod Koul, Neil Armstrong
Cc: netdev, Paolo Abeni, Bjørn Mork, linux-kernel,
Venkat Rao Bagalkote, Christophe Leroy (CS GROUP)
Kconfig option CONFIG_PHY_COMMON_PROPS, which builds
drivers/phy/phy-common-props.c, was intended to be selectable
independently of CONFIG_GENERIC_PHY. Yet it lives in drivers/phy/, which
is entered by the Makefile only if CONFIG_GENERIC_PHY is set.
Allow the Makefile to enter one level deeper, but stop at drivers/phy/
if CONFIG_GENERIC_PHY is unselected (i.e. do not enter vendor folders).
The other stuff from drivers/phy/Makefile except for CONFIG_PHY_COMMON_PROPS,
like CONFIG_PHY_NXP_PTN3222, all depends on CONFIG_GENERIC_PHY.
Fixes: e7556b59ba65 ("phy: add phy_get_rx_polarity() and phy_get_tx_polarity()")
Closes: https://lore.kernel.org/lkml/43ea0202-891d-4582-980b-5cb557b41114@linux.ibm.com/
Reported-by: Venkat Rao Bagalkote <venkat88@linux.ibm.com>
Debugged-by: "Christophe Leroy (CS GROUP)" <chleroy@kernel.org>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
drivers/Makefile | 2 +-
drivers/phy/Makefile | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/Makefile b/drivers/Makefile
index ccc05f1eae3e..53fbd2e0acdd 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -10,7 +10,7 @@ obj-y += cache/
obj-y += irqchip/
obj-y += bus/
-obj-$(CONFIG_GENERIC_PHY) += phy/
+obj-y += phy/
# GPIO must come after pinctrl as gpios may need to mux pins etc
obj-$(CONFIG_PINCTRL) += pinctrl/
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 30b150d68de7..93715ea0d010 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -15,7 +15,7 @@ obj-$(CONFIG_PHY_SNPS_EUSB2) += phy-snps-eusb2.o
obj-$(CONFIG_USB_LGM_PHY) += phy-lgm-usb.o
obj-$(CONFIG_PHY_AIROHA_PCIE) += phy-airoha-pcie.o
obj-$(CONFIG_PHY_NXP_PTN3222) += phy-nxp-ptn3222.o
-obj-y += allwinner/ \
+obj-$(CONFIG_GENERIC_PHY) += allwinner/ \
amlogic/ \
broadcom/ \
cadence/ \
--
2.43.0
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^ permalink raw reply related
* Re: [next-20260122] Build failure on IBM Power Server
From: Vladimir Oltean @ 2026-01-23 11:07 UTC (permalink / raw)
To: Christophe Leroy (CS GROUP)
Cc: Venkat Rao Bagalkote, Randy Dunlap, Madhavan Srinivasan, broonie,
Linux Next Mailing List, Maxime Chevallier, Jakub Kicinski, LKML,
linuxppc-dev, netdev@vger.kernel.org, Vinod Koul, linux-phy
In-Reply-To: <2b41debd-9a05-4707-b270-a8fa3dd7768c@kernel.org>
On Fri, Jan 23, 2026 at 11:52:45AM +0100, Christophe Leroy (CS GROUP) wrote:
> Le 23/01/2026 à 11:39, Vladimir Oltean a écrit :
> > On Fri, Jan 23, 2026 at 10:52:49AM +0100, Christophe Leroy (CS GROUP) wrote:
> > > +Vladimir, Maxime, Jakub and netdev
> > >
> > > Le 23/01/2026 à 10:11, Venkat Rao Bagalkote a écrit :
> > > >
> > > > On 23/01/26 1:17 pm, Randy Dunlap wrote:
> > > > >
> > > > > On 1/22/26 8:15 PM, Venkat Rao Bagalkote wrote:
> > > > > > Greetings!!
> > > > > >
> > > > > > IBM CI has reported build failure of 20260122 on IBM Power server.
> > > > > >
> > > > > >
> > > > > > Error:
> > > > > >
> > > > > >
> > > > > > ERROR: modpost: "phy_get_rx_polarity" [drivers/net/phy/
> > > > > > air_en8811h.ko] undefined!
> > > > > > ERROR: modpost: "phy_get_tx_polarity" [drivers/net/phy/
> > > > > > air_en8811h.ko] undefined!
> > > > > > make[2]: *** [scripts/Makefile.modpost:147: Module.symvers] Error 1
> > > > > > make[1]: *** [/home/upstreamci/linux/Makefile:2040: modpost] Error 2
> > > > > > make: *** [Makefile:248: __sub-make] Error 2
> > >
> > > Thanks for the config file.
> > >
> > > The probleme is because allthough CONFIG_PHY_COMMON_PROPS is selected,
> > > drivers/phy/phy-common-props.o is not built because CONFIG_GENERIC_PHY
> > > is not selected.
> > >
> > > Likely comes from commit 66d8a334b57e ("net: phy: air_en8811h: deprecate
> > > "airoha,pnswap-rx" and "airoha,pnswap-tx"")
> > >
> > > Christophe
> >
> > The intention was for drivers/phy/phy-common-props.o to be
> > buildable/usable without CONFIG_GENERIC_PHY.
> >
> > Does this help?
>
> Yes it fixes the build for me.
>
> Christophe
Patch sent:
https://lore.kernel.org/linux-phy/20260123110600.3118561-1-vladimir.oltean@nxp.com/
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