* Re: [PATCH v2 4/6] dt-bindings: phy: mediatek,dsi-phy: Add support for mt8167
From: Krzysztof Kozlowski @ 2026-02-17 7:55 UTC (permalink / raw)
To: Luca Leonardo Scorcia
Cc: linux-mediatek, Chun-Kuang Hu, Philipp Zabel, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, David Airlie, Simona Vetter,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Chunfeng Yun,
Vinod Koul, Neil Armstrong, Matthias Brugger,
AngeloGioacchino Del Regno, Jitao Shi, Fabien Parent, dri-devel,
devicetree, linux-kernel, linux-arm-kernel, linux-phy
In-Reply-To: <66fbd5dd3604ffc4fda45022c1db68e4e0be6714.1771258407.git.l.scorcia@gmail.com>
On Mon, Feb 16, 2026 at 04:22:15PM +0000, Luca Leonardo Scorcia wrote:
> Add support for the MediaTek mt8167 SoC: the DSI PHY found
> in this chip is fully compatible with the one found in the mt2701 SoC.
>
> Signed-off-by: Luca Leonardo Scorcia <l.scorcia@gmail.com>
> ---
> Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml | 1 +
> 1 file changed, 1 insertion(+)
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
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* Re: [PATCH v3] phy: k1-usb: add disconnect function support
From: Vladimir Oltean @ 2026-02-16 22:12 UTC (permalink / raw)
To: Yixun Lan
Cc: Vinod Koul, Neil Armstrong, Ze Huang, Junzhong Pan, spacemit,
linux-phy, linux-riscv, linux-kernel
In-Reply-To: <20260216152653.25244-1-dlan@kernel.org>
On Mon, Feb 16, 2026 at 11:26:53PM +0800, Yixun Lan wrote:
> A disconnect status BIT of USB2 PHY need to be cleared, otherwise
> it will fail to work properly during next connection when devices
> connect to roothub directly.
>
> Fixes: fe4bc1a08638 ("phy: spacemit: support K1 USB2.0 PHY controller")
> Signed-off-by: Yixun Lan <dlan@kernel.org>
> ---
> To: Vinod Koul <vkoul@kernel.org>
> To: Neil Armstrong <neil.armstrong@linaro.org>
> To: Ze Huang <huang.ze@linux.dev>
> Cc: Vladimir Oltean <olteanv@gmail.com>
> Cc: Junzhong Pan <panjunzhong@linux.spacemit.com>
> Cc: spacemit@lists.linux.dev
> Cc: linux-phy@lists.infradead.org
> Cc: linux-riscv@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
>
> Change in v3:
> - split from v2 as bug fix
> - fix alignment to open parenthesis
> - http://lore.kernel.org/r/20260216090112.n5jjpui3luqsybb5@skbuf
> - Link to v2: https://lore.kernel.org/r/20260214-11-k3-usb2-phy-v2-0-6ed31e031ab4@kernel.org
> ---
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
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* [PATCH v2 6/6] gpu: drm: mediatek: ovl: add specific entry for mt8167
From: Luca Leonardo Scorcia @ 2026-02-16 16:22 UTC (permalink / raw)
To: linux-mediatek
Cc: Val Packett, Luca Leonardo Scorcia, AngeloGioacchino Del Regno,
Chun-Kuang Hu, Philipp Zabel, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Chunfeng Yun, Vinod Koul,
Neil Armstrong, Matthias Brugger, Jitao Shi, Fabien Parent,
dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-phy
In-Reply-To: <cover.1771258407.git.l.scorcia@gmail.com>
From: Val Packett <val@packett.cool>
From: Val Packett <val@packett.cool>
While this configuration is otherwise identical to mt8173, according
to Android kernel sources, this SoC does need smi_id_en.
Signed-off-by: Val Packett <val@packett.cool>
Signed-off-by: Luca Leonardo Scorcia <l.scorcia@gmail.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index e0236353d499..97a899e4bd99 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -671,6 +671,16 @@ static const struct mtk_disp_ovl_data mt2701_ovl_driver_data = {
.num_formats = ARRAY_SIZE(mt8173_formats),
};
+static const struct mtk_disp_ovl_data mt8167_ovl_driver_data = {
+ .addr = DISP_REG_OVL_ADDR_MT8173,
+ .gmc_bits = 8,
+ .layer_nr = 4,
+ .fmt_rgb565_is_0 = true,
+ .smi_id_en = true,
+ .formats = mt8173_formats,
+ .num_formats = ARRAY_SIZE(mt8173_formats),
+};
+
static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = {
.addr = DISP_REG_OVL_ADDR_MT8173,
.gmc_bits = 8,
@@ -742,6 +752,8 @@ static const struct mtk_disp_ovl_data mt8195_ovl_driver_data = {
static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
{ .compatible = "mediatek,mt2701-disp-ovl",
.data = &mt2701_ovl_driver_data},
+ { .compatible = "mediatek,mt8167-disp-ovl",
+ .data = &mt8167_ovl_driver_data},
{ .compatible = "mediatek,mt8173-disp-ovl",
.data = &mt8173_ovl_driver_data},
{ .compatible = "mediatek,mt8183-disp-ovl",
--
2.43.0
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* [PATCH v2 5/6] arm64: dts: mediatek: mt8167: Add DRM nodes
From: Luca Leonardo Scorcia @ 2026-02-16 16:22 UTC (permalink / raw)
To: linux-mediatek
Cc: Luca Leonardo Scorcia, Chun-Kuang Hu, Philipp Zabel,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chunfeng Yun, Vinod Koul, Neil Armstrong, Matthias Brugger,
AngeloGioacchino Del Regno, Jitao Shi, Fabien Parent, dri-devel,
devicetree, linux-kernel, linux-arm-kernel, linux-phy
In-Reply-To: <cover.1771258407.git.l.scorcia@gmail.com>
Add all the DRM nodes required to get DSI to work on MT8167 SoC.
Signed-off-by: Luca Leonardo Scorcia <l.scorcia@gmail.com>
---
arch/arm64/boot/dts/mediatek/mt8167.dtsi | 317 +++++++++++++++++++++++
1 file changed, 317 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
index 27cf32d7ae35..c131513ba240 100644
--- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
@@ -16,6 +16,20 @@
/ {
compatible = "mediatek,mt8167";
+ aliases {
+ aal0 = &aal;
+ ccorr0 = &ccorr;
+ color0 = &color;
+ dither0 = &dither;
+ dsi0 = &dsi;
+ gamma0 = γ
+ ovl0 = &ovl0;
+ pwm0 = &disp_pwm;
+ rdma0 = &rdma0;
+ rdma1 = &rdma1;
+ wdma0 = &wdma;
+ };
+
soc {
topckgen: topckgen@10000000 {
compatible = "mediatek,mt8167-topckgen", "syscon";
@@ -120,10 +134,303 @@ iommu: m4u@10203000 {
#iommu-cells = <1>;
};
+ disp_pwm: pwm@1100f000 {
+ compatible = "mediatek,mt8167-disp-pwm", "mediatek,mt8173-disp-pwm";
+ reg = <0 0x1100f000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_DISP_PWM_26M>, <&mmsys CLK_MM_DISP_PWM_MM>;
+ clock-names = "main", "mm";
+ power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
mmsys: syscon@14000000 {
compatible = "mediatek,mt8167-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;
+ power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
#clock-cells = <1>;
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mmsys_main: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&ovl0_in>;
+ };
+
+ mmsys_ext: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&rdma1_in>;
+ };
+ };
+ };
+
+ ovl0: ovl0@14007000 {
+ compatible = "mediatek,mt8167-disp-ovl";
+ reg = <0 0x14007000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_DISP_OVL0>;
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_LOW>;
+ iommus = <&iommu M4U_PORT_DISP_OVL0>;
+ power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ ovl0_in: endpoint {
+ remote-endpoint = <&mmsys_main>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ ovl0_out: endpoint {
+ remote-endpoint = <&color_in>;
+ };
+ };
+ };
+ };
+
+ rdma0: rdma0@14009000 {
+ compatible = "mediatek,mt8167-disp-rdma", "mediatek,mt2701-disp-rdma";
+ reg = <0 0x14009000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA0>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>;
+ iommus = <&iommu M4U_PORT_DISP_RDMA0>;
+ power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ rdma0_in: endpoint {
+ remote-endpoint = <&dither_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ rdma0_out: endpoint {
+ remote-endpoint = <&dsi_in>;
+ };
+ };
+ };
+ };
+
+ rdma1: rdma1@1400a000 {
+ compatible = "mediatek,mt8167-disp-rdma", "mediatek,mt2701-disp-rdma";
+ reg = <0 0x1400a000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA1>;
+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_LOW>;
+ iommus = <&iommu M4U_PORT_DISP_RDMA1>;
+ power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ rdma1_in: endpoint {
+ remote-endpoint = <&mmsys_ext>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ rdma1_out: endpoint { };
+ };
+ };
+ };
+
+ wdma: wdma0@1400b000 {
+ compatible = "mediatek,mt8167-disp-wdma", "mediatek,mt8173-disp-wdma";
+ reg = <0 0x1400b000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_DISP_WDMA>;
+ interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>;
+ iommus = <&iommu M4U_PORT_DISP_WDMA0>;
+ power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+ };
+
+ color: color@1400c000 {
+ compatible = "mediatek,mt8167-disp-color";
+ reg = <0 0x1400c000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_DISP_COLOR>;
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ color_in: endpoint {
+ remote-endpoint = <&ovl0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ color_out: endpoint {
+ remote-endpoint = <&ccorr_in>;
+ };
+ };
+ };
+ };
+
+ ccorr: ccorr@1400d000 {
+ compatible = "mediatek,mt8167-disp-ccorr", "mediatek,mt8183-disp-ccorr";
+ reg = <0 0x1400d000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_DISP_CCORR>;
+ interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ ccorr_in: endpoint {
+ remote-endpoint = <&color_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ ccorr_out: endpoint {
+ remote-endpoint = <&aal_in>;
+ };
+ };
+ };
+ };
+
+ aal: aal@1400e000 {
+ compatible = "mediatek,mt8167-disp-aal", "mediatek,mt8173-disp-aal";
+ reg = <0 0x1400e000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_DISP_AAL>;
+ interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ aal_in: endpoint {
+ remote-endpoint = <&ccorr_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ aal_out: endpoint {
+ remote-endpoint = <&gamma_in>;
+ };
+ };
+ };
+ };
+
+ gamma: gamma@1400f000 {
+ compatible = "mediatek,mt8167-disp-gamma", "mediatek,mt8173-disp-gamma";
+ reg = <0 0x1400f000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_DISP_GAMMA>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ gamma_in: endpoint {
+ remote-endpoint = <&aal_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ gamma_out: endpoint {
+ remote-endpoint = <&dither_in>;
+ };
+ };
+ };
+ };
+
+ dither: dither@14010000 {
+ compatible = "mediatek,mt8167-disp-dither", "mediatek,mt8183-disp-dither";
+ reg = <0 0x14010000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_DISP_DITHER>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dither_in: endpoint {
+ remote-endpoint = <&gamma_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dither_out: endpoint {
+ remote-endpoint = <&rdma0_in>;
+ };
+ };
+ };
+ };
+
+ dsi: dsi@14012000 {
+ compatible = "mediatek,mt8167-dsi", "mediatek,mt2701-dsi";
+ reg = <0 0x14012000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_DSI_ENGINE>, <&mmsys CLK_MM_DSI_DIGITAL>,
+ <&mipi_tx>;
+ clock-names = "engine", "digital", "hs";
+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_LOW>;
+ phys = <&mipi_tx>;
+ phy-names = "dphy";
+ power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi_in: endpoint {
+ remote-endpoint = <&rdma0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi_out: endpoint { };
+ };
+ };
+ };
+
+ mutex: mutex@14015000 {
+ compatible = "mediatek,mt8167-disp-mutex";
+ reg = <0 0x14015000 0 0x1000>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
};
larb0: larb@14016000 {
@@ -145,6 +452,16 @@ smi_common: smi@14017000 {
power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
};
+ mipi_tx: dsi-phy@14018000 {
+ compatible = "mediatek,mt8167-mipi-tx", "mediatek,mt2701-mipi-tx";
+ reg = <0 0x14018000 0 0x90>;
+ clocks = <&topckgen CLK_TOP_MIPI_26M_DBG>;
+ clock-output-names = "mipi_tx0_pll";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
imgsys: syscon@15000000 {
compatible = "mediatek,mt8167-imgsys", "syscon";
reg = <0 0x15000000 0 0x1000>;
--
2.43.0
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* [PATCH v2 4/6] dt-bindings: phy: mediatek,dsi-phy: Add support for mt8167
From: Luca Leonardo Scorcia @ 2026-02-16 16:22 UTC (permalink / raw)
To: linux-mediatek
Cc: Luca Leonardo Scorcia, Chun-Kuang Hu, Philipp Zabel,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chunfeng Yun, Vinod Koul, Neil Armstrong, Matthias Brugger,
AngeloGioacchino Del Regno, Jitao Shi, Fabien Parent, dri-devel,
devicetree, linux-kernel, linux-arm-kernel, linux-phy
In-Reply-To: <cover.1771258407.git.l.scorcia@gmail.com>
Add support for the MediaTek mt8167 SoC: the DSI PHY found
in this chip is fully compatible with the one found in the mt2701 SoC.
Signed-off-by: Luca Leonardo Scorcia <l.scorcia@gmail.com>
---
Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml
index acdbce937b0a..c6d0bbdbe0e2 100644
--- a/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml
@@ -23,6 +23,7 @@ properties:
- items:
- enum:
- mediatek,mt7623-mipi-tx
+ - mediatek,mt8167-mipi-tx
- const: mediatek,mt2701-mipi-tx
- items:
- enum:
--
2.43.0
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* [PATCH v2 3/6] dt-bindings: display: mediatek: Correct compatibility for mt8167-dsi
From: Luca Leonardo Scorcia @ 2026-02-16 16:22 UTC (permalink / raw)
To: linux-mediatek
Cc: Luca Leonardo Scorcia, Chun-Kuang Hu, Philipp Zabel, David Airlie,
Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chunfeng Yun, Vinod Koul, Neil Armstrong, Matthias Brugger,
AngeloGioacchino Del Regno, Jitao Shi, Fabien Parent, dri-devel,
devicetree, linux-kernel, linux-arm-kernel, linux-phy
In-Reply-To: <cover.1771258407.git.l.scorcia@gmail.com>
Remove the dedicated "mediatek,mt8167-dsi" compatible from the device list and
describe it as compatible with mt2701 instead. It is safe to do so because:
- Bootloader doesn't rely on this single compatible; and
- There was never any upstreamed devicetree using this single compatible; and
- The MT8167 DSI Controller is fully compatible with the one found in MT2701.
Fixes: 8867c4b39361 ("dt-bindings: display: mediatek: dsi: add documentation for MT8167 SoC")
Signed-off-by: Luca Leonardo Scorcia <l.scorcia@gmail.com>
---
.../devicetree/bindings/display/mediatek/mediatek,dsi.yaml | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
index 27ffbccc2a08..bcbde16648c0 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
@@ -25,11 +25,14 @@ properties:
- enum:
- mediatek,mt2701-dsi
- mediatek,mt7623-dsi
- - mediatek,mt8167-dsi
- mediatek,mt8173-dsi
- mediatek,mt8183-dsi
- mediatek,mt8186-dsi
- mediatek,mt8188-dsi
+ - items:
+ - enum:
+ - mediatek,mt8167-dsi
+ - const: mediatek,mt2701-dsi
- items:
- enum:
- mediatek,mt6795-dsi
--
2.43.0
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* [PATCH v2 2/6] dt-bindings: display: mediatek: Add compatibles for MediaTek mt8167
From: Luca Leonardo Scorcia @ 2026-02-16 16:22 UTC (permalink / raw)
To: linux-mediatek
Cc: Luca Leonardo Scorcia, Krzysztof Kozlowski, Chun-Kuang Hu,
Philipp Zabel, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Chunfeng Yun, Vinod Koul,
Neil Armstrong, Matthias Brugger, AngeloGioacchino Del Regno,
Jitao Shi, Fabien Parent, dri-devel, devicetree, linux-kernel,
linux-arm-kernel, linux-phy
In-Reply-To: <cover.1771258407.git.l.scorcia@gmail.com>
Add compatibles for various display-related blocks of MediaTek mt8167.
Signed-off-by: Luca Leonardo Scorcia <l.scorcia@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
.../devicetree/bindings/display/mediatek/mediatek,aal.yaml | 1 +
.../devicetree/bindings/display/mediatek/mediatek,ccorr.yaml | 4 +++-
.../devicetree/bindings/display/mediatek/mediatek,dither.yaml | 1 +
.../devicetree/bindings/display/mediatek/mediatek,gamma.yaml | 1 +
.../devicetree/bindings/display/mediatek/mediatek,ovl.yaml | 1 +
.../devicetree/bindings/display/mediatek/mediatek,rdma.yaml | 1 +
.../devicetree/bindings/display/mediatek/mediatek,wdma.yaml | 4 +++-
7 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
index daf90ebb39bf..4bbea72b292a 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml
@@ -33,6 +33,7 @@ properties:
- enum:
- mediatek,mt2712-disp-aal
- mediatek,mt6795-disp-aal
+ - mediatek,mt8167-disp-aal
- const: mediatek,mt8173-disp-aal
- items:
- enum:
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
index fca8e7bb0cbc..5c5068128d0c 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
@@ -25,7 +25,9 @@ properties:
- mediatek,mt8183-disp-ccorr
- mediatek,mt8192-disp-ccorr
- items:
- - const: mediatek,mt8365-disp-ccorr
+ - enum:
+ - mediatek,mt8167-disp-ccorr
+ - mediatek,mt8365-disp-ccorr
- const: mediatek,mt8183-disp-ccorr
- items:
- enum:
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
index abaf27916d13..891c95be15b9 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dither.yaml
@@ -26,6 +26,7 @@ properties:
- mediatek,mt8183-disp-dither
- items:
- enum:
+ - mediatek,mt8167-disp-dither
- mediatek,mt8186-disp-dither
- mediatek,mt8188-disp-dither
- mediatek,mt8192-disp-dither
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
index 48542dc7e784..ec1054bb06d4 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,gamma.yaml
@@ -28,6 +28,7 @@ properties:
- items:
- enum:
- mediatek,mt6795-disp-gamma
+ - mediatek,mt8167-disp-gamma
- const: mediatek,mt8173-disp-gamma
- items:
- enum:
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
index 4f110635afb6..679f731f0f15 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml
@@ -23,6 +23,7 @@ properties:
oneOf:
- enum:
- mediatek,mt2701-disp-ovl
+ - mediatek,mt8167-disp-ovl
- mediatek,mt8173-disp-ovl
- mediatek,mt8183-disp-ovl
- mediatek,mt8192-disp-ovl
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
index 878f676b581f..cb187a95c11e 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml
@@ -36,6 +36,7 @@ properties:
- enum:
- mediatek,mt7623-disp-rdma
- mediatek,mt2712-disp-rdma
+ - mediatek,mt8167-disp-rdma
- const: mediatek,mt2701-disp-rdma
- items:
- enum:
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
index a3a2b71a4523..816841a96133 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
@@ -24,7 +24,9 @@ properties:
- enum:
- mediatek,mt8173-disp-wdma
- items:
- - const: mediatek,mt6795-disp-wdma
+ - enum:
+ - mediatek,mt6795-disp-wdma
+ - mediatek,mt8167-disp-wdma
- const: mediatek,mt8173-disp-wdma
reg:
--
2.43.0
--
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^ permalink raw reply related
* [PATCH v2 1/6] arm64: dts: mt8167: Reorder nodes according to mmio address
From: Luca Leonardo Scorcia @ 2026-02-16 16:22 UTC (permalink / raw)
To: linux-mediatek
Cc: Luca Leonardo Scorcia, AngeloGioacchino Del Regno, Chun-Kuang Hu,
Philipp Zabel, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Chunfeng Yun, Vinod Koul,
Neil Armstrong, Matthias Brugger, Jitao Shi, Fabien Parent,
dri-devel, devicetree, linux-kernel, linux-arm-kernel, linux-phy
In-Reply-To: <cover.1771258407.git.l.scorcia@gmail.com>
In preparation for adding display nodes. No other changes.
Signed-off-by: Luca Leonardo Scorcia <l.scorcia@gmail.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8167.dtsi | 68 ++++++++++++------------
1 file changed, 34 insertions(+), 34 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
index 2374c0953057..27cf32d7ae35 100644
--- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
@@ -29,12 +29,6 @@ infracfg: infracfg@10001000 {
#clock-cells = <1>;
};
- apmixedsys: apmixedsys@10018000 {
- compatible = "mediatek,mt8167-apmixedsys", "syscon";
- reg = <0 0x10018000 0 0x710>;
- #clock-cells = <1>;
- };
-
scpsys: syscon@10006000 {
compatible = "mediatek,mt8167-scpsys", "syscon", "simple-mfd";
reg = <0 0x10006000 0 0x1000>;
@@ -101,18 +95,6 @@ power-domain@MT8167_POWER_DOMAIN_CONN {
};
};
- imgsys: syscon@15000000 {
- compatible = "mediatek,mt8167-imgsys", "syscon";
- reg = <0 0x15000000 0 0x1000>;
- #clock-cells = <1>;
- };
-
- vdecsys: syscon@16000000 {
- compatible = "mediatek,mt8167-vdecsys", "syscon";
- reg = <0 0x16000000 0 0x1000>;
- #clock-cells = <1>;
- };
-
pio: pinctrl@1000b000 {
compatible = "mediatek,mt8167-pinctrl";
reg = <0 0x1000b000 0 0x1000>;
@@ -124,12 +106,36 @@ pio: pinctrl@1000b000 {
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
};
+ apmixedsys: apmixedsys@10018000 {
+ compatible = "mediatek,mt8167-apmixedsys", "syscon";
+ reg = <0 0x10018000 0 0x710>;
+ #clock-cells = <1>;
+ };
+
+ iommu: m4u@10203000 {
+ compatible = "mediatek,mt8167-m4u";
+ reg = <0 0x10203000 0 0x1000>;
+ mediatek,larbs = <&larb0>, <&larb1>, <&larb2>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_LOW>;
+ #iommu-cells = <1>;
+ };
+
mmsys: syscon@14000000 {
compatible = "mediatek,mt8167-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;
#clock-cells = <1>;
};
+ larb0: larb@14016000 {
+ compatible = "mediatek,mt8167-smi-larb";
+ reg = <0 0x14016000 0 0x1000>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&mmsys CLK_MM_SMI_LARB0>,
+ <&mmsys CLK_MM_SMI_LARB0>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+ };
+
smi_common: smi@14017000 {
compatible = "mediatek,mt8167-smi-common";
reg = <0 0x14017000 0 0x1000>;
@@ -139,14 +145,10 @@ smi_common: smi@14017000 {
power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
};
- larb0: larb@14016000 {
- compatible = "mediatek,mt8167-smi-larb";
- reg = <0 0x14016000 0 0x1000>;
- mediatek,smi = <&smi_common>;
- clocks = <&mmsys CLK_MM_SMI_LARB0>,
- <&mmsys CLK_MM_SMI_LARB0>;
- clock-names = "apb", "smi";
- power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+ imgsys: syscon@15000000 {
+ compatible = "mediatek,mt8167-imgsys", "syscon";
+ reg = <0 0x15000000 0 0x1000>;
+ #clock-cells = <1>;
};
larb1: larb@15001000 {
@@ -159,6 +161,12 @@ larb1: larb@15001000 {
power-domains = <&spm MT8167_POWER_DOMAIN_ISP>;
};
+ vdecsys: syscon@16000000 {
+ compatible = "mediatek,mt8167-vdecsys", "syscon";
+ reg = <0 0x16000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
larb2: larb@16010000 {
compatible = "mediatek,mt8167-smi-larb";
reg = <0 0x16010000 0 0x1000>;
@@ -168,13 +176,5 @@ larb2: larb@16010000 {
clock-names = "apb", "smi";
power-domains = <&spm MT8167_POWER_DOMAIN_VDEC>;
};
-
- iommu: m4u@10203000 {
- compatible = "mediatek,mt8167-m4u";
- reg = <0 0x10203000 0 0x1000>;
- mediatek,larbs = <&larb0>, <&larb1>, <&larb2>;
- interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_LOW>;
- #iommu-cells = <1>;
- };
};
};
--
2.43.0
--
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^ permalink raw reply related
* [PATCH v2 0/6] Add support for mt8167 display blocks
From: Luca Leonardo Scorcia @ 2026-02-16 16:22 UTC (permalink / raw)
To: linux-mediatek
Cc: Luca Leonardo Scorcia, Chun-Kuang Hu, Philipp Zabel, David Airlie,
Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chunfeng Yun, Vinod Koul, Neil Armstrong, Matthias Brugger,
AngeloGioacchino Del Regno, Jitao Shi, Fabien Parent, dri-devel,
devicetree, linux-kernel, linux-arm-kernel, linux-phy
This series adds support for the display blocks on MediaTek mt8167.
Tested on Xiaomi Mi Smart Clock x04g.
The first patch just does some reordering of dts nodes with no other changes
as this makes later patches cleaner and easier to follow.
v2:
- Separate patch for mediatek,dsi-phy binding;
- Separate patch for mt8167-dsi binding;
- Simplified OF graph endpoints in mt8167.dtsi.
Luca Leonardo Scorcia (5):
arm64: dts: mt8167: Reorder nodes according to mmio address
dt-bindings: display: mediatek: Add compatibles for MediaTek mt8167
dt-bindings: display: mediatek: Correct compatibility for mt8167-dsi
dt-bindings: phy: mediatek,dsi-phy: Add support for mt8167
arm64: dts: mediatek: mt8167: Add DRM nodes
Val Packett (1):
gpu: drm: mediatek: ovl: add specific entry for mt8167
.../display/mediatek/mediatek,aal.yaml | 1 +
.../display/mediatek/mediatek,ccorr.yaml | 4 +-
.../display/mediatek/mediatek,dither.yaml | 1 +
.../display/mediatek/mediatek,dsi.yaml | 5 +-
.../display/mediatek/mediatek,gamma.yaml | 1 +
.../display/mediatek/mediatek,ovl.yaml | 1 +
.../display/mediatek/mediatek,rdma.yaml | 1 +
.../display/mediatek/mediatek,wdma.yaml | 4 +-
.../bindings/phy/mediatek,dsi-phy.yaml | 1 +
arch/arm64/boot/dts/mediatek/mt8167.dtsi | 381 ++++++++++++++++--
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 12 +
11 files changed, 377 insertions(+), 35 deletions(-)
--
2.43.0
--
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^ permalink raw reply
* Re: [PATCH v2 2/3] phy: k1-usb: add disconnect function support
From: Yixun Lan @ 2026-02-16 15:29 UTC (permalink / raw)
To: Vladimir Oltean
Cc: Yixun Lan, Vinod Koul, Neil Armstrong, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Ze Huang, Junzhong Pan,
linux-phy, devicetree, linux-riscv, spacemit, linux-kernel
In-Reply-To: <20260216090112.n5jjpui3luqsybb5@skbuf>
On 11:01 Mon 16 Feb , Vladimir Oltean wrote:
> Hello Yixun,
>
> On Sat, Feb 14, 2026 at 08:29:15PM +0800, Yixun Lan wrote:
> > A disconnect status BIT of USB2 PHY need to be cleared, otherwise
> > it will fail to work properly during next connection when devices
> > connect to roothub directly.
> >
> > Fixes: fe4bc1a08638 ("phy: spacemit: support K1 USB2.0 PHY controller")
> > Signed-off-by: Yixun Lan <dlan@kernel.org>
> > ---
> > drivers/phy/spacemit/phy-k1-usb2.c | 14 ++++++++++++++
> > 1 file changed, 14 insertions(+)
> >
> > diff --git a/drivers/phy/spacemit/phy-k1-usb2.c b/drivers/phy/spacemit/phy-k1-usb2.c
> > index 342061380012..959bf79c7a72 100644
> > --- a/drivers/phy/spacemit/phy-k1-usb2.c
> > +++ b/drivers/phy/spacemit/phy-k1-usb2.c
> > @@ -48,6 +48,9 @@
> > #define PHY_CLK_HSTXP_EN BIT(3) /* clock hstxp enable */
> > #define PHY_HSTXP_MODE BIT(4) /* 0: force en_txp to be 1; 1: no force */
> >
> > +#define PHY_K1_HS_HOST_DISC 0x40
> > +#define PHY_K1_HS_HOST_DISC_CLR BIT(0)
> > +
> > #define PHY_PLL_DIV_CFG 0x98
> > #define PHY_FDIV_FRACT_8_15 GENMASK(7, 0)
> > #define PHY_FDIV_FRACT_16_19 GENMASK(11, 8)
> > @@ -142,9 +145,20 @@ static int spacemit_usb2phy_exit(struct phy *phy)
> > return 0;
> > }
> >
> > +static int spacemit_usb2phy_disconnect(struct phy *phy, int port)
> > +{
> > + struct spacemit_usb2phy *sphy = phy_get_drvdata(phy);
> > +
> > + regmap_update_bits(sphy->regmap_base, PHY_K1_HS_HOST_DISC,
> > + PHY_K1_HS_HOST_DISC_CLR, PHY_K1_HS_HOST_DISC_CLR);
>
> Please align function arguments to the open parenthesis.
>
Ok
> Since we are in the merge window, it is likely that new features will
> not be picked up at this stage.
>
Sure, no problem and I expect this is normal..
> But this seems to be a fix for existing SpacemiT K1 support, currently
> in the linux-phy/next branch. The linux-phy pull request hasn't been
> sent yet, so if you can resend just this patch and we can get an ACK for
> it in time, perhaps it can be included for v7.0.
>
Ok, done
http://lore.kernel.org/r/20260216152653.25244-1-dlan@kernel.org
> The K3 support should be resent after the merge window.
>
will do once new -rc1 is tagged
--
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^ permalink raw reply
* [PATCH v3] phy: k1-usb: add disconnect function support
From: Yixun Lan @ 2026-02-16 15:26 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Ze Huang
Cc: Yixun Lan, Vladimir Oltean, Junzhong Pan, spacemit, linux-phy,
linux-riscv, linux-kernel
A disconnect status BIT of USB2 PHY need to be cleared, otherwise
it will fail to work properly during next connection when devices
connect to roothub directly.
Fixes: fe4bc1a08638 ("phy: spacemit: support K1 USB2.0 PHY controller")
Signed-off-by: Yixun Lan <dlan@kernel.org>
---
To: Vinod Koul <vkoul@kernel.org>
To: Neil Armstrong <neil.armstrong@linaro.org>
To: Ze Huang <huang.ze@linux.dev>
Cc: Vladimir Oltean <olteanv@gmail.com>
Cc: Junzhong Pan <panjunzhong@linux.spacemit.com>
Cc: spacemit@lists.linux.dev
Cc: linux-phy@lists.infradead.org
Cc: linux-riscv@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Change in v3:
- split from v2 as bug fix
- fix alignment to open parenthesis
- http://lore.kernel.org/r/20260216090112.n5jjpui3luqsybb5@skbuf
- Link to v2: https://lore.kernel.org/r/20260214-11-k3-usb2-phy-v2-0-6ed31e031ab4@kernel.org
---
drivers/phy/spacemit/phy-k1-usb2.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/phy/spacemit/phy-k1-usb2.c b/drivers/phy/spacemit/phy-k1-usb2.c
index 342061380012..9215d0b223b2 100644
--- a/drivers/phy/spacemit/phy-k1-usb2.c
+++ b/drivers/phy/spacemit/phy-k1-usb2.c
@@ -48,6 +48,9 @@
#define PHY_CLK_HSTXP_EN BIT(3) /* clock hstxp enable */
#define PHY_HSTXP_MODE BIT(4) /* 0: force en_txp to be 1; 1: no force */
+#define PHY_K1_HS_HOST_DISC 0x40
+#define PHY_K1_HS_HOST_DISC_CLR BIT(0)
+
#define PHY_PLL_DIV_CFG 0x98
#define PHY_FDIV_FRACT_8_15 GENMASK(7, 0)
#define PHY_FDIV_FRACT_16_19 GENMASK(11, 8)
@@ -142,9 +145,20 @@ static int spacemit_usb2phy_exit(struct phy *phy)
return 0;
}
+static int spacemit_usb2phy_disconnect(struct phy *phy, int port)
+{
+ struct spacemit_usb2phy *sphy = phy_get_drvdata(phy);
+
+ regmap_update_bits(sphy->regmap_base, PHY_K1_HS_HOST_DISC,
+ PHY_K1_HS_HOST_DISC_CLR, PHY_K1_HS_HOST_DISC_CLR);
+
+ return 0;
+}
+
static const struct phy_ops spacemit_usb2phy_ops = {
.init = spacemit_usb2phy_init,
.exit = spacemit_usb2phy_exit,
+ .disconnect = spacemit_usb2phy_disconnect,
.owner = THIS_MODULE,
};
--
2.52.0
--
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^ permalink raw reply related
* Re: [PATCH v9 1/7] phy: can-transceiver: rename temporary helper function to avoid conflict
From: Andreas Kemnade @ 2026-02-16 15:24 UTC (permalink / raw)
To: Vladimir Oltean
Cc: Josua Mayer, Geert Uytterhoeven, Marc Kleine-Budde,
Vincent Mailhol, Vinod Koul, Neil Armstrong, Peter Rosin,
Aaro Koskinen, Kevin Hilman, Roger Quadros, Tony Lindgren,
Janusz Krzysztofik, Vignesh R, Andi Shyti, Ulf Hansson,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Magnus Damm, Wolfram Sang, Yazan Shhady,
Jon Nettleton, Mikhail Anikin, linux-can@vger.kernel.org,
linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-omap@vger.kernel.org, linux-i2c@vger.kernel.org,
linux-mmc@vger.kernel.org, devicetree@vger.kernel.org,
linux-renesas-soc@vger.kernel.org
In-Reply-To: <20260216092914.kmvl7aep7dantcsd@skbuf>
On Mon, 16 Feb 2026 11:29:14 +0200
Vladimir Oltean <olteanv@gmail.com> wrote:
> Hi Josua,
>
> On Mon, Feb 16, 2026 at 08:19:27AM +0000, Josua Mayer wrote:
> > >> In the future, when you have a series with cross-tree dependencies,
> > >> please try to think of it as individual mini-series for each tree's
> > >> 'next' branch, and specify clearly that you need stable tags (to be
> > >> pulled into other trees).
> >
> > I don't really understand how I could split my series up to avoid this
> > issue.
> >
> > Due to the fact that one (and now two) drivers implemented local
> > mux helpers, to undo that an atomic change must be made tree-wide.
> >
> > Meanwhile it must be avoided that while the mux core helpers are being
> > tested / reviewed, that any tree adds another driver-local mux helper
> > like appears to have happened here.
> >
> > Note that my patch-set did go to linux-phy@lists.infradead.org list, too.
> >
> > The second challenge for this series was that mux framework is being
> > enabled only by drivers Kconfig "select" - and not possible by menuconfig.
> > This is e.g. responsible for being unable to test =m build with arm64
> > defconfig - and lead to it only being detected through kernel robot
> > x86_64 allmodconfig.
>
> To avoid this, a combination of developer due diligence + maintainer due
> diligence is probably required.
>
> From linux-phy perspective, there will be some automated build testing
> (which did not exist at the time of your submission). This would have
> caught the 'hidden' devm_mux_state_get_optional() call present only in
> linux-phy/next, when testing patch 2/7.
>
> But, to work, the build automation needs to be able to apply the entire
> patch set on linux-phy/next. So expect some pushback if it doesn't
> (hence the recommendation to send a mini-series to linux-phy first, and
> request a stable tag).
>
I do not think that is at all the duty of the patch submitter. I think as
long as every dependencies and side effects are documented, it is IMHO up to the
maintainers to decide how it can be merged best. They know best whether there
is any danger of conflicts in their working tree because that is an area
where people are working on. Especially this patchset is around for months.
In MFD where it is
more common practice to have cross-subsystem patchsets, once acks from
everyone are there, MFD Maintainer creates an immutable branch with a tag.
The maintainers of the affected subsystems pull it in.
Regards,
Andreas
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^ permalink raw reply
* Re: [PATCH 4/5] PCI: qcom: Add link retention support
From: Manivannan Sadhasivam @ 2026-02-16 15:08 UTC (permalink / raw)
To: Krishna Chaitanya Chundru
Cc: Vinod Koul, Neil Armstrong, Philipp Zabel, Jingoo Han,
Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring,
Bjorn Helgaas, linux-arm-msm, linux-phy, linux-kernel, linux-pci
In-Reply-To: <20260109-link_retain-v1-4-7e6782230f4b@oss.qualcomm.com>
On Fri, Jan 09, 2026 at 12:51:09PM +0530, Krishna Chaitanya Chundru wrote:
> Some platforms keep the PCIe link active across bootloader and kernel
> handoff. Reinitializing the controller and toggling PERST# in such cases
> is unnecessary if driver doesn't want to do link training again.
>
> Introduce link_retain in both qcom_pcie_cfg and qcom_pcie to
> indicate when link retention is supported. During initialization, check
> the LTSSM state, if the link is already in L0 or L1 idle and LTSSM is
> enabled, set pp.link_retain and skip controller reset, PERST# toggling,
> and other post-init steps.
>
> If there is a devicetree property to restrict PCIe data rate and lane
> width go with the normal execution instead of link retantion logic.
>
Mention the properties here and also make it clear that the link will not be
retained if the values do not match bootloader programmed ones.
> Configure DBI and ATU base in this scenerio, since bootloader DBI & ATU
> base may differ from HLOS one. So use the DBI & ATU provided from the
> devicetree.
>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
> ---
> drivers/pci/controller/dwc/pcie-qcom.c | 50 ++++++++++++++++++++++++++++++++--
> 1 file changed, 47 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 9342f9c75f1c3017b55614069a7aa821a6fb8da7..bdd5bdb462c5f6814c8311be96411173456b6b14 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -259,12 +259,14 @@ struct qcom_pcie_ops {
> * @override_no_snoop: Override NO_SNOOP attribute in TLP to enable cache
> * snooping
> * @firmware_managed: Set if the Root Complex is firmware managed
> + * @link_retain: Set if controller supports link retain from bootloader
s/"link retain"/"retaining link"
> */
> struct qcom_pcie_cfg {
> const struct qcom_pcie_ops *ops;
> bool override_no_snoop;
> bool firmware_managed;
> bool no_l0s;
> + bool link_retain;
> };
>
> struct qcom_pcie_port {
> @@ -965,6 +967,35 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
> return 0;
> }
>
> +static bool qcom_pcie_check_link_retain(struct qcom_pcie *pcie)
> +{
> + u32 cap, speed, val, ltssm, width;
> + struct dw_pcie *pci = pcie->pci;
> + u8 offset;
> +
> + val = readl(pcie->parf + PARF_LTSSM);
> + ltssm = val & 0x1f;
> + if ((val & LTSSM_EN) &&
> + (ltssm == DW_PCIE_LTSSM_L0 || ltssm == DW_PCIE_LTSSM_L1_IDLE)) {
> + qcom_pcie_configure_dbi_atu_base(pcie);
> +
> + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
> + cap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
> + speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, cap);
> + width = dw_pcie_link_get_max_link_width(pci);
> +
> + if (pci->max_link_speed > 0 && speed < pci->max_link_speed)
> + return false;
> +
> + if (pci->num_lanes > 0 && width > pci->num_lanes)
> + return false;
IIUC, these checks are in place to override the link retention if the users want
to change the lane/width count than what was already programmed by the
bootloader.
If so, please add comment on top of this helper to make it explicit.
> +
> + return true;
> + }
> +
> + return false;
> +}
> +
> static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
> {
> struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
> @@ -983,6 +1014,14 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
> if (ret < 0)
> goto err_disable_regulators;
>
> + if (pcie->cfg->link_retain) {
> + pci->pp.link_retain = qcom_pcie_check_link_retain(pcie);
> + if (pci->pp.link_retain) {
> + dev_info(dev, "Enabling link retain\n");
"Retaining PCIe link"
- Mani
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* Re: [PATCH 3/3] phy: qcom: qmp-usbc: Simplify check for non-NULL pointer
From: Abel Vesa @ 2026-02-16 14:58 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Sven Peter, Janne Grunau, Neal Gompa, Vinod Koul, Neil Armstrong,
Philipp Zabel, asahi, linux-arm-kernel, linux-phy, linux-kernel,
linux-arm-msm
In-Reply-To: <20260216110413.159994-6-krzysztof.kozlowski@oss.qualcomm.com>
On 26-02-16 12:04:16, Krzysztof Kozlowski wrote:
> Pointers should not use explicit '0' comparison, so just use standard
> evaluation as non-NULL:
>
> phy-qcom-qmp-usbc.c:1682:31: warning: Using plain integer as NULL pointer
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
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* Re: [PATCH 3/5] PCI: qcom: Keep PERST# GPIO state as-is during probe
From: Manivannan Sadhasivam @ 2026-02-16 14:58 UTC (permalink / raw)
To: Krishna Chaitanya Chundru
Cc: Vinod Koul, Neil Armstrong, Philipp Zabel, Jingoo Han,
Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring,
Bjorn Helgaas, linux-arm-msm, linux-phy, linux-kernel, linux-pci
In-Reply-To: <20260109-link_retain-v1-3-7e6782230f4b@oss.qualcomm.com>
On Fri, Jan 09, 2026 at 12:51:08PM +0530, Krishna Chaitanya Chundru wrote:
> The PERST# signal is used to reset PCIe devices. Currently, the driver
> requests the GPIO with GPIOD_OUT_HIGH, which forces the line high
> during probe. This can unintentionally assert reset early, breaking
> link retention or causing unexpected device behavior.
>
There is no way asserting PERST# is going to cause 'unexpected device behavior'.
> Change the request to use GPIOD_ASIS so the driver preserves the
> existing state configured by the bootloader or firmware. This allows
> platforms that manage PERST# externally to maintain proper reset
> sequencing.
>
You should also mention the fact that the driver asserts PERST# during the start
of qcom_pcie_host_init(). So requesting PERST# with GPIOD_OUT_HIGH is redundant
anyway.
- Mani
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
> ---
> drivers/pci/controller/dwc/pcie-qcom.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index 7b92e7a1c0d9364a9cefe1450818f9cbfc7fd3ac..9342f9c75f1c3017b55614069a7aa821a6fb8da7 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -1711,7 +1711,7 @@ static int qcom_pcie_parse_port(struct qcom_pcie *pcie, struct device_node *node
> int ret;
>
> reset = devm_fwnode_gpiod_get(dev, of_fwnode_handle(node),
> - "reset", GPIOD_OUT_HIGH, "PERST#");
> + "reset", GPIOD_ASIS, "PERST#");
> if (IS_ERR(reset))
> return PTR_ERR(reset);
>
> @@ -1772,7 +1772,7 @@ static int qcom_pcie_parse_legacy_binding(struct qcom_pcie *pcie)
> if (IS_ERR(phy))
> return PTR_ERR(phy);
>
> - reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH);
> + reset = devm_gpiod_get_optional(dev, "perst", GPIOD_ASIS);
> if (IS_ERR(reset))
> return PTR_ERR(reset);
>
>
> --
> 2.34.1
>
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* Re: [PATCH 1/5] phy: qcom: qmp-pcie: Skip PHY reset if already up
From: Konrad Dybcio @ 2026-02-16 14:56 UTC (permalink / raw)
To: Manivannan Sadhasivam, Dmitry Baryshkov
Cc: Neil Armstrong, Krishna Chaitanya Chundru, Vinod Koul,
Philipp Zabel, Jingoo Han, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas,
linux-arm-msm, linux-phy, linux-kernel, linux-pci
In-Reply-To: <aaqqdz2ssnetfgtybuerjfnkgr7r22xj2whaawaqhgm4y2ygom@jtkn5z2nw7aq>
On 2/16/26 3:53 PM, Manivannan Sadhasivam wrote:
> On Fri, Jan 09, 2026 at 04:03:37PM +0200, Dmitry Baryshkov wrote:
>> On Fri, Jan 09, 2026 at 02:10:49PM +0100, Neil Armstrong wrote:
>>> On 1/9/26 14:08, Dmitry Baryshkov wrote:
>>>> On Fri, Jan 09, 2026 at 12:51:06PM +0530, Krishna Chaitanya Chundru wrote:
>>>>> If the bootloader has already powered up the PCIe PHY, doing a full
>>>>> reset and waiting for it to come up again slows down boot time.
>>>>
>>>> How big is the delay caused by it?
>>>>
>>>>>
>>>>> Add a check for PHY status and skip the reset steps when the PHY is
>>>>> already active. In this case, only enable the required resources during
>>>>> power-on. This works alongside the existing logic that skips the init
>>>>> sequence.
>>>>
>>>> Can we end up in a state where the bootloader has mis-setup the link? Or
>>>> the link going bad because of any glitch during the bootup?
>>>
>>> Good question, can we add a module parameter to force a full reset of the PHY in case
>>> the bootloader is buggy ?
>>
>> I'd suggest a simpler thing: if the reset was skipped, reset the PHY in
>> case of an error and retry. That's also one of the reasons why I asked
>> for skip_reset not to be the persistent value.
>>
>
> I'm not sure what value would resetting the PHY provide in the case of failure.
> As per this patch, skip_reset is only going to be set for platforms where
> bootloader has already configured the PHY. So in the case of PHY link failure,
> simply resetting the PHY won't help IMO as the PHY register contents are going
> to be presistent due to nocsr_reset.
We can pull the not-nocsr_reset though?
Konrad
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* Re: [PATCH 1/5] phy: qcom: qmp-pcie: Skip PHY reset if already up
From: Manivannan Sadhasivam @ 2026-02-16 14:53 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Neil Armstrong, Krishna Chaitanya Chundru, Vinod Koul,
Philipp Zabel, Jingoo Han, Lorenzo Pieralisi,
Krzysztof Wilczyński, Rob Herring, Bjorn Helgaas,
linux-arm-msm, linux-phy, linux-kernel, linux-pci
In-Reply-To: <cvxvq7f2ku6aq5gbbqav42ckqk2raesbxq2bx46mxvapcza5v4@5zuyjdtn5us2>
On Fri, Jan 09, 2026 at 04:03:37PM +0200, Dmitry Baryshkov wrote:
> On Fri, Jan 09, 2026 at 02:10:49PM +0100, Neil Armstrong wrote:
> > On 1/9/26 14:08, Dmitry Baryshkov wrote:
> > > On Fri, Jan 09, 2026 at 12:51:06PM +0530, Krishna Chaitanya Chundru wrote:
> > > > If the bootloader has already powered up the PCIe PHY, doing a full
> > > > reset and waiting for it to come up again slows down boot time.
> > >
> > > How big is the delay caused by it?
> > >
> > > >
> > > > Add a check for PHY status and skip the reset steps when the PHY is
> > > > already active. In this case, only enable the required resources during
> > > > power-on. This works alongside the existing logic that skips the init
> > > > sequence.
> > >
> > > Can we end up in a state where the bootloader has mis-setup the link? Or
> > > the link going bad because of any glitch during the bootup?
> >
> > Good question, can we add a module parameter to force a full reset of the PHY in case
> > the bootloader is buggy ?
>
> I'd suggest a simpler thing: if the reset was skipped, reset the PHY in
> case of an error and retry. That's also one of the reasons why I asked
> for skip_reset not to be the persistent value.
>
I'm not sure what value would resetting the PHY provide in the case of failure.
As per this patch, skip_reset is only going to be set for platforms where
bootloader has already configured the PHY. So in the case of PHY link failure,
simply resetting the PHY won't help IMO as the PHY register contents are going
to be presistent due to nocsr_reset.
- Mani
> >
> > >
> > > >
> > > > Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
> > > > ---
> > > > drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 28 ++++++++++++++++++----------
> > > > 1 file changed, 18 insertions(+), 10 deletions(-)
> > > >
> > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> > > > index 86b1b7e2da86a8675e3e48e90b782afb21cafd77..c93e613cf80b2612f0f225fa2125f78dbec1a33f 100644
> > > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> > > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> > > > @@ -3153,6 +3153,7 @@ struct qmp_pcie {
> > > > const struct qmp_phy_cfg *cfg;
> > > > bool tcsr_4ln_config;
> > > > bool skip_init;
> > > > + bool skip_reset;
> > > > void __iomem *serdes;
> > > > void __iomem *pcs;
> > > > @@ -4537,6 +4538,9 @@ static int qmp_pcie_init(struct phy *phy)
> > > > qphy_checkbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START) &&
> > > > qphy_checkbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], cfg->pwrdn_ctrl);
> > > > + qmp->skip_reset = qmp->skip_init && !qphy_checkbits(pcs, cfg->regs[QPHY_PCS_STATUS],
> > >
> > > It is definitely not a long-term state, there is no need to store it in
> > > qmp_pcie struct.
> > >
> > > > + cfg->phy_status);
> > > > +
> > > > if (!qmp->skip_init && !cfg->tbls.serdes_num) {
> > > > dev_err(qmp->dev, "Init sequence not available\n");
> > > > return -ENODATA;
> > > > @@ -4560,13 +4564,15 @@ static int qmp_pcie_init(struct phy *phy)
> > > > }
> > > > }
> > > > - ret = reset_control_assert(qmp->nocsr_reset);
> > > > - if (ret) {
> > > > - dev_err(qmp->dev, "no-csr reset assert failed\n");
> > > > - goto err_assert_reset;
> > > > - }
> > > > + if (!qmp->skip_reset) {
> > > > + ret = reset_control_assert(qmp->nocsr_reset);
> > > > + if (ret) {
> > > > + dev_err(qmp->dev, "no-csr reset assert failed\n");
> > > > + goto err_assert_reset;
> > > > + }
> > > > - usleep_range(200, 300);
> > > > + usleep_range(200, 300);
> > > > + }
> > > > if (!qmp->skip_init) {
> > > > ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets);
> > > > @@ -4641,10 +4647,12 @@ static int qmp_pcie_power_on(struct phy *phy)
> > > > if (ret)
> > > > return ret;
> > > > - ret = reset_control_deassert(qmp->nocsr_reset);
> > > > - if (ret) {
> > > > - dev_err(qmp->dev, "no-csr reset deassert failed\n");
> > > > - goto err_disable_pipe_clk;
> > > > + if (!qmp->skip_reset) {
> > > > + ret = reset_control_deassert(qmp->nocsr_reset);
> > > > + if (ret) {
> > > > + dev_err(qmp->dev, "no-csr reset deassert failed\n");
> > > > + goto err_disable_pipe_clk;
> > > > + }
> > > > }
> > > > if (qmp->skip_init)
> > > >
> > > > --
> > > > 2.34.1
> > > >
> > >
> >
>
> --
> With best wishes
> Dmitry
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* [PATCH v7 23/23] scsi: ufs: mediatek: Add MT8196 compatible, update copyright
From: Nicolas Frattaroli @ 2026-02-16 13:37 UTC (permalink / raw)
To: Alim Akhtar, Avri Altman, Bart Van Assche, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chunfeng Yun, Vinod Koul,
Kishon Vijay Abraham I, Peter Wang, Stanley Jhu,
James E.J. Bottomley, Martin K. Petersen, Philipp Zabel,
Liam Girdwood, Mark Brown, Chaotian Jing, Neil Armstrong
Cc: Louis-Alexis Eyraud, kernel, linux-scsi, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-phy, Nicolas Frattaroli
In-Reply-To: <20260216-mt8196-ufs-v7-0-b5f2907c6da7@collabora.com>
THe MT8196's UFS controller has a new compatible. Add the necessary
struct definitions to support it.
Also update the copyrights and authors, without tabs following spaces to
avoid checkpatch errors, to list myself as having contributed to this
driver after the preceding rework patches.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
drivers/ufs/host/ufs-mediatek.c | 17 +++++++++++++++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index dfa104207cc6..122bc741294d 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -1,9 +1,11 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 MediaTek Inc.
+ * Copyright (C) 2025 Collabora Ltd.
* Authors:
- * Stanley Chu <stanley.chu@mediatek.com>
- * Peter Wang <peter.wang@mediatek.com>
+ * Stanley Chu <stanley.chu@mediatek.com>
+ * Peter Wang <peter.wang@mediatek.com>
+ * Nicolas Frattaroli <nicolas.frattaroli@collabora.com> (Major cleanups)
*/
#include <linux/arm-smccc.h>
@@ -2200,6 +2202,10 @@ static const char *const ufs_mtk_regs_avdd12_ckbuf_avdd18[] = {
"avdd12", "avdd12-ckbuf", "avdd18"
};
+static const char *const ufs_mtk_regs_avdd12_ckbuf[] = {
+ "avdd12", "avdd12-ckbuf"
+};
+
static const struct ufs_mtk_soc_data mt8183_data = {
.has_avdd09 = true,
.reg_names = ufs_mtk_regs_avdd12_avdd18,
@@ -2212,10 +2218,17 @@ static const struct ufs_mtk_soc_data mt8192_8195_data = {
.num_reg_names = ARRAY_SIZE(ufs_mtk_regs_avdd12_ckbuf_avdd18),
};
+static const struct ufs_mtk_soc_data mt8196_data = {
+ .has_avdd09 = true,
+ .reg_names = ufs_mtk_regs_avdd12_ckbuf,
+ .num_reg_names = ARRAY_SIZE(ufs_mtk_regs_avdd12_ckbuf),
+};
+
static const struct of_device_id ufs_mtk_of_match[] = {
{ .compatible = "mediatek,mt8183-ufshci", .data = &mt8183_data },
{ .compatible = "mediatek,mt8192-ufshci", .data = &mt8192_8195_data },
{ .compatible = "mediatek,mt8195-ufshci", .data = &mt8192_8195_data },
+ { .compatible = "mediatek,mt8196-ufshci", .data = &mt8196_data },
{},
};
MODULE_DEVICE_TABLE(of, ufs_mtk_of_match);
--
2.53.0
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* [PATCH v7 22/23] scsi: ufs: mediatek: Remove undocumented "clk-scale-up-vcore-min"
From: Nicolas Frattaroli @ 2026-02-16 13:37 UTC (permalink / raw)
To: Alim Akhtar, Avri Altman, Bart Van Assche, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chunfeng Yun, Vinod Koul,
Kishon Vijay Abraham I, Peter Wang, Stanley Jhu,
James E.J. Bottomley, Martin K. Petersen, Philipp Zabel,
Liam Girdwood, Mark Brown, Chaotian Jing, Neil Armstrong
Cc: Louis-Alexis Eyraud, kernel, linux-scsi, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-phy, Nicolas Frattaroli
In-Reply-To: <20260216-mt8196-ufs-v7-0-b5f2907c6da7@collabora.com>
The MediaTek UFS driver contains support for an undocumented,
non-vendor-prefixed u32 property named "clk-scale-up-vcore-min".
Since it is not part of any binding, and would not pass a bindings
review in its current form, remove it.
To return this functionality, it needs to be resubmitted in a series
that also introduces it to the binding, and justifies what it is used
for. Compatibility with downstream device trees is not a valid
justification for its existence.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
drivers/ufs/host/ufs-mediatek.c | 19 -------------------
1 file changed, 19 deletions(-)
diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index e863e4f8af55..dfa104207cc6 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -880,8 +880,6 @@ static void ufs_mtk_init_clocks(struct ufs_hba *hba)
struct ufs_mtk_host *host = ufshcd_get_variant(hba);
struct list_head *head = &hba->clk_list_head;
struct ufs_clk_info *clki, *clki_tmp;
- struct device *dev = hba->dev;
- u32 volt;
/*
* Find private clocks and store them in struct ufs_mtk_clk.
@@ -918,24 +916,7 @@ static void ufs_mtk_init_clocks(struct ufs_hba *hba)
if (!ufs_mtk_is_clk_scale_ready(hba)) {
hba->caps &= ~UFSHCD_CAP_CLK_SCALING;
dev_info(hba->dev, "%s: Clock scaling unavailable", __func__);
- return;
- }
-
- if (!host->reg_vcore)
- return;
-
- if (of_property_read_u32(dev->of_node, "clk-scale-up-vcore-min",
- &volt)) {
- dev_info(dev, "failed to get clk-scale-up-vcore-min");
- return;
}
-
- host->mclk.vcore_volt = volt;
-
- /* If default boot is max gear, request vcore */
- if (volt && host->clk_scale_up)
- if (regulator_set_voltage(host->reg_vcore, volt, INT_MAX))
- dev_err(hba->dev, "Failed to set vcore to %d\n", volt);
}
static void ufs_mtk_setup_clk_gating(struct ufs_hba *hba)
--
2.53.0
--
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* [PATCH v7 21/23] scsi: ufs: mediatek: Remove ret local from link_startup_notify
From: Nicolas Frattaroli @ 2026-02-16 13:37 UTC (permalink / raw)
To: Alim Akhtar, Avri Altman, Bart Van Assche, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chunfeng Yun, Vinod Koul,
Kishon Vijay Abraham I, Peter Wang, Stanley Jhu,
James E.J. Bottomley, Martin K. Petersen, Philipp Zabel,
Liam Girdwood, Mark Brown, Chaotian Jing, Neil Armstrong
Cc: Louis-Alexis Eyraud, kernel, linux-scsi, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-phy, Nicolas Frattaroli
In-Reply-To: <20260216-mt8196-ufs-v7-0-b5f2907c6da7@collabora.com>
Remove the "ret" local variable from ufs_mtk_link_startup_notify, as
it's pointless; in all cases it is assigned, it is returned right after
without being read first.
Rework the code to just return directly, and get rid of the default
branch while at it.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
drivers/ufs/host/ufs-mediatek.c | 12 +++---------
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index 046e2f9bb6c7..e863e4f8af55 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -1500,21 +1500,15 @@ static void ufs_mtk_post_link(struct ufs_hba *hba)
static int ufs_mtk_link_startup_notify(struct ufs_hba *hba,
enum ufs_notify_change_status stage)
{
- int ret = 0;
-
switch (stage) {
case PRE_CHANGE:
- ret = ufs_mtk_pre_link(hba);
- break;
+ return ufs_mtk_pre_link(hba);
case POST_CHANGE:
ufs_mtk_post_link(hba);
- break;
- default:
- ret = -EINVAL;
- break;
+ return 0;
}
- return ret;
+ return -EINVAL;
}
static int ufs_mtk_device_reset(struct ufs_hba *hba)
--
2.53.0
--
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^ permalink raw reply related
* [PATCH v7 19/23] scsi: ufs: mediatek: Rework hardware version reading
From: Nicolas Frattaroli @ 2026-02-16 13:37 UTC (permalink / raw)
To: Alim Akhtar, Avri Altman, Bart Van Assche, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chunfeng Yun, Vinod Koul,
Kishon Vijay Abraham I, Peter Wang, Stanley Jhu,
James E.J. Bottomley, Martin K. Petersen, Philipp Zabel,
Liam Girdwood, Mark Brown, Chaotian Jing, Neil Armstrong
Cc: Louis-Alexis Eyraud, kernel, linux-scsi, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-phy, Nicolas Frattaroli
In-Reply-To: <20260216-mt8196-ufs-v7-0-b5f2907c6da7@collabora.com>
Split assignment to the host struct out from the read function, and
utilise bitfield helpers to simplify the code. Also move the debug print
out of the legacy version helper, which means it no longer has to take a
struct ufs_hba as an input, and can be rewritten as a pure function.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
drivers/ufs/host/ufs-mediatek.c | 65 +++++++++++++++++++++--------------------
1 file changed, 33 insertions(+), 32 deletions(-)
diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index e39412d59847..ee677af6c700 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -797,50 +797,47 @@ static void ufs_mtk_mcq_set_irq_affinity(struct ufs_hba *hba, unsigned int cpu)
dev_dbg(hba->dev, "set irq %d affinity to CPU %d\n", irq, _cpu);
}
-static bool ufs_mtk_is_legacy_chipset(struct ufs_hba *hba, u32 hw_ip_ver)
+static bool __pure ufs_mtk_is_legacy_chipset(u32 hw_ip_ver)
{
- bool is_legacy = false;
-
switch (hw_ip_ver) {
case IP_LEGACY_VER_MT6893:
case IP_LEGACY_VER_MT6781:
/* can add other legacy chipset ID here accordingly */
- is_legacy = true;
- break;
- default:
- break;
+ return true;
}
- dev_dbg(hba->dev, "IP version 0x%x, legacy = %s", hw_ip_ver,
- str_true_false(is_legacy));
- return is_legacy;
+ return false;
}
-/*
- * HW version format has been changed from 01MMmmmm to 1MMMmmmm, since
- * project MT6878. In order to perform correct version comparison,
- * version number is changed by SW for the following projects.
- * IP_VER_MT6983 0x00360000 to 0x10360000
- * IP_VER_MT6897 0x01440000 to 0x10440000
- * IP_VER_MT6989 0x01450000 to 0x10450000
- * IP_VER_MT6991 0x01460000 to 0x10460000
+#define MTK_UFS_VER_PREFIX_M (0xFF << 24)
+
+/**
+ * ufs_mtk_get_hw_ip_version - read and return adjusted hardware version
+ * @hba: pointer to this device's &struct ufs_hba
+ *
+ * Reads, transforms and returns the hardware version.
+ *
+ * Since MT6878, the versioning scheme was changed from 01MMmmmm to 1MMMmmmm.
+ * In order to support version comparisons across these different versioning
+ * schemes, this function transforms the older style to the newer one.
+ *
+ * For example:
+ * MT6983 is transformed from 0x00360000 to 0x10360000
+ * MT6897 is transformed from 0x01440000 to 0x10440000
+ * MT6989 is transformed from 0x01450000 to 0x10450000
+ * MT6991 is transformed from 0x01460000 to 0x10460000
+ *
+ * Returns a u32 representing the hardware version.
*/
-static void ufs_mtk_get_hw_ip_version(struct ufs_hba *hba)
+static u32 ufs_mtk_get_hw_ip_version(struct ufs_hba *hba)
{
- struct ufs_mtk_host *host = ufshcd_get_variant(hba);
- u32 hw_ip_ver;
+ u32 version = ufshcd_readl(hba, REG_UFS_MTK_IP_VER);
+ u32 prefix = FIELD_GET(MTK_UFS_VER_PREFIX_M, version);
- hw_ip_ver = ufshcd_readl(hba, REG_UFS_MTK_IP_VER);
+ if (prefix <= 1)
+ FIELD_MODIFY(MTK_UFS_VER_PREFIX_M, &version, BIT(28));
- if (((hw_ip_ver & (0xFF << 24)) == (0x1 << 24)) ||
- ((hw_ip_ver & (0xFF << 24)) == 0)) {
- hw_ip_ver &= ~(0xFF << 24);
- hw_ip_ver |= (0x1 << 28);
- }
-
- host->ip_ver = hw_ip_ver;
-
- host->legacy_ip_ver = ufs_mtk_is_legacy_chipset(hba, hw_ip_ver);
+ return version;
}
static void ufs_mtk_get_controller_version(struct ufs_hba *hba)
@@ -1191,7 +1188,11 @@ static int ufs_mtk_init(struct ufs_hba *hba)
ufs_mtk_setup_clocks(hba, true, POST_CHANGE);
- ufs_mtk_get_hw_ip_version(hba);
+ host->ip_ver = ufs_mtk_get_hw_ip_version(hba);
+ host->legacy_ip_ver = ufs_mtk_is_legacy_chipset(host->ip_ver);
+
+ dev_dbg(hba->dev, "IP version 0x%x, legacy = %s", host->ip_ver,
+ str_true_false(host->legacy_ip_ver));
return 0;
--
2.53.0
--
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^ permalink raw reply related
* [PATCH v7 20/23] scsi: ufs: mediatek: Back up idle timer in per-instance struct
From: Nicolas Frattaroli @ 2026-02-16 13:37 UTC (permalink / raw)
To: Alim Akhtar, Avri Altman, Bart Van Assche, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chunfeng Yun, Vinod Koul,
Kishon Vijay Abraham I, Peter Wang, Stanley Jhu,
James E.J. Bottomley, Martin K. Petersen, Philipp Zabel,
Liam Girdwood, Mark Brown, Chaotian Jing, Neil Armstrong
Cc: Louis-Alexis Eyraud, kernel, linux-scsi, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-phy, Nicolas Frattaroli
In-Reply-To: <20260216-mt8196-ufs-v7-0-b5f2907c6da7@collabora.com>
The MediaTek UFS driver uses a function-scope static variable to back up
a hardware register across a power change in the
ufs_mtk_pwr_change_notify function. This is dangerous, as it's only
correct if only ever one instance of the driver is loaded, which isn't
true if there's more than one device on a SoC that needs it, or it
otherwise gets loaded a second time.
Back it up into a member of the host struct instead, as this struct is
per-instance. Rework the function to not use a pointless "ret" local as
well.
Fixes: f5ca8d0c7a63 ("scsi: ufs: host: mediatek: Disable auto-hibern8 during power mode changes")
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
drivers/ufs/host/ufs-mediatek.c | 20 ++++++++------------
drivers/ufs/host/ufs-mediatek.h | 1 +
2 files changed, 9 insertions(+), 12 deletions(-)
diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index ee677af6c700..046e2f9bb6c7 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -1398,28 +1398,24 @@ static int ufs_mtk_pwr_change_notify(struct ufs_hba *hba,
const struct ufs_pa_layer_attr *dev_max_params,
struct ufs_pa_layer_attr *dev_req_params)
{
- int ret = 0;
- static u32 reg;
+ struct ufs_mtk_host *host = ufshcd_get_variant(hba);
switch (stage) {
case PRE_CHANGE:
if (ufshcd_is_auto_hibern8_supported(hba)) {
- reg = ufshcd_readl(hba, REG_AUTO_HIBERNATE_IDLE_TIMER);
+ host->hibernate_idle_timer = ufshcd_readl(
+ hba, REG_AUTO_HIBERNATE_IDLE_TIMER);
ufs_mtk_auto_hibern8_disable(hba);
}
- ret = ufs_mtk_pre_pwr_change(hba, dev_max_params,
- dev_req_params);
- break;
+ return ufs_mtk_pre_pwr_change(hba, dev_max_params, dev_req_params);
case POST_CHANGE:
if (ufshcd_is_auto_hibern8_supported(hba))
- ufshcd_writel(hba, reg, REG_AUTO_HIBERNATE_IDLE_TIMER);
- break;
- default:
- ret = -EINVAL;
- break;
+ ufshcd_writel(hba, host->hibernate_idle_timer,
+ REG_AUTO_HIBERNATE_IDLE_TIMER);
+ return 0;
}
- return ret;
+ return -EINVAL;
}
static int ufs_mtk_unipro_set_lpm(struct ufs_hba *hba, bool lpm)
diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediatek.h
index fa27ab4d6d6c..e5a3f70e7024 100644
--- a/drivers/ufs/host/ufs-mediatek.h
+++ b/drivers/ufs/host/ufs-mediatek.h
@@ -187,6 +187,7 @@ struct ufs_mtk_host {
u16 ref_clk_gating_wait_us;
u32 ip_ver;
bool legacy_ip_ver;
+ u32 hibernate_idle_timer;
bool mcq_set_intr;
bool is_mcq_intr_enabled;
--
2.53.0
--
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* [PATCH v7 18/23] scsi: ufs: mediatek: Don't acquire dvfsrc-vcore twice
From: Nicolas Frattaroli @ 2026-02-16 13:37 UTC (permalink / raw)
To: Alim Akhtar, Avri Altman, Bart Van Assche, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chunfeng Yun, Vinod Koul,
Kishon Vijay Abraham I, Peter Wang, Stanley Jhu,
James E.J. Bottomley, Martin K. Petersen, Philipp Zabel,
Liam Girdwood, Mark Brown, Chaotian Jing, Neil Armstrong
Cc: Louis-Alexis Eyraud, kernel, linux-scsi, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-phy, Nicolas Frattaroli
In-Reply-To: <20260216-mt8196-ufs-v7-0-b5f2907c6da7@collabora.com>
As part of its featureset, the ufs-mediatek driver needs to play with an
optional dvfsrc-vcore regulator for some of them.
However, it currently does this by acquiring two different references to
it in two different places, needlessly duplicating logic.
Move reg_vcore to the host struct, acquire it in the same function as
avdd09 is acquired, and rework the users of reg_vcore.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
drivers/ufs/host/ufs-mediatek.c | 73 +++++++++++++++++++----------------------
drivers/ufs/host/ufs-mediatek.h | 3 +-
2 files changed, 34 insertions(+), 42 deletions(-)
diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index b5c75d228c85..e39412d59847 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -519,15 +519,13 @@ static void ufs_mtk_boost_crypt(struct ufs_hba *hba, bool boost)
{
struct ufs_mtk_host *host = ufshcd_get_variant(hba);
struct ufs_mtk_crypt_cfg *cfg;
- struct regulator *reg;
int volt, ret;
- if (!ufs_mtk_is_boost_crypt_enabled(hba))
+ if (!ufs_mtk_is_boost_crypt_enabled(hba) || !host->reg_vcore)
return;
cfg = host->crypt;
volt = cfg->vcore_volt;
- reg = cfg->reg_vcore;
ret = clk_prepare_enable(cfg->clk_crypt_mux);
if (ret) {
@@ -537,7 +535,7 @@ static void ufs_mtk_boost_crypt(struct ufs_hba *hba, bool boost)
}
if (boost) {
- ret = regulator_set_voltage(reg, volt, INT_MAX);
+ ret = regulator_set_voltage(host->reg_vcore, volt, INT_MAX);
if (ret) {
dev_err(hba->dev, "%s: Failed to set vcore to %d: %pe\n",
__func__, volt, ERR_PTR(ret));
@@ -548,7 +546,7 @@ static void ufs_mtk_boost_crypt(struct ufs_hba *hba, bool boost)
if (ret) {
dev_err(hba->dev, "%s: Failed to reparent clk_crypt_perf: %pe\n",
__func__, ERR_PTR(ret));
- regulator_set_voltage(reg, 0, INT_MAX);
+ regulator_set_voltage(host->reg_vcore, 0, INT_MAX);
goto out;
}
} else {
@@ -559,7 +557,7 @@ static void ufs_mtk_boost_crypt(struct ufs_hba *hba, bool boost)
goto out;
}
- ret = regulator_set_voltage(reg, 0, INT_MAX);
+ ret = regulator_set_voltage(host->reg_vcore, 0, INT_MAX);
if (ret) {
dev_err(hba->dev, "%s: Failed to set vcore to minimum: %pe\n",
__func__, ERR_PTR(ret));
@@ -576,15 +574,12 @@ static void ufs_mtk_init_boost_crypt(struct ufs_hba *hba)
struct device *dev = hba->dev;
int ret;
- cfg = devm_kzalloc(dev, sizeof(*cfg), GFP_KERNEL);
- if (!cfg)
+ if (!host->reg_vcore)
return;
- cfg->reg_vcore = devm_regulator_get_optional(dev, "dvfsrc-vcore");
- if (IS_ERR(cfg->reg_vcore)) {
- dev_err(dev, "Failed to get dvfsrc-vcore: %pe", cfg->reg_vcore);
+ cfg = devm_kzalloc(dev, sizeof(*cfg), GFP_KERNEL);
+ if (!cfg)
return;
- }
ret = of_property_read_u32(dev->of_node, "mediatek,boost-crypt-vcore-min",
&cfg->vcore_volt);
@@ -889,7 +884,6 @@ static void ufs_mtk_init_clocks(struct ufs_hba *hba)
struct list_head *head = &hba->clk_list_head;
struct ufs_clk_info *clki, *clki_tmp;
struct device *dev = hba->dev;
- struct regulator *reg;
u32 volt;
/*
@@ -930,16 +924,8 @@ static void ufs_mtk_init_clocks(struct ufs_hba *hba)
return;
}
- /*
- * Default get vcore if dts have these settings.
- * No matter clock scaling support or not. (may disable by customer)
- */
- reg = devm_regulator_get_optional(dev, "dvfsrc-vcore");
- if (IS_ERR(reg)) {
- if (PTR_ERR(reg) != -ENODEV)
- dev_err(dev, "Failed to get dvfsrc-vcore: %pe\n", reg);
+ if (!host->reg_vcore)
return;
- }
if (of_property_read_u32(dev->of_node, "clk-scale-up-vcore-min",
&volt)) {
@@ -947,12 +933,11 @@ static void ufs_mtk_init_clocks(struct ufs_hba *hba)
return;
}
- host->mclk.reg_vcore = reg;
host->mclk.vcore_volt = volt;
/* If default boot is max gear, request vcore */
- if (reg && volt && host->clk_scale_up)
- if (regulator_set_voltage(reg, volt, INT_MAX))
+ if (volt && host->clk_scale_up)
+ if (regulator_set_voltage(host->reg_vcore, volt, INT_MAX))
dev_err(hba->dev, "Failed to set vcore to %d\n", volt);
}
@@ -1064,6 +1049,17 @@ static int ufs_mtk_get_supplies(struct ufs_mtk_host *host)
const struct ufs_mtk_soc_data *data = of_device_get_match_data(dev);
int ret;
+ host->reg_vcore = devm_regulator_get_optional(dev, "dvfsrc-vcore");
+ if (IS_ERR(host->reg_vcore)) {
+ if (PTR_ERR(host->reg_vcore) != -ENODEV) {
+ dev_err(dev, "Failed to get dvfsrc-vcore supply: %pe\n",
+ host->reg_vcore);
+ return PTR_ERR(host->reg_vcore);
+ }
+
+ host->reg_vcore = NULL;
+ }
+
if (!data)
return 0;
@@ -1081,14 +1077,13 @@ static int ufs_mtk_get_supplies(struct ufs_mtk_host *host)
host->reg_avdd09 = devm_regulator_get_optional(dev, "avdd09");
if (IS_ERR(host->reg_avdd09)) {
- if (PTR_ERR(host->reg_avdd09) == -ENODEV) {
- host->reg_avdd09 = NULL;
- return 0;
+ if (PTR_ERR(host->reg_avdd09) != -ENODEV) {
+ dev_err(dev, "Failed to get avdd09 regulator: %pe\n",
+ host->reg_avdd09);
+ return PTR_ERR(host->reg_avdd09);
}
- dev_err(dev, "Failed to get avdd09 regulator: %pe\n",
- host->reg_avdd09);
- return PTR_ERR(host->reg_avdd09);
+ host->reg_avdd09 = NULL;
}
return 0;
@@ -1119,6 +1114,10 @@ static int ufs_mtk_init(struct ufs_hba *hba)
host->hba = hba;
ufshcd_set_variant(hba, host);
+ err = ufs_mtk_get_supplies(host);
+ if (err)
+ goto out_variant_clear;
+
/* Initialize host capability */
ufs_mtk_init_host_caps(hba);
@@ -1173,10 +1172,6 @@ static int ufs_mtk_init(struct ufs_hba *hba)
ufs_mtk_init_clocks(hba);
- err = ufs_mtk_get_supplies(host);
- if (err)
- goto out_phy_exit;
-
/*
* ufshcd_vops_init() is invoked after
* ufshcd_setup_clock(true) in ufshcd_hba_init() thus
@@ -1916,7 +1911,6 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba, bool scale_up)
struct ufs_mtk_clk *mclk = &host->mclk;
struct ufs_clk_info *clki = mclk->ufs_sel_clki;
struct ufs_clk_info *fde_clki = mclk->ufs_fde_clki;
- struct regulator *reg;
int volt, ret = 0;
bool clk_bind_vcore = false;
bool clk_fde_scale = false;
@@ -1927,9 +1921,8 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba, bool scale_up)
if (!clki || !fde_clki)
return;
- reg = host->mclk.reg_vcore;
volt = host->mclk.vcore_volt;
- if (reg && volt != 0)
+ if (host->reg_vcore && volt)
clk_bind_vcore = true;
if (mclk->ufs_fde_max_clki && mclk->ufs_fde_min_clki)
@@ -1953,7 +1946,7 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba, bool scale_up)
if (scale_up) {
if (clk_bind_vcore) {
- ret = regulator_set_voltage(reg, volt, INT_MAX);
+ ret = regulator_set_voltage(host->reg_vcore, volt, INT_MAX);
if (ret) {
dev_err(hba->dev, "Failed to set vcore to %d\n", volt);
goto out;
@@ -1993,7 +1986,7 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba, bool scale_up)
}
if (clk_bind_vcore) {
- ret = regulator_set_voltage(reg, 0, INT_MAX);
+ ret = regulator_set_voltage(host->reg_vcore, 0, INT_MAX);
if (ret) {
dev_err(hba->dev, "%s: Failed to set vcore to minimum: %pe\n",
__func__, ERR_PTR(ret));
diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediatek.h
index 9c377745f7a0..fa27ab4d6d6c 100644
--- a/drivers/ufs/host/ufs-mediatek.h
+++ b/drivers/ufs/host/ufs-mediatek.h
@@ -141,7 +141,6 @@ enum ufs_mtk_host_caps {
};
struct ufs_mtk_crypt_cfg {
- struct regulator *reg_vcore;
struct clk *clk_crypt_perf;
struct clk *clk_crypt_mux;
struct clk *clk_crypt_lp;
@@ -155,7 +154,6 @@ struct ufs_mtk_clk {
struct ufs_clk_info *ufs_fde_clki; /* Mux */
struct ufs_clk_info *ufs_fde_max_clki; /* Max src */
struct ufs_clk_info *ufs_fde_min_clki; /* Min src */
- struct regulator *reg_vcore;
int vcore_volt;
};
@@ -174,6 +172,7 @@ struct ufs_mtk_mcq_intr_info {
struct ufs_mtk_host {
struct phy *mphy;
struct regulator *reg_avdd09;
+ struct regulator *reg_vcore;
struct reset_control_bulk_data resets[MTK_UFS_NUM_RESETS];
struct ufs_hba *hba;
struct ufs_mtk_crypt_cfg *crypt;
--
2.53.0
--
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* [PATCH v7 16/23] scsi: ufs: mediatek: Clean up logging prints
From: Nicolas Frattaroli @ 2026-02-16 13:37 UTC (permalink / raw)
To: Alim Akhtar, Avri Altman, Bart Van Assche, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chunfeng Yun, Vinod Koul,
Kishon Vijay Abraham I, Peter Wang, Stanley Jhu,
James E.J. Bottomley, Martin K. Petersen, Philipp Zabel,
Liam Girdwood, Mark Brown, Chaotian Jing, Neil Armstrong
Cc: Louis-Alexis Eyraud, kernel, linux-scsi, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-phy, Nicolas Frattaroli
In-Reply-To: <20260216-mt8196-ufs-v7-0-b5f2907c6da7@collabora.com>
The Linux kernel's log buffer provides many levels of verbosity,
associated with different semantic meanings. Care should be taken to
only log useful information to the info level, and log errors to the
error level.
The MediaTek UFS driver does not do this. It freely logs verbose debug
information to the info level, errors to the info level, and sometimes
errors to the warning level.
Adjust all the wrapped kprintf invocations to rectify this situation.
Use user-friendly %pe format codes for printing errors where possible.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
drivers/ufs/host/ufs-mediatek.c | 99 ++++++++++++++++++-----------------------
1 file changed, 43 insertions(+), 56 deletions(-)
diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index ecf16e82a326..2b1f26b55782 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -192,8 +192,8 @@ static void ufs_mtk_crypto_enable(struct ufs_hba *hba)
ufs_mtk_crypto_ctrl(res, 1);
if (res.a0) {
- dev_info(hba->dev, "%s: crypto enable failed, err: %lu\n",
- __func__, res.a0);
+ dev_err(hba->dev, "%s: crypto enable failed with error %lu, disabling\n",
+ __func__, res.a0);
hba->caps &= ~UFSHCD_CAP_CRYPTO;
}
}
@@ -542,40 +542,38 @@ static void ufs_mtk_boost_crypt(struct ufs_hba *hba, bool boost)
ret = clk_prepare_enable(cfg->clk_crypt_mux);
if (ret) {
- dev_info(hba->dev, "clk_prepare_enable(): %d\n",
- ret);
+ dev_err(hba->dev, "%s: Failed to enable clk_crypt_mux: %pe\n",
+ __func__, ERR_PTR(ret));
return;
}
if (boost) {
ret = regulator_set_voltage(reg, volt, INT_MAX);
if (ret) {
- dev_info(hba->dev,
- "failed to set vcore to %d\n", volt);
+ dev_err(hba->dev, "%s: Failed to set vcore to %d: %pe\n",
+ __func__, volt, ERR_PTR(ret));
goto out;
}
- ret = clk_set_parent(cfg->clk_crypt_mux,
- cfg->clk_crypt_perf);
+ ret = clk_set_parent(cfg->clk_crypt_mux, cfg->clk_crypt_perf);
if (ret) {
- dev_info(hba->dev,
- "failed to set clk_crypt_perf\n");
+ dev_err(hba->dev, "%s: Failed to reparent clk_crypt_perf: %pe\n",
+ __func__, ERR_PTR(ret));
regulator_set_voltage(reg, 0, INT_MAX);
goto out;
}
} else {
- ret = clk_set_parent(cfg->clk_crypt_mux,
- cfg->clk_crypt_lp);
+ ret = clk_set_parent(cfg->clk_crypt_mux, cfg->clk_crypt_lp);
if (ret) {
- dev_info(hba->dev,
- "failed to set clk_crypt_lp\n");
+ dev_err(hba->dev, "%s: Failed to reparent clk_crypt_lp: %pe\n",
+ __func__, ERR_PTR(ret));
goto out;
}
ret = regulator_set_voltage(reg, 0, INT_MAX);
if (ret) {
- dev_info(hba->dev,
- "failed to set vcore to MIN\n");
+ dev_err(hba->dev, "%s: Failed to set vcore to minimum: %pe\n",
+ __func__, ERR_PTR(ret));
}
}
out:
@@ -763,10 +761,8 @@ static int ufs_mtk_setup_clocks(struct ufs_hba *hba, bool on,
if (clk_pwr_off) {
ufs_mtk_pwr_ctrl(hba, false);
} else {
- dev_warn(hba->dev, "Clock is not turned off, hba->ahit = 0x%x, AHIT = 0x%x\n",
- hba->ahit,
- ufshcd_readl(hba,
- REG_AUTO_HIBERNATE_IDLE_TIMER));
+ dev_warn(hba->dev, "Clock isn't off, hba->ahit = 0x%x, AHIT = 0x%x\n",
+ hba->ahit, ufshcd_readl(hba, REG_AUTO_HIBERNATE_IDLE_TIMER));
}
ufs_mtk_mcq_disable_irq(hba);
} else if (on && status == POST_CHANGE) {
@@ -810,11 +806,11 @@ static void ufs_mtk_mcq_set_irq_affinity(struct ufs_hba *hba, unsigned int cpu)
_cpu = (cpu == 0) ? 3 : cpu;
ret = irq_set_affinity(irq, cpumask_of(_cpu));
if (ret) {
- dev_err(hba->dev, "set irq %d affinity to CPU %d failed\n",
+ dev_err(hba->dev, "setting irq %d affinity to CPU %d failed\n",
irq, _cpu);
return;
}
- dev_info(hba->dev, "set irq %d affinity to CPU: %d\n", irq, _cpu);
+ dev_dbg(hba->dev, "set irq %d affinity to CPU %d\n", irq, _cpu);
}
static bool ufs_mtk_is_legacy_chipset(struct ufs_hba *hba, u32 hw_ip_ver)
@@ -830,7 +826,8 @@ static bool ufs_mtk_is_legacy_chipset(struct ufs_hba *hba, u32 hw_ip_ver)
default:
break;
}
- dev_info(hba->dev, "legacy IP version - 0x%x, is legacy : %d", hw_ip_ver, is_legacy);
+ dev_dbg(hba->dev, "IP version 0x%x, legacy = %s", hw_ip_ver,
+ str_true_false(is_legacy));
return is_legacy;
}
@@ -935,15 +932,12 @@ static void ufs_mtk_init_clocks(struct ufs_hba *hba)
}
}
- list_for_each_entry(clki, head, list) {
- dev_info(hba->dev, "clk \"%s\" present", clki->name);
- }
+ list_for_each_entry(clki, head, list)
+ dev_dbg(hba->dev, "clk \"%s\" present", clki->name);
if (!ufs_mtk_is_clk_scale_ready(hba)) {
hba->caps &= ~UFSHCD_CAP_CLK_SCALING;
- dev_info(hba->dev,
- "%s: Clk-scaling not ready. Feature disabled.",
- __func__);
+ dev_info(hba->dev, "%s: Clock scaling unavailable", __func__);
return;
}
@@ -953,8 +947,8 @@ static void ufs_mtk_init_clocks(struct ufs_hba *hba)
*/
reg = devm_regulator_get_optional(dev, "dvfsrc-vcore");
if (IS_ERR(reg)) {
- dev_info(dev, "failed to get dvfsrc-vcore: %ld",
- PTR_ERR(reg));
+ if (PTR_ERR(reg) != -ENODEV)
+ dev_err(dev, "Failed to get dvfsrc-vcore: %pe\n", reg);
return;
}
@@ -968,12 +962,9 @@ static void ufs_mtk_init_clocks(struct ufs_hba *hba)
host->mclk.vcore_volt = volt;
/* If default boot is max gear, request vcore */
- if (reg && volt && host->clk_scale_up) {
- if (regulator_set_voltage(reg, volt, INT_MAX)) {
- dev_info(hba->dev,
- "Failed to set vcore to %d\n", volt);
- }
- }
+ if (reg && volt && host->clk_scale_up)
+ if (regulator_set_voltage(reg, volt, INT_MAX))
+ dev_err(hba->dev, "Failed to set vcore to %d\n", volt);
}
static void ufs_mtk_setup_clk_gating(struct ufs_hba *hba)
@@ -1060,7 +1051,7 @@ static void ufs_mtk_init_mcq_irq(struct ufs_hba *hba)
}
host->mcq_intr_info[i].hba = hba;
host->mcq_intr_info[i].irq = irq;
- dev_info(hba->dev, "get platform mcq irq: %d, %d\n", i, irq);
+ dev_dbg(hba->dev, "get platform mcq irq: %d, %d\n", i, irq);
}
return;
@@ -1307,10 +1298,8 @@ static int ufs_mtk_pre_pwr_change(struct ufs_hba *hba,
host_params.desired_working_mode = UFS_PWM_MODE;
ret = ufshcd_negotiate_pwr_params(&host_params, dev_max_params, dev_req_params);
- if (ret) {
- pr_info("%s: failed to determine capabilities\n",
- __func__);
- }
+ if (ret)
+ dev_warn(hba->dev, "%s: failed to determine capabilities\n", __func__);
if (ufs_mtk_pmc_via_fastauto(hba, dev_req_params)) {
ufs_mtk_adjust_sync_length(hba);
@@ -1356,10 +1345,9 @@ static int ufs_mtk_pre_pwr_change(struct ufs_hba *hba,
ret = ufshcd_uic_change_pwr_mode(hba,
FASTAUTO_MODE << 4 | FASTAUTO_MODE);
- if (ret) {
- dev_err(hba->dev, "%s: HSG1B FASTAUTO failed ret=%d\n",
- __func__, ret);
- }
+ if (ret)
+ dev_err(hba->dev, "%s: HSG1B FASTAUTO failed: %pe\n",
+ __func__, ERR_PTR(ret));
}
/* if already configured to the requested pwr_mode, skip adapt */
@@ -1409,7 +1397,7 @@ static int ufs_mtk_auto_hibern8_disable(struct ufs_hba *hba)
out:
if (ret) {
- dev_warn(hba->dev, "exit h8 state fail, ret=%d\n", ret);
+ dev_err(hba->dev, "Failed to exit h8 state: %pe\n", ERR_PTR(ret));
ufshcd_force_error_recovery(hba);
@@ -1571,7 +1559,7 @@ static int ufs_mtk_device_reset(struct ufs_hba *hba)
/* Some devices may need time to respond to rst_n */
usleep_range(10000, 15000);
- dev_info(hba->dev, "device reset done\n");
+ dev_dbg(hba->dev, "device reset done\n");
return 0;
}
@@ -1607,12 +1595,12 @@ static int ufs_mtk_link_set_hpm(struct ufs_hba *hba)
/* Check link state to make sure exit h8 success */
err = ufs_mtk_wait_idle_state(hba, 5);
if (err) {
- dev_warn(hba->dev, "wait idle fail, err=%d\n", err);
+ dev_err(hba->dev, "Failed to wait for idle: %pe\n", ERR_PTR(err));
return err;
}
err = ufs_mtk_wait_link_state(hba, VS_LINK_UP, 100);
if (err) {
- dev_warn(hba->dev, "exit h8 state fail, err=%d\n", err);
+ dev_err(hba->dev, "Failed to wait for link to be up: %pe\n", ERR_PTR(err));
return err;
}
ufshcd_set_link_active(hba);
@@ -1905,20 +1893,19 @@ static void ufs_mtk_event_notify(struct ufs_hba *hba,
/* Print details of UIC Errors */
if (evt <= UFS_EVT_DME_ERR) {
- dev_info(hba->dev,
- "Host UIC Error Code (%s): %08x\n",
- ufs_uic_err_str[evt], val);
+ dev_err(hba->dev, "Host UIC Error Code (%s): %08x\n",
+ ufs_uic_err_str[evt], val);
reg = val;
}
if (evt == UFS_EVT_PA_ERR) {
for_each_set_bit(bit, ®, ARRAY_SIZE(ufs_uic_pa_err_str))
- dev_info(hba->dev, "%s\n", ufs_uic_pa_err_str[bit]);
+ dev_err(hba->dev, "%s\n", ufs_uic_pa_err_str[bit]);
}
if (evt == UFS_EVT_DL_ERR) {
for_each_set_bit(bit, ®, ARRAY_SIZE(ufs_uic_dl_err_str))
- dev_info(hba->dev, "%s\n", ufs_uic_dl_err_str[bit]);
+ dev_err(hba->dev, "%s\n", ufs_uic_dl_err_str[bit]);
}
}
@@ -2123,7 +2110,7 @@ static int ufs_mtk_mcq_config_resource(struct ufs_hba *hba)
/* fail mcq initialization if interrupt is not filled properly */
if (!host->mcq_nr_intr) {
- dev_info(hba->dev, "IRQs not ready. MCQ disabled.");
+ dev_err(hba->dev, "IRQs not ready. MCQ disabled.");
return -EINVAL;
}
--
2.53.0
--
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^ permalink raw reply related
* [PATCH v7 17/23] scsi: ufs: mediatek: Rework ufs_mtk_wait_idle_state
From: Nicolas Frattaroli @ 2026-02-16 13:37 UTC (permalink / raw)
To: Alim Akhtar, Avri Altman, Bart Van Assche, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chunfeng Yun, Vinod Koul,
Kishon Vijay Abraham I, Peter Wang, Stanley Jhu,
James E.J. Bottomley, Martin K. Petersen, Philipp Zabel,
Liam Girdwood, Mark Brown, Chaotian Jing, Neil Armstrong
Cc: Louis-Alexis Eyraud, kernel, linux-scsi, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-phy, Nicolas Frattaroli
In-Reply-To: <20260216-mt8196-ufs-v7-0-b5f2907c6da7@collabora.com>
While ufs_mtk_wait_idle state has some code smells for me (the
VS_HCE_BASE early exit seems racey at best), it can still benefit from
some general cleanup to make the code flow less convoluted.
Use the iopoll helpers, for one, and specifically the one that sleeps
and does not busy delay, as it's being done for up to 5ms.
The register read is split out to a helper function that branches
between new and old style flow.
Every called uses the same 5ms timeout value, so there is no point in
making this a parameter. Just assume a 5ms timeout in the function.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
drivers/ufs/host/ufs-mediatek.c | 71 +++++++++++++++++------------------------
1 file changed, 30 insertions(+), 41 deletions(-)
diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index 2b1f26b55782..b5c75d228c85 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -10,6 +10,7 @@
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/delay.h>
+#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
@@ -380,51 +381,39 @@ static void ufs_mtk_dbg_sel(struct ufs_hba *hba)
}
}
-static int ufs_mtk_wait_idle_state(struct ufs_hba *hba,
- unsigned long retry_ms)
+static u32 ufs_mtk_read_state(struct ufs_hba *hba, bool old_style)
{
- u64 timeout, time_checked;
- u32 val, sm;
- bool wait_idle;
- struct ufs_mtk_host *host = ufshcd_get_variant(hba);
-
- /* cannot use plain ktime_get() in suspend */
- timeout = ktime_get_mono_fast_ns() + retry_ms * 1000000UL;
-
- /* wait a specific time after check base */
- udelay(10);
- wait_idle = false;
+ u32 val;
- do {
- time_checked = ktime_get_mono_fast_ns();
- if (host->legacy_ip_ver || host->ip_ver < IP_VER_MT6899) {
- ufs_mtk_dbg_sel(hba);
- val = ufshcd_readl(hba, REG_UFS_PROBE);
- } else {
- val = ufshcd_readl(hba, REG_UFS_UFS_MMIO_OTSD_CTRL);
- val = val >> 16;
- }
+ if (old_style) {
+ ufs_mtk_dbg_sel(hba);
+ val = ufshcd_readl(hba, REG_UFS_PROBE);
+ } else {
+ val = ufshcd_readl(hba, REG_UFS_UFS_MMIO_OTSD_CTRL) >> 16;
+ }
- sm = val & 0x1f;
+ return FIELD_GET(0x1f, val);
+}
- /*
- * if state is in H8 enter and H8 enter confirm
- * wait until return to idle state.
- */
- if ((sm >= VS_HIB_ENTER) && (sm <= VS_HIB_EXIT)) {
- wait_idle = true;
- udelay(50);
- continue;
- } else if (!wait_idle)
- break;
+static int ufs_mtk_wait_idle_state(struct ufs_hba *hba)
+{
+ struct ufs_mtk_host *host = ufshcd_get_variant(hba);
+ bool old_style = (host->legacy_ip_ver || host->ip_ver < IP_VER_MT6899);
+ u32 val;
+ int ret;
- if (wait_idle && (sm == VS_HCE_BASE))
- break;
- } while (time_checked < timeout);
+ /* If the device is already in the base state after 10us, don't wait. */
+ udelay(10);
+ if (ufs_mtk_read_state(hba, old_style) == VS_HCE_BASE)
+ return 0;
- if (wait_idle && sm != VS_HCE_BASE) {
- dev_info(hba->dev, "wait idle tmo: 0x%x\n", val);
- return -ETIMEDOUT;
+ /* Poll to wait for idle */
+ ret = read_poll_timeout(ufs_mtk_read_state, val,
+ (val < VS_HIB_ENTER || val > VS_HIB_EXIT), 50,
+ 5 * USEC_PER_MSEC, false, hba, old_style);
+ if (ret) {
+ dev_err(hba->dev, "Timed out waiting for idle state, val = 0x%x\n", val);
+ return ret;
}
return 0;
@@ -1389,7 +1378,7 @@ static int ufs_mtk_auto_hibern8_disable(struct ufs_hba *hba)
ufshcd_writel(hba, 0, REG_AUTO_HIBERNATE_IDLE_TIMER);
/* wait host return to idle state when auto-hibern8 off */
- ret = ufs_mtk_wait_idle_state(hba, 5);
+ ret = ufs_mtk_wait_idle_state(hba);
if (ret)
goto out;
@@ -1593,7 +1582,7 @@ static int ufs_mtk_link_set_hpm(struct ufs_hba *hba)
return err;
/* Check link state to make sure exit h8 success */
- err = ufs_mtk_wait_idle_state(hba, 5);
+ err = ufs_mtk_wait_idle_state(hba);
if (err) {
dev_err(hba->dev, "Failed to wait for idle: %pe\n", ERR_PTR(err));
return err;
--
2.53.0
--
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