* Re: [PATCH v3] dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: document the Eliza QMP UFS PHY
From: Vinod Koul @ 2026-02-27 15:29 UTC (permalink / raw)
To: Neil Armstrong, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Abel Vesa
Cc: Nitin Rawat, Konrad Dybcio, linux-arm-msm, linux-phy, devicetree,
linux-kernel, Krzysztof Kozlowski
In-Reply-To: <20260223-eliza-bindings-phy-ufs-v3-1-2b0c0f00bcb6@oss.qualcomm.com>
On Mon, 23 Feb 2026 10:19:38 +0200, Abel Vesa wrote:
> Document the QMP UFS PHY compatible for the Eliza Platform. It is fully
> compatible with the PHY implemented in SM8650, so use the SM8650
> compatible as fallback.
>
> While at it, move the QCS8300 one so that it is sorted correctly by
> fallback compatible.
>
> [...]
Applied, thanks!
[1/1] dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: document the Eliza QMP UFS PHY
commit: caf08514bbee0736c31d8d4f406e3415cdf726bb
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* Re: [PATCH] phy: qcom: m31-eusb2: clear PLL_EN during init
From: Vinod Koul @ 2026-02-27 15:29 UTC (permalink / raw)
To: Konrad Dybcio, Neil Armstrong, Wesley Cheng, Johan Hovold,
Dmitry Baryshkov, Elson Serrao
Cc: linux-arm-msm, linux-phy, linux-kernel, stable
In-Reply-To: <20260217201130.2804550-1-elson.serrao@oss.qualcomm.com>
On Tue, 17 Feb 2026 12:11:30 -0800, Elson Serrao wrote:
> The driver currently sets bit 0 of USB_PHY_CFG1 (PLL_EN) during PHY
> initialization. According to the M31 EUSB2 PHY hardware documentation,
> this bit is intended only for test/debug scenarios and does not control
> mission mode operation. Keeping PLL_EN asserted causes the PHY to draw
> additional current during USB bus suspend. Clearing this bit results in
> lower suspend power consumption without affecting normal operation.
>
> [...]
Applied, thanks!
[1/1] phy: qcom: m31-eusb2: clear PLL_EN during init
commit: 520a98bdf7ae0130e22d8adced3d69a2e211b41f
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* Re: [PATCH v9 0/2] Add driver support for Eswin EIC7700 SoC SATA PHY
From: Vinod Koul @ 2026-02-27 15:29 UTC (permalink / raw)
To: neil.armstrong, robh, krzk+dt, conor+dt, p.zabel, linux-phy,
devicetree, linux-kernel, Yulin Lu
Cc: ningyu, linmin, fenglin
In-Reply-To: <20260205082009.1780-1-luyulin@eswincomputing.com>
On Thu, 05 Feb 2026 16:20:09 +0800, Yulin Lu wrote:
> Updates:
> v9 -> v8:
> - eswin,eic7700-sata-phy.yaml
> - Modify the format of the "default" field in the
> "eswin,tx-amplitude-tuning" and "eswin,tx-preemph-tuning"
> properties.
> - phy-eic7700-sata.c
> - Correct the incorrectly formatted symbol "-" in the comments.
> - Link to v8: https://lore.kernel.org/lkml/20260123024823.1612-1-luyulin@eswincomputing.com/
>
> [...]
Applied, thanks!
[1/2] dt-bindings: phy: eswin: Document the EIC7700 SoC SATA PHY
commit: 820265f7b666d588bcb7df06f3332265c59e8cea
[2/2] phy: eswin: Create eswin directory and add EIC7700 SATA PHY driver
commit: 67ee9ccaa34a11c317411bb8e7d305d93d0b4111
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* Re: [PATCH phy-next v2] phy: apple: apple: Use local variable for ioremap return value
From: Vinod Koul @ 2026-02-27 15:29 UTC (permalink / raw)
To: Sven Peter, Neal Gompa, Neil Armstrong, Philipp Zabel,
Janne Grunau
Cc: asahi, linux-phy, linux-kernel, linux-arm-kernel, Dan Carpenter,
Vladimir Oltean
In-Reply-To: <20260215-phy-apple-resource-err-ptr-v2-1-e43c22453682@jannau.net>
On Sun, 15 Feb 2026 09:02:51 +0100, Janne Grunau wrote:
> The indirection through the resources array is unnecessarily complicated
> and resuling in using IS_ERR() and PTR_ERR() on a valid address. A local
> variable for the devm_ioremap_resource() return value is both easier to
> read and matches expectations when reading code.
>
>
Applied, thanks!
[1/1] phy: apple: apple: Use local variable for ioremap return value
commit: 290a35756aaef85bbe0527eaf451f533a61b5f6c
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* Re: [PATCH 1/3] phy: apple: atc: Make atcphy_dwc3_reset_ops variable static
From: Vinod Koul @ 2026-02-27 15:29 UTC (permalink / raw)
To: Sven Peter, Janne Grunau, Neal Gompa, Neil Armstrong,
Philipp Zabel, asahi, linux-arm-kernel, linux-phy, linux-kernel,
linux-arm-msm, Krzysztof Kozlowski
In-Reply-To: <20260216110413.159994-4-krzysztof.kozlowski@oss.qualcomm.com>
On Mon, 16 Feb 2026 12:04:14 +0100, Krzysztof Kozlowski wrote:
> File-scope 'atcphy_dwc3_reset_ops' is not used outside of this unit, so
> make it static to silence sparse warning:
>
> atc.c:2026:32: warning: symbol 'atcphy_dwc3_reset_ops' was not declared. Should it be static?
>
>
Applied, thanks!
[1/3] phy: apple: atc: Make atcphy_dwc3_reset_ops variable static
commit: b3fddddf3fb49c7472e73680d6ea5d771f9514e8
[2/3] phy: marvell: mmp3-hsic: Avoid re-casting __iomem
commit: c77eee5b44b8d32d471cf17fa193b395e321ef37
[3/3] phy: qcom: qmp-usbc: Simplify check for non-NULL pointer
commit: b6b7d1ae0653dcaa356be31c0de221311e922ccd
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* Re: (subset) [PATCH v3 0/6] Add support for mt8167 display blocks
From: Vinod Koul @ 2026-02-27 15:29 UTC (permalink / raw)
To: linux-mediatek, Luca Leonardo Scorcia
Cc: Chun-Kuang Hu, Philipp Zabel, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Chunfeng Yun, Neil Armstrong,
Matthias Brugger, AngeloGioacchino Del Regno, dri-devel,
devicetree, linux-kernel, linux-arm-kernel, linux-phy
In-Reply-To: <cover.1771863641.git.l.scorcia@gmail.com>
On Mon, 23 Feb 2026 16:22:44 +0000, Luca Leonardo Scorcia wrote:
> This series adds support for the display blocks on MediaTek mt8167.
> Tested on Xiaomi Mi Smart Clock x04g.
>
> The first patch just does some reordering of dts nodes with no other
> changes as this makes later patches cleaner and easier to follow.
>
> v3:
> - Added mt8167-dsi compatible to driver instead of changing the binding;
> - Resolved patch formatting issues.
>
> [...]
Applied, thanks!
[3/6] dt-bindings: phy: mediatek,dsi-phy: Add support for mt8167
commit: 7df891f2c39442c120fb4f9bfdd7c80e6de84015
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* Re: (subset) [PATCH v5 0/4] Add USB support for Canaan K230
From: Vinod Koul @ 2026-02-27 15:29 UTC (permalink / raw)
To: gregkh, conor, Jiayu Du
Cc: neil.armstrong, robh, krzk+dt, pjw, palmer, aou, alex, linux-phy,
linux-usb, devicetree, linux-riscv, linux-kernel
In-Reply-To: <20260121145526.14672-1-jiayu.riscv@isrc.iscas.ac.cn>
On Wed, 21 Jan 2026 22:55:21 +0800, Jiayu Du wrote:
> Add support for the USB PHY and DWC2 IP which is used by Canaan K230,
> and made relevant changes to the DTS.
>
> This series is based on the initial 100ask K230 DshanPi series [1] which
> is based on the clock and pinctrl series. Check the details in the link.
>
> Link: https://lore.kernel.org/all/20260115060801.16819-1-jiayu.riscv@isrc.iscas.ac.cn/ [1]
>
> [...]
Applied, thanks!
[1/4] dt-bindings: phy: Add Canaan K230 USB PHY
commit: 50357e7d7992ba8f02c87ff7a5c4db17918635da
[3/4] phy: usb: Add driver for Canaan K230 USB 2.0 PHY
commit: 8787fa1da603e9e51efff11841e97b5d374aef34
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* Re: [PATCH] phy: phy-mtk-tphy: Update names and format of kernel-doc comments
From: Vinod Koul @ 2026-02-27 15:29 UTC (permalink / raw)
To: linux-phy, Vinod Koul; +Cc: Neil Armstrong, Vladimir Oltean, chunfeng.yun
In-Reply-To: <20260223071032.408425-1-vkoul@kernel.org>
On Mon, 23 Feb 2026 12:40:32 +0530, Vinod Koul wrote:
> mtk_phy_pdata documentation does not use correct tag for struct, while at
> it fix one of member wrongly documented.
>
> Warning: drivers/phy/mediatek/phy-mtk-tphy.c:289 cannot understand function prototype: 'struct mtk_phy_pdata'
> Warning: drivers/phy/mediatek/phy-mtk-tphy.c:296 struct member 'slew_ref_clock_mhz' not described in 'mtk_phy_pdata'
>
>
> [...]
Applied, thanks!
[1/1] phy: phy-mtk-tphy: Update names and format of kernel-doc comments
commit: 8d869bc943cfe5db08f5aff355b1d8d3abeda865
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* Re: [PATCH] phy: Sort the subsystem Kconfig
From: Vinod Koul @ 2026-02-27 15:29 UTC (permalink / raw)
To: linux-phy, Vinod Koul; +Cc: Neil Armstrong, Vladimir Oltean
In-Reply-To: <20260223065819.395612-1-vkoul@kernel.org>
On Mon, 23 Feb 2026 12:28:19 +0530, Vinod Koul wrote:
> Kconfig is supposed to be sorted alphabetically, sadly it has bitrotted
> so fix that
>
>
Applied, thanks!
[1/1] phy: Sort the subsystem Kconfig
commit: dee40773abe543723adab47319bc25dc70de10a2
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* Re: [PATCH] phy: Sort the subsystem Makefile
From: Vinod Koul @ 2026-02-27 15:29 UTC (permalink / raw)
To: linux-phy, Vinod Koul; +Cc: Neil Armstrong, Vladimir Oltean
In-Reply-To: <20260223065743.395539-1-vkoul@kernel.org>
On Mon, 23 Feb 2026 12:27:43 +0530, Vinod Koul wrote:
> Makefile is supposed to be sorted alphabetically, sadly it has bitrotted
> so fix that
>
>
Applied, thanks!
[1/1] phy: Sort the subsystem Makefile
commit: d8f0ef2aebaa90c0155e266c1fdd6fa2aef44bb1
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* Re: [PATCH] phy: move spacemit pcie driver to its subfolder
From: Vinod Koul @ 2026-02-27 15:29 UTC (permalink / raw)
To: linux-phy, Vinod Koul
Cc: Neil Armstrong, Vladimir Oltean, Alex Elder, Ze Huang, spacemit
In-Reply-To: <20260223064240.386617-1-vkoul@kernel.org>
On Mon, 23 Feb 2026 12:12:39 +0530, Vinod Koul wrote:
> Commit fe4bc1a08638 ("phy: spacemit: support K1 USB2.0 PHY controller")
> created spacemit subfolder with usb driver while commit 57e920b92724
> ("phy: spacemit: Introduce PCIe/combo PHY") added pcie driver in phy
> folder. Move latter into spacemit subfolder and rename file to
> phy-k1-pcie.c
>
>
> [...]
Applied, thanks!
[1/1] phy: move spacemit pcie driver to its subfolder
commit: 75fb1a33f9ac4c9730e61bb19aaaab02023a99b2
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* Re: [PATCH net-next 0/9] net: stmmac: qcom-ethqos: further serdes reorganisation
From: Vladimir Oltean @ 2026-02-27 15:27 UTC (permalink / raw)
To: Vinod Koul
Cc: Russell King (Oracle), Andrew Lunn, Alexandre Torgue, Andrew Lunn,
David S. Miller, Eric Dumazet, Jakub Kicinski, linux-arm-kernel,
linux-arm-msm, linux-phy, linux-stm32, Mohd Ayaan Anwar,
Neil Armstrong, netdev, Paolo Abeni
In-Reply-To: <aaGgWUpM2A5y11Wh@vaman>
Hi Vinod,
On Fri, Feb 27, 2026 at 07:17:05PM +0530, Vinod Koul wrote:
> On 25-02-26, 09:02, Russell King (Oracle) wrote:
> > Note: only 8 patches in this series, not 9 as the subject line says,
> > as the set_clk_tx_rate() patch became part of the first series.
> >
> > On Wed, Feb 25, 2026 at 09:00:41AM +0000, Russell King (Oracle) wrote:
> > > This is part 2 of the qcom-ethqos series, part 1 has now been merged.
> > >
> > > This part of the series focuses on the generic PHY driver, but these
> > > changes have dependencies on the ethernet driver, hence why
> > > it will need to go via net-next. Furthermore, subsequent changes
> > > depend on these patches.
>
> This lgtm, can we get signed tag so that we can pull this into phy tree
> as well
I think this series is obsolete. It has been superseded in the netdev
patchwork by:
[PATCH RESEND2 net-next 0/8] net: stmmac: qcom-ethqos: further serdes reorganisation
├─>[PATCH RESEND2 net-next 1/8] net: stmmac: qcom-ethqos: move ethqos_set_serdes_speed()
├─>[PATCH RESEND2 net-next 2/8] phy: qcom-sgmii-eth: add .set_mode() and .validate() methods
├─>[PATCH RESEND2 net-next 3/8] net: stmmac: qcom-ethqos: convert to use phy_set_mode_ext()
├─>[PATCH RESEND2 net-next 4/8] phy: qcom-sgmii-eth: remove .set_speed() implementation
├─>[PATCH RESEND2 net-next 5/8] phy: qcom-sgmii-eth: use PHY interface mode for SerDes settings
├─>[PATCH RESEND2 net-next 6/8] phy: qcom-sgmii-eth: remove qcom_dwmac_sgmii_phy_interface()
├─>[PATCH RESEND2 net-next 7/8] phy: qcom-sgmii-eth: relax order of .power_on() vs .set_mode*()
└─>[PATCH RESEND2 net-next 8/8] net: stmmac: qcom-ethqos: remove phy_set_mode_ext() after phy_power_on()
(with which it is only partially overlapping)
I guess you should give your Acks there as well.
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* Re: [PATCH] phy: qcom: qmp-ufs: Fix SM8650 PCS table for Gear 4
From: Vinod Koul @ 2026-02-27 15:25 UTC (permalink / raw)
To: Neil Armstrong, Konrad Dybcio, Abel Vesa
Cc: Manivannan Sadhasivam, linux-arm-msm, linux-phy, linux-kernel,
stable, Nitin Rawat
In-Reply-To: <20260219-phy-qcom-qmp-ufs-fix-sm8650-pcs-g4-table-v1-1-f136505b57f6@oss.qualcomm.com>
On Thu, 19 Feb 2026 13:11:48 +0200, Abel Vesa wrote:
> According to internal documentation, on SM8650, when the PHY is configured
> in Gear 4, the QPHY_V6_PCS_UFS_PLL_CNTL register needs to have the same
> value as for Gear 5.
>
> At the moment, there is no board that comes with a UFS 3.x device, so
> this issue doesn't show up, but with the new Eliza SoC, which uses the
> same init sequence as SM8650, on the MTP board, the link startup fails
> with the current Gear 4 PCS table.
>
> [...]
Applied, thanks!
[1/1] phy: qcom: qmp-ufs: Fix SM8650 PCS table for Gear 4
commit: 81af9e40e2e4e1aa95f09fb34811760be6742c58
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* Re: [PATCH v2] phy: ti: j721e-wiz: Fix device node reference leak in wiz_get_lane_phy_types()
From: Vinod Koul @ 2026-02-27 15:25 UTC (permalink / raw)
To: Neil Armstrong, Kishon Vijay Abraham I, Jyri Sarha,
Vladimir Oltean, Felix Gu
Cc: linux-phy, linux-kernel
In-Reply-To: <20260212-wiz-v2-1-6e8bd4cc7a4a@gmail.com>
On Thu, 12 Feb 2026 18:39:19 +0800, Felix Gu wrote:
> The serdes device_node is obtained using of_get_child_by_name(),
> which increments the reference count. However, it is never put,
> leading to a reference leak.
>
> Add the missing of_node_put() calls to ensure the reference count is
> properly balanced.
>
> [...]
Applied, thanks!
[1/1] phy: ti: j721e-wiz: Fix device node reference leak in wiz_get_lane_phy_types()
commit: 584b457f4166293bdfa50f930228e9fb91a38392
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* Re: [PATCH v3] phy: k1-usb: add disconnect function support
From: Vinod Koul @ 2026-02-27 15:25 UTC (permalink / raw)
To: Neil Armstrong, Ze Huang, Yixun Lan
Cc: Vladimir Oltean, Junzhong Pan, spacemit, linux-phy, linux-riscv,
linux-kernel
In-Reply-To: <20260216152653.25244-1-dlan@kernel.org>
On Mon, 16 Feb 2026 23:26:53 +0800, Yixun Lan wrote:
> A disconnect status BIT of USB2 PHY need to be cleared, otherwise
> it will fail to work properly during next connection when devices
> connect to roothub directly.
>
>
Applied, thanks!
[1/1] phy: k1-usb: add disconnect function support
commit: f0cf0a882a02dcf28547f32264f6fd37e9a7b147
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* Re: [PATCH phy-fixes] phy: lynx-28g: skip CDR lock workaround for lanes disabled in the device tree
From: Vinod Koul @ 2026-02-27 15:25 UTC (permalink / raw)
To: linux-phy, Vladimir Oltean; +Cc: Neil Armstrong, Ioana Ciornei, linux-kernel
In-Reply-To: <20260226182853.1103616-1-vladimir.oltean@nxp.com>
On Thu, 26 Feb 2026 20:28:53 +0200, Vladimir Oltean wrote:
> The blamed commit introduced support for specifying individual lanes as
> OF nodes in the device, and these can have status = "disabled".
>
> When that happens, for_each_available_child_of_node() skips them and
> lynx_28g_probe_lane() -> devm_phy_create() is not called, so lane->phy
> will be NULL. Yet it will be dereferenced in lynx_28g_cdr_lock_check(),
> resulting in a crash.
>
> [...]
Applied, thanks!
[1/1] phy: lynx-28g: skip CDR lock workaround for lanes disabled in the device tree
commit: a258d843a3e4cb687da19437f8f81fee55ad7d35
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* Re: [PATCH phy-fixes] phy: make PHY_COMMON_PROPS Kconfig symbol conditionally user-selectable
From: Vinod Koul @ 2026-02-27 15:25 UTC (permalink / raw)
To: linux-phy, Vladimir Oltean
Cc: Neil Armstrong, Bjørn Mork, linux-kernel, Geert Uytterhoeven
In-Reply-To: <20260226153315.3530378-1-vladimir.oltean@nxp.com>
On Thu, 26 Feb 2026 17:33:15 +0200, Vladimir Oltean wrote:
> Geert reports that enabling CONFIG_KUNIT_ALL_TESTS shouldn't enable
> features that aren't enabled without it. That isn't what "*all* tests"
> means, but as the prompt puts it, "All KUnit tests with satisfied
> dependencies".
>
> The impact is that enabling CONFIG_KUNIT_ALL_TESTS brings features which
> cannot be disabled as built-in into the kernel.
>
> [...]
Applied, thanks!
[1/1] phy: make PHY_COMMON_PROPS Kconfig symbol conditionally user-selectable
commit: 48fafffcf29bb968c9dee6bf507c1e57d0ccb6b5
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* Re: [PATCH v2 3/3] phy: k1-usb: k3: add USB2 PHY support
From: Vinod Koul @ 2026-02-27 14:59 UTC (permalink / raw)
To: Yixun Lan
Cc: Neil Armstrong, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Ze Huang, Junzhong Pan, linux-phy, devicetree, linux-riscv,
spacemit, linux-kernel
In-Reply-To: <20260214-11-k3-usb2-phy-v2-3-6ed31e031ab4@kernel.org>
On 14-02-26, 20:29, Yixun Lan wrote:
> Add USB2 PHY support for SpacemiT K3 SoC.
>
> Register layout of handling USB disconnect operation has been changed,
> So introducing a platform data to distinguish the different SoCs.
>
> Signed-off-by: Yixun Lan <dlan@kernel.org>
> ---
> drivers/phy/spacemit/phy-k1-usb2.c | 34 +++++++++++++++++++++++++++++-----
> 1 file changed, 29 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/phy/spacemit/phy-k1-usb2.c b/drivers/phy/spacemit/phy-k1-usb2.c
> index 959bf79c7a72..b4ba97481ddd 100644
> --- a/drivers/phy/spacemit/phy-k1-usb2.c
> +++ b/drivers/phy/spacemit/phy-k1-usb2.c
> @@ -51,6 +51,9 @@
> #define PHY_K1_HS_HOST_DISC 0x40
> #define PHY_K1_HS_HOST_DISC_CLR BIT(0)
>
> +#define PHY_K3_HS_HOST_DISC 0x20
> +#define PHY_K3_HS_HOST_DISC_CLR BIT(8)
> +
> #define PHY_PLL_DIV_CFG 0x98
> #define PHY_FDIV_FRACT_8_15 GENMASK(7, 0)
> #define PHY_FDIV_FRACT_16_19 GENMASK(11, 8)
> @@ -145,7 +148,7 @@ static int spacemit_usb2phy_exit(struct phy *phy)
> return 0;
> }
>
> -static int spacemit_usb2phy_disconnect(struct phy *phy, int port)
> +static int spacemit_k1_usb2phy_disconnect(struct phy *phy, int port)
> {
> struct spacemit_usb2phy *sphy = phy_get_drvdata(phy);
>
> @@ -155,10 +158,27 @@ static int spacemit_usb2phy_disconnect(struct phy *phy, int port)
> return 0;
> }
>
> -static const struct phy_ops spacemit_usb2phy_ops = {
> +static int spacemit_k3_usb2phy_disconnect(struct phy *phy, int port)
> +{
> + struct spacemit_usb2phy *sphy = phy_get_drvdata(phy);
> +
> + regmap_update_bits(sphy->regmap_base, PHY_K3_HS_HOST_DISC,
> + PHY_K3_HS_HOST_DISC_CLR, PHY_K3_HS_HOST_DISC_CLR);
Please match this with preceding open parenthesis
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* Re: [PATCH v2 2/4] phy: axiado: add Axiado eMMC PHY driver
From: Vinod Koul @ 2026-02-27 14:53 UTC (permalink / raw)
To: Tzu-Hao Wei
Cc: SriNavmani A, Prasad Bolisetty, Neil Armstrong, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, linux-phy, devicetree,
linux-arm-kernel, linux-kernel, openbmc
In-Reply-To: <20260206-axiado-ax3000-add-emmc-phy-driver-support-v2-2-a2f59e97a92d@axiado.com>
On 06-02-26, 16:22, Tzu-Hao Wei wrote:
> From: SriNavmani A <srinavmani@axiado.com>
>
> It provides the required configurations for Axiado eMMC PHY driver for
> HS200 mode.
>
> Signed-off-by: SriNavmani A <srinavmani@axiado.com>
> Co-developed-by: Prasad Bolisetty <pbolisetty@axiado.com>
> Signed-off-by: Prasad Bolisetty <pbolisetty@axiado.com>
> Signed-off-by: Tzu-Hao Wei <twei@axiado.com>
> ---
> drivers/phy/Kconfig | 1 +
> drivers/phy/Makefile | 1 +
> drivers/phy/axiado/Kconfig | 11 ++
> drivers/phy/axiado/Makefile | 1 +
> drivers/phy/axiado/phy-axiado-emmc.c | 221 +++++++++++++++++++++++++++++++++++
> 5 files changed, 235 insertions(+)
>
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 678dd0452f0aa0597773433f04d2a9ba77474d2a..b802274ea45a84bd36d7c0b7fb90e368a5c018b4 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -103,6 +103,7 @@ config PHY_NXP_PTN3222
>
> source "drivers/phy/allwinner/Kconfig"
> source "drivers/phy/amlogic/Kconfig"
> +source "drivers/phy/axiado/Kconfig"
> source "drivers/phy/broadcom/Kconfig"
> source "drivers/phy/cadence/Kconfig"
> source "drivers/phy/freescale/Kconfig"
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index bfb27fb5a494283d7fd05dd670ebd1b12df8b1a1..f1b9e4a8673bcde3fdc0fdc06a3deddb5785ced1 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -15,6 +15,7 @@ obj-$(CONFIG_PHY_AIROHA_PCIE) += phy-airoha-pcie.o
> obj-$(CONFIG_PHY_NXP_PTN3222) += phy-nxp-ptn3222.o
> obj-y += allwinner/ \
> amlogic/ \
> + axiado/ \
> broadcom/ \
> cadence/ \
> freescale/ \
> diff --git a/drivers/phy/axiado/Kconfig b/drivers/phy/axiado/Kconfig
> new file mode 100644
> index 0000000000000000000000000000000000000000..d159e0345345987c7f48dcd12d3237997735d2b5
> --- /dev/null
> +++ b/drivers/phy/axiado/Kconfig
> @@ -0,0 +1,11 @@
> +#
> +# PHY drivers for Axiado platforms
> +#
> +
> +config PHY_AX3000_EMMC
> + tristate "Axiado eMMC PHY driver"
> + depends on OF && (ARCH_AXIADO || COMPILE_TEST)
> + select GENERIC_PHY
> + help
> + Enables this to support for the AX3000 EMMC PHY driver.
> + If unsure, say N.
> diff --git a/drivers/phy/axiado/Makefile b/drivers/phy/axiado/Makefile
> new file mode 100644
> index 0000000000000000000000000000000000000000..1e2b1ba016092eaffdbd7acbd9cdc8577d79b35c
> --- /dev/null
> +++ b/drivers/phy/axiado/Makefile
> @@ -0,0 +1 @@
> +obj-$(CONFIG_PHY_AX3000_EMMC) += phy-axiado-emmc.o
> diff --git a/drivers/phy/axiado/phy-axiado-emmc.c b/drivers/phy/axiado/phy-axiado-emmc.c
> new file mode 100644
> index 0000000000000000000000000000000000000000..28d2a30c3b35ee7dba917487959e226941e8ea4b
> --- /dev/null
> +++ b/drivers/phy/axiado/phy-axiado-emmc.c
> @@ -0,0 +1,221 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * Axiado eMMC PHY driver
> + *
> + * Copyright (C) 2017 Arasan Chip Systems Inc.
> + * Copyright (C) 2022-2025 Axiado Corporation (or its affiliates).
2026
> + *
> + * Based on Arasan Driver (sdhci-pci-arasan.c)
> + * sdhci-pci-arasan.c - Driver for Arasan PCI Controller with integrated phy.
> + */
> +#include <linux/bitfield.h>
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +
> +/* Arasan eMMC 5.1 - PHY configuration registers */
> +#define CAP_REG_IN_S1_LSB 0x00
> +#define CAP_REG_IN_S1_MSB 0x04
> +#define PHY_CTRL_1 0x38
> +#define PHY_CTRL_2 0x3C
smaller hex case please, here and other places
> +#define PHY_CTRL_3 0x40
> +#define STATUS 0x50
> +
> +#define DLL_ENBL BIT(26)
> +#define RTRIM_EN BIT(21)
> +#define PDB_ENBL BIT(23)
> +#define RETB_ENBL BIT(1)
> +
> +#define REN_STRB BIT(27)
> +#define REN_CMD BIT(12)
> +#define REN_DAT0 BIT(13)
> +#define REN_DAT1 BIT(14)
> +#define REN_DAT2 BIT(15)
> +#define REN_DAT3 BIT(16)
> +#define REN_DAT4 BIT(17)
> +#define REN_DAT5 BIT(18)
> +#define REN_DAT6 BIT(19)
> +#define REN_DAT7 BIT(20)
> +#define REN_CMD_EN (REN_CMD | REN_DAT0 | REN_DAT1 | REN_DAT2 | \
> + REN_DAT3 | REN_DAT4 | REN_DAT5 | REN_DAT6 | REN_DAT7)
> +
> +/* Pull-UP Enable on CMD Line */
> +#define PU_CMD BIT(3)
> +#define PU_DAT0 BIT(4)
> +#define PU_DAT1 BIT(5)
> +#define PU_DAT2 BIT(6)
> +#define PU_DAT3 BIT(7)
> +#define PU_DAT4 BIT(8)
> +#define PU_DAT5 BIT(9)
> +#define PU_DAT6 BIT(10)
> +#define PU_DAT7 BIT(11)
> +#define PU_CMD_EN (PU_CMD | PU_DAT0 | PU_DAT1 | PU_DAT2 | PU_DAT3 | \
> + PU_DAT4 | PU_DAT5 | PU_DAT6 | PU_DAT7)
The bit define are used only once, why not define the cmd with
respective bits here
> +
> +/* Selection value for the optimum delay from 1-32 output tap lines */
> +#define OTAP_DLY 0x02
> +/* DLL charge pump current trim default [1000] */
> +#define DLL_TRM_ICP 0x08
> +/* Select the frequency range of DLL Operation */
> +#define FRQ_SEL 0x01
> +
> +#define OTAP_SEL_MASK GENMASK(10, 7)
> +#define DLL_TRM_MASK GENMASK(25, 22)
> +#define DLL_FRQSEL_MASK GENMASK(27, 25)
> +
> +#define OTAP_SEL(x) (FIELD_PREP(OTAP_SEL_MASK, x) | OTAPDLY_EN)
> +#define DLL_TRM(x) (FIELD_PREP(DLL_TRM_MASK, x) | DLL_ENBL)
> +#define DLL_FRQSEL(x) FIELD_PREP(DLL_FRQSEL_MASK, x)
> +
> +#define OTAPDLY_EN BIT(11)
> +
> +#define SEL_DLY_RXCLK BIT(18)
> +#define SEL_DLY_TXCLK BIT(19)
> +
> +#define CALDONE_MASK 0x40
> +#define DLL_RDY_MASK 0x1
> +#define MAX_CLK_BUF0 BIT(20)
> +#define MAX_CLK_BUF1 BIT(21)
> +#define MAX_CLK_BUF2 BIT(22)
> +
> +#define CLK_MULTIPLIER 0xC008E
> +#define POLL_TIMEOUT_MS 3000
> +#define POLL_DELAY_US 100
> +
> +struct axiado_emmc_phy {
> + void __iomem *reg_base;
> + struct device *dev;
> +};
> +
> +static int axiado_emmc_phy_init(struct phy *phy)
> +{
> + struct axiado_emmc_phy *ax_phy = phy_get_drvdata(phy);
> + struct device *dev = ax_phy->dev;
> + u32 val;
> + int ret;
> +
> + val = readl(ax_phy->reg_base + PHY_CTRL_1);
> + writel(val | RETB_ENBL | RTRIM_EN, ax_phy->reg_base + PHY_CTRL_1);
> +
> + val = readl(ax_phy->reg_base + PHY_CTRL_3);
> + writel(val | PDB_ENBL, ax_phy->reg_base + PHY_CTRL_3);
> +
> + ret = readl_poll_timeout(ax_phy->reg_base + STATUS, val,
> + val & CALDONE_MASK, POLL_DELAY_US,
> + POLL_TIMEOUT_MS * 1000);
> + if (ret) {
> + dev_err(dev, "PHY calibration timeout\n");
> + return ret;
> + }
> +
> + val = readl(ax_phy->reg_base + PHY_CTRL_1);
> + writel(val | REN_CMD_EN | PU_CMD_EN, ax_phy->reg_base + PHY_CTRL_1);
> +
> + val = readl(ax_phy->reg_base + PHY_CTRL_2);
> + writel(val | REN_STRB, ax_phy->reg_base + PHY_CTRL_2);
> +
> + val = readl(ax_phy->reg_base + PHY_CTRL_3);
> + writel(val | MAX_CLK_BUF0 | MAX_CLK_BUF1 | MAX_CLK_BUF2,
> + ax_phy->reg_base + PHY_CTRL_3);
> +
> + writel(CLK_MULTIPLIER, ax_phy->reg_base + CAP_REG_IN_S1_MSB);
> +
> + val = readl(ax_phy->reg_base + PHY_CTRL_3);
> + writel(val | SEL_DLY_RXCLK | SEL_DLY_TXCLK,
> + ax_phy->reg_base + PHY_CTRL_3);
> +
> + return 0;
> +}
> +
> +static int axiado_emmc_phy_power_on(struct phy *phy)
> +{
> + struct axiado_emmc_phy *ax_phy = phy_get_drvdata(phy);
> + struct device *dev = ax_phy->dev;
> + u32 val;
> + int ret;
> +
> + val = readl(ax_phy->reg_base + PHY_CTRL_1);
> + writel(val | RETB_ENBL, ax_phy->reg_base + PHY_CTRL_1);
> +
> + val = readl(ax_phy->reg_base + PHY_CTRL_3);
> + writel(val | PDB_ENBL, ax_phy->reg_base + PHY_CTRL_3);
> +
> + val = readl(ax_phy->reg_base + PHY_CTRL_2);
> + writel(val | OTAP_SEL(OTAP_DLY), ax_phy->reg_base + PHY_CTRL_2);
> +
> + val = readl(ax_phy->reg_base + PHY_CTRL_1);
> + writel(val | DLL_TRM(DLL_TRM_ICP), ax_phy->reg_base + PHY_CTRL_1);
> +
> + val = readl(ax_phy->reg_base + PHY_CTRL_3);
> + writel(val | DLL_FRQSEL(FRQ_SEL), ax_phy->reg_base + PHY_CTRL_3);
> +
> + ret = read_poll_timeout(readl, val, val & DLL_RDY_MASK, POLL_DELAY_US,
> + POLL_TIMEOUT_MS * 1000, false,
> + ax_phy->reg_base + STATUS);
> + if (ret) {
> + dev_err(dev, "DLL ready timeout\n");
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static const struct phy_ops axiado_emmc_phy_ops = {
> + .init = axiado_emmc_phy_init,
> + .power_on = axiado_emmc_phy_power_on,
no power_off?
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* Re: [PATCH v6 3/8] phy: Add driver for EyeQ5 Ethernet PHY wrapper
From: Vinod Koul @ 2026-02-27 14:08 UTC (permalink / raw)
To: Théo Lebrun
Cc: Vladimir Kondratiev, Grégory Clement, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Kishon Vijay Abraham I,
Michael Turquette, Stephen Boyd, Philipp Zabel,
Thomas Bogendoerfer, Neil Armstrong, linux-mips, devicetree,
linux-kernel, linux-phy, linux-clk, Benoît Monin,
Tawfik Bayouk, Thomas Petazzoni, Luca Ceresoli
In-Reply-To: <DGO5XYKELMA3.14FPOZ2FCD8NN@bootlin.com>
On 25-02-26, 16:54, Théo Lebrun wrote:
> On Wed Feb 25, 2026 at 4:00 PM CET, Vinod Koul wrote:
> > On 27-01-26, 18:09, Théo Lebrun wrote:
> >> EyeQ5 embeds a system-controller called OLB. It features many unrelated
> >> registers, and some of those are registers used to configure the
> >> integration of the RGMII/SGMII Cadence PHY used by MACB/GEM instances.
> >>
> >> Wrap in a neat generic PHY provider, exposing two PHYs with standard
> >> phy_init() / phy_set_mode() / phy_power_on() operations.
> >
> > Is there a dependency of this patch with rest of the series. If not
> > please post different series for subsystems.
>
> ACK. It felt sensible to keep patches close together to understand their
> reasoning.
> - clk patches are there because they imply we get a dev->of_node.
> Without them we don't and therefore the driver is useless.
> - DTS/MIPS patches are there because they exploit this new driver.
> They show the first users of this driver.
You can add that in cover letter for people interested to read. It is
easy for me to pick a series rather than find which patches to review
and apply
>
> Will split for next revision.
Thanks
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* Re: [PATCH v7 1/2] phy: sort Kconfig and Makefile
From: Vinod Koul @ 2026-02-27 13:55 UTC (permalink / raw)
To: Théo Lebrun
Cc: Neil Armstrong, linux-phy, linux-kernel, linux-mips,
Vladimir Kondratiev, Gregory CLEMENT, Benoît Monin,
Tawfik Bayouk, Thomas Petazzoni, Luca Ceresoli
In-Reply-To: <20260225-macb-phy-v7-1-e5211a61db56@bootlin.com>
On 25-02-26, 17:54, Théo Lebrun wrote:
> Neither Kconfig nor Makefile are sorted; reorder them.
>
> $ diff -U100 <(grep ^config drivers/phy/Kconfig) \
> <(grep ^config drivers/phy/Kconfig | sort)
>
> $ diff -U100 <(grep ^obj-\\$ drivers/phy/Makefile) \
> <(grep ^obj-\\$ drivers/phy/Makefile | sort)
>
> PHY_COMMON_PROPS{,_TEST} are kept at the top which does not respect
> sorting order.
>
> Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
> Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
> ---
> drivers/phy/Kconfig | 86 ++++++++++++++++++++++++++--------------------------
> drivers/phy/Makefile | 8 ++---
> 2 files changed, 47 insertions(+), 47 deletions(-)
>
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 02467dfd4fb0..c86e90027443 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -47,6 +47,26 @@ config GENERIC_PHY_MIPI_DPHY
> Provides a number of helpers a core functions for MIPI D-PHY
> drivers to us.
>
> +config PHY_AIROHA_PCIE
> + tristate "Airoha PCIe-PHY Driver"
> + depends on ARCH_AIROHA || COMPILE_TEST
> + depends on OF
> + select GENERIC_PHY
> + help
> + Say Y here to add support for Airoha PCIe PHY driver.
> + This driver create the basic PHY instance and provides initialize
> + callback for PCIe GEN3 port.
> +
> +config PHY_CAN_TRANSCEIVER
> + tristate "CAN transceiver PHY"
> + select GENERIC_PHY
> + select MULTIPLEXER
> + help
> + This option enables support for CAN transceivers as a PHY. This
> + driver provides function for putting the transceivers in various
> + functional modes using gpios and sets the attribute max link
> + rate, for CAN drivers.
> +
> config PHY_GOOGLE_USB
> tristate "Google Tensor SoC USB PHY driver"
> select GENERIC_PHY
> @@ -69,6 +89,17 @@ config PHY_LPC18XX_USB_OTG
> This driver is need for USB0 support on LPC18xx/43xx and takes
> care of enabling and clock setup.
>
> +config PHY_NXP_PTN3222
> + tristate "NXP PTN3222 1-port eUSB2 to USB2 redriver"
> + depends on I2C
> + depends on OF
> + select GENERIC_PHY
> + help
> + Enable this to support NXP PTN3222 1-port eUSB2 to USB2 Redriver.
> + This redriver performs translation between eUSB2 and USB2 signalling
> + schemes. It supports all three USB 2.0 data rates: Low Speed, Full
> + Speed and High Speed.
> +
> config PHY_PISTACHIO_USB
> tristate "IMG Pistachio USB2.0 PHY driver"
> depends on MIPS || COMPILE_TEST
> @@ -84,6 +115,18 @@ config PHY_SNPS_EUSB2
> Enable support for the USB high-speed SNPS eUSB2 phy on select
> SoCs. The PHY is usually paired with a Synopsys DWC3 USB controller.
>
> +config PHY_SPACEMIT_K1_PCIE
> + tristate "PCIe and combo PHY driver for the SpacemiT K1 SoC"
> + depends on ARCH_SPACEMIT || COMPILE_TEST
> + depends on COMMON_CLK
> + depends on HAS_IOMEM
> + depends on OF
> + select GENERIC_PHY
> + default ARCH_SPACEMIT
> + help
> + Enable support for the PCIe and USB 3 combo PHY and two
> + PCIe-only PHYs used in the SpacemiT K1 SoC.
I moved this into spacemit directory and while at it notice the file is
not sorted and patched that up.20260223065743.395539-1-vkoul@kernel.org
Sorry I missed this and earlier one
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* Re: [PATCH v11 5/9] phy: renesas: rcar-gen3-usb2: drop helper getting optional mux-state
From: Vinod Koul @ 2026-02-27 13:53 UTC (permalink / raw)
To: Josua Mayer
Cc: Marc Kleine-Budde, Vincent Mailhol, Neil Armstrong, Peter Rosin,
Aaro Koskinen, Andreas Kemnade, Kevin Hilman, Roger Quadros,
Tony Lindgren, Janusz Krzysztofik, Vignesh R, Andi Shyti,
Ulf Hansson, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Magnus Damm, Wolfram Sang, Yoshihiro Shimoda,
Yazan Shhady, Jon Nettleton, Vladimir Oltean, Mikhail Anikin,
linux-can, linux-phy, linux-kernel, linux-omap, linux-i2c,
linux-mmc, devicetree, linux-renesas-soc
In-Reply-To: <20260226-rz-sdio-mux-v11-5-c2a350f9bbd3@solid-run.com>
On 26-02-26, 15:21, Josua Mayer wrote:
> Multiplexer subsystem has now added helpers for getting managed optional
> mux-state.
>
> Switch to the new devm_mux_state_get_optional_selected helper.
Acked-by: Vinod Koul <vkoul@kernel.org>
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* Re: [PATCH v11 2/9] phy: renesas: rcar-gen3-usb2: rename local mux helper to avoid conflict
From: Vinod Koul @ 2026-02-27 13:52 UTC (permalink / raw)
To: Josua Mayer
Cc: Marc Kleine-Budde, Vincent Mailhol, Neil Armstrong, Peter Rosin,
Aaro Koskinen, Andreas Kemnade, Kevin Hilman, Roger Quadros,
Tony Lindgren, Janusz Krzysztofik, Vignesh R, Andi Shyti,
Ulf Hansson, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Magnus Damm, Wolfram Sang, Yoshihiro Shimoda,
Yazan Shhady, Jon Nettleton, Vladimir Oltean, Mikhail Anikin,
linux-can, linux-phy, linux-kernel, linux-omap, linux-i2c,
linux-mmc, devicetree, linux-renesas-soc
In-Reply-To: <20260226-rz-sdio-mux-v11-2-c2a350f9bbd3@solid-run.com>
On 26-02-26, 15:21, Josua Mayer wrote:
> Rename the temporary devm_mux_state_get_optional function to avoid
> conflict with upcoming implementation in multiplexer subsystem.
Acked-by: Vinod Koul <vkoul@kernel.org>
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* Re: [PATCH v11 1/9] phy: can-transceiver: rename temporary helper function to avoid conflict
From: Vinod Koul @ 2026-02-27 13:52 UTC (permalink / raw)
To: Josua Mayer
Cc: Marc Kleine-Budde, Vincent Mailhol, Neil Armstrong, Peter Rosin,
Aaro Koskinen, Andreas Kemnade, Kevin Hilman, Roger Quadros,
Tony Lindgren, Janusz Krzysztofik, Vignesh R, Andi Shyti,
Ulf Hansson, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Magnus Damm, Wolfram Sang, Yoshihiro Shimoda,
Yazan Shhady, Jon Nettleton, Vladimir Oltean, Mikhail Anikin,
linux-can, linux-phy, linux-kernel, linux-omap, linux-i2c,
linux-mmc, devicetree, linux-renesas-soc
In-Reply-To: <20260226-rz-sdio-mux-v11-1-c2a350f9bbd3@solid-run.com>
On 26-02-26, 15:21, Josua Mayer wrote:
> Rename the temporary devm_mux_state_get_optional function to avoid
> conflict with upcoming implementation in multiplexer subsystem.
Acked-by: Vinod Koul <vkoul@kernel.org>
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* Re: [PATCH net-next 0/9] net: stmmac: qcom-ethqos: further serdes reorganisation
From: Vinod Koul @ 2026-02-27 13:47 UTC (permalink / raw)
To: Russell King (Oracle)
Cc: Andrew Lunn, Alexandre Torgue, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, linux-arm-kernel, linux-arm-msm,
linux-phy, linux-stm32, Mohd Ayaan Anwar, Neil Armstrong, netdev,
Paolo Abeni
In-Reply-To: <aZ66uXCwGgH7B_A-@shell.armlinux.org.uk>
On 25-02-26, 09:02, Russell King (Oracle) wrote:
> Note: only 8 patches in this series, not 9 as the subject line says,
> as the set_clk_tx_rate() patch became part of the first series.
>
> On Wed, Feb 25, 2026 at 09:00:41AM +0000, Russell King (Oracle) wrote:
> > This is part 2 of the qcom-ethqos series, part 1 has now been merged.
> >
> > This part of the series focuses on the generic PHY driver, but these
> > changes have dependencies on the ethernet driver, hence why
> > it will need to go via net-next. Furthermore, subsequent changes
> > depend on these patches.
This lgtm, can we get signed tag so that we can pull this into phy tree
as well
Thanks
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~Vinod
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