* [PATCH v8 12/23] scsi: ufs: mediatek: Remove vendor kernel quirks cruft
From: Nicolas Frattaroli @ 2026-03-04 14:53 UTC (permalink / raw)
To: Alim Akhtar, Avri Altman, Bart Van Assche, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chunfeng Yun, Vinod Koul,
Kishon Vijay Abraham I, Peter Wang, Stanley Jhu,
James E.J. Bottomley, Martin K. Petersen, Philipp Zabel,
Liam Girdwood, Mark Brown, Chaotian Jing, Neil Armstrong
Cc: Louis-Alexis Eyraud, kernel, linux-scsi, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-phy, Nicolas Frattaroli,
Krzysztof Kozlowski
In-Reply-To: <20260304-mt8196-ufs-v8-0-5b0eac23314f@collabora.com>
Both ufs_mtk_vreg_fix_vcc and ufs_mtk_vreg_fix_vccqx look like they are
vendor kernel hacks to work around existing downstream device trees.
Mainline does not need or want them, so remove them.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Peter Wang <peter.wang@mediatek.com>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
drivers/ufs/host/ufs-mediatek.c | 69 -----------------------------------------
1 file changed, 69 deletions(-)
diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index 5f08fbbaa447..c2ece9a2e7b4 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -1017,73 +1017,6 @@ static void ufs_mtk_init_clocks(struct ufs_hba *hba)
}
}
-#define MAX_VCC_NAME 30
-static int ufs_mtk_vreg_fix_vcc(struct ufs_hba *hba)
-{
- struct ufs_vreg_info *info = &hba->vreg_info;
- struct device_node *np = hba->dev->of_node;
- struct device *dev = hba->dev;
- char vcc_name[MAX_VCC_NAME];
- struct arm_smccc_res res;
- int err, ver;
-
- if (info->vcc)
- return 0;
-
- if (of_property_read_bool(np, "mediatek,ufs-vcc-by-num")) {
- ufs_mtk_get_vcc_num(res);
- if (res.a1 > UFS_VCC_NONE && res.a1 < UFS_VCC_MAX)
- snprintf(vcc_name, MAX_VCC_NAME, "vcc-opt%lu", res.a1);
- else
- return -ENODEV;
- } else if (of_property_read_bool(np, "mediatek,ufs-vcc-by-ver")) {
- ver = (hba->dev_info.wspecversion & 0xF00) >> 8;
- snprintf(vcc_name, MAX_VCC_NAME, "vcc-ufs%u", ver);
- } else {
- return 0;
- }
-
- err = ufshcd_populate_vreg(dev, vcc_name, &info->vcc, false);
- if (err)
- return err;
-
- err = ufshcd_get_vreg(dev, info->vcc);
- if (err)
- return err;
-
- err = regulator_enable(info->vcc->reg);
- if (!err) {
- info->vcc->enabled = true;
- dev_info(dev, "%s: %s enabled\n", __func__, vcc_name);
- }
-
- return err;
-}
-
-static void ufs_mtk_vreg_fix_vccqx(struct ufs_hba *hba)
-{
- struct ufs_vreg_info *info = &hba->vreg_info;
- struct ufs_vreg **vreg_on, **vreg_off;
-
- if (hba->dev_info.wspecversion >= 0x0300) {
- vreg_on = &info->vccq;
- vreg_off = &info->vccq2;
- } else {
- vreg_on = &info->vccq2;
- vreg_off = &info->vccq;
- }
-
- if (*vreg_on)
- (*vreg_on)->always_on = true;
-
- if (*vreg_off) {
- regulator_disable((*vreg_off)->reg);
- devm_kfree(hba->dev, (*vreg_off)->name);
- devm_kfree(hba->dev, *vreg_off);
- *vreg_off = NULL;
- }
-}
-
static void ufs_mtk_setup_clk_gating(struct ufs_hba *hba)
{
unsigned long flags;
@@ -1981,8 +1914,6 @@ static void ufs_mtk_fixup_dev_quirks(struct ufs_hba *hba)
hba->dev_quirks &= ~UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM;
}
- ufs_mtk_vreg_fix_vcc(hba);
- ufs_mtk_vreg_fix_vccqx(hba);
ufs_mtk_fix_ahit(hba);
ufs_mtk_fix_clock_scaling(hba);
}
--
2.53.0
--
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^ permalink raw reply related
* [PATCH v8 13/23] scsi: ufs: mediatek: Use the common PHY framework
From: Nicolas Frattaroli @ 2026-03-04 14:53 UTC (permalink / raw)
To: Alim Akhtar, Avri Altman, Bart Van Assche, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chunfeng Yun, Vinod Koul,
Kishon Vijay Abraham I, Peter Wang, Stanley Jhu,
James E.J. Bottomley, Martin K. Petersen, Philipp Zabel,
Liam Girdwood, Mark Brown, Chaotian Jing, Neil Armstrong
Cc: Louis-Alexis Eyraud, kernel, linux-scsi, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-phy, Nicolas Frattaroli
In-Reply-To: <20260304-mt8196-ufs-v8-0-5b0eac23314f@collabora.com>
There is no need to reinvent the PHY framework, especially not its OF
parsing.
Change the code to simply use the PHY framework to acquire the device's
PHY in the ufshcd init, so that it's device linked to the right device.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
drivers/ufs/host/ufs-mediatek.c | 135 +++++++++++++---------------------------
drivers/ufs/host/ufs-mediatek.h | 1 -
2 files changed, 42 insertions(+), 94 deletions(-)
diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index c2ece9a2e7b4..e7948fad2e39 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -293,44 +293,6 @@ static int ufs_mtk_hce_enable_notify(struct ufs_hba *hba,
return 0;
}
-static int ufs_mtk_bind_mphy(struct ufs_hba *hba)
-{
- struct ufs_mtk_host *host = ufshcd_get_variant(hba);
- struct device *dev = hba->dev;
- struct device_node *np = dev->of_node;
- int err = 0;
-
- host->mphy = devm_of_phy_get_by_index(dev, np, 0);
-
- if (host->mphy == ERR_PTR(-EPROBE_DEFER)) {
- /*
- * UFS driver might be probed before the phy driver does.
- * In that case we would like to return EPROBE_DEFER code.
- */
- err = -EPROBE_DEFER;
- dev_info(dev,
- "%s: required phy hasn't probed yet. err = %d\n",
- __func__, err);
- } else if (IS_ERR(host->mphy)) {
- err = PTR_ERR(host->mphy);
- if (err != -ENODEV) {
- dev_info(dev, "%s: PHY get failed %d\n", __func__,
- err);
- }
- }
-
- if (err)
- host->mphy = NULL;
- /*
- * Allow unbound mphy because not every platform needs specific
- * mphy control.
- */
- if (err == -ENODEV)
- err = 0;
-
- return err;
-}
-
static int ufs_mtk_setup_ref_clk(struct ufs_hba *hba, bool on)
{
struct ufs_mtk_host *host = ufshcd_get_variant(hba);
@@ -1185,13 +1147,21 @@ static int ufs_mtk_init(struct ufs_hba *hba)
ufs_mtk_init_mcq_irq(hba);
- err = ufs_mtk_bind_mphy(hba);
- if (err)
+ host->mphy = devm_phy_get(dev, NULL);
+ if (IS_ERR(host->mphy)) {
+ err = dev_err_probe(dev, PTR_ERR(host->mphy), "Failed to get PHY\n");
+ goto out_variant_clear;
+ }
+
+ err = phy_init(host->mphy);
+ if (err) {
+ dev_err_probe(dev, err, "Failed to initialize PHY\n");
goto out_variant_clear;
+ }
err = ufs_mtk_init_reset(hba);
if (err)
- goto out_variant_clear;
+ goto out_phy_exit;
/* Enable runtime autosuspend */
hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND;
@@ -1230,7 +1200,7 @@ static int ufs_mtk_init(struct ufs_hba *hba)
err = ufs_mtk_get_supplies(host);
if (err)
- goto out_variant_clear;
+ goto out_phy_exit;
/*
* ufshcd_vops_init() is invoked after
@@ -1255,11 +1225,22 @@ static int ufs_mtk_init(struct ufs_hba *hba)
return 0;
+out_phy_exit:
+ phy_exit(host->mphy);
out_variant_clear:
ufshcd_set_variant(hba, NULL);
return err;
}
+static void ufs_mtk_exit(struct ufs_hba *hba)
+{
+ struct ufs_mtk_host *host = ufshcd_get_variant(hba);
+
+ ufs_mtk_mphy_power_on(hba, false);
+
+ phy_exit(host->mphy);
+}
+
static bool ufs_mtk_pmc_via_fastauto(struct ufs_hba *hba,
struct ufs_pa_layer_attr *dev_req_params)
{
@@ -2255,6 +2236,7 @@ static const struct ufs_hba_variant_ops ufs_hba_mtk_vops = {
.name = "mediatek.ufshci",
.max_num_rtt = MTK_MAX_NUM_RTT,
.init = ufs_mtk_init,
+ .exit = ufs_mtk_exit,
.get_ufs_hci_version = ufs_mtk_get_ufs_hci_version,
.setup_clocks = ufs_mtk_setup_clocks,
.hce_enable_notify = ufs_mtk_hce_enable_notify,
@@ -2313,48 +2295,15 @@ MODULE_DEVICE_TABLE(of, ufs_mtk_of_match);
*/
static int ufs_mtk_probe(struct platform_device *pdev)
{
- int err;
- struct ufs_hba *hba;
- struct platform_device *phy_pdev = NULL;
struct device *dev = &pdev->dev;
- struct device_node *phy_node = NULL;
- struct ufs_mtk_host *host;
-
- /* find phy node */
- phy_node = of_parse_phandle(dev->of_node, "phys", 0);
-
- if (phy_node) {
- phy_pdev = of_find_device_by_node(phy_node);
- if (!phy_pdev)
- goto skip_phy;
- phy_dev = &phy_pdev->dev;
-
- pm_runtime_set_active(phy_dev);
- pm_runtime_enable(phy_dev);
- pm_runtime_get_sync(phy_dev);
-
- put_device(phy_dev);
- dev_info(dev, "phys node found\n");
- } else {
- dev_notice(dev, "phys node not found\n");
- }
+ struct ufs_hba *hba;
+ int ret;
-skip_phy:
- /* perform generic probe */
- err = ufshcd_pltfrm_init(pdev, &ufs_hba_mtk_vops);
- if (err) {
- dev_err(dev, "probe failed %d\n", err);
- goto out;
- }
+ ret = ufshcd_pltfrm_init(pdev, &ufs_hba_mtk_vops);
+ if (ret)
+ return dev_err_probe(dev, ret, "Generic platform probe failed\n");
hba = platform_get_drvdata(pdev);
- if (!hba)
- goto out;
-
- if (phy_node && phy_dev) {
- host = ufshcd_get_variant(hba);
- host->phy_dev = phy_dev;
- }
/*
* Because the default power setting of VSx (the upper layer of
@@ -2363,17 +2312,12 @@ static int ufs_mtk_probe(struct platform_device *pdev)
*/
ufs_mtk_dev_vreg_set_lpm(hba, false);
-out:
- of_node_put(phy_node);
- of_node_put(reset_node);
- return err;
+ return 0;
}
/**
* ufs_mtk_remove - set driver_data of the device to NULL
* @pdev: pointer to platform device handle
- *
- * Always return 0
*/
static void ufs_mtk_remove(struct platform_device *pdev)
{
@@ -2430,9 +2374,8 @@ static int ufs_mtk_system_resume(struct device *dev)
static int ufs_mtk_runtime_suspend(struct device *dev)
{
struct ufs_hba *hba = dev_get_drvdata(dev);
- struct ufs_mtk_host *host = ufshcd_get_variant(hba);
struct arm_smccc_res res;
- int ret = 0;
+ int ret;
ret = ufshcd_runtime_suspend(dev);
if (ret)
@@ -2443,8 +2386,11 @@ static int ufs_mtk_runtime_suspend(struct device *dev)
if (ufs_mtk_is_rtff_mtcmos(hba))
ufs_mtk_mtcmos_ctrl(false, res);
- if (host->phy_dev)
- pm_runtime_put_sync(host->phy_dev);
+ ret = ufs_mtk_mphy_power_on(hba, false);
+ if (ret) {
+ dev_err(dev, "Failed to power off PHY: %pe\n", ERR_PTR(ret));
+ return ret;
+ }
return 0;
}
@@ -2452,14 +2398,17 @@ static int ufs_mtk_runtime_suspend(struct device *dev)
static int ufs_mtk_runtime_resume(struct device *dev)
{
struct ufs_hba *hba = dev_get_drvdata(dev);
- struct ufs_mtk_host *host = ufshcd_get_variant(hba);
struct arm_smccc_res res;
+ int ret;
if (ufs_mtk_is_rtff_mtcmos(hba))
ufs_mtk_mtcmos_ctrl(true, res);
- if (host->phy_dev)
- pm_runtime_get_sync(host->phy_dev);
+ ret = ufs_mtk_mphy_power_on(hba, true);
+ if (ret) {
+ dev_err(dev, "Failed to power on PHY: %pe\n", ERR_PTR(ret));
+ return ret;
+ }
ufs_mtk_dev_vreg_set_lpm(hba, false);
diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediatek.h
index 24c8941f6b86..4e6a34f4ac39 100644
--- a/drivers/ufs/host/ufs-mediatek.h
+++ b/drivers/ufs/host/ufs-mediatek.h
@@ -195,7 +195,6 @@ struct ufs_mtk_host {
bool is_mcq_intr_enabled;
int mcq_nr_intr;
struct ufs_mtk_mcq_intr_info mcq_intr_info[UFSHCD_MAX_Q_NR];
- struct device *phy_dev;
};
/* MTK delay of autosuspend: 500 ms */
--
2.53.0
--
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^ permalink raw reply related
* [PATCH v8 10/23] scsi: ufs: mediatek: Handle misc host voltage regulators
From: Nicolas Frattaroli @ 2026-03-04 14:53 UTC (permalink / raw)
To: Alim Akhtar, Avri Altman, Bart Van Assche, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chunfeng Yun, Vinod Koul,
Kishon Vijay Abraham I, Peter Wang, Stanley Jhu,
James E.J. Bottomley, Martin K. Petersen, Philipp Zabel,
Liam Girdwood, Mark Brown, Chaotian Jing, Neil Armstrong
Cc: Louis-Alexis Eyraud, kernel, linux-scsi, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-phy, Nicolas Frattaroli
In-Reply-To: <20260304-mt8196-ufs-v8-0-5b0eac23314f@collabora.com>
MediaTek SoCs handled by this driver contain a per-SoC specific set of
miscellaneous supplies. These feed parts of the UFS controller silicon
inside the SoC, as opposed to the UFS card.
Add the necessary driver code to acquire these supplies using the
regulator bulk API. They should be kept on during suspend, so enable
them when acquiring.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Peter Wang <peter.wang@mediatek.com>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
drivers/ufs/host/ufs-mediatek.c | 37 ++++++++++++++++++++++++++++++++++---
1 file changed, 34 insertions(+), 3 deletions(-)
diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index 9b7d7e4ba4ba..3282b2d2d498 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -40,6 +40,8 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba, bool scale_up);
struct ufs_mtk_soc_data {
bool has_avdd09;
+ u8 num_reg_names;
+ const char *const *reg_names;
};
static const struct ufs_dev_quirk ufs_mtk_dev_fixups[] = {
@@ -1188,8 +1190,21 @@ static int ufs_mtk_get_supplies(struct ufs_mtk_host *host)
{
struct device *dev = host->hba->dev;
const struct ufs_mtk_soc_data *data = of_device_get_match_data(dev);
+ int ret;
+
+ if (!data)
+ return 0;
+
+ if (data->num_reg_names) {
+ ret = devm_regulator_bulk_get_enable(dev, data->num_reg_names,
+ data->reg_names);
+ if (ret) {
+ dev_err(dev, "Failed to get misc regulators: %pe\n", ERR_PTR(ret));
+ return ret;
+ }
+ }
- if (!data || !data->has_avdd09)
+ if (!data->has_avdd09)
return 0;
host->reg_avdd09 = devm_regulator_get_optional(dev, "avdd09");
@@ -2331,14 +2346,30 @@ static const struct ufs_hba_variant_ops ufs_hba_mtk_vops = {
.config_scsi_dev = ufs_mtk_config_scsi_dev,
};
+static const char *const ufs_mtk_regs_avdd12_avdd18[] = {
+ "avdd12", "avdd18"
+};
+
+static const char *const ufs_mtk_regs_avdd12_ckbuf_avdd18[] = {
+ "avdd12", "avdd12-ckbuf", "avdd18"
+};
+
static const struct ufs_mtk_soc_data mt8183_data = {
.has_avdd09 = true,
+ .reg_names = ufs_mtk_regs_avdd12_avdd18,
+ .num_reg_names = ARRAY_SIZE(ufs_mtk_regs_avdd12_avdd18),
+};
+
+static const struct ufs_mtk_soc_data mt8192_8195_data = {
+ .has_avdd09 = false,
+ .reg_names = ufs_mtk_regs_avdd12_ckbuf_avdd18,
+ .num_reg_names = ARRAY_SIZE(ufs_mtk_regs_avdd12_ckbuf_avdd18),
};
static const struct of_device_id ufs_mtk_of_match[] = {
{ .compatible = "mediatek,mt8183-ufshci", .data = &mt8183_data },
- { .compatible = "mediatek,mt8192-ufshci" },
- { .compatible = "mediatek,mt8195-ufshci" },
+ { .compatible = "mediatek,mt8192-ufshci", .data = &mt8192_8195_data },
+ { .compatible = "mediatek,mt8195-ufshci", .data = &mt8192_8195_data },
{},
};
MODULE_DEVICE_TABLE(of, ufs_mtk_of_match);
--
2.53.0
--
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^ permalink raw reply related
* [PATCH v8 11/23] scsi: ufs: mediatek: Remove undocumented downstream reset cruft
From: Nicolas Frattaroli @ 2026-03-04 14:53 UTC (permalink / raw)
To: Alim Akhtar, Avri Altman, Bart Van Assche, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chunfeng Yun, Vinod Koul,
Kishon Vijay Abraham I, Peter Wang, Stanley Jhu,
James E.J. Bottomley, Martin K. Petersen, Philipp Zabel,
Liam Girdwood, Mark Brown, Chaotian Jing, Neil Armstrong
Cc: Louis-Alexis Eyraud, kernel, linux-scsi, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-phy, Nicolas Frattaroli
In-Reply-To: <20260304-mt8196-ufs-v8-0-5b0eac23314f@collabora.com>
The MediaTek UFS host driver's probe function allows using a
ti,syscon-reset as a reset, without going through the appropriate
abstractions, or by documenting this in the binding at all.
Remove this, it's downstream code and does not belong here.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
drivers/ufs/host/ufs-mediatek.c | 32 +++-----------------------------
1 file changed, 3 insertions(+), 29 deletions(-)
diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index 3282b2d2d498..5f08fbbaa447 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -2383,38 +2383,12 @@ MODULE_DEVICE_TABLE(of, ufs_mtk_of_match);
static int ufs_mtk_probe(struct platform_device *pdev)
{
int err;
- struct device *dev = &pdev->dev, *phy_dev = NULL;
- struct device_node *reset_node, *phy_node = NULL;
- struct platform_device *reset_pdev, *phy_pdev = NULL;
- struct device_link *link;
struct ufs_hba *hba;
+ struct platform_device *phy_pdev = NULL;
+ struct device *dev = &pdev->dev;
+ struct device_node *phy_node = NULL;
struct ufs_mtk_host *host;
- reset_node = of_find_compatible_node(NULL, NULL,
- "ti,syscon-reset");
- if (!reset_node) {
- dev_notice(dev, "find ti,syscon-reset fail\n");
- goto skip_reset;
- }
- reset_pdev = of_find_device_by_node(reset_node);
- if (!reset_pdev) {
- dev_notice(dev, "find reset_pdev fail\n");
- goto skip_reset;
- }
- link = device_link_add(dev, &reset_pdev->dev,
- DL_FLAG_AUTOPROBE_CONSUMER);
- put_device(&reset_pdev->dev);
- if (!link) {
- dev_notice(dev, "add reset device_link fail\n");
- goto skip_reset;
- }
- /* supplier is not probed */
- if (link->status == DL_STATE_DORMANT) {
- err = -EPROBE_DEFER;
- goto out;
- }
-
-skip_reset:
/* find phy node */
phy_node = of_parse_phandle(dev->of_node, "phys", 0);
--
2.53.0
--
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^ permalink raw reply related
* [PATCH v8 09/23] scsi: ufs: mediatek: Rework the crypt-boost stuff
From: Nicolas Frattaroli @ 2026-03-04 14:53 UTC (permalink / raw)
To: Alim Akhtar, Avri Altman, Bart Van Assche, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chunfeng Yun, Vinod Koul,
Kishon Vijay Abraham I, Peter Wang, Stanley Jhu,
James E.J. Bottomley, Martin K. Petersen, Philipp Zabel,
Liam Girdwood, Mark Brown, Chaotian Jing, Neil Armstrong
Cc: Louis-Alexis Eyraud, kernel, linux-scsi, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-phy, Nicolas Frattaroli
In-Reply-To: <20260304-mt8196-ufs-v8-0-5b0eac23314f@collabora.com>
I don't know whether the crypt-boost functionality as it is currently
implemented is even appropriate for mainline. It might be better done in
some generic way. But what I do know is that I can rework the code to
make it less obtuse.
Prefix the boost stuff with the appropriate vendor prefix, remove the
pointless clock wrappers, and rework the function.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Peter Wang (王信友) <peter.wang@mediatek.com>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
drivers/ufs/host/ufs-mediatek.c | 89 ++++++++++++++---------------------------
1 file changed, 30 insertions(+), 59 deletions(-)
diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index 392383e03ab0..9b7d7e4ba4ba 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -562,21 +562,6 @@ static int ufs_mtk_mphy_power_on(struct ufs_hba *hba, bool on)
return 0;
}
-static int ufs_mtk_get_host_clk(struct device *dev, const char *name,
- struct clk **clk_out)
-{
- struct clk *clk;
- int err = 0;
-
- clk = devm_clk_get(dev, name);
- if (IS_ERR(clk))
- err = PTR_ERR(clk);
- else
- *clk_out = clk;
-
- return err;
-}
-
static void ufs_mtk_boost_crypt(struct ufs_hba *hba, bool boost)
{
struct ufs_mtk_host *host = ufshcd_get_variant(hba);
@@ -633,65 +618,51 @@ static void ufs_mtk_boost_crypt(struct ufs_hba *hba, bool boost)
clk_disable_unprepare(cfg->clk_crypt_mux);
}
-static int ufs_mtk_init_host_clk(struct ufs_hba *hba, const char *name,
- struct clk **clk)
-{
- int ret;
-
- ret = ufs_mtk_get_host_clk(hba->dev, name, clk);
- if (ret) {
- dev_info(hba->dev, "%s: failed to get %s: %d", __func__,
- name, ret);
- }
-
- return ret;
-}
-
static void ufs_mtk_init_boost_crypt(struct ufs_hba *hba)
{
struct ufs_mtk_host *host = ufshcd_get_variant(hba);
struct ufs_mtk_crypt_cfg *cfg;
struct device *dev = hba->dev;
- struct regulator *reg;
- u32 volt;
+ int ret;
- host->crypt = devm_kzalloc(dev, sizeof(*(host->crypt)),
- GFP_KERNEL);
- if (!host->crypt)
- goto disable_caps;
+ cfg = devm_kzalloc(dev, sizeof(*cfg), GFP_KERNEL);
+ if (!cfg)
+ return;
- reg = devm_regulator_get_optional(dev, "dvfsrc-vcore");
- if (IS_ERR(reg)) {
- dev_info(dev, "failed to get dvfsrc-vcore: %ld",
- PTR_ERR(reg));
- goto disable_caps;
+ cfg->reg_vcore = devm_regulator_get_optional(dev, "dvfsrc-vcore");
+ if (IS_ERR(cfg->reg_vcore)) {
+ dev_err(dev, "Failed to get dvfsrc-vcore: %pe", cfg->reg_vcore);
+ return;
}
- if (of_property_read_u32(dev->of_node, "boost-crypt-vcore-min",
- &volt)) {
- dev_info(dev, "failed to get boost-crypt-vcore-min");
- goto disable_caps;
+ ret = of_property_read_u32(dev->of_node, "mediatek,boost-crypt-vcore-min",
+ &cfg->vcore_volt);
+ if (ret) {
+ dev_err(dev, "Failed to get mediatek,boost-crypt-vcore-min: %pe\n",
+ ERR_PTR(ret));
+ return;
}
- cfg = host->crypt;
- if (ufs_mtk_init_host_clk(hba, "crypt_mux",
- &cfg->clk_crypt_mux))
- goto disable_caps;
+ cfg->clk_crypt_mux = devm_clk_get(dev, "crypt_mux");
+ if (IS_ERR(cfg->clk_crypt_mux)) {
+ dev_err(dev, "Failed to get clock crypt_mux: %pe\n", cfg->clk_crypt_mux);
+ return;
+ }
- if (ufs_mtk_init_host_clk(hba, "crypt_lp",
- &cfg->clk_crypt_lp))
- goto disable_caps;
+ cfg->clk_crypt_lp = devm_clk_get(dev, "crypt_lp");
+ if (IS_ERR(cfg->clk_crypt_lp)) {
+ dev_err(dev, "Failed to get clock crypt_lp: %pe\n", cfg->clk_crypt_lp);
+ return;
+ }
- if (ufs_mtk_init_host_clk(hba, "crypt_perf",
- &cfg->clk_crypt_perf))
- goto disable_caps;
+ cfg->clk_crypt_perf = devm_clk_get(dev, "crypt_perf");
+ if (IS_ERR(cfg->clk_crypt_perf)) {
+ dev_err(dev, "Failed to get clock crypt_perf: %pe\n", cfg->clk_crypt_perf);
+ return;
+ }
- cfg->reg_vcore = reg;
- cfg->vcore_volt = volt;
+ host->crypt = cfg;
host->caps |= UFS_MTK_CAP_BOOST_CRYPT_ENGINE;
-
-disable_caps:
- return;
}
static void ufs_mtk_init_host_caps(struct ufs_hba *hba)
--
2.53.0
--
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linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH v8 08/23] scsi: ufs: mediatek: Rework init function
From: Nicolas Frattaroli @ 2026-03-04 14:53 UTC (permalink / raw)
To: Alim Akhtar, Avri Altman, Bart Van Assche, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chunfeng Yun, Vinod Koul,
Kishon Vijay Abraham I, Peter Wang, Stanley Jhu,
James E.J. Bottomley, Martin K. Petersen, Philipp Zabel,
Liam Girdwood, Mark Brown, Chaotian Jing, Neil Armstrong
Cc: Louis-Alexis Eyraud, kernel, linux-scsi, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-phy, Nicolas Frattaroli
In-Reply-To: <20260304-mt8196-ufs-v8-0-5b0eac23314f@collabora.com>
Printing an error message on ENOMEM is pointless. The print will not
work because there is no memory.
Adding an of_match_device to the init function is pointless. Why would a
different device with a different probe function ever use the same init
function? Get rid of it.
zero-initialising an error variable just so you can then goto a bare
return statement with that error variable to signal success is also
pointless, just return directly, there's no unwind being done.
Reviewed-by: Peter Wang <peter.wang@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
drivers/ufs/host/ufs-mediatek.c | 19 ++++---------------
1 file changed, 4 insertions(+), 15 deletions(-)
diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index 0d22ac4c925c..392383e03ab0 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -1248,29 +1248,19 @@ static int ufs_mtk_get_supplies(struct ufs_mtk_host *host)
*/
static int ufs_mtk_init(struct ufs_hba *hba)
{
- const struct of_device_id *id;
struct device *dev = hba->dev;
struct ufs_mtk_host *host;
struct Scsi_Host *shost = hba->host;
- int err = 0;
+ int err;
struct arm_smccc_res res;
host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
- if (!host) {
- err = -ENOMEM;
- dev_info(dev, "%s: no memory for mtk ufs host\n", __func__);
- goto out;
- }
+ if (!host)
+ return -ENOMEM;
host->hba = hba;
ufshcd_set_variant(hba, host);
- id = of_match_device(ufs_mtk_of_match, dev);
- if (!id) {
- err = -EINVAL;
- goto out;
- }
-
/* Initialize host capability */
ufs_mtk_init_host_caps(hba);
@@ -1344,11 +1334,10 @@ static int ufs_mtk_init(struct ufs_hba *hba)
ufs_mtk_get_hw_ip_version(hba);
- goto out;
+ return 0;
out_variant_clear:
ufshcd_set_variant(hba, NULL);
-out:
return err;
}
--
2.53.0
--
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linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH v8 07/23] scsi: ufs: mediatek: Rework 0.9V regulator
From: Nicolas Frattaroli @ 2026-03-04 14:53 UTC (permalink / raw)
To: Alim Akhtar, Avri Altman, Bart Van Assche, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chunfeng Yun, Vinod Koul,
Kishon Vijay Abraham I, Peter Wang, Stanley Jhu,
James E.J. Bottomley, Martin K. Petersen, Philipp Zabel,
Liam Girdwood, Mark Brown, Chaotian Jing, Neil Armstrong
Cc: Louis-Alexis Eyraud, kernel, linux-scsi, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-phy, Nicolas Frattaroli
In-Reply-To: <20260304-mt8196-ufs-v8-0-5b0eac23314f@collabora.com>
The mediatek UFS host driver does some pretty bad stuff with regards to
the 0.9V regulator. Instead of just checking for the presence of the
regulator, it adds a cap if it's there, and then checks for the cap. It
also sleeps to stabilise the supply after enabling the regulator, which
is something that should be done by the regulator framework with the
appropriate delay properties in the DTS instead of random sleeps in the
driver code.
Rework this code and rename it to the avdd09 name I've chosen in the
binding for this supply name, instead of the downstream "va09" name that
isn't used by the datasheets for any of these chips.
Reviewed-by: Peter Wang <peter.wang@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
drivers/ufs/host/ufs-mediatek.c | 153 ++++++++++++++++++++++++++--------------
drivers/ufs/host/ufs-mediatek.h | 3 +-
2 files changed, 101 insertions(+), 55 deletions(-)
diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index 206794ce46c8..0d22ac4c925c 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -38,6 +38,10 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba, bool scale_up);
#define MAX_SUPP_MAC 64
#define MCQ_QUEUE_OFFSET(c) ((((c) >> 16) & 0xFF) * 0x200)
+struct ufs_mtk_soc_data {
+ bool has_avdd09;
+};
+
static const struct ufs_dev_quirk ufs_mtk_dev_fixups[] = {
{ .wmanufacturerid = UFS_ANY_VENDOR,
.model = UFS_ANY_MODEL,
@@ -48,13 +52,6 @@ static const struct ufs_dev_quirk ufs_mtk_dev_fixups[] = {
{}
};
-static const struct of_device_id ufs_mtk_of_match[] = {
- { .compatible = "mediatek,mt8183-ufshci" },
- { .compatible = "mediatek,mt8195-ufshci" },
- {},
-};
-MODULE_DEVICE_TABLE(of, ufs_mtk_of_match);
-
/*
* Details of UIC Errors
*/
@@ -106,13 +103,6 @@ static bool ufs_mtk_is_boost_crypt_enabled(struct ufs_hba *hba)
return host->caps & UFS_MTK_CAP_BOOST_CRYPT_ENGINE;
}
-static bool ufs_mtk_is_va09_supported(struct ufs_hba *hba)
-{
- struct ufs_mtk_host *host = ufshcd_get_variant(hba);
-
- return host->caps & UFS_MTK_CAP_VA09_PWR_CTRL;
-}
-
static bool ufs_mtk_is_broken_vcc(struct ufs_hba *hba)
{
struct ufs_mtk_host *host = ufshcd_get_variant(hba);
@@ -506,44 +496,70 @@ static int ufs_mtk_wait_link_state(struct ufs_hba *hba, u32 state,
return -ETIMEDOUT;
}
+static int ufs_mtk_09v_off(struct ufs_mtk_host *host)
+{
+ struct arm_smccc_res res;
+ int ret;
+
+ if (!host->reg_avdd09)
+ return 0;
+
+ ufs_mtk_va09_pwr_ctrl(res, 0);
+ ret = regulator_disable(host->reg_avdd09);
+ if (ret) {
+ dev_err(host->hba->dev, "Failed to disable avdd09-supply: %pe\n",
+ ERR_PTR(ret));
+ ufs_mtk_va09_pwr_ctrl(res, 1);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int ufs_mtk_09v_on(struct ufs_mtk_host *host)
+{
+ struct arm_smccc_res res;
+ int ret;
+
+ if (!host->reg_avdd09)
+ return 0;
+
+ ret = regulator_enable(host->reg_avdd09);
+ if (ret) {
+ dev_err(host->hba->dev, "Failed to enable avdd09-supply: %pe\n",
+ ERR_PTR(ret));
+ return ret;
+ }
+
+ ufs_mtk_va09_pwr_ctrl(res, 1);
+
+ return 0;
+}
+
static int ufs_mtk_mphy_power_on(struct ufs_hba *hba, bool on)
{
struct ufs_mtk_host *host = ufshcd_get_variant(hba);
struct phy *mphy = host->mphy;
- struct arm_smccc_res res;
- int ret = 0;
+ int ret;
- if (!mphy || !(on ^ host->mphy_powered_on))
+ if (!mphy || on == host->mphy_powered_on)
return 0;
if (on) {
- if (ufs_mtk_is_va09_supported(hba)) {
- ret = regulator_enable(host->reg_va09);
- if (ret < 0)
- goto out;
- /* wait 200 us to stablize VA09 */
- usleep_range(200, 210);
- ufs_mtk_va09_pwr_ctrl(res, 1);
- }
+ ret = ufs_mtk_09v_on(host);
+ if (ret)
+ return ret;
phy_power_on(mphy);
} else {
phy_power_off(mphy);
- if (ufs_mtk_is_va09_supported(hba)) {
- ufs_mtk_va09_pwr_ctrl(res, 0);
- ret = regulator_disable(host->reg_va09);
- }
- }
-out:
- if (ret) {
- dev_info(hba->dev,
- "failed to %s va09: %d\n",
- on ? "enable" : "disable",
- ret);
- } else {
- host->mphy_powered_on = on;
+ ret = ufs_mtk_09v_off(host);
+ if (ret)
+ return ret;
}
- return ret;
+ host->mphy_powered_on = on;
+
+ return 0;
}
static int ufs_mtk_get_host_clk(struct device *dev, const char *name,
@@ -678,17 +694,6 @@ static void ufs_mtk_init_boost_crypt(struct ufs_hba *hba)
return;
}
-static void ufs_mtk_init_va09_pwr_ctrl(struct ufs_hba *hba)
-{
- struct ufs_mtk_host *host = ufshcd_get_variant(hba);
-
- host->reg_va09 = regulator_get(hba->dev, "va09");
- if (IS_ERR(host->reg_va09))
- dev_info(hba->dev, "failed to get va09");
- else
- host->caps |= UFS_MTK_CAP_VA09_PWR_CTRL;
-}
-
static void ufs_mtk_init_host_caps(struct ufs_hba *hba)
{
struct ufs_mtk_host *host = ufshcd_get_variant(hba);
@@ -697,9 +702,6 @@ static void ufs_mtk_init_host_caps(struct ufs_hba *hba)
if (of_property_read_bool(np, "mediatek,ufs-boost-crypt"))
ufs_mtk_init_boost_crypt(hba);
- if (of_property_read_bool(np, "mediatek,ufs-support-va09"))
- ufs_mtk_init_va09_pwr_ctrl(hba);
-
if (of_property_read_bool(np, "mediatek,ufs-disable-ah8"))
host->caps |= UFS_MTK_CAP_DISABLE_AH8;
@@ -1205,6 +1207,35 @@ static void ufs_mtk_init_mcq_irq(struct ufs_hba *hba)
host->mcq_nr_intr = 0;
}
+/**
+ * ufs_mtk_get_supplies - acquire variant-specific supplies
+ * @host: pointer to driver's private &struct ufs_mtk_host instance
+ *
+ * Returns 0 on success, negative errno on error.
+ */
+static int ufs_mtk_get_supplies(struct ufs_mtk_host *host)
+{
+ struct device *dev = host->hba->dev;
+ const struct ufs_mtk_soc_data *data = of_device_get_match_data(dev);
+
+ if (!data || !data->has_avdd09)
+ return 0;
+
+ host->reg_avdd09 = devm_regulator_get_optional(dev, "avdd09");
+ if (IS_ERR(host->reg_avdd09)) {
+ if (PTR_ERR(host->reg_avdd09) == -ENODEV) {
+ host->reg_avdd09 = NULL;
+ return 0;
+ }
+
+ dev_err(dev, "Failed to get avdd09 regulator: %pe\n",
+ host->reg_avdd09);
+ return PTR_ERR(host->reg_avdd09);
+ }
+
+ return 0;
+}
+
/**
* ufs_mtk_init - find other essential mmio bases
* @hba: host controller instance
@@ -1288,6 +1319,10 @@ static int ufs_mtk_init(struct ufs_hba *hba)
ufs_mtk_init_clocks(hba);
+ err = ufs_mtk_get_supplies(host);
+ if (err)
+ goto out_variant_clear;
+
/*
* ufshcd_vops_init() is invoked after
* ufshcd_setup_clock(true) in ufshcd_hba_init() thus
@@ -2336,6 +2371,18 @@ static const struct ufs_hba_variant_ops ufs_hba_mtk_vops = {
.config_scsi_dev = ufs_mtk_config_scsi_dev,
};
+static const struct ufs_mtk_soc_data mt8183_data = {
+ .has_avdd09 = true,
+};
+
+static const struct of_device_id ufs_mtk_of_match[] = {
+ { .compatible = "mediatek,mt8183-ufshci", .data = &mt8183_data },
+ { .compatible = "mediatek,mt8192-ufshci" },
+ { .compatible = "mediatek,mt8195-ufshci" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, ufs_mtk_of_match);
+
/**
* ufs_mtk_probe - probe routine of the driver
* @pdev: pointer to Platform device handle
diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediatek.h
index 4fce29d131d1..24c8941f6b86 100644
--- a/drivers/ufs/host/ufs-mediatek.h
+++ b/drivers/ufs/host/ufs-mediatek.h
@@ -125,7 +125,6 @@ enum {
*/
enum ufs_mtk_host_caps {
UFS_MTK_CAP_BOOST_CRYPT_ENGINE = 1 << 0,
- UFS_MTK_CAP_VA09_PWR_CTRL = 1 << 1,
UFS_MTK_CAP_DISABLE_AH8 = 1 << 2,
UFS_MTK_CAP_BROKEN_VCC = 1 << 3,
@@ -176,7 +175,7 @@ struct ufs_mtk_mcq_intr_info {
struct ufs_mtk_host {
struct phy *mphy;
- struct regulator *reg_va09;
+ struct regulator *reg_avdd09;
struct reset_control_bulk_data resets[MTK_UFS_NUM_RESETS];
struct ufs_hba *hba;
struct ufs_mtk_crypt_cfg *crypt;
--
2.53.0
--
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^ permalink raw reply related
* [PATCH v8 06/23] scsi: ufs: mediatek: Rework resets
From: Nicolas Frattaroli @ 2026-03-04 14:53 UTC (permalink / raw)
To: Alim Akhtar, Avri Altman, Bart Van Assche, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chunfeng Yun, Vinod Koul,
Kishon Vijay Abraham I, Peter Wang, Stanley Jhu,
James E.J. Bottomley, Martin K. Petersen, Philipp Zabel,
Liam Girdwood, Mark Brown, Chaotian Jing, Neil Armstrong
Cc: Louis-Alexis Eyraud, kernel, linux-scsi, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-phy, Nicolas Frattaroli
In-Reply-To: <20260304-mt8196-ufs-v8-0-5b0eac23314f@collabora.com>
Rework the reset control getting in the driver's probe function to use
the bulk reset APIs. Use the optional variant instead of defaulting to
NULL if the resets fail, so that absent resets can be distinguished from
erroneous resets.
Also remove all remnants of the MPHY reset ever having lived in this
driver.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Peter Wang <peter.wang@mediatek.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
drivers/ufs/host/ufs-mediatek-sip.h | 8 ----
drivers/ufs/host/ufs-mediatek.c | 78 ++++++++++++++++++-------------------
drivers/ufs/host/ufs-mediatek.h | 7 ++--
3 files changed, 42 insertions(+), 51 deletions(-)
diff --git a/drivers/ufs/host/ufs-mediatek-sip.h b/drivers/ufs/host/ufs-mediatek-sip.h
index d627dfb4a766..256598cc3b5b 100644
--- a/drivers/ufs/host/ufs-mediatek-sip.h
+++ b/drivers/ufs/host/ufs-mediatek-sip.h
@@ -31,11 +31,6 @@ enum ufs_mtk_vcc_num {
UFS_VCC_MAX
};
-enum ufs_mtk_mphy_op {
- UFS_MPHY_BACKUP = 0,
- UFS_MPHY_RESTORE
-};
-
/*
* SMC call wrapper function
*/
@@ -84,9 +79,6 @@ static inline void _ufs_mtk_smc(struct ufs_mtk_smc_arg s)
#define ufs_mtk_device_pwr_ctrl(on, ufs_version, res) \
ufs_mtk_smc(UFS_MTK_SIP_DEVICE_PWR_CTRL, &(res), on, ufs_version)
-#define ufs_mtk_mphy_ctrl(op, res) \
- ufs_mtk_smc(UFS_MTK_SIP_MPHY_CTRL, &(res), op)
-
#define ufs_mtk_mtcmos_ctrl(op, res) \
ufs_mtk_smc(UFS_MTK_SIP_MTCMOS_CTRL, &(res), op)
diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index b3daaa07e925..206794ce46c8 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -93,6 +93,12 @@ static const char *const ufs_uic_dl_err_str[] = {
"PA_INIT"
};
+static const char *const ufs_reset_names[] = {
+ "unipro",
+ "crypto",
+ "hci",
+};
+
static bool ufs_mtk_is_boost_crypt_enabled(struct ufs_hba *hba)
{
struct ufs_mtk_host *host = ufshcd_get_variant(hba);
@@ -203,49 +209,45 @@ static void ufs_mtk_crypto_enable(struct ufs_hba *hba)
static void ufs_mtk_host_reset(struct ufs_hba *hba)
{
struct ufs_mtk_host *host = ufshcd_get_variant(hba);
- struct arm_smccc_res res;
-
- reset_control_assert(host->hci_reset);
- reset_control_assert(host->crypto_reset);
- reset_control_assert(host->unipro_reset);
- reset_control_assert(host->mphy_reset);
-
- usleep_range(100, 110);
+ int ret;
- reset_control_deassert(host->unipro_reset);
- reset_control_deassert(host->crypto_reset);
- reset_control_deassert(host->hci_reset);
- reset_control_deassert(host->mphy_reset);
+ ret = reset_control_bulk_assert(MTK_UFS_NUM_RESETS, host->resets);
+ if (ret)
+ dev_warn(hba->dev, "Host reset assert failed: %pe\n", ERR_PTR(ret));
- /* restore mphy setting aftre mphy reset */
- if (host->mphy_reset)
- ufs_mtk_mphy_ctrl(UFS_MPHY_RESTORE, res);
-}
+ ret = phy_reset(host->mphy);
-static void ufs_mtk_init_reset_control(struct ufs_hba *hba,
- struct reset_control **rc,
- char *str)
-{
- *rc = devm_reset_control_get(hba->dev, str);
- if (IS_ERR(*rc)) {
- dev_info(hba->dev, "Failed to get reset control %s: %ld\n",
- str, PTR_ERR(*rc));
- *rc = NULL;
+ /*
+ * Only sleep if MPHY doesn't have a reset implemented (which already
+ * sleeps) or the PHY reset function failed somehow, just to be safe
+ */
+ if (ret) {
+ usleep_range(100, 110);
+ if (ret != -EOPNOTSUPP)
+ dev_warn(hba->dev, "PHY reset failed: %pe\n", ERR_PTR(ret));
}
+
+ ret = reset_control_bulk_deassert(MTK_UFS_NUM_RESETS, host->resets);
+ if (ret)
+ dev_warn(hba->dev, "Host reset deassert failed: %pe\n", ERR_PTR(ret));
}
-static void ufs_mtk_init_reset(struct ufs_hba *hba)
+static int ufs_mtk_init_reset(struct ufs_hba *hba)
{
struct ufs_mtk_host *host = ufshcd_get_variant(hba);
+ int ret, i;
+
+ for (i = 0; i < MTK_UFS_NUM_RESETS; i++)
+ host->resets[i].id = ufs_reset_names[i];
- ufs_mtk_init_reset_control(hba, &host->hci_reset,
- "hci_rst");
- ufs_mtk_init_reset_control(hba, &host->unipro_reset,
- "unipro_rst");
- ufs_mtk_init_reset_control(hba, &host->crypto_reset,
- "crypto_rst");
- ufs_mtk_init_reset_control(hba, &host->mphy_reset,
- "mphy_rst");
+ ret = devm_reset_control_bulk_get_optional_exclusive(hba->dev, MTK_UFS_NUM_RESETS,
+ host->resets);
+ if (ret) {
+ dev_err(hba->dev, "Failed to get resets: %pe\n", ERR_PTR(ret));
+ return ret;
+ }
+
+ return 0;
}
static int ufs_mtk_hce_enable_notify(struct ufs_hba *hba,
@@ -1247,11 +1249,9 @@ static int ufs_mtk_init(struct ufs_hba *hba)
if (err)
goto out_variant_clear;
- ufs_mtk_init_reset(hba);
-
- /* backup mphy setting if mphy can reset */
- if (host->mphy_reset)
- ufs_mtk_mphy_ctrl(UFS_MPHY_BACKUP, res);
+ err = ufs_mtk_init_reset(hba);
+ if (err)
+ goto out_variant_clear;
/* Enable runtime autosuspend */
hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND;
diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediatek.h
index 9747277f11e8..4fce29d131d1 100644
--- a/drivers/ufs/host/ufs-mediatek.h
+++ b/drivers/ufs/host/ufs-mediatek.h
@@ -7,12 +7,14 @@
#define _UFS_MEDIATEK_H
#include <linux/bitops.h>
+#include <linux/reset.h>
/*
* MCQ define and struct
*/
#define UFSHCD_MAX_Q_NR 8
#define MTK_MCQ_INVALID_IRQ 0xFFFF
+#define MTK_UFS_NUM_RESETS 3
/* REG_UFS_MMIO_OPT_CTRL_0 160h */
#define EHS_EN BIT(0)
@@ -175,10 +177,7 @@ struct ufs_mtk_mcq_intr_info {
struct ufs_mtk_host {
struct phy *mphy;
struct regulator *reg_va09;
- struct reset_control *hci_reset;
- struct reset_control *unipro_reset;
- struct reset_control *crypto_reset;
- struct reset_control *mphy_reset;
+ struct reset_control_bulk_data resets[MTK_UFS_NUM_RESETS];
struct ufs_hba *hba;
struct ufs_mtk_crypt_cfg *crypt;
struct ufs_mtk_clk mclk;
--
2.53.0
--
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linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH v8 05/23] phy: mediatek: ufs: Add support for resets
From: Nicolas Frattaroli @ 2026-03-04 14:53 UTC (permalink / raw)
To: Alim Akhtar, Avri Altman, Bart Van Assche, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chunfeng Yun, Vinod Koul,
Kishon Vijay Abraham I, Peter Wang, Stanley Jhu,
James E.J. Bottomley, Martin K. Petersen, Philipp Zabel,
Liam Girdwood, Mark Brown, Chaotian Jing, Neil Armstrong
Cc: Louis-Alexis Eyraud, kernel, linux-scsi, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-phy, Nicolas Frattaroli
In-Reply-To: <20260304-mt8196-ufs-v8-0-5b0eac23314f@collabora.com>
The MediaTek UFS PHY supports PHY resets. Until now, they've been
implemented in the UFS host driver. Since they were never documented in
the UFS HCI node's DT bindings, and no mainline DT uses it, it's fine if
it's moved to the correct location, which is the PHY driver.
Implement the MPHY reset logic in this driver and expose it through the
phy subsystem's reset op. The reset itself is optional, as judging by
other mainline devices that use this hardware, it's not required for the
device to function.
If no reset is present, the reset op returns -EOPNOTSUPP, which means
that the ufshci driver can detect it's present and not double sleep in
its own reset function, where it will call the phy reset.
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Peter Wang <peter.wang@mediatek.com>
Acked-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
drivers/phy/mediatek/phy-mtk-ufs.c | 71 ++++++++++++++++++++++++++++++++++++++
1 file changed, 71 insertions(+)
diff --git a/drivers/phy/mediatek/phy-mtk-ufs.c b/drivers/phy/mediatek/phy-mtk-ufs.c
index 0cb5a25b1b7a..48f8e4dbf928 100644
--- a/drivers/phy/mediatek/phy-mtk-ufs.c
+++ b/drivers/phy/mediatek/phy-mtk-ufs.c
@@ -4,6 +4,7 @@
* Author: Stanley Chu <stanley.chu@mediatek.com>
*/
+#include <linux/arm-smccc.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h>
@@ -11,6 +12,8 @@
#include <linux/module.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
+#include <linux/reset.h>
+#include <linux/soc/mediatek/mtk_sip_svc.h>
#include "phy-mtk-io.h"
@@ -36,9 +39,17 @@
#define UFSPHY_CLKS_CNT 2
+#define UFS_MTK_SIP_MPHY_CTRL BIT(8)
+
+enum ufs_mtk_mphy_op {
+ UFS_MPHY_BACKUP = 0,
+ UFS_MPHY_RESTORE
+};
+
struct ufs_mtk_phy {
struct device *dev;
void __iomem *mmio;
+ struct reset_control *reset;
struct clk_bulk_data clks[UFSPHY_CLKS_CNT];
};
@@ -141,9 +152,59 @@ static int ufs_mtk_phy_power_off(struct phy *generic_phy)
return 0;
}
+static int ufs_mtk_phy_ctrl(struct ufs_mtk_phy *phy, enum ufs_mtk_mphy_op op)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(MTK_SIP_UFS_CONTROL, UFS_MTK_SIP_MPHY_CTRL, op,
+ 0, 0, 0, 0, 0, &res);
+
+ switch (res.a0) {
+ case SMCCC_RET_NOT_SUPPORTED:
+ return -EOPNOTSUPP;
+ case SMCCC_RET_INVALID_PARAMETER:
+ return -EINVAL;
+ default:
+ return 0;
+ }
+}
+
+static int ufs_mtk_phy_reset(struct phy *generic_phy)
+{
+ struct ufs_mtk_phy *phy = get_ufs_mtk_phy(generic_phy);
+ int ret;
+
+ if (!phy->reset)
+ return -EOPNOTSUPP;
+
+ ret = reset_control_assert(phy->reset);
+ if (ret)
+ return ret;
+
+ usleep_range(100, 110);
+
+ ret = reset_control_deassert(phy->reset);
+ if (ret)
+ return ret;
+
+ /*
+ * To avoid double-sleep and other unintended side-effects in the ufshci
+ * driver, don't return the phy_ctrl retval here, but just return -EPROTO.
+ */
+ ret = ufs_mtk_phy_ctrl(phy, UFS_MPHY_RESTORE);
+ if (ret) {
+ dev_err(phy->dev, "UFS_MPHY_RESTORE SMC command failed: %pe\n",
+ ERR_PTR(ret));
+ return -EPROTO;
+ }
+
+ return 0;
+}
+
static const struct phy_ops ufs_mtk_phy_ops = {
.power_on = ufs_mtk_phy_power_on,
.power_off = ufs_mtk_phy_power_off,
+ .reset = ufs_mtk_phy_reset,
.owner = THIS_MODULE,
};
@@ -163,8 +224,18 @@ static int ufs_mtk_phy_probe(struct platform_device *pdev)
if (IS_ERR(phy->mmio))
return PTR_ERR(phy->mmio);
+ phy->reset = devm_reset_control_get_optional_exclusive(dev, NULL);
+ if (IS_ERR(phy->reset))
+ return dev_err_probe(dev, PTR_ERR(phy->reset), "Failed to get reset\n");
+
phy->dev = dev;
+ if (phy->reset) {
+ ret = ufs_mtk_phy_ctrl(phy, UFS_MPHY_BACKUP);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to back up MPHY\n");
+ }
+
ret = ufs_mtk_phy_clk_init(phy);
if (ret)
return ret;
--
2.53.0
--
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linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH v8 03/23] dt-bindings: ufs: mediatek,ufs: Add mt8196 variant
From: Nicolas Frattaroli @ 2026-03-04 14:53 UTC (permalink / raw)
To: Alim Akhtar, Avri Altman, Bart Van Assche, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chunfeng Yun, Vinod Koul,
Kishon Vijay Abraham I, Peter Wang, Stanley Jhu,
James E.J. Bottomley, Martin K. Petersen, Philipp Zabel,
Liam Girdwood, Mark Brown, Chaotian Jing, Neil Armstrong
Cc: Louis-Alexis Eyraud, kernel, linux-scsi, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-phy, Nicolas Frattaroli,
Conor Dooley
In-Reply-To: <20260304-mt8196-ufs-v8-0-5b0eac23314f@collabora.com>
The MediaTek MT8196 SoC's UFS controller uses three additional clocks
compared to the MT8195, and a different set of supplies. It is therefore
not compatible with the MT8195.
While it does have a AVDD09_UFS_1 pin in addition to the AVDD09_UFS pin,
it appears that these two pins are commoned together, as the board
schematic I have access to uses the same supply for both, and the
downstream driver does not distinguish between the two supplies either.
Add a compatible for it, and modify the binding correspondingly.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Vinod Koul <vkoul@kernel.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
.../devicetree/bindings/ufs/mediatek,ufs.yaml | 58 +++++++++++++++++++++-
1 file changed, 57 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml b/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml
index e0aef3e5f56b..a82119ecbfe8 100644
--- a/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml
+++ b/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml
@@ -16,10 +16,11 @@ properties:
- mediatek,mt8183-ufshci
- mediatek,mt8192-ufshci
- mediatek,mt8195-ufshci
+ - mediatek,mt8196-ufshci
clocks:
minItems: 1
- maxItems: 13
+ maxItems: 16
clock-names:
minItems: 1
@@ -37,6 +38,9 @@ properties:
- const: crypt_perf
- const: ufs_rx_symbol0
- const: ufs_rx_symbol1
+ - const: ufs_sel
+ - const: ufs_sel_min_src
+ - const: ufs_sel_max_src
operating-points-v2: true
@@ -131,9 +135,27 @@ allOf:
properties:
clocks:
minItems: 13
+ maxItems: 13
clock-names:
minItems: 13
+ maxItems: 13
avdd09-supply: false
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: mediatek,mt8196-ufshci
+ then:
+ properties:
+ clocks:
+ minItems: 16
+ maxItems: 16
+ clock-names:
+ minItems: 16
+ maxItems: 16
+ avdd18-supply: false
+ required:
+ - operating-points-v2
examples:
- |
@@ -183,3 +205,37 @@ examples:
mediatek,ufs-disable-mcq;
};
+ - |
+ #include <dt-bindings/reset/mediatek,mt8196-resets.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ ufshci@16810000 {
+ compatible = "mediatek,mt8196-ufshci";
+ reg = <0x16810000 0x2a00>;
+ interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&ufs_ao_clk 6>, <&ufs_ao_clk 7>, <&clk26m>, <&ufs_ao_clk 3>,
+ <&clk26m>, <&ufs_ao_clk 4>, <&ufs_ao_clk 0>,
+ <&topckgen 7>, <&topckgen 41>, <&topckgen 105>, <&topckgen 83>,
+ <&ufs_ao_clk 1>, <&ufs_ao_clk 2>, <&topckgen 42>,
+ <&topckgen 84>, <&topckgen 102>;
+ clock-names = "ufs", "ufs_aes", "ufs_tick", "unipro_sysclk",
+ "unipro_tick", "unipro_mp_bclk", "ufs_tx_symbol",
+ "ufs_mem_sub", "crypt_mux", "crypt_lp", "crypt_perf",
+ "ufs_rx_symbol0", "ufs_rx_symbol1", "ufs_sel",
+ "ufs_sel_min_src", "ufs_sel_max_src";
+
+ operating-points-v2 = <&ufs_opp_table>;
+
+ phys = <&ufsphy>;
+
+ avdd09-supply = <&mt6363_vsram_modem>;
+ vcc-supply = <&mt6363_vemc>;
+ vccq-supply = <&mt6363_vufs12>;
+
+ resets = <&ufs_ao_clk MT8196_UFSAO_RST1_UFS_UNIPRO>,
+ <&ufs_ao_clk MT8196_UFSAO_RST1_UFS_CRYPTO>,
+ <&ufs_ao_clk MT8196_UFSAO_RST1_UFSHCI>;
+ reset-names = "unipro", "crypto", "hci";
+ mediatek,ufs-disable-mcq;
+ };
--
2.53.0
--
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linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH v8 04/23] scsi: ufs: mediatek: Move MTK_SIP_UFS_CONTROL to mtk_sip_svc.h
From: Nicolas Frattaroli @ 2026-03-04 14:53 UTC (permalink / raw)
To: Alim Akhtar, Avri Altman, Bart Van Assche, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chunfeng Yun, Vinod Koul,
Kishon Vijay Abraham I, Peter Wang, Stanley Jhu,
James E.J. Bottomley, Martin K. Petersen, Philipp Zabel,
Liam Girdwood, Mark Brown, Chaotian Jing, Neil Armstrong
Cc: Louis-Alexis Eyraud, kernel, linux-scsi, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-phy, Nicolas Frattaroli
In-Reply-To: <20260304-mt8196-ufs-v8-0-5b0eac23314f@collabora.com>
SMC commands used by multiple drivers need to live in a shared header
file somewhere to avoid code duplication. In order to rework the MPHY
reset control to be in the phy-mtk-ufs.c driver, both ufs-mediatek and
the phy driver need access to this command.
Move it to mtk_sip_svc.h, where other such command definitions already
live.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Peter Wang <peter.wang@mediatek.com>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
drivers/ufs/host/ufs-mediatek-sip.h | 1 -
include/linux/soc/mediatek/mtk_sip_svc.h | 3 +++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/ufs/host/ufs-mediatek-sip.h b/drivers/ufs/host/ufs-mediatek-sip.h
index 7d17aedf6fb8..d627dfb4a766 100644
--- a/drivers/ufs/host/ufs-mediatek-sip.h
+++ b/drivers/ufs/host/ufs-mediatek-sip.h
@@ -11,7 +11,6 @@
/*
* SiP (Slicon Partner) commands
*/
-#define MTK_SIP_UFS_CONTROL MTK_SIP_SMC_CMD(0x276)
#define UFS_MTK_SIP_VA09_PWR_CTRL BIT(0)
#define UFS_MTK_SIP_DEVICE_RESET BIT(1)
#define UFS_MTK_SIP_CRYPTO_CTRL BIT(2)
diff --git a/include/linux/soc/mediatek/mtk_sip_svc.h b/include/linux/soc/mediatek/mtk_sip_svc.h
index abe24a73ee19..7265ff2a6e2a 100644
--- a/include/linux/soc/mediatek/mtk_sip_svc.h
+++ b/include/linux/soc/mediatek/mtk_sip_svc.h
@@ -22,6 +22,9 @@
ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, MTK_SIP_SMC_CONVENTION, \
ARM_SMCCC_OWNER_SIP, fn_id)
+/* UFS related SMC call */
+#define MTK_SIP_UFS_CONTROL MTK_SIP_SMC_CMD(0x276)
+
/* DVFSRC SMC calls */
#define MTK_SIP_DVFSRC_VCOREFS_CONTROL MTK_SIP_SMC_CMD(0x506)
--
2.53.0
--
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https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH v8 02/23] dt-bindings: ufs: mediatek,ufs: Complete the binding
From: Nicolas Frattaroli @ 2026-03-04 14:53 UTC (permalink / raw)
To: Alim Akhtar, Avri Altman, Bart Van Assche, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chunfeng Yun, Vinod Koul,
Kishon Vijay Abraham I, Peter Wang, Stanley Jhu,
James E.J. Bottomley, Martin K. Petersen, Philipp Zabel,
Liam Girdwood, Mark Brown, Chaotian Jing, Neil Armstrong
Cc: Louis-Alexis Eyraud, kernel, linux-scsi, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-phy, Nicolas Frattaroli,
Conor Dooley
In-Reply-To: <20260304-mt8196-ufs-v8-0-5b0eac23314f@collabora.com>
As it stands, the mediatek,ufs.yaml binding is startlingly incomplete.
Its one example, which is the only real "user" of this binding in
mainline, uses the deprecated freq-table-hz property.
The resets, of which there are three optional ones, are completely
absent.
The clock description for MT8195 is incomplete, as is the one for
MT8192. It's not known if the one clock binding for MT8183 is even
correct, but I do not have access to the necessary code and
documentation to find this out myself.
The power supply situation is not much better; the binding describes one
required power supply, but it's the UFS card supply, not any of the
supplies feeding the controller silicon.
No second example is present in the binding, making verification
difficult.
Disallow freq-table-hz and move to operating-points-v2. It's fine to
break compatibility here, as the binding is currently unused and would
be impossible to correctly use in its current state.
Add the three resets and the corresponding reset-names property. These
resets appear to be optional, i.e. not required for the functioning of
the device.
Move the list of clock names out of the if condition, and expand it for
the confirmed clocks I could find by cross-referencing several clock
drivers. For MT8195, increase the minimum number of clocks to include
the crypt and rx_symbol ones, as they're internal to the SoC and should
always be present, and should therefore not be omitted.
MT8192 gets to have at least 3 clocks, as these were the ones I could
quickly confirm from a glance at various trees. I can't say this was an
exhaustive search though, but it's better than the current situation.
Properly document all supplies, with which pin name on the SoCs they
supply. Complete the example with them.
Also add a MT8195 example to the binding, using supply labels that I am
pretty sure would be the right ones for e.g. the Radxa NIO 12L.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
.../devicetree/bindings/ufs/mediatek,ufs.yaml | 117 ++++++++++++++++++---
1 file changed, 100 insertions(+), 17 deletions(-)
diff --git a/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml b/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml
index 15c347f5e660..e0aef3e5f56b 100644
--- a/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml
+++ b/Documentation/devicetree/bindings/ufs/mediatek,ufs.yaml
@@ -19,11 +19,28 @@ properties:
clocks:
minItems: 1
- maxItems: 8
+ maxItems: 13
clock-names:
minItems: 1
- maxItems: 8
+ items:
+ - const: ufs
+ - const: ufs_aes
+ - const: ufs_tick
+ - const: unipro_sysclk
+ - const: unipro_tick
+ - const: unipro_mp_bclk
+ - const: ufs_tx_symbol
+ - const: ufs_mem_sub
+ - const: crypt_mux
+ - const: crypt_lp
+ - const: crypt_perf
+ - const: ufs_rx_symbol0
+ - const: ufs_rx_symbol1
+
+ operating-points-v2: true
+
+ freq-table-hz: false
phys:
maxItems: 1
@@ -31,8 +48,36 @@ properties:
reg:
maxItems: 1
+ resets:
+ items:
+ - description: reset for the UniPro layer
+ - description: reset for the cryptography engine
+ - description: reset for the host controller
+
+ reset-names:
+ items:
+ - const: unipro
+ - const: crypto
+ - const: hci
+
+ avdd09-supply:
+ description: Phandle to the 0.9V supply powering the AVDD09_UFS pin
+
+ avdd12-supply:
+ description: Phandle to the 1.2V supply powering the AVDD12_UFS pin
+
+ avdd12-ckbuf-supply:
+ description: Phandle to the 1.2V supply powering the AVDD12_CKBUF_UFS pin
+
+ avdd18-supply:
+ description: Phandle to the 1.8V supply powering the AVDD18_UFS pin
+
vcc-supply: true
+ vccq-supply: true
+
+ vccq2-supply: true
+
mediatek,ufs-disable-mcq:
$ref: /schemas/types.yaml#/definitions/flag
description: The mask to disable MCQ (Multi-Circular Queue) for UFS host.
@@ -54,29 +99,41 @@ allOf:
properties:
compatible:
contains:
- enum:
- - mediatek,mt8195-ufshci
+ const: mediatek,mt8183-ufshci
then:
properties:
clocks:
- minItems: 8
+ maxItems: 1
clock-names:
items:
- const: ufs
- - const: ufs_aes
- - const: ufs_tick
- - const: unipro_sysclk
- - const: unipro_tick
- - const: unipro_mp_bclk
- - const: ufs_tx_symbol
- - const: ufs_mem_sub
- else:
+ avdd12-ckbuf-supply: false
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: mediatek,mt8192-ufshci
+ then:
properties:
clocks:
- maxItems: 1
+ minItems: 3
+ maxItems: 3
+ clocks-names:
+ minItems: 3
+ maxItems: 3
+ avdd09-supply: false
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: mediatek,mt8195-ufshci
+ then:
+ properties:
+ clocks:
+ minItems: 13
clock-names:
- items:
- - const: ufs
+ minItems: 13
+ avdd09-supply: false
examples:
- |
@@ -95,8 +152,34 @@ examples:
clocks = <&infracfg_ao CLK_INFRA_UFS>;
clock-names = "ufs";
- freq-table-hz = <0 0>;
vcc-supply = <&mt_pmic_vemc_ldo_reg>;
};
};
+ - |
+ ufshci@11270000 {
+ compatible = "mediatek,mt8195-ufshci";
+ reg = <0x11270000 0x2300>;
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&ufsphy>;
+ clocks = <&infracfg_ao 63>, <&infracfg_ao 64>, <&infracfg_ao 65>,
+ <&infracfg_ao 54>, <&infracfg_ao 55>,
+ <&infracfg_ao 56>, <&infracfg_ao 90>,
+ <&infracfg_ao 93>, <&topckgen 60>, <&topckgen 152>,
+ <&topckgen 125>, <&topckgen 212>, <&topckgen 215>;
+ clock-names = "ufs", "ufs_aes", "ufs_tick",
+ "unipro_sysclk", "unipro_tick",
+ "unipro_mp_bclk", "ufs_tx_symbol",
+ "ufs_mem_sub", "crypt_mux", "crypt_lp",
+ "crypt_perf", "ufs_rx_symbol0", "ufs_rx_symbol1";
+
+ operating-points-v2 = <&ufs_opp_table>;
+
+ avdd12-supply = <&mt6359_vrf12_ldo_reg>;
+ avdd12-ckbuf-supply = <&mt6359_vbbck_ldo_reg>;
+ avdd18-supply = <&mt6359_vio18_ldo_reg>;
+ vcc-supply = <&mt6359_vemc_1_ldo_reg>;
+ vccq2-supply = <&mt6359_vufs_ldo_reg>;
+
+ mediatek,ufs-disable-mcq;
+ };
--
2.53.0
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^ permalink raw reply related
* [PATCH v8 00/23] MediaTek UFS Cleanup and MT8196 Enablement
From: Nicolas Frattaroli @ 2026-03-04 14:53 UTC (permalink / raw)
To: Alim Akhtar, Avri Altman, Bart Van Assche, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chunfeng Yun, Vinod Koul,
Kishon Vijay Abraham I, Peter Wang, Stanley Jhu,
James E.J. Bottomley, Martin K. Petersen, Philipp Zabel,
Liam Girdwood, Mark Brown, Chaotian Jing, Neil Armstrong
Cc: Louis-Alexis Eyraud, kernel, linux-scsi, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-phy, Nicolas Frattaroli,
Conor Dooley, Krzysztof Kozlowski
In this series, the existing MediaTek UFS binding is expanded and
completed to correctly describe not just the existing compatibles, but
also to introduce a new compatible in the from of the MT8196 SoC.
The resets, which until now were completely absent from both the UFS
host controller binding and the UFS PHY binding, are introduced to both.
This also means the driver's undocumented and, in mainline, unused reset
logic is reworked. In particular, the PHY reset is no longer a reset of
the host controller node, but of the PHY node.
This means the host controller can reset the PHY through the common PHY
framework.
The resets remain optional.
Additionally, a massive number of driver cleanups are introduced. These
were prompted by me inspecting the driver more closely as I was
adjusting it to correspond to the binding.
The driver still implements vendor properties that are undocumented in
the binding. I did not touch most of those, as I neither want to
convince the bindings maintainers that they are needed without knowing
precisely what they're for, nor do I want to argue with the driver
authors when removing them.
Due to the "Marie Kondo with a chainsaw" nature of the driver cleanup
patches, I humbly request that reviewers do not comment on displeasing
code they see in the context portion of a patch before they've read the
whole patch series, as that displeasing code may in fact be reworked in
a subsequent patch of this series. Please keep comments focused on the
changed lines of the diff; I know there's more that can be done, but it
doesn't necessarily need to be part of this series.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
Changes in v8:
- Split "Rework probe function" into two, turn the reset removal into
its own patch and squash the PHY changes into the common PHY framework
patch.
- Leave "device reset done" logging print at INFO level
- Remove redundant falsy check for reg_vcore in "Don't acquire
dvfsrc-vcore twice".
- Change ufs_mtk_wait_idle_state to early-exit on all non-HIB states,
and poll for VS_HCE_BASE instead.
- Link to v7: https://lore.kernel.org/r/20260216-mt8196-ufs-v7-0-b5f2907c6da7@collabora.com
Changes in v7:
- Rebase onto next-20260205, which drops "scsi: ufs: mediatek: Switch to
newer PM ops helpers" as Arnd sent an equivalent patch that also fixes
the PM-less build failure.
- Link to v6: https://lore.kernel.org/r/20260124-mt8196-ufs-v6-0-e7c005b60028@collabora.com
Changes in v6:
- Reword "Rework probe function" commit to better justify the changes
being made.
- Drop "Add vendor prefix to clk-scale-up-vcore-min"
- Add patch to remove clk-scale-up-vcore-min entirely, describing the
process for bringing it back (in a different form) in the commit
message.
- Link to v5: https://lore.kernel.org/r/20260108-mt8196-ufs-v5-0-49215157ec41@collabora.com
Changes in v5:
- Drop "scsi: ufs: mediatek: Make scale_us in setup_clk_gating const" as
someone else already got a patch in for this into next.
- Make mtk_init_boost_crypt void
- Don't disable/enable misc regulators during suspend/resume, but enable
them once when acquiring with a devm helper.
- Link to v4: https://lore.kernel.org/r/20251218-mt8196-ufs-v4-0-ddec7a369dd2@collabora.com
Changes in v4:
- bindings: Redo the supply situation, as the avdd pins don't describe
the vcc(q2) card supplies.
- bindings: format clock in mt8196 example more tersely.
- phy: use devm_reset_control_get_optional_exclusive directly
- driver: get and enable/disable the aforementioned avdd supplies.
- Link to v3: https://lore.kernel.org/r/20251023-mt8196-ufs-v3-0-0f04b4a795ff@collabora.com
Changes in v3:
- Split mediatek,ufs bindings change into two patches, one for
completing the existing binding, one for the MT8196
- Add over a dozen driver cleanup patches
- Add explicit support for the MT8196 compatible to the driver
- Note: next-20251023, on which I based this, currently has a broken
build due to an unrelated OPP core change that was merged with no
build testing. I can't use next-20251022 either, as that lacks the
recent mediatek UFS changes. It is what it is.
- Link to v2: https://lore.kernel.org/r/20251016-mt8196-ufs-v2-0-c373834c4e7a@collabora.com
Changes in v2:
- Reorder define in mtk_sip_svc.h
- Use bulk reset APIs in UFS host driver
- Link to v1: https://lore.kernel.org/r/20251014-mt8196-ufs-v1-0-195dceb83bc8@collabora.com
---
Nicolas Frattaroli (23):
dt-bindings: phy: Add mediatek,mt8196-ufsphy variant
dt-bindings: ufs: mediatek,ufs: Complete the binding
dt-bindings: ufs: mediatek,ufs: Add mt8196 variant
scsi: ufs: mediatek: Move MTK_SIP_UFS_CONTROL to mtk_sip_svc.h
phy: mediatek: ufs: Add support for resets
scsi: ufs: mediatek: Rework resets
scsi: ufs: mediatek: Rework 0.9V regulator
scsi: ufs: mediatek: Rework init function
scsi: ufs: mediatek: Rework the crypt-boost stuff
scsi: ufs: mediatek: Handle misc host voltage regulators
scsi: ufs: mediatek: Remove undocumented downstream reset cruft
scsi: ufs: mediatek: Remove vendor kernel quirks cruft
scsi: ufs: mediatek: Use the common PHY framework
scsi: ufs: mediatek: Remove mediatek,ufs-broken-rtc property
scsi: ufs: mediatek: Rework _ufs_mtk_clk_scale error paths
scsi: ufs: mediatek: Clean up logging prints
scsi: ufs: mediatek: Rework ufs_mtk_wait_idle_state
scsi: ufs: mediatek: Don't acquire dvfsrc-vcore twice
scsi: ufs: mediatek: Rework hardware version reading
scsi: ufs: mediatek: Back up idle timer in per-instance struct
scsi: ufs: mediatek: Remove ret local from link_startup_notify
scsi: ufs: mediatek: Remove undocumented "clk-scale-up-vcore-min"
scsi: ufs: mediatek: Add MT8196 compatible, update copyright
.../devicetree/bindings/phy/mediatek,ufs-phy.yaml | 16 +
.../devicetree/bindings/ufs/mediatek,ufs.yaml | 173 +++-
drivers/phy/mediatek/phy-mtk-ufs.c | 71 ++
drivers/ufs/host/ufs-mediatek-sip.h | 9 -
drivers/ufs/host/ufs-mediatek.c | 958 +++++++++------------
drivers/ufs/host/ufs-mediatek.h | 17 +-
include/linux/soc/mediatek/mtk_sip_svc.h | 3 +
7 files changed, 650 insertions(+), 597 deletions(-)
---
base-commit: 11e703f54ac21f4dc609ea12ab578ffa47c87e11
change-id: 20251014-mt8196-ufs-cec4b9a97e53
Best regards,
--
Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
--
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^ permalink raw reply
* [PATCH v8 01/23] dt-bindings: phy: Add mediatek,mt8196-ufsphy variant
From: Nicolas Frattaroli @ 2026-03-04 14:53 UTC (permalink / raw)
To: Alim Akhtar, Avri Altman, Bart Van Assche, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chunfeng Yun, Vinod Koul,
Kishon Vijay Abraham I, Peter Wang, Stanley Jhu,
James E.J. Bottomley, Martin K. Petersen, Philipp Zabel,
Liam Girdwood, Mark Brown, Chaotian Jing, Neil Armstrong
Cc: Louis-Alexis Eyraud, kernel, linux-scsi, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-phy, Nicolas Frattaroli,
Conor Dooley
In-Reply-To: <20260304-mt8196-ufs-v8-0-5b0eac23314f@collabora.com>
The MediaTek MT8196 SoC includes an M-PHY compatible with the already
existing mt8183 binding.
However, one omission from the original binding was that all of these
variants may have an optional reset.
Add the new compatible, and also the resets property, with an example.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Peter Wang <peter.wang@mediatek.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
.../devicetree/bindings/phy/mediatek,ufs-phy.yaml | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml
index 6e2edd43fc2a..ee71dfa4e0c0 100644
--- a/Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml
@@ -27,6 +27,7 @@ properties:
- items:
- enum:
- mediatek,mt8195-ufsphy
+ - mediatek,mt8196-ufsphy
- const: mediatek,mt8183-ufsphy
- const: mediatek,mt8183-ufsphy
@@ -43,6 +44,10 @@ properties:
- const: unipro
- const: mp
+ resets:
+ items:
+ - description: Optional UFS M-PHY reset.
+
"#phy-cells":
const: 0
@@ -66,5 +71,16 @@ examples:
clock-names = "unipro", "mp";
#phy-cells = <0>;
};
+ - |
+ #include <dt-bindings/reset/mediatek,mt8196-resets.h>
+ ufs-phy@16800000 {
+ compatible = "mediatek,mt8196-ufsphy", "mediatek,mt8183-ufsphy";
+ reg = <0x16800000 0x10000>;
+ clocks = <&ufs_ao_clk 3>,
+ <&ufs_ao_clk 5>;
+ clock-names = "unipro", "mp";
+ resets = <&ufs_ao_clk MT8196_UFSAO_RST0_UFS_MPHY>;
+ #phy-cells = <0>;
+ };
...
--
2.53.0
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^ permalink raw reply related
* Re: [RESEND 1/1] phy: freescale: imx8qm-hsio: provide regmap names
From: Alexander Stein @ 2026-03-04 14:36 UTC (permalink / raw)
To: Frank Li, Vinod Koul
Cc: Neil Armstrong, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, linux-phy, imx, linux-arm-kernel, linux-kernel
In-Reply-To: <aYygzojdO0QACdqX@lizhi-Precision-Tower-5810>
[-- Attachment #1.1: Type: text/plain, Size: 3277 bytes --]
Hi,
Am Mittwoch, 11. Februar 2026, 16:31:26 CET schrieb Frank Li:
> On Wed, Feb 11, 2026 at 03:49:48PM +0100, Alexander Stein wrote:
> > This driver uses multiple regmaps, which will causes name conflicts
> > in debugfs like:
> > debugfs: '5f1a0000.phy' already exists in 'regmap'
> > Fix this by using a dedicated regmap config for each resource, each
> > having a dedicated regmap name.
> >
> > Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> > ---
> Reviewed-by: Frank Li <Frank.Li@nxp.com>
gentle ping. Any additional feedback?
Best regards,
Alexander
> > Same as the one sent in December but with an updated CC list.
> >
> > drivers/phy/freescale/phy-fsl-imx8qm-hsio.c | 23 +++++++++++++++++----
> > 1 file changed, 19 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c b/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
> > index 279b8ac7822df..4ab45c9f53dff 100644
> > --- a/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
> > +++ b/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
> > @@ -107,7 +107,22 @@ static const char * const lan2_pcieb_clks[] = {"apb_pclk2", "pclk2", "ctl1_crr",
> > static const char * const lan2_sata_clks[] = {"pclk2", "epcs_tx", "epcs_rx",
> > "phy1_crr", "misc_crr"};
> >
> > -static const struct regmap_config regmap_config = {
> > +static const struct regmap_config regmap_phy_config = {
> > + .name = "phy",
> > + .reg_bits = 32,
> > + .val_bits = 32,
> > + .reg_stride = 4,
> > +};
> > +
> > +static const struct regmap_config regmap_ctrl_config = {
> > + .name = "ctrl",
> > + .reg_bits = 32,
> > + .val_bits = 32,
> > + .reg_stride = 4,
> > +};
> > +
> > +static const struct regmap_config regmap_misc_config = {
> > + .name = "misc",
> > .reg_bits = 32,
> > .val_bits = 32,
> > .reg_stride = 4,
> > @@ -562,19 +577,19 @@ static int imx_hsio_probe(struct platform_device *pdev)
> > return PTR_ERR(priv->base);
> >
> > off = devm_platform_ioremap_resource_byname(pdev, "phy");
> > - priv->phy = devm_regmap_init_mmio(dev, off, ®map_config);
> > + priv->phy = devm_regmap_init_mmio(dev, off, ®map_phy_config);
> > if (IS_ERR(priv->phy))
> > return dev_err_probe(dev, PTR_ERR(priv->phy),
> > "unable to find phy csr registers\n");
> >
> > off = devm_platform_ioremap_resource_byname(pdev, "ctrl");
> > - priv->ctrl = devm_regmap_init_mmio(dev, off, ®map_config);
> > + priv->ctrl = devm_regmap_init_mmio(dev, off, ®map_ctrl_config);
> > if (IS_ERR(priv->ctrl))
> > return dev_err_probe(dev, PTR_ERR(priv->ctrl),
> > "unable to find ctrl csr registers\n");
> >
> > off = devm_platform_ioremap_resource_byname(pdev, "misc");
> > - priv->misc = devm_regmap_init_mmio(dev, off, ®map_config);
> > + priv->misc = devm_regmap_init_mmio(dev, off, ®map_misc_config);
> > if (IS_ERR(priv->misc))
> > return dev_err_probe(dev, PTR_ERR(priv->misc),
> > "unable to find misc csr registers\n");
> > --
> > 2.43.0
> >
>
--
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Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
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^ permalink raw reply
* Re: [PATCH] phy: rockchip: naneng-combphy: configure SSC for PCIe on rk3588 and rk3576
From: Shawn Lin @ 2026-03-04 13:47 UTC (permalink / raw)
To: Vinod Koul, linux-rockchip
Cc: shawn.lin, linux-phy, Heiko Stuebner, Neil Armstrong,
linux-kernel
In-Reply-To: <1772619211-99875-1-git-send-email-shawn.lin@rock-chips.com>
在 2026/03/04 星期三 18:13, Shawn Lin 写道:
> Add a dedicated function rk_combphy_cfg_ssc_for_pcie() to configure
> Spread Spectrum Clocking (SSC) for the PCIe PHY on compatible platforms.
>
> The function first checks the device tree node's compatible string.
> Currently, SSC tuning is specifically implemented and applied only for
> "rockchip,rk3588-naneng-combphy" and "rockchip,rk3576-naneng-combphy".
>
Sorry, I amended the patch in the last minute before sending it which
seems not able to work after re-testing. Will update v2.
> The correct SSC configuration for these platforms involves:
> 1. Enabling SSC via the RK3568_PHYREG8_SSC_EN bit.
> 2. Setting the PLL SSC module control via the newly defined
> RK3568_PHYREG33_PLL_SSC_CTRL bit.
> 3. For PCIe phys with a 24MHz reference clock, additional PLL loop
> divider and signal adjustment values are programmed to optimiz
> performance.
>
> This SSC configuration is intended to improve EMI characteristics or
> meet specific clock tolerance requirements for PCIe interfaces on
> these SoCs.
>
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
> ---
>
> drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 93 +++++++++++++---------
> 1 file changed, 55 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> index b60d6bf..aa09d71 100644
> --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> @@ -121,6 +121,7 @@
> #define RK3568_PHYREG32_SSC_OFFSET_500PPM 1
>
> #define RK3568_PHYREG33 0x80
> +#define RK3568_PHYREG33_PLL_SSC_CTRL BIT(5)
> #define RK3568_PHYREG33_PLL_KVCO_MASK GENMASK(4, 2)
> #define RK3568_PHYREG33_PLL_KVCO_SHIFT 2
> #define RK3568_PHYREG33_PLL_KVCO_VALUE 2
> @@ -964,6 +965,56 @@ static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = {
> .combphy_cfg = rk3568_combphy_cfg,
> };
>
> +static void rk_combphy_cfg_ssc_for_pcie(struct rockchip_combphy_priv *priv, unsigned long rate)
> +{
> + struct device_node *np = priv->dev->of_node;
> + u32 val;
> +
> + /* Some SoCs' combphys share the same PCIe SSC tuning result */
> + if (!of_device_is_compatible(np, "rockchip,rk3588-naneng-combphy") ||
> + !of_device_is_compatible(np, "rockchip,rk3576-naneng-combphy")) {
> + dev_warn(priv->dev, "Incompatible platform\n");
> + return;
> + }
> +
> + val = readl(priv->mmio + RK3568_PHYREG8);
> + val |= RK3568_PHYREG8_SSC_EN;
> + writel(val, priv->mmio + RK3568_PHYREG8);
> +
> + /* PLL control SSC module period should be set */
> + val = readl(priv->mmio + RK3568_PHYREG33);
> + val |= RK3568_PHYREG33_PLL_SSC_CTRL;
> + writel(val, priv->mmio + RK3568_PHYREG33);
> +
> + if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_24MHz) {
> + /* Set PLL loop divider */
> + writel(0x00, priv->mmio + RK3576_PHYREG17);
> + writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18);
> +
> + /* Set up rx_pck invert and rx msb to disable */
> + writel(0x00, priv->mmio + RK3588_PHYREG27);
> +
> + /*
> + * Set up SU adjust signal:
> + * su_trim[7:0], PLL KVCO adjust bits[2:0] to min
> + * su_trim[15:8], PLL LPF R1 adujst bits[9:7]=3'b101
> + * su_trim[23:16], CKRCV adjust
> + * su_trim[31:24], CKDRV adjust
> + */
> + writel(0x90, priv->mmio + RK3568_PHYREG11);
> + writel(0x02, priv->mmio + RK3568_PHYREG12);
> + writel(0x08, priv->mmio + RK3568_PHYREG13);
> + writel(0x57, priv->mmio + RK3568_PHYREG14);
> + writel(0x40, priv->mmio + RK3568_PHYREG15);
> +
> + writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16);
> +
> + val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK,
> + RK3576_PHYREG33_PLL_KVCO_VALUE);
> + writel(val, priv->mmio + RK3568_PHYREG33);
> + }
> +}
> +
> static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
> {
> const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
> @@ -1156,39 +1207,8 @@ static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
> }
> }
>
> - if (priv->enable_ssc) {
> - val = readl(priv->mmio + RK3568_PHYREG8);
> - val |= RK3568_PHYREG8_SSC_EN;
> - writel(val, priv->mmio + RK3568_PHYREG8);
> -
> - if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_24MHz) {
> - /* Set PLL loop divider */
> - writel(0x00, priv->mmio + RK3576_PHYREG17);
> - writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18);
> -
> - /* Set up rx_pck invert and rx msb to disable */
> - writel(0x00, priv->mmio + RK3588_PHYREG27);
> -
> - /*
> - * Set up SU adjust signal:
> - * su_trim[7:0], PLL KVCO adjust bits[2:0] to min
> - * su_trim[15:8], PLL LPF R1 adujst bits[9:7]=3'b101
> - * su_trim[23:16], CKRCV adjust
> - * su_trim[31:24], CKDRV adjust
> - */
> - writel(0x90, priv->mmio + RK3568_PHYREG11);
> - writel(0x02, priv->mmio + RK3568_PHYREG12);
> - writel(0x08, priv->mmio + RK3568_PHYREG13);
> - writel(0x57, priv->mmio + RK3568_PHYREG14);
> - writel(0x40, priv->mmio + RK3568_PHYREG15);
> -
> - writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16);
> -
> - val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK,
> - RK3576_PHYREG33_PLL_KVCO_VALUE);
> - writel(val, priv->mmio + RK3568_PHYREG33);
> - }
> - }
> + if (priv->enable_ssc)
> + rk_combphy_cfg_ssc_for_pcie(priv, rate);
>
> return 0;
> }
> @@ -1371,11 +1391,8 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
> }
> }
>
> - if (priv->enable_ssc) {
> - val = readl(priv->mmio + RK3568_PHYREG8);
> - val |= RK3568_PHYREG8_SSC_EN;
> - writel(val, priv->mmio + RK3568_PHYREG8);
> - }
> + if (priv->enable_ssc)
> + rk_combphy_cfg_ssc_for_pcie(priv, rate);
>
> return 0;
> }
>
--
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^ permalink raw reply
* Re: [PATCH v2] phy: qcom: qmp-combo: Move pipe_clk on/off to common
From: Konrad Dybcio @ 2026-03-04 12:19 UTC (permalink / raw)
To: Val Packett, Vinod Koul, Kishon Vijay Abraham I, Bjorn Andersson,
Wesley Cheng, Neil Armstrong
Cc: Dmitry Baryshkov, linux-arm-msm, linux-phy, linux-kernel
In-Reply-To: <20260228220634.22778-2-val@packett.cool>
On 2/28/26 11:05 PM, Val Packett wrote:
> Keep the USB pipe clock working when the phy is in DP-only mode, because
> the dwc controller still needs it for USB 2.0 over the same Type-C port.
>
> Tested with the BenQ RD280UA monitor which has a downstream-facing port
> for data passthrough that's manually switchable between USB 2 and 3,
> corresponding to 4-lane and 2-lane DP respectively.
>
> Note: the suspend/resume callbacks were already gating the enable/disable
> of this clock only on init_count and not usb_init_count!
>
> Signed-off-by: Val Packett <val@packett.cool>
> ---
> See https://lore.kernel.org/all/389ca5d3-a698-4dac-911c-39ba057e3d17@oss.qualcomm.com/ for more info.
> BTW https://lore.kernel.org/all/20260205160240.748371-2-loic.poulain@oss.qualcomm.com/ helped with coldplug.
>
> v2: Reorder disables as suggested
> v1: https://lore.kernel.org/all/20250927093915.45124-2-val@packett.cool/
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 16 ++++++++--------
> 1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> index 93f1aa10d400..28428a8d1192 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> @@ -3691,6 +3691,13 @@ static int qmp_combo_com_init(struct qmp_combo *qmp, bool force)
> if (ret)
> goto err_assert_reset;
>
> + /* In DP-only mode, the pipe clk is still required for USB2 */
> + ret = clk_prepare_enable(qmp->pipe_clk);
> + if (ret) {
> + dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
> + return ret;
I didn't notice this before - please add this hunk
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
index 28428a8d1192..cdcfad2e86b1 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
@@ -3695,7 +3695,7 @@ static int qmp_combo_com_init(struct qmp_combo *qmp, bool force)
ret = clk_prepare_enable(qmp->pipe_clk);
if (ret) {
dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
- return ret;
+ goto err_disable_clocks;
}
qphy_setbits(com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, SW_PWRDN);
@@ -3756,6 +3756,8 @@ static int qmp_combo_com_init(struct qmp_combo *qmp, bool force)
return 0;
+err_disable_clocks:
+ clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
err_assert_reset:
reset_control_bulk_assert(cfg->num_resets, qmp->resets);
err_disable_regulators:
Konrad
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^ permalink raw reply related
* Re: [PATCH v3 1/2] dt-bindings: phy: qcom: Add CSI2 C-PHY/DPHY schema
From: Konrad Dybcio @ 2026-03-04 10:32 UTC (permalink / raw)
To: Bryan O'Donoghue, Bryan O'Donoghue, Bryan O'Donoghue,
Vijay Kumar Tumati, Vinod Koul, Kishon Vijay Abraham I,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Neil Armstrong
Cc: Vladimir Zapolskiy, linux-arm-msm, linux-phy, linux-media,
devicetree, linux-kernel
In-Reply-To: <1082062b-87a7-4254-b5e7-2dc3769a619f@linaro.org>
On 3/3/26 3:56 PM, Bryan O'Donoghue wrote:
> On 03/03/2026 12:34, Konrad Dybcio wrote:
>> That depends on the use case.
>>
>> MXA is always-on (that's the 'A' in the name, as opposed to 'C'
>> for 'Collapsible'), but it's not always at the required performance
>> state (svs, nom, etc.). For some clock controllers specifically, there
>> is no need to put them into the picture, as the rail may be unconnected
>> altogether, or only used for some retention mechanisms (which only
>> require the rail to be enabled and nothing more)
>
> Does this rail have an OPP table you can share ?
Camera clocks on X1 (mclks and the fixed PLL2, which is exclusively used
to derive MCLKs) that potentially depend on this rail (awaiting Taniya's
opinion on the other thread [1]) would only need LOWSVS_D1 for all of
their configurations (ftbl_cam_cc_mclk0_clk_src[])
i.e. let's wait for a definitive answer as there's a lot of layers..
[1] https://lore.kernel.org/linux-arm-msm/382725b5-1e72-44b2-b9ae-38aea1f7a976@oss.qualcomm.com/
Konrad
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^ permalink raw reply
* [PATCH] phy: tegra: xusb: Fix per-pad high-speed termination calibration
From: Wei-Cheng Chen @ 2026-03-04 10:26 UTC (permalink / raw)
To: jckuo, vkoul, neil.armstrong, thierry.reding, jonathanh
Cc: linux-phy, linux-tegra, linux-kernel, waynec, wtsai,
Wei-Cheng Chen
From: Wayne Chang <waynec@nvidia.com>
The existing code reads a single hs_term_range_adj value from bit field
[10:7] of FUSE_SKU_CALIB_0 and applies it to all USB2 pads uniformly.
However, on SoCs that support per-pad termination, each pad has its own
hs_term_range_adj field: pad 0 in FUSE_SKU_CALIB_0[10:7], and pads 1-3
in FUSE_USB_CALIB_EXT_0 at bit offsets [8:5], [12:9], and [16:13]
respectively.
Fix the calibration by reading per-pad values from the appropriate fuse
registers. For SoCs that do not support per-pad termination, replicate
pad 0's value to all pads to maintain existing behavior.
Add a has_per_pad_term flag to the SoC data to indicate whether per-pad
termination values are available in FUSE_USB_CALIB_EXT_0.
Fixes: 1ef535c6ba8e ("phy: tegra: xusb: Add Tegra194 support")
Cc: stable@vger.kernel.org
Signed-off-by: Wayne Chang <waynec@nvidia.com>
Signed-off-by: Wei-Cheng Chen <weichengc@nvidia.com>
---
drivers/phy/tegra/xusb-tegra186.c | 33 ++++++++++++++++++++++++-------
drivers/phy/tegra/xusb.h | 1 +
2 files changed, 27 insertions(+), 7 deletions(-)
diff --git a/drivers/phy/tegra/xusb-tegra186.c b/drivers/phy/tegra/xusb-tegra186.c
index bec9616c4a2..4452e73fb82 100644
--- a/drivers/phy/tegra/xusb-tegra186.c
+++ b/drivers/phy/tegra/xusb-tegra186.c
@@ -20,8 +20,8 @@
/* FUSE USB_CALIB registers */
#define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
#define HS_CURR_LEVEL_PAD_MASK 0x3f
-#define HS_TERM_RANGE_ADJ_SHIFT 7
-#define HS_TERM_RANGE_ADJ_MASK 0xf
+#define HS_TERM_RANGE_ADJ_PADX_SHIFT(x) ((x) ? (5 + (x - 1) * 4) : 7)
+#define HS_TERM_RANGE_ADJ_PAD_MASK 0xf
#define HS_SQUELCH_SHIFT 29
#define HS_SQUELCH_MASK 0x7
@@ -253,7 +253,7 @@
struct tegra_xusb_fuse_calibration {
u32 *hs_curr_level;
u32 hs_squelch;
- u32 hs_term_range_adj;
+ u32 *hs_term_range_adj;
u32 rpd_ctrl;
};
@@ -930,7 +930,7 @@ static int tegra186_utmi_phy_power_on(struct phy *phy)
value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
value &= ~TERM_RANGE_ADJ(~0);
- value |= TERM_RANGE_ADJ(priv->calib.hs_term_range_adj);
+ value |= TERM_RANGE_ADJ(priv->calib.hs_term_range_adj[index]);
value &= ~RPD_CTRL(~0);
value |= RPD_CTRL(priv->calib.rpd_ctrl);
padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
@@ -1464,17 +1464,23 @@ static const char * const tegra186_usb3_functions[] = {
static int
tegra186_xusb_read_fuse_calibration(struct tegra186_xusb_padctl *padctl)
{
+ const struct tegra_xusb_padctl_soc *soc = padctl->base.soc;
struct device *dev = padctl->base.dev;
unsigned int i, count;
u32 value, *level;
+ u32 *hs_term_range_adj;
int err;
- count = padctl->base.soc->ports.usb2.count;
+ count = soc->ports.usb2.count;
level = devm_kcalloc(dev, count, sizeof(u32), GFP_KERNEL);
if (!level)
return -ENOMEM;
+ hs_term_range_adj = devm_kcalloc(dev, count, sizeof(u32), GFP_KERNEL);
+ if (!hs_term_range_adj)
+ return -ENOMEM;
+
err = tegra_fuse_readl(TEGRA_FUSE_SKU_CALIB_0, &value);
if (err)
return dev_err_probe(dev, err,
@@ -1490,8 +1496,8 @@ tegra186_xusb_read_fuse_calibration(struct tegra186_xusb_padctl *padctl)
padctl->calib.hs_squelch = (value >> HS_SQUELCH_SHIFT) &
HS_SQUELCH_MASK;
- padctl->calib.hs_term_range_adj = (value >> HS_TERM_RANGE_ADJ_SHIFT) &
- HS_TERM_RANGE_ADJ_MASK;
+ hs_term_range_adj[0] = (value >> HS_TERM_RANGE_ADJ_PADX_SHIFT(0)) &
+ HS_TERM_RANGE_ADJ_PAD_MASK;
err = tegra_fuse_readl(TEGRA_FUSE_USB_CALIB_EXT_0, &value);
if (err) {
@@ -1503,6 +1509,17 @@ tegra186_xusb_read_fuse_calibration(struct tegra186_xusb_padctl *padctl)
padctl->calib.rpd_ctrl = (value >> RPD_CTRL_SHIFT) & RPD_CTRL_MASK;
+ for (i = 1; i < count; i++) {
+ if (soc->has_per_pad_term)
+ hs_term_range_adj[i] =
+ (value >> HS_TERM_RANGE_ADJ_PADX_SHIFT(i)) &
+ HS_TERM_RANGE_ADJ_PAD_MASK;
+ else
+ hs_term_range_adj[i] = hs_term_range_adj[0];
+ }
+
+ padctl->calib.hs_term_range_adj = hs_term_range_adj;
+
return 0;
}
@@ -1708,6 +1725,7 @@ const struct tegra_xusb_padctl_soc tegra194_xusb_padctl_soc = {
.num_supplies = ARRAY_SIZE(tegra194_xusb_padctl_supply_names),
.supports_gen2 = true,
.poll_trk_completed = true,
+ .has_per_pad_term = true,
};
EXPORT_SYMBOL_GPL(tegra194_xusb_padctl_soc);
@@ -1732,6 +1750,7 @@ const struct tegra_xusb_padctl_soc tegra234_xusb_padctl_soc = {
.trk_hw_mode = false,
.trk_update_on_idle = true,
.supports_lp_cfg_en = true,
+ .has_per_pad_term = true,
};
EXPORT_SYMBOL_GPL(tegra234_xusb_padctl_soc);
#endif
diff --git a/drivers/phy/tegra/xusb.h b/drivers/phy/tegra/xusb.h
index d2b5f956513..810b410672f 100644
--- a/drivers/phy/tegra/xusb.h
+++ b/drivers/phy/tegra/xusb.h
@@ -436,6 +436,7 @@ struct tegra_xusb_padctl_soc {
bool trk_hw_mode;
bool trk_update_on_idle;
bool supports_lp_cfg_en;
+ bool has_per_pad_term;
};
struct tegra_xusb_padctl {
--
2.43.0
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^ permalink raw reply related
* [PATCH] phy: rockchip: naneng-combphy: configure SSC for PCIe on rk3588 and rk3576
From: Shawn Lin @ 2026-03-04 10:13 UTC (permalink / raw)
To: Vinod Koul
Cc: linux-rockchip, linux-phy, Heiko Stuebner, Neil Armstrong,
linux-kernel, Shawn Lin
Add a dedicated function rk_combphy_cfg_ssc_for_pcie() to configure
Spread Spectrum Clocking (SSC) for the PCIe PHY on compatible platforms.
The function first checks the device tree node's compatible string.
Currently, SSC tuning is specifically implemented and applied only for
"rockchip,rk3588-naneng-combphy" and "rockchip,rk3576-naneng-combphy".
The correct SSC configuration for these platforms involves:
1. Enabling SSC via the RK3568_PHYREG8_SSC_EN bit.
2. Setting the PLL SSC module control via the newly defined
RK3568_PHYREG33_PLL_SSC_CTRL bit.
3. For PCIe phys with a 24MHz reference clock, additional PLL loop
divider and signal adjustment values are programmed to optimiz
performance.
This SSC configuration is intended to improve EMI characteristics or
meet specific clock tolerance requirements for PCIe interfaces on
these SoCs.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 93 +++++++++++++---------
1 file changed, 55 insertions(+), 38 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
index b60d6bf..aa09d71 100644
--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -121,6 +121,7 @@
#define RK3568_PHYREG32_SSC_OFFSET_500PPM 1
#define RK3568_PHYREG33 0x80
+#define RK3568_PHYREG33_PLL_SSC_CTRL BIT(5)
#define RK3568_PHYREG33_PLL_KVCO_MASK GENMASK(4, 2)
#define RK3568_PHYREG33_PLL_KVCO_SHIFT 2
#define RK3568_PHYREG33_PLL_KVCO_VALUE 2
@@ -964,6 +965,56 @@ static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = {
.combphy_cfg = rk3568_combphy_cfg,
};
+static void rk_combphy_cfg_ssc_for_pcie(struct rockchip_combphy_priv *priv, unsigned long rate)
+{
+ struct device_node *np = priv->dev->of_node;
+ u32 val;
+
+ /* Some SoCs' combphys share the same PCIe SSC tuning result */
+ if (!of_device_is_compatible(np, "rockchip,rk3588-naneng-combphy") ||
+ !of_device_is_compatible(np, "rockchip,rk3576-naneng-combphy")) {
+ dev_warn(priv->dev, "Incompatible platform\n");
+ return;
+ }
+
+ val = readl(priv->mmio + RK3568_PHYREG8);
+ val |= RK3568_PHYREG8_SSC_EN;
+ writel(val, priv->mmio + RK3568_PHYREG8);
+
+ /* PLL control SSC module period should be set */
+ val = readl(priv->mmio + RK3568_PHYREG33);
+ val |= RK3568_PHYREG33_PLL_SSC_CTRL;
+ writel(val, priv->mmio + RK3568_PHYREG33);
+
+ if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_24MHz) {
+ /* Set PLL loop divider */
+ writel(0x00, priv->mmio + RK3576_PHYREG17);
+ writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18);
+
+ /* Set up rx_pck invert and rx msb to disable */
+ writel(0x00, priv->mmio + RK3588_PHYREG27);
+
+ /*
+ * Set up SU adjust signal:
+ * su_trim[7:0], PLL KVCO adjust bits[2:0] to min
+ * su_trim[15:8], PLL LPF R1 adujst bits[9:7]=3'b101
+ * su_trim[23:16], CKRCV adjust
+ * su_trim[31:24], CKDRV adjust
+ */
+ writel(0x90, priv->mmio + RK3568_PHYREG11);
+ writel(0x02, priv->mmio + RK3568_PHYREG12);
+ writel(0x08, priv->mmio + RK3568_PHYREG13);
+ writel(0x57, priv->mmio + RK3568_PHYREG14);
+ writel(0x40, priv->mmio + RK3568_PHYREG15);
+
+ writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16);
+
+ val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK,
+ RK3576_PHYREG33_PLL_KVCO_VALUE);
+ writel(val, priv->mmio + RK3568_PHYREG33);
+ }
+}
+
static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
{
const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
@@ -1156,39 +1207,8 @@ static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
}
}
- if (priv->enable_ssc) {
- val = readl(priv->mmio + RK3568_PHYREG8);
- val |= RK3568_PHYREG8_SSC_EN;
- writel(val, priv->mmio + RK3568_PHYREG8);
-
- if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_24MHz) {
- /* Set PLL loop divider */
- writel(0x00, priv->mmio + RK3576_PHYREG17);
- writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18);
-
- /* Set up rx_pck invert and rx msb to disable */
- writel(0x00, priv->mmio + RK3588_PHYREG27);
-
- /*
- * Set up SU adjust signal:
- * su_trim[7:0], PLL KVCO adjust bits[2:0] to min
- * su_trim[15:8], PLL LPF R1 adujst bits[9:7]=3'b101
- * su_trim[23:16], CKRCV adjust
- * su_trim[31:24], CKDRV adjust
- */
- writel(0x90, priv->mmio + RK3568_PHYREG11);
- writel(0x02, priv->mmio + RK3568_PHYREG12);
- writel(0x08, priv->mmio + RK3568_PHYREG13);
- writel(0x57, priv->mmio + RK3568_PHYREG14);
- writel(0x40, priv->mmio + RK3568_PHYREG15);
-
- writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16);
-
- val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK,
- RK3576_PHYREG33_PLL_KVCO_VALUE);
- writel(val, priv->mmio + RK3568_PHYREG33);
- }
- }
+ if (priv->enable_ssc)
+ rk_combphy_cfg_ssc_for_pcie(priv, rate);
return 0;
}
@@ -1371,11 +1391,8 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
}
}
- if (priv->enable_ssc) {
- val = readl(priv->mmio + RK3568_PHYREG8);
- val |= RK3568_PHYREG8_SSC_EN;
- writel(val, priv->mmio + RK3568_PHYREG8);
- }
+ if (priv->enable_ssc)
+ rk_combphy_cfg_ssc_for_pcie(priv, rate);
return 0;
}
--
2.7.4
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^ permalink raw reply related
* Re: [PATCH 1/8] dt-bindings: clock, reset: Add econet EN751221 bindings
From: Caleb James DeLisle @ 2026-03-04 9:57 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: linux-mips, naseefkm, mturquette, sboyd, robh, krzk+dt, conor+dt,
tsbogend, ryder.lee, jianjun.wang, lpieralisi, kwilczynski, mani,
bhelgaas, vkoul, neil.armstrong, p.zabel, matthias.bgg,
angelogioacchino.delregno, nbd, ansuelsmth, linux-clk, devicetree,
linux-kernel, linux-pci, linux-mediatek, linux-phy,
linux-arm-kernel
In-Reply-To: <419c552a-a57f-4f67-9923-5315ea43a4d9@kernel.org>
On 04/03/2026 10:46, Krzysztof Kozlowski wrote:
> On 04/03/2026 10:09, Caleb James DeLisle wrote:
>>>> +
>>>> +description:
>>>> + The EcoNet chip-scu block provides a configuration interface for clock,
>>>> + io-muxing and other functionalities used by multiple controllers (e.g. clock,
>>>> + pinctrl, ecc) on EN751221 SoC.
>>>> +
>>>> +properties:
>>>> + compatible:
>>>> + items:
>>>> + - const: econet,en751221-chip-scu
>>>> + - const: syscon
>>> And it does not fit existing syscon bindings file, because ... ?
>>
>> If you're asking why it needs to be named "econet,en751221-chip-scu" and
> No, I am asking why you cannot put it with other syscon bindings - git
> grep syscon? What is missing here (we expect complete binding for given
> hardware)?
Ahh so mfd/bindings/syscon.yaml, that looks fine to me. Two reasons I
didn't do that: 1. didn't know it existed, 2. Assumed
arm/airoha,en7581-chip-scu.yaml was done The Best Way Possible. I'll be
happy to re-send using syscon.yaml
Thanks,
Caleb
>
>
> Best regards,
> Krzysztof
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* Re: [PATCH 1/8] dt-bindings: clock, reset: Add econet EN751221 bindings
From: Krzysztof Kozlowski @ 2026-03-04 9:46 UTC (permalink / raw)
To: Caleb James DeLisle
Cc: linux-mips, naseefkm, mturquette, sboyd, robh, krzk+dt, conor+dt,
tsbogend, ryder.lee, jianjun.wang, lpieralisi, kwilczynski, mani,
bhelgaas, vkoul, neil.armstrong, p.zabel, matthias.bgg,
angelogioacchino.delregno, nbd, ansuelsmth, linux-clk, devicetree,
linux-kernel, linux-pci, linux-mediatek, linux-phy,
linux-arm-kernel
In-Reply-To: <7888e449-fec9-4a23-8133-ad0c9651a354@cjdns.fr>
On 04/03/2026 10:09, Caleb James DeLisle wrote:
>>> +
>>> +description:
>>> + The EcoNet chip-scu block provides a configuration interface for clock,
>>> + io-muxing and other functionalities used by multiple controllers (e.g. clock,
>>> + pinctrl, ecc) on EN751221 SoC.
>>> +
>>> +properties:
>>> + compatible:
>>> + items:
>>> + - const: econet,en751221-chip-scu
>>> + - const: syscon
>> And it does not fit existing syscon bindings file, because ... ?
>
>
> If you're asking why it needs to be named "econet,en751221-chip-scu" and
No, I am asking why you cannot put it with other syscon bindings - git
grep syscon? What is missing here (we expect complete binding for given
hardware)?
Best regards,
Krzysztof
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* [PATCH v15 9/9] arm64: dts: rockchip: rk3399-evb-ind: Add support for DisplayPort
From: Chaoyi Chen @ 2026-03-04 9:41 UTC (permalink / raw)
To: Heikki Krogerus, Greg Kroah-Hartman, Dmitry Baryshkov, Peter Chen,
Luca Ceresoli, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Vinod Koul, Kishon Vijay Abraham I, Heiko Stuebner, Sandy Huang,
Andy Yan, Yubing Zhang, Frank Wang, Andrzej Hajda, Neil Armstrong,
Robert Foss, Laurent Pinchart, Jonas Karlman, Jernej Skrabec,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Amit Sunil Dhamne, Dragan Simic, Johan Jonker,
Diederik de Haas, Peter Robinson, Hugh Cole-Baker
Cc: linux-usb, devicetree, linux-kernel, linux-phy, linux-arm-kernel,
linux-rockchip, dri-devel, Chaoyi Chen
In-Reply-To: <20260304094152.92-1-kernel@airkyi.com>
From: Chaoyi Chen <chaoyi.chen@rock-chips.com>
The RK3399 EVB IND board has a Type-C interface DisplayPort.
It use fusb302 chip as Type-C controller.
fusb302 chip ---> USB/DP PHY0 <----> CDN-DP controller
Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
---
(no changes since v10)
Changes in v9:
- Add usb role switch for Type-C.
- Remove USB2 PHY in Type-C connection.
(no changes since v4)
Changes in v3:
- Fix wrong vdo value.
- Fix port node in usb-c-connector.
Changes in v2:
- Add endpoint to link DP PHY and DP controller.
- Fix devicetree coding style.
---
.../boot/dts/rockchip/rk3399-evb-ind.dts | 147 ++++++++++++++++++
1 file changed, 147 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-evb-ind.dts b/arch/arm64/boot/dts/rockchip/rk3399-evb-ind.dts
index 70aee1ab904c..be1e90f7a453 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-evb-ind.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-evb-ind.dts
@@ -4,6 +4,7 @@
*/
/dts-v1/;
+#include <dt-bindings/usb/pd.h>
#include "rk3399.dtsi"
/ {
@@ -19,6 +20,21 @@ chosen {
stdout-path = "serial2:1500000n8";
};
+ sound: sound {
+ compatible = "rockchip,rk3399-gru-sound";
+ rockchip,cpu = <&i2s0 &spdif>;
+ };
+
+ vbus_typec: regulator-vbus-typec {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_typec0_en>;
+ regulator-name = "vbus_typec";
+ vin-supply = <&vcc5v0_sys>;
+ };
+
vcc5v0_sys: regulator-vcc5v0-sys {
compatible = "regulator-fixed";
enable-active-high;
@@ -31,6 +47,11 @@ vcc5v0_sys: regulator-vcc5v0-sys {
};
};
+&cdn_dp {
+ phys = <&tcphy0_dp>;
+ status = "okay";
+};
+
&cpu_b0 {
cpu-supply = <&vdd_cpu_b>;
};
@@ -55,6 +76,12 @@ &cpu_l3 {
cpu-supply = <&vdd_cpu_l>;
};
+&dp_out {
+ dp_controller_output: endpoint {
+ remote-endpoint = <&dp_phy_in>;
+ };
+};
+
&emmc_phy {
status = "okay";
};
@@ -341,6 +368,71 @@ regulator-state-mem {
};
};
+&i2c4 {
+ i2c-scl-rising-time-ns = <475>;
+ i2c-scl-falling-time-ns = <26>;
+ status = "okay";
+
+ usbc0: typec-portc@22 {
+ compatible = "fcs,fusb302";
+ reg = <0x22>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usbc0_int>;
+ vbus-supply = <&vbus_typec>;
+
+ usb_con: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ data-role = "dual";
+ power-role = "dual";
+ try-power-role = "sink";
+ op-sink-microwatt = <1000000>;
+ sink-pdos =
+ <PDO_FIXED(5000, 2500, PDO_FIXED_USB_COMM)>;
+ source-pdos =
+ <PDO_FIXED(5000, 1500, PDO_FIXED_USB_COMM)>;
+
+ altmodes {
+ displayport {
+ svid = /bits/ 16 <0xff01>;
+ vdo = <0x00001c46>;
+ };
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usbc0_orien_sw: endpoint {
+ remote-endpoint = <&tcphy0_orientation_switch>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usbc0_role_sw: endpoint {
+ remote-endpoint = <&dwc3_0_role_switch>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ dp_altmode_mux: endpoint {
+ remote-endpoint = <&tcphy0_typec_dp>;
+ };
+ };
+ };
+ };
+ };
+};
+
&i2s2 {
status = "okay";
};
@@ -354,6 +446,16 @@ &io_domains {
};
&pinctrl {
+ usb-typec {
+ usbc0_int: usbc0-int {
+ rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+
+ vcc5v0_typec0_en: vcc5v0-typec0-en {
+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
@@ -400,10 +502,48 @@ &sdmmc {
status = "okay";
};
+&sound {
+ rockchip,codec = <&cdn_dp>;
+ status = "okay";
+};
+
+&spdif {
+ status = "okay";
+};
+
&tcphy0 {
status = "okay";
};
+&tcphy0_dp {
+ mode-switch;
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcphy0_typec_dp: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&dp_altmode_mux>;
+ };
+
+ dp_phy_in: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&dp_controller_output>;
+ };
+ };
+};
+
+&tcphy0_usb3 {
+ orientation-switch;
+
+ port {
+ tcphy0_orientation_switch: endpoint {
+ remote-endpoint = <&usbc0_orien_sw>;
+ };
+ };
+};
+
&tcphy1 {
status = "okay";
};
@@ -461,7 +601,14 @@ &usb_host1_ohci {
};
&usbdrd_dwc3_0 {
+ usb-role-switch;
status = "okay";
+
+ port {
+ dwc3_0_role_switch: endpoint {
+ remote-endpoint = <&usbc0_role_sw>;
+ };
+ };
};
&usbdrd3_0 {
--
2.51.1
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* [PATCH v15 6/9] drm/rockchip: cdn-dp: Support handle lane info without extcon
From: Chaoyi Chen @ 2026-03-04 9:41 UTC (permalink / raw)
To: Heikki Krogerus, Greg Kroah-Hartman, Dmitry Baryshkov, Peter Chen,
Luca Ceresoli, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Vinod Koul, Kishon Vijay Abraham I, Heiko Stuebner, Sandy Huang,
Andy Yan, Yubing Zhang, Frank Wang, Andrzej Hajda, Neil Armstrong,
Robert Foss, Laurent Pinchart, Jonas Karlman, Jernej Skrabec,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Amit Sunil Dhamne, Dragan Simic, Johan Jonker,
Diederik de Haas, Peter Robinson, Hugh Cole-Baker
Cc: linux-usb, devicetree, linux-kernel, linux-phy, linux-arm-kernel,
linux-rockchip, dri-devel, Chaoyi Chen
In-Reply-To: <20260304094152.92-1-kernel@airkyi.com>
From: Chaoyi Chen <chaoyi.chen@rock-chips.com>
This patch add support for get PHY lane info without help of extcon.
There is no extcon needed if the Type-C controller is present. In this
case, the lane info can be get from PHY instead of extcon.
The extcon device should still be supported if Type-C controller is
not present.
Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
---
(no changes since v5)
Changes in v4:
- Remove cdn_dp_hpd_notify().
(no changes since v3)
Changes in v2:
- Ignore duplicate HPD events.
---
drivers/gpu/drm/rockchip/cdn-dp-core.c | 25 +++++++++++++++++--------
1 file changed, 17 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.c b/drivers/gpu/drm/rockchip/cdn-dp-core.c
index b7e3f5dcf8d5..1e27301584a4 100644
--- a/drivers/gpu/drm/rockchip/cdn-dp-core.c
+++ b/drivers/gpu/drm/rockchip/cdn-dp-core.c
@@ -156,6 +156,9 @@ static int cdn_dp_get_port_lanes(struct cdn_dp_port *port)
int dptx;
u8 lanes;
+ if (!edev)
+ return phy_get_bus_width(port->phy);
+
dptx = extcon_get_state(edev, EXTCON_DISP_DP);
if (dptx > 0) {
extcon_get_property(edev, EXTCON_DISP_DP,
@@ -219,7 +222,7 @@ static bool cdn_dp_check_sink_connection(struct cdn_dp_device *dp)
* some docks need more time to power up.
*/
while (time_before(jiffies, timeout)) {
- if (!extcon_get_state(port->extcon, EXTCON_DISP_DP))
+ if (port->extcon && !extcon_get_state(port->extcon, EXTCON_DISP_DP))
return false;
if (!cdn_dp_get_sink_count(dp, &sink_count))
@@ -385,11 +388,14 @@ static int cdn_dp_enable_phy(struct cdn_dp_device *dp, struct cdn_dp_port *port)
goto err_power_on;
}
- ret = extcon_get_property(port->extcon, EXTCON_DISP_DP,
- EXTCON_PROP_USB_TYPEC_POLARITY, &property);
- if (ret) {
- DRM_DEV_ERROR(dp->dev, "get property failed\n");
- goto err_power_on;
+ property.intval = 0;
+ if (port->extcon) {
+ ret = extcon_get_property(port->extcon, EXTCON_DISP_DP,
+ EXTCON_PROP_USB_TYPEC_POLARITY, &property);
+ if (ret) {
+ DRM_DEV_ERROR(dp->dev, "get property failed\n");
+ goto err_power_on;
+ }
}
port->lanes = cdn_dp_get_port_lanes(port);
@@ -1028,6 +1034,9 @@ static int cdn_dp_bind(struct device *dev, struct device *master, void *data)
for (i = 0; i < dp->ports; i++) {
port = dp->port[i];
+ if (!port->extcon)
+ continue;
+
port->event_nb.notifier_call = cdn_dp_pd_event;
ret = devm_extcon_register_notifier(dp->dev, port->extcon,
EXTCON_DISP_DP,
@@ -1120,14 +1129,14 @@ static int cdn_dp_probe(struct platform_device *pdev)
PTR_ERR(phy) == -EPROBE_DEFER)
return -EPROBE_DEFER;
- if (IS_ERR(extcon) || IS_ERR(phy))
+ if (IS_ERR(phy) || PTR_ERR(extcon) != -ENODEV)
continue;
port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
if (!port)
return -ENOMEM;
- port->extcon = extcon;
+ port->extcon = IS_ERR(extcon) ? NULL : extcon;
port->phy = phy;
port->dp = dp;
port->id = i;
--
2.51.1
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* [PATCH v15 5/9] phy: rockchip: phy-rockchip-typec: Add DRM AUX bridge
From: Chaoyi Chen @ 2026-03-04 9:41 UTC (permalink / raw)
To: Heikki Krogerus, Greg Kroah-Hartman, Dmitry Baryshkov, Peter Chen,
Luca Ceresoli, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Vinod Koul, Kishon Vijay Abraham I, Heiko Stuebner, Sandy Huang,
Andy Yan, Yubing Zhang, Frank Wang, Andrzej Hajda, Neil Armstrong,
Robert Foss, Laurent Pinchart, Jonas Karlman, Jernej Skrabec,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Amit Sunil Dhamne, Dragan Simic, Johan Jonker,
Diederik de Haas, Peter Robinson, Hugh Cole-Baker
Cc: linux-usb, devicetree, linux-kernel, linux-phy, linux-arm-kernel,
linux-rockchip, dri-devel, Chaoyi Chen
In-Reply-To: <20260304094152.92-1-kernel@airkyi.com>
From: Chaoyi Chen <chaoyi.chen@rock-chips.com>
Using the DRM_AUX_BRIDGE helper to create the transparent DRM bridge
device.
Signed-off-by: Chaoyi Chen <chaoyi.chen@rock-chips.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
---
(no changes since v11)
Changes in v10:
- Use drm_aux_bridge_register_from_node() instead.
(no changes since v7)
Changes in v6:
- Fix depend in Kconfig.
---
drivers/phy/rockchip/Kconfig | 2 ++
drivers/phy/rockchip/phy-rockchip-typec.c | 5 +++++
2 files changed, 7 insertions(+)
diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig
index db4adc7c53da..bcb5476222fc 100644
--- a/drivers/phy/rockchip/Kconfig
+++ b/drivers/phy/rockchip/Kconfig
@@ -120,6 +120,8 @@ config PHY_ROCKCHIP_TYPEC
tristate "Rockchip TYPEC PHY Driver"
depends on OF && (ARCH_ROCKCHIP || COMPILE_TEST)
depends on TYPEC || TYPEC=n
+ depends on DRM || DRM=n
+ select DRM_AUX_BRIDGE if DRM_BRIDGE
select EXTCON
select GENERIC_PHY
select RESET_CONTROLLER
diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c b/drivers/phy/rockchip/phy-rockchip-typec.c
index 1f5b4142cbe4..e31b778c3537 100644
--- a/drivers/phy/rockchip/phy-rockchip-typec.c
+++ b/drivers/phy/rockchip/phy-rockchip-typec.c
@@ -56,6 +56,7 @@
#include <linux/phy/phy.h>
#include <linux/usb/typec_dp.h>
#include <linux/usb/typec_mux.h>
+#include <drm/bridge/aux-bridge.h>
#define CMN_SSM_BANDGAP (0x21 << 2)
#define CMN_SSM_BIAS (0x22 << 2)
@@ -1312,6 +1313,10 @@ static int tcphy_setup_typec_mux(struct rockchip_typec_phy *tcphy)
if (!of_property_read_bool(np, "mode-switch"))
goto put_np;
+ ret = drm_aux_bridge_register_from_node(tcphy->dev, np);
+ if (ret)
+ goto put_np;
+
mux_desc.drvdata = tcphy;
mux_desc.fwnode = device_get_named_child_node(tcphy->dev, "dp-port");
mux_desc.set = tcphy_typec_mux_set;
--
2.51.1
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