* Re: [PATCH 5/5] arch: arm64: dts: qcom: Add support for PCIe3a
From: Dmitry Baryshkov @ 2026-03-05 0:02 UTC (permalink / raw)
To: Qiang Yu
Cc: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Bjorn Andersson, Konrad Dybcio,
linux-arm-msm, linux-phy, devicetree, linux-kernel
In-Reply-To: <20260304-glymur_gen5x8_phy-v1-5-849e9a72e125@oss.qualcomm.com>
On Wed, Mar 04, 2026 at 12:21:59AM -0800, Qiang Yu wrote:
> Describe PCIe3a controller and PHY. Also add required system resources
> like regulators, clocks, interrupts and registers configuration for PCIe3a.
>
> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/glymur.dtsi | 314 ++++++++++++++++++++++++++++++++++-
> 1 file changed, 313 insertions(+), 1 deletion(-)
>
> + pcie3a_phy: phy@f00000 {
> + compatible = "qcom,glymur-qmp-gen5x8-pcie-phy";
> + reg = <0 0x00f00000 0 0x10000>;
> +
> + clocks = <&gcc GCC_PCIE_PHY_3A_AUX_CLK>,
> + <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
> + <&tcsr TCSR_PCIE_3_CLKREF_EN>,
> + <&gcc GCC_PCIE_3A_PHY_RCHNG_CLK>,
> + <&gcc GCC_PCIE_3A_PIPE_CLK>,
> + <&gcc GCC_PCIE_PHY_3B_AUX_CLK>;
> + clock-names = "aux",
> + "cfg_ahb",
> + "ref",
> + "rchng",
Please align on "
> + "pipe",
> + "phy_b_aux";
> +
> + resets = <&gcc GCC_PCIE_3A_PHY_BCR>,
> + <&gcc GCC_PCIE_3A_NOCSR_COM_PHY_BCR>,
> + <&gcc GCC_PCIE_3B_PHY_BCR>,
> + <&gcc GCC_PCIE_3B_NOCSR_COM_PHY_BCR>;
> + reset-names = "phy",
> + "phy_nocsr",
> + "phy_b",
> + "phy_b_nocsr";
Should we be supplying _b components by default? What about the
platforms which might use separate 3a and 3b?
> +
> + assigned-clocks = <&gcc GCC_PCIE_3A_PHY_RCHNG_CLK>;
> + assigned-clock-rates = <100000000>;
> +
> + power-domains = <&gcc GCC_PCIE_3A_PHY_GDSC>,
> + <&gcc GCC_PCIE_3B_PHY_GDSC>;
> +
> + #clock-cells = <0>;
> + clock-output-names = "pcie3a_pipe_clk";
> +
> + #phy-cells = <0>;
> +
> + status = "disabled";
> + };
> +
> pcie4: pci@1bf0000 {
> device_type = "pci";
> compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100";
>
> --
> 2.34.1
>
--
With best wishes
Dmitry
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply
* Re: [PATCH 2/5] phy: qcom: qmp-pcie: Add multiple power-domains support
From: Dmitry Baryshkov @ 2026-03-04 23:58 UTC (permalink / raw)
To: Qiang Yu
Cc: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Bjorn Andersson, Konrad Dybcio,
linux-arm-msm, linux-phy, devicetree, linux-kernel
In-Reply-To: <20260304-glymur_gen5x8_phy-v1-2-849e9a72e125@oss.qualcomm.com>
On Wed, Mar 04, 2026 at 12:21:56AM -0800, Qiang Yu wrote:
> The Glymur SoC's 3rd PCIe instance supports 8-lane mode using two PHYs in
> a bifurcated configuration. Each PHY has its own power domain (phy_gdsc)
> that must be powered on before initialization per hardware requirements.
>
> Current PHY power management assumes a single power domain per PHY,
> preventing proper setup for this dual-PHY scenario. Add support for
> multiple power domains by using devm_pm_domain_attach_list() to attach
> power domains manually, while maintaining compatibility with single
> power domain PHYs.
>
> Enable runtime PM to allow power domain control when the PCIe driver
> calls phy_power_on/phy_power_off:
>
> - Single power domain: QMP PHY platform device directly attaches to
> power domain and controls it during runtime resume/suspend
> - Multiple power domains: devm_pm_domain_attach_list() creates virtual
> devices as power domain suppliers, linked to the QMP PHY platform
> device as consumer
>
> This ensures power domains are properly attached and turned on/off
> for both single and multiple power domain configurations.
>
> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> index fed2fc9bb31108d51f88d34f3379c7744681f485..7369c291be51aa1ad7a330459dcb857f5a1988f6 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> @@ -17,6 +17,7 @@
> #include <linux/phy/pcie.h>
> #include <linux/phy/phy.h>
> #include <linux/platform_device.h>
> +#include <linux/pm_domain.h>
> #include <linux/regmap.h>
> #include <linux/regulator/consumer.h>
> #include <linux/reset.h>
> @@ -3334,6 +3335,8 @@ struct qmp_pcie {
>
> struct clk_fixed_rate pipe_clk_fixed;
> struct clk_fixed_rate aux_clk_fixed;
> +
> + struct dev_pm_domain_list *pd_list;
> };
>
> static bool qphy_checkbits(const void __iomem *base, u32 offset, u32 val)
> @@ -5348,6 +5351,16 @@ static int qmp_pcie_probe(struct platform_device *pdev)
> WARN_ON_ONCE(!qmp->cfg->pwrdn_ctrl);
> WARN_ON_ONCE(!qmp->cfg->phy_status);
>
> + ret = devm_pm_domain_attach_list(dev, NULL, &qmp->pd_list);
> + if (ret < 0 && ret != -EEXIST) {
> + dev_err(dev, "Failed to attach power domain\n");
> + return ret;
> + }
> +
> + ret = devm_pm_runtime_enable(dev);
> + if (ret)
> + return ret;
These two should be separate commits.
> +
> ret = qmp_pcie_clk_init(qmp);
> if (ret)
> return ret;
>
> --
> 2.34.1
>
--
With best wishes
Dmitry
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply
* Re: [PATCH phy-next 21/22] phy: remove temporary provider compatibility from consumer header
From: Dmitry Baryshkov @ 2026-03-04 23:56 UTC (permalink / raw)
To: Vladimir Oltean
Cc: linux-phy, Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-sunxi,
linux-tegra, linux-usb, netdev, spacemit, UNGLinuxDriver
In-Reply-To: <20260304175735.2660419-22-vladimir.oltean@nxp.com>
On Wed, Mar 04, 2026 at 07:57:34PM +0200, Vladimir Oltean wrote:
> Now that all consumers have been updated to no longer dereference fields
> inside struct phy, we can hide its definition altogether from public view.
>
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> ---
> include/linux/phy/phy.h | 2 --
> 1 file changed, 2 deletions(-)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
--
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^ permalink raw reply
* Re: [PATCH phy-next 20/22] phy: include PHY provider header
From: Dmitry Baryshkov @ 2026-03-04 23:56 UTC (permalink / raw)
To: Vladimir Oltean
Cc: linux-phy, Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-sunxi,
linux-tegra, linux-usb, netdev, spacemit, UNGLinuxDriver
In-Reply-To: <20260304175735.2660419-21-vladimir.oltean@nxp.com>
On Wed, Mar 04, 2026 at 07:57:33PM +0200, Vladimir Oltean wrote:
> The majority of PHY drivers are PHY providers (obviously).
>
> Some are providers *and* consumers (phy-meson-axg-mipi-dphy,
> phy-meson-axg-pcie). These are the Amlogic AXG SoCs, which split the
> physical layer into two chained PHYs: the digital layer and the analog
> layer. The DSI or PCIe controller interacts only with the digital PHY,
> presumably for simplicity.
>
> The rest of PHY drivers which include <linux/phy/phy.h> do so because
> they call phy_set_bus_width(), a consumer function.
>
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> ---
> drivers/phy/allwinner/phy-sun4i-usb.c | 3 ++-
> drivers/phy/allwinner/phy-sun50i-usb3.c | 3 ++-
> drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 4 ++--
> drivers/phy/allwinner/phy-sun9i-usb.c | 3 ++-
> drivers/phy/amlogic/phy-meson-axg-mipi-dphy.c | 2 ++
> drivers/phy/amlogic/phy-meson-axg-mipi-pcie-analog.c | 3 ++-
> drivers/phy/amlogic/phy-meson-axg-pcie.c | 2 ++
> drivers/phy/amlogic/phy-meson-g12a-mipi-dphy-analog.c | 3 ++-
> drivers/phy/amlogic/phy-meson-g12a-usb2.c | 2 ++
> drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c | 3 ++-
> drivers/phy/amlogic/phy-meson-gxl-usb2.c | 3 ++-
> drivers/phy/amlogic/phy-meson8-hdmi-tx.c | 3 ++-
> drivers/phy/amlogic/phy-meson8b-usb2.c | 3 ++-
> drivers/phy/apple/atc.c | 3 ++-
> drivers/phy/broadcom/phy-bcm-cygnus-pcie.c | 3 ++-
> drivers/phy/broadcom/phy-bcm-kona-usb2.c | 4 +++-
> drivers/phy/broadcom/phy-bcm-ns-usb2.c | 3 ++-
> drivers/phy/broadcom/phy-bcm-ns-usb3.c | 3 ++-
> drivers/phy/broadcom/phy-bcm-ns2-pcie.c | 3 ++-
> drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c | 3 ++-
> drivers/phy/broadcom/phy-bcm-sr-pcie.c | 3 ++-
> drivers/phy/broadcom/phy-bcm-sr-usb.c | 3 ++-
> drivers/phy/broadcom/phy-bcm63xx-usbh.c | 3 ++-
> drivers/phy/broadcom/phy-brcm-sata.c | 3 ++-
> drivers/phy/broadcom/phy-brcm-usb.c | 2 +-
> drivers/phy/cadence/cdns-dphy-rx.c | 3 ++-
> drivers/phy/cadence/cdns-dphy.c | 4 ++--
> drivers/phy/cadence/phy-cadence-salvo.c | 3 ++-
> drivers/phy/cadence/phy-cadence-sierra.c | 3 ++-
> drivers/phy/cadence/phy-cadence-torrent.c | 3 ++-
> drivers/phy/canaan/phy-k230-usb.c | 3 ++-
> drivers/phy/eswin/phy-eic7700-sata.c | 3 ++-
> drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c | 3 ++-
> drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 4 ++--
> drivers/phy/freescale/phy-fsl-imx8mq-usb.c | 3 ++-
> drivers/phy/freescale/phy-fsl-imx8qm-hsio.c | 6 +++---
> drivers/phy/freescale/phy-fsl-imx8qm-lvds-phy.c | 3 ++-
> drivers/phy/freescale/phy-fsl-lynx-28g.c | 3 ++-
> drivers/phy/hisilicon/phy-hi3660-usb3.c | 3 ++-
> drivers/phy/hisilicon/phy-hi3670-pcie.c | 3 ++-
> drivers/phy/hisilicon/phy-hi3670-usb3.c | 3 ++-
> drivers/phy/hisilicon/phy-hi6220-usb.c | 3 ++-
> drivers/phy/hisilicon/phy-hisi-inno-usb2.c | 4 +++-
> drivers/phy/hisilicon/phy-histb-combphy.c | 3 ++-
> drivers/phy/hisilicon/phy-hix5hd2-sata.c | 3 ++-
> drivers/phy/ingenic/phy-ingenic-usb.c | 3 ++-
> drivers/phy/intel/phy-intel-keembay-emmc.c | 3 ++-
> drivers/phy/intel/phy-intel-keembay-usb.c | 3 ++-
> drivers/phy/intel/phy-intel-lgm-combo.c | 4 ++--
> drivers/phy/intel/phy-intel-lgm-emmc.c | 3 ++-
> drivers/phy/lantiq/phy-lantiq-rcu-usb2.c | 3 ++-
> drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c | 4 ++--
> drivers/phy/marvell/phy-armada375-usb2.c | 3 ++-
> drivers/phy/marvell/phy-armada38x-comphy.c | 3 ++-
> drivers/phy/marvell/phy-berlin-sata.c | 3 ++-
> drivers/phy/marvell/phy-berlin-usb.c | 3 ++-
> drivers/phy/marvell/phy-mmp3-hsic.c | 3 ++-
> drivers/phy/marvell/phy-mmp3-usb.c | 3 ++-
> drivers/phy/marvell/phy-mvebu-a3700-comphy.c | 3 ++-
> drivers/phy/marvell/phy-mvebu-a3700-utmi.c | 3 ++-
> drivers/phy/marvell/phy-mvebu-cp110-comphy.c | 3 ++-
> drivers/phy/marvell/phy-mvebu-cp110-utmi.c | 3 ++-
> drivers/phy/marvell/phy-mvebu-sata.c | 3 ++-
> drivers/phy/marvell/phy-pxa-28nm-hsic.c | 3 ++-
> drivers/phy/marvell/phy-pxa-28nm-usb2.c | 3 ++-
> drivers/phy/marvell/phy-pxa-usb.c | 3 ++-
> drivers/phy/mediatek/phy-mtk-dp.c | 3 ++-
> drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c | 1 -
> drivers/phy/mediatek/phy-mtk-hdmi.h | 3 ++-
> drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c | 2 +-
> drivers/phy/mediatek/phy-mtk-mipi-dsi.h | 3 ++-
> drivers/phy/mediatek/phy-mtk-pcie.c | 2 +-
> drivers/phy/mediatek/phy-mtk-tphy.c | 2 +-
> drivers/phy/mediatek/phy-mtk-ufs.c | 2 +-
> drivers/phy/mediatek/phy-mtk-xfi-tphy.c | 2 +-
> drivers/phy/mediatek/phy-mtk-xsphy.c | 2 +-
> drivers/phy/microchip/lan966x_serdes.c | 4 ++--
> drivers/phy/microchip/sparx5_serdes.c | 2 +-
> drivers/phy/motorola/phy-cpcap-usb.c | 3 ++-
> drivers/phy/motorola/phy-mapphone-mdm6600.c | 4 +++-
> drivers/phy/mscc/phy-ocelot-serdes.c | 3 ++-
> drivers/phy/nuvoton/phy-ma35d1-usb2.c | 3 ++-
> drivers/phy/phy-airoha-pcie.c | 2 +-
> drivers/phy/phy-can-transceiver.c | 3 ++-
> drivers/phy/phy-core-mipi-dphy.c | 4 ++--
> drivers/phy/phy-core.c | 2 ++
> drivers/phy/phy-google-usb.c | 3 ++-
> drivers/phy/phy-lpc18xx-usb-otg.c | 3 ++-
> drivers/phy/phy-nxp-ptn3222.c | 3 ++-
> drivers/phy/phy-pistachio-usb.c | 4 ++--
> drivers/phy/phy-snps-eusb2.c | 2 ++
> drivers/phy/phy-xgene.c | 3 ++-
> drivers/phy/qualcomm/phy-ath79-usb.c | 3 ++-
> drivers/phy/qualcomm/phy-qcom-apq8064-sata.c | 3 ++-
> drivers/phy/qualcomm/phy-qcom-edp.c | 3 ++-
> drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c | 3 ++-
> drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c | 3 ++-
> drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c | 3 ++-
> drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c | 3 ++-
> drivers/phy/qualcomm/phy-qcom-m31-eusb2.c | 2 ++
> drivers/phy/qualcomm/phy-qcom-m31.c | 3 ++-
> drivers/phy/qualcomm/phy-qcom-pcie2.c | 3 ++-
> drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 3 ++-
> drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 3 ++-
> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 3 ++-
> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 3 ++-
> drivers/phy/qualcomm/phy-qcom-qmp-usb-legacy.c | 3 ++-
> drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 3 ++-
> drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 3 ++-
> drivers/phy/qualcomm/phy-qcom-qusb2.c | 4 ++--
> drivers/phy/qualcomm/phy-qcom-sgmii-eth.c | 3 ++-
> drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c | 3 ++-
> drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c | 3 ++-
> drivers/phy/qualcomm/phy-qcom-usb-hs-28nm.c | 3 ++-
> drivers/phy/qualcomm/phy-qcom-usb-hs.c | 3 ++-
> drivers/phy/qualcomm/phy-qcom-usb-hsic.c | 3 ++-
> drivers/phy/qualcomm/phy-qcom-usb-ss.c | 3 ++-
> drivers/phy/ralink/phy-mt7621-pci.c | 3 ++-
> drivers/phy/ralink/phy-ralink-usb.c | 3 ++-
> drivers/phy/realtek/phy-rtk-usb2.c | 3 ++-
> drivers/phy/realtek/phy-rtk-usb3.c | 3 ++-
> drivers/phy/renesas/phy-rcar-gen2.c | 3 ++-
> drivers/phy/renesas/phy-rcar-gen3-pcie.c | 3 ++-
> drivers/phy/renesas/phy-rcar-gen3-usb2.c | 3 ++-
> drivers/phy/renesas/phy-rcar-gen3-usb3.c | 3 ++-
> drivers/phy/renesas/phy-rzg3e-usb3.c | 3 ++-
> drivers/phy/renesas/r8a779f0-ether-serdes.c | 3 ++-
> drivers/phy/rockchip/phy-rockchip-dp.c | 3 ++-
> drivers/phy/rockchip/phy-rockchip-dphy-rx0.c | 3 ++-
> drivers/phy/rockchip/phy-rockchip-emmc.c | 3 ++-
> drivers/phy/rockchip/phy-rockchip-inno-csidphy.c | 3 ++-
> drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c | 4 ++--
> drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 2 ++
> drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 3 ++-
> drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 3 ++-
> drivers/phy/rockchip/phy-rockchip-pcie.c | 2 +-
> drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c | 3 ++-
> drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 2 ++
> drivers/phy/rockchip/phy-rockchip-snps-pcie3.c | 3 ++-
> drivers/phy/rockchip/phy-rockchip-typec.c | 4 ++--
> drivers/phy/rockchip/phy-rockchip-usb.c | 3 ++-
> drivers/phy/rockchip/phy-rockchip-usbdp.c | 2 ++
> drivers/phy/samsung/phy-exynos-dp-video.c | 3 ++-
> drivers/phy/samsung/phy-exynos-mipi-video.c | 3 ++-
> drivers/phy/samsung/phy-exynos-pcie.c | 3 ++-
> drivers/phy/samsung/phy-exynos4210-usb2.c | 3 ++-
> drivers/phy/samsung/phy-exynos4x12-usb2.c | 3 ++-
> drivers/phy/samsung/phy-exynos5-usbdrd.c | 2 ++
> drivers/phy/samsung/phy-exynos5250-sata.c | 3 ++-
> drivers/phy/samsung/phy-exynos5250-usb2.c | 3 ++-
> drivers/phy/samsung/phy-s5pv210-usb2.c | 3 ++-
> drivers/phy/samsung/phy-samsung-ufs.c | 2 +-
> drivers/phy/samsung/phy-samsung-ufs.h | 3 ++-
> drivers/phy/samsung/phy-samsung-usb2.c | 2 ++
> drivers/phy/samsung/phy-samsung-usb2.h | 3 ++-
> drivers/phy/socionext/phy-uniphier-ahci.c | 3 ++-
> drivers/phy/socionext/phy-uniphier-pcie.c | 3 ++-
> drivers/phy/socionext/phy-uniphier-usb2.c | 3 ++-
> drivers/phy/socionext/phy-uniphier-usb3hs.c | 3 ++-
> drivers/phy/socionext/phy-uniphier-usb3ss.c | 3 ++-
> drivers/phy/sophgo/phy-cv1800-usb2.c | 3 ++-
> drivers/phy/spacemit/phy-k1-pcie.c | 4 ++--
> drivers/phy/spacemit/phy-k1-usb2.c | 3 ++-
> drivers/phy/st/phy-miphy28lp.c | 4 ++--
> drivers/phy/st/phy-spear1310-miphy.c | 3 ++-
> drivers/phy/st/phy-spear1340-miphy.c | 3 ++-
> drivers/phy/st/phy-stih407-usb.c | 3 ++-
> drivers/phy/st/phy-stm32-combophy.c | 3 ++-
> drivers/phy/st/phy-stm32-usbphyc.c | 2 ++
> drivers/phy/starfive/phy-jh7110-dphy-rx.c | 3 ++-
> drivers/phy/starfive/phy-jh7110-dphy-tx.c | 3 ++-
> drivers/phy/starfive/phy-jh7110-pcie.c | 3 ++-
> drivers/phy/starfive/phy-jh7110-usb.c | 3 ++-
> drivers/phy/sunplus/phy-sunplus-usb2.c | 3 ++-
> drivers/phy/tegra/phy-tegra194-p2u.c | 3 ++-
> drivers/phy/tegra/xusb-tegra124.c | 2 +-
> drivers/phy/tegra/xusb-tegra186.c | 2 +-
> drivers/phy/tegra/xusb-tegra210.c | 2 +-
> drivers/phy/tegra/xusb.c | 2 +-
> drivers/phy/ti/phy-am654-serdes.c | 3 ++-
> drivers/phy/ti/phy-da8xx-usb.c | 3 ++-
> drivers/phy/ti/phy-dm816x-usb.c | 3 ++-
> drivers/phy/ti/phy-gmii-sel.c | 3 ++-
> drivers/phy/ti/phy-omap-usb2.c | 3 ++-
> drivers/phy/ti/phy-ti-pipe3.c | 3 ++-
> drivers/phy/ti/phy-twl4030-usb.c | 3 ++-
> drivers/phy/xilinx/phy-zynqmp.c | 4 ++--
> include/linux/phy/phy-sun4i-usb.h | 2 +-
> include/linux/phy/ulpi_phy.h | 2 +-
> 189 files changed, 363 insertions(+), 193 deletions(-)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> #phy/qualcomm
--
With best wishes
Dmitry
--
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linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply
* Re: [PATCH phy-next 12/22] phy: move provider API out of public <linux/phy/phy.h>
From: Dmitry Baryshkov @ 2026-03-04 23:54 UTC (permalink / raw)
To: Vladimir Oltean
Cc: linux-phy, Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-sunxi,
linux-tegra, linux-usb, netdev, spacemit, UNGLinuxDriver
In-Reply-To: <20260304175735.2660419-13-vladimir.oltean@nxp.com>
On Wed, Mar 04, 2026 at 07:57:25PM +0200, Vladimir Oltean wrote:
> The major goal is to hide the contents of struct phy from consumer
> drivers.
>
> The idea with "phy-props.h" is that both consumers and providers make
> use of some data types. So both headers include "phy-props.h".
>
> Two slight points of contention.
>
> 1. phy_set_bus_width(): Vinod explains that despite the current caller
> situation (9 providers, 1 consumer), it is a consumer API function.
>
> The use case is that the controller (for example UFS) may have
> limitations and should set the expected lanes to be used and width on
> those lanes. A number of Generic PHYs can support multiple lanes and
> multiple width so this is way for controller telling I am using this
> configuration.
>
> 2. phy-provider.h should go to include/linux/phy/ or to drivers/phy/?
> We do have 3 PHY providers outside of drivers/phy/:
>
> drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.c
> drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
> drivers/pinctrl/tegra/pinctrl-tegra-xusb.c
>
> but the practice is not encouraged, and with time, these should be
> moved to the subsystem. This is not something that I can do now.
>
> For temporary compatibility, keep including the provider header. This
> will be removed when abuses are all gotten rid of.
>
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> ---
> drivers/phy/phy-core.c | 34 +++
> drivers/phy/phy-provider.h | 256 +++++++++++++++++
> include/linux/phy/phy-props.h | 75 +++++
> include/linux/phy/phy.h | 499 +++++++---------------------------
> 4 files changed, 458 insertions(+), 406 deletions(-)
> create mode 100644 drivers/phy/phy-provider.h
> create mode 100644 include/linux/phy/phy-props.h
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
--
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^ permalink raw reply
* Re: [PATCH phy-next 11/22] drm/msm/dp: remove debugging prints with internal struct phy state
From: Dmitry Baryshkov @ 2026-03-04 23:53 UTC (permalink / raw)
To: Vladimir Oltean
Cc: linux-phy, Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-sunxi,
linux-tegra, linux-usb, netdev, spacemit, UNGLinuxDriver,
Rob Clark, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang,
Sean Paul, Marijn Suijten, David Airlie, Simona Vetter
In-Reply-To: <20260304175735.2660419-12-vladimir.oltean@nxp.com>
On Wed, Mar 04, 2026 at 07:57:24PM +0200, Vladimir Oltean wrote:
> These do not provide much value, and will become hard to maintain once
> the Generic PHY framework starts hiding the contents of struct phy from
> consumers.
>
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> ---
> Cc: Rob Clark <robin.clark@oss.qualcomm.com>
> Cc: Dmitry Baryshkov <lumag@kernel.org>
> Cc: Abhinav Kumar <abhinav.kumar@linux.dev>
> Cc: Jessica Zhang <jesszhan0024@gmail.com>
> Cc: Sean Paul <sean@poorly.run>
> Cc: Marijn Suijten <marijn.suijten@somainline.org>
> Cc: David Airlie <airlied@gmail.com>
> Cc: Simona Vetter <simona@ffwll.ch>
> ---
> drivers/gpu/drm/msm/dp/dp_ctrl.c | 18 ------------------
> 1 file changed, 18 deletions(-)
>
Acked-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
--
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^ permalink raw reply
* [PATCH] dt-bindings: display/msm: move DSI PHY bindings to phy/ subdir
From: Dmitry Baryshkov @ 2026-03-04 23:47 UTC (permalink / raw)
To: Rob Clark, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang,
Sean Paul, Marijn Suijten, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Vinod Koul, Neil Armstrong,
Krishna Manikandan, Jonathan Marek
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
linux-phy
Historically DSI PHY bindings landed to the display/msm subdir, however
they describe PHYs and as such they should be in the phy/ subdir.
Follow the example of other Qualcomm display-related PHYs (HDMI, eDP)
and move bindings for the Qualcomm DSI PHYs to the correct subdir.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
Merge strategy: I'd ask to merge bindings through the msm tree, reducing
the conflicts for the current kernel development cycle. Starting from
the cycle after this patch is merged, DSI PHY bindings should go through
the PHY tree.
---
.../{display/msm/dsi-phy-10nm.yaml => phy/qcom,dsi-phy-10nm.yaml} | 4 ++--
.../{display/msm/dsi-phy-14nm.yaml => phy/qcom,dsi-phy-14nm.yaml} | 4 ++--
.../{display/msm/dsi-phy-20nm.yaml => phy/qcom,dsi-phy-20nm.yaml} | 4 ++--
.../{display/msm/dsi-phy-28nm.yaml => phy/qcom,dsi-phy-28nm.yaml} | 4 ++--
.../{display/msm/dsi-phy-7nm.yaml => phy/qcom,dsi-phy-7nm.yaml} | 4 ++--
.../{display/msm/dsi-phy-common.yaml => phy/qcom,dsi-phy-common.yaml} | 2 +-
6 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml b/Documentation/devicetree/bindings/phy/qcom,dsi-phy-10nm.yaml
similarity index 96%
rename from Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml
rename to Documentation/devicetree/bindings/phy/qcom,dsi-phy-10nm.yaml
index fc9abf090f0d..d98217747ad1 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,dsi-phy-10nm.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
-$id: http://devicetree.org/schemas/display/msm/dsi-phy-10nm.yaml#
+$id: http://devicetree.org/schemas/phy/qcom,dsi-phy-10nm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display DSI 10nm PHY
@@ -10,7 +10,7 @@ maintainers:
- Krishna Manikandan <quic_mkrishn@quicinc.com>
allOf:
- - $ref: dsi-phy-common.yaml#
+ - $ref: qcom,dsi-phy-common.yaml#
properties:
compatible:
diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml b/Documentation/devicetree/bindings/phy/qcom,dsi-phy-14nm.yaml
similarity index 94%
rename from Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
rename to Documentation/devicetree/bindings/phy/qcom,dsi-phy-14nm.yaml
index 206a9a4b3845..be31b9bac9d5 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,dsi-phy-14nm.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
-$id: http://devicetree.org/schemas/display/msm/dsi-phy-14nm.yaml#
+$id: http://devicetree.org/schemas/phy/qcom,dsi-phy-14nm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display DSI 14nm PHY
@@ -10,7 +10,7 @@ maintainers:
- Krishna Manikandan <quic_mkrishn@quicinc.com>
allOf:
- - $ref: dsi-phy-common.yaml#
+ - $ref: qcom,dsi-phy-common.yaml#
properties:
compatible:
diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml b/Documentation/devicetree/bindings/phy/qcom,dsi-phy-20nm.yaml
similarity index 93%
rename from Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml
rename to Documentation/devicetree/bindings/phy/qcom,dsi-phy-20nm.yaml
index 93570052992a..1d135419d015 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,dsi-phy-20nm.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
-$id: http://devicetree.org/schemas/display/msm/dsi-phy-20nm.yaml#
+$id: http://devicetree.org/schemas/phy/qcom,dsi-phy-20nm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display DSI 20nm PHY
@@ -10,7 +10,7 @@ maintainers:
- Krishna Manikandan <quic_mkrishn@quicinc.com>
allOf:
- - $ref: dsi-phy-common.yaml#
+ - $ref: qcom,dsi-phy-common.yaml#
properties:
compatible:
diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml b/Documentation/devicetree/bindings/phy/qcom,dsi-phy-28nm.yaml
similarity index 94%
rename from Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml
rename to Documentation/devicetree/bindings/phy/qcom,dsi-phy-28nm.yaml
index 371befa9f9d2..f8fe75fa29d7 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,dsi-phy-28nm.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
-$id: http://devicetree.org/schemas/display/msm/dsi-phy-28nm.yaml#
+$id: http://devicetree.org/schemas/phy/qcom,dsi-phy-28nm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display DSI 28nm PHY
@@ -10,7 +10,7 @@ maintainers:
- Krishna Manikandan <quic_mkrishn@quicinc.com>
allOf:
- - $ref: dsi-phy-common.yaml#
+ - $ref: qcom,dsi-phy-common.yaml#
properties:
compatible:
diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml b/Documentation/devicetree/bindings/phy/qcom,dsi-phy-7nm.yaml
similarity index 95%
rename from Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml
rename to Documentation/devicetree/bindings/phy/qcom,dsi-phy-7nm.yaml
index 9a9a6c4abf43..d45015e24639 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,dsi-phy-7nm.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
-$id: http://devicetree.org/schemas/display/msm/dsi-phy-7nm.yaml#
+$id: http://devicetree.org/schemas/phy/qcom,dsi-phy-7nm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display DSI 7nm PHY
@@ -10,7 +10,7 @@ maintainers:
- Jonathan Marek <jonathan@marek.ca>
allOf:
- - $ref: dsi-phy-common.yaml#
+ - $ref: qcom,dsi-phy-common.yaml#
properties:
compatible:
diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-common.yaml b/Documentation/devicetree/bindings/phy/qcom,dsi-phy-common.yaml
similarity index 91%
rename from Documentation/devicetree/bindings/display/msm/dsi-phy-common.yaml
rename to Documentation/devicetree/bindings/phy/qcom,dsi-phy-common.yaml
index d0ce85a08b6d..849321e56b2f 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi-phy-common.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,dsi-phy-common.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
-$id: http://devicetree.org/schemas/display/msm/dsi-phy-common.yaml#
+$id: http://devicetree.org/schemas/phy/qcom,dsi-phy-common.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display DSI PHY Common Properties
---
base-commit: ac47870fd795549f03d57e0879fc730c79119f4b
change-id: 20260305-msm-dsi-phy-96b063cce7b5
Best regards,
--
With best wishes
Dmitry
--
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https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH] phy: miphy28lp: kzalloc + kcalloc to single kzalloc
From: Rosen Penev @ 2026-03-04 23:28 UTC (permalink / raw)
To: linux-phy
Cc: Patrice Chotard, Vinod Koul, Neil Armstrong, Kees Cook,
Gustavo A. R. Silva, moderated list:ARM/STI ARCHITECTURE,
open list,
open list:KERNEL HARDENING (not covered by other areas):Keyword:b__counted_by(_le|_be)?b
Use flex array to simplify allocation.
Allows using __counted_by for extra runtime analysis.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
---
drivers/phy/st/phy-miphy28lp.c | 12 +++++-------
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/drivers/phy/st/phy-miphy28lp.c b/drivers/phy/st/phy-miphy28lp.c
index 43cef89af55e..fd931ede7162 100644
--- a/drivers/phy/st/phy-miphy28lp.c
+++ b/drivers/phy/st/phy-miphy28lp.c
@@ -224,8 +224,8 @@ struct miphy28lp_dev {
struct device *dev;
struct regmap *regmap;
struct mutex miphy_mutex;
- struct miphy28lp_phy **phys;
int nphys;
+ struct miphy28lp_phy *phys[] __counted_by(nphys);
};
enum miphy_sata_gen { SATA_GEN1, SATA_GEN2, SATA_GEN3 };
@@ -1168,16 +1168,14 @@ static int miphy28lp_probe(struct platform_device *pdev)
struct phy_provider *provider;
struct phy *phy;
int ret, port = 0;
+ size_t nphys;
- miphy_dev = devm_kzalloc(&pdev->dev, sizeof(*miphy_dev), GFP_KERNEL);
+ nphys = of_get_child_count(np);
+ miphy_dev = devm_kzalloc(&pdev->dev, struct_size(wiphy_dev, phys, nphys) ,GFP_KERNEL);
if (!miphy_dev)
return -ENOMEM;
- miphy_dev->nphys = of_get_child_count(np);
- miphy_dev->phys = devm_kcalloc(&pdev->dev, miphy_dev->nphys,
- sizeof(*miphy_dev->phys), GFP_KERNEL);
- if (!miphy_dev->phys)
- return -ENOMEM;
+ miphy_dev->nphys = nphys;
miphy_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
if (IS_ERR(miphy_dev->regmap)) {
--
2.53.0
--
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^ permalink raw reply related
* [PATCH] phy: qualcomm: usb-hs-28nm: use flex array
From: Rosen Penev @ 2026-03-04 23:06 UTC (permalink / raw)
To: linux-phy
Cc: Vinod Koul, Neil Armstrong, Kees Cook, Gustavo A. R. Silva,
open list:ARM/QUALCOMM MAILING LIST, open list,
open list:KERNEL HARDENING (not covered by other areas):Keyword:b__counted_by(_le|_be)?b
Allows simplifying allocation to a single kzalloc call.
Also allows using __counted_by for extra runtime analysis.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
---
drivers/phy/qualcomm/phy-qcom-usb-hs-28nm.c | 14 ++++++--------
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-usb-hs-28nm.c b/drivers/phy/qualcomm/phy-qcom-usb-hs-28nm.c
index a52a9bf13b75..b2ea038a8f25 100644
--- a/drivers/phy/qualcomm/phy-qcom-usb-hs-28nm.c
+++ b/drivers/phy/qualcomm/phy-qcom-usb-hs-28nm.c
@@ -56,13 +56,13 @@ struct hsphy_data {
struct hsphy_priv {
void __iomem *base;
- struct clk_bulk_data *clks;
int num_clks;
struct reset_control *phy_reset;
struct reset_control *por_reset;
struct regulator_bulk_data vregs[VREG_NUM];
const struct hsphy_data *data;
enum phy_mode mode;
+ struct clk_bulk_data clks[] __counted_by(num_clks);
};
static int qcom_snps_hsphy_set_mode(struct phy *phy, enum phy_mode mode,
@@ -309,23 +309,21 @@ static int qcom_snps_hsphy_probe(struct platform_device *pdev)
struct phy_provider *provider;
struct hsphy_priv *priv;
struct phy *phy;
+ size_t size;
int ret;
int i;
- priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ size = ARRAY_SIZE(qcom_snps_hsphy_clks);
+ priv = devm_kzalloc(dev, struct_size(priv, clks, size), GFP_KERNEL);
if (!priv)
return -ENOMEM;
+ priv->num_clks = size;
+
priv->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
- priv->num_clks = ARRAY_SIZE(qcom_snps_hsphy_clks);
- priv->clks = devm_kcalloc(dev, priv->num_clks, sizeof(*priv->clks),
- GFP_KERNEL);
- if (!priv->clks)
- return -ENOMEM;
-
for (i = 0; i < priv->num_clks; i++)
priv->clks[i].id = qcom_snps_hsphy_clks[i];
--
2.53.0
--
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^ permalink raw reply related
* Re: [PATCH phy-next 02/22] PCI: add missing headers transitively included by <linux/phy/phy.h>
From: Vladimir Oltean @ 2026-03-04 22:34 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: linux-phy, Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-sunxi,
linux-tegra, linux-usb, netdev, spacemit, UNGLinuxDriver,
Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas, Heiko Stuebner,
Shawn Guo, Yixun Lan, Thierry Reding, Jonathan Hunter, Shawn Lin,
Kevin Xie
In-Reply-To: <20260304222408.GA40990@bhelgaas>
On Wed, Mar 04, 2026 at 04:24:08PM -0600, Bjorn Helgaas wrote:
> Update subject line to match history:
>
> PCI: Add missing headers transitively included by <linux/phy/phy.h>
My case-insensitive brain didn't understand what you mean by this.
I had to power on my case-sensitive part :-/
> On Wed, Mar 04, 2026 at 07:57:15PM +0200, Vladimir Oltean wrote:
> > The tegra as well as a few dwc PCI controller drivers uses PM runtime
> > operations without including the required <linux/pm_runtime.h> header.
> >
> > Similarly, pcie-rockchip-host, pcie-starfive as well as a few dwc PCI
> > controllers use the regulator consumer API without including
> > <linux/regulator/consumer.h>.
> >
> > It seems these function prototypes were indirectly provided by
> > <linux/phy/phy.h>, mostly by mistake (none of the functions it exports
> > need it).
> >
> > Before the PHY header can drop the unnecessary includes, make sure the
> > PCI controller drivers include what they use.
> >
> > Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
>
> With the subject line update:
>
> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Thanks for looking!
--
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^ permalink raw reply
* Re: [PATCH phy-next 08/22] PCI: remove device links to PHY
From: Bjorn Helgaas @ 2026-03-04 22:28 UTC (permalink / raw)
To: Vladimir Oltean
Cc: linux-phy, Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-sunxi,
linux-tegra, linux-usb, netdev, spacemit, UNGLinuxDriver,
Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas,
Vignesh Raghavendra, Siddharth Vadapalli
In-Reply-To: <20260304175735.2660419-9-vladimir.oltean@nxp.com>
Update subject line to:
PCI: Remove redundant device links to PHY
On Wed, Mar 04, 2026 at 07:57:21PM +0200, Vladimir Oltean wrote:
> This is practically a full revert of commit
> 7a4db656a635 ("PCI: dra7xx: Create functional dependency between PCIe and PHY")
> and a partial revert of the device link pieces from commits
> dfb80534692d ("PCI: cadence: Add generic PHY support to host and EP drivers")
> 49229238ab47 ("PCI: keystone: Cleanup PHY handling")
>
> The trouble with these commits is that they dereference fields inside
> struct phy from a consumer driver, which will become no longer possible.
>
> Since commit 987351e1ea77 ("phy: core: Add consumer device link
> support") from 2019, the PHY core also adds a device link to order PHY
> provider and consumer suspend/resume operations. All reverted commits
> are from 2017-2018, and what they do should actually be redundant now.
>
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
With subject line update:
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Thanks for doing this; it's great to get rid of all that code.
> ---
> Cc: Lorenzo Pieralisi <lpieralisi@kernel.org>
> Cc: "Krzysztof Wilczyński" <kwilczynski@kernel.org>
> Cc: Manivannan Sadhasivam <mani@kernel.org>
> Cc: Rob Herring <robh@kernel.org>
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Cc: Vignesh Raghavendra <vigneshr@ti.com>
> Cc: Siddharth Vadapalli <s-vadapalli@ti.com>
> ---
> drivers/pci/controller/cadence/pcie-cadence.c | 16 +---------
> drivers/pci/controller/dwc/pci-dra7xx.c | 16 ----------
> drivers/pci/controller/dwc/pci-keystone.c | 31 +++----------------
> 3 files changed, 5 insertions(+), 58 deletions(-)
>
> diff --git a/drivers/pci/controller/cadence/pcie-cadence.c b/drivers/pci/controller/cadence/pcie-cadence.c
> index a1eada56edba..0ac980249941 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence.c
> +++ b/drivers/pci/controller/cadence/pcie-cadence.c
> @@ -222,7 +222,6 @@ int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie)
> struct device_node *np = dev->of_node;
> int phy_count;
> struct phy **phy;
> - struct device_link **link;
> int i;
> int ret;
> const char *name;
> @@ -238,10 +237,6 @@ int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie)
> if (!phy)
> return -ENOMEM;
>
> - link = devm_kcalloc(dev, phy_count, sizeof(*link), GFP_KERNEL);
> - if (!link)
> - return -ENOMEM;
> -
> for (i = 0; i < phy_count; i++) {
> of_property_read_string_index(np, "phy-names", i, &name);
> phy[i] = devm_phy_get(dev, name);
> @@ -249,17 +244,10 @@ int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie)
> ret = PTR_ERR(phy[i]);
> goto err_phy;
> }
> - link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS);
> - if (!link[i]) {
> - devm_phy_put(dev, phy[i]);
> - ret = -EINVAL;
> - goto err_phy;
> - }
> }
>
> pcie->phy_count = phy_count;
> pcie->phy = phy;
> - pcie->link = link;
>
> ret = cdns_pcie_enable_phy(pcie);
> if (ret)
> @@ -268,10 +256,8 @@ int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie)
> return 0;
>
> err_phy:
> - while (--i >= 0) {
> - device_link_del(link[i]);
> + while (--i >= 0)
> devm_phy_put(dev, phy[i]);
> - }
>
> return ret;
> }
> diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c
> index d5d26229063f..b91ab37845c9 100644
> --- a/drivers/pci/controller/dwc/pci-dra7xx.c
> +++ b/drivers/pci/controller/dwc/pci-dra7xx.c
> @@ -9,7 +9,6 @@
>
> #include <linux/clk.h>
> #include <linux/delay.h>
> -#include <linux/device.h>
> #include <linux/err.h>
> #include <linux/interrupt.h>
> #include <linux/irq.h>
> @@ -683,7 +682,6 @@ static int dra7xx_pcie_probe(struct platform_device *pdev)
> int i;
> int phy_count;
> struct phy **phy;
> - struct device_link **link;
> void __iomem *base;
> struct dw_pcie *pci;
> struct dra7xx_pcie *dra7xx;
> @@ -731,10 +729,6 @@ static int dra7xx_pcie_probe(struct platform_device *pdev)
> if (!phy)
> return -ENOMEM;
>
> - link = devm_kcalloc(dev, phy_count, sizeof(*link), GFP_KERNEL);
> - if (!link)
> - return -ENOMEM;
> -
> dra7xx->clk = devm_clk_get_optional(dev, NULL);
> if (IS_ERR(dra7xx->clk))
> return dev_err_probe(dev, PTR_ERR(dra7xx->clk),
> @@ -749,12 +743,6 @@ static int dra7xx_pcie_probe(struct platform_device *pdev)
> phy[i] = devm_phy_get(dev, name);
> if (IS_ERR(phy[i]))
> return PTR_ERR(phy[i]);
> -
> - link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS);
> - if (!link[i]) {
> - ret = -EINVAL;
> - goto err_link;
> - }
> }
>
> dra7xx->base = base;
> @@ -856,10 +844,6 @@ static int dra7xx_pcie_probe(struct platform_device *pdev)
> pm_runtime_disable(dev);
> dra7xx_pcie_disable_phy(dra7xx);
>
> -err_link:
> - while (--i >= 0)
> - device_link_del(link[i]);
> -
> return ret;
> }
>
> diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c
> index 642e4c45eefc..07698c645e02 100644
> --- a/drivers/pci/controller/dwc/pci-keystone.c
> +++ b/drivers/pci/controller/dwc/pci-keystone.c
> @@ -130,7 +130,6 @@ struct keystone_pcie {
> int num_lanes;
> u32 num_viewport;
> struct phy **phy;
> - struct device_link **link;
> struct device_node *msi_intc_np;
> struct irq_domain *intx_irq_domain;
> struct device_node *np;
> @@ -1118,7 +1117,6 @@ static int ks_pcie_probe(struct platform_device *pdev)
> enum dw_pcie_device_mode mode;
> struct dw_pcie *pci;
> struct keystone_pcie *ks_pcie;
> - struct device_link **link;
> struct gpio_desc *gpiod;
> struct resource *res;
> void __iomem *base;
> @@ -1189,31 +1187,17 @@ static int ks_pcie_probe(struct platform_device *pdev)
> if (!phy)
> return -ENOMEM;
>
> - link = devm_kcalloc(dev, num_lanes, sizeof(*link), GFP_KERNEL);
> - if (!link)
> - return -ENOMEM;
> -
> for (i = 0; i < num_lanes; i++) {
> snprintf(name, sizeof(name), "pcie-phy%d", i);
> phy[i] = devm_phy_optional_get(dev, name);
> if (IS_ERR(phy[i])) {
> ret = PTR_ERR(phy[i]);
> - goto err_link;
> - }
> -
> - if (!phy[i])
> - continue;
> -
> - link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS);
> - if (!link[i]) {
> - ret = -EINVAL;
> - goto err_link;
> + goto err;
> }
> }
>
> ks_pcie->np = np;
> ks_pcie->pci = pci;
> - ks_pcie->link = link;
> ks_pcie->num_lanes = num_lanes;
> ks_pcie->phy = phy;
>
> @@ -1223,7 +1207,7 @@ static int ks_pcie_probe(struct platform_device *pdev)
> ret = PTR_ERR(gpiod);
> if (ret != -EPROBE_DEFER)
> dev_err(dev, "Failed to get reset GPIO\n");
> - goto err_link;
> + goto err;
> }
>
> /* Obtain references to the PHYs */
> @@ -1238,7 +1222,7 @@ static int ks_pcie_probe(struct platform_device *pdev)
>
> if (ret) {
> dev_err(dev, "failed to enable phy\n");
> - goto err_link;
> + goto err;
> }
>
> platform_set_drvdata(pdev, ks_pcie);
> @@ -1325,25 +1309,18 @@ static int ks_pcie_probe(struct platform_device *pdev)
> pm_runtime_disable(dev);
> ks_pcie_disable_phy(ks_pcie);
>
> -err_link:
> - while (--i >= 0 && link[i])
> - device_link_del(link[i]);
> -
> +err:
> return ret;
> }
>
> static void ks_pcie_remove(struct platform_device *pdev)
> {
> struct keystone_pcie *ks_pcie = platform_get_drvdata(pdev);
> - struct device_link **link = ks_pcie->link;
> - int num_lanes = ks_pcie->num_lanes;
> struct device *dev = &pdev->dev;
>
> pm_runtime_put(dev);
> pm_runtime_disable(dev);
> ks_pcie_disable_phy(ks_pcie);
> - while (num_lanes--)
> - device_link_del(link[num_lanes]);
> }
>
> static struct platform_driver ks_pcie_driver = {
> --
> 2.43.0
>
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* Re: [PATCH phy-next 02/22] PCI: add missing headers transitively included by <linux/phy/phy.h>
From: Bjorn Helgaas @ 2026-03-04 22:24 UTC (permalink / raw)
To: Vladimir Oltean
Cc: linux-phy, Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-sunxi,
linux-tegra, linux-usb, netdev, spacemit, UNGLinuxDriver,
Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas, Heiko Stuebner,
Shawn Guo, Yixun Lan, Thierry Reding, Jonathan Hunter, Shawn Lin,
Kevin Xie
In-Reply-To: <20260304175735.2660419-3-vladimir.oltean@nxp.com>
Update subject line to match history:
PCI: Add missing headers transitively included by <linux/phy/phy.h>
On Wed, Mar 04, 2026 at 07:57:15PM +0200, Vladimir Oltean wrote:
> The tegra as well as a few dwc PCI controller drivers uses PM runtime
> operations without including the required <linux/pm_runtime.h> header.
>
> Similarly, pcie-rockchip-host, pcie-starfive as well as a few dwc PCI
> controllers use the regulator consumer API without including
> <linux/regulator/consumer.h>.
>
> It seems these function prototypes were indirectly provided by
> <linux/phy/phy.h>, mostly by mistake (none of the functions it exports
> need it).
>
> Before the PHY header can drop the unnecessary includes, make sure the
> PCI controller drivers include what they use.
>
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
With the subject line update:
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
> ---
> Cc: Lorenzo Pieralisi <lpieralisi@kernel.org>
> Cc: "Krzysztof Wilczyński" <kwilczynski@kernel.org>
> Cc: Manivannan Sadhasivam <mani@kernel.org>
> Cc: Rob Herring <robh@kernel.org>
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Cc: Heiko Stuebner <heiko@sntech.de>
> Cc: Shawn Guo <shawn.guo@linaro.org>
> Cc: Yixun Lan <dlan@kernel.org>
> Cc: Thierry Reding <thierry.reding@gmail.com>
> Cc: Jonathan Hunter <jonathanh@nvidia.com>
> Cc: Shawn Lin <shawn.lin@rock-chips.com>
> Cc: Kevin Xie <kevin.xie@starfivetech.com>
> ---
> drivers/pci/controller/dwc/pci-keystone.c | 1 +
> drivers/pci/controller/dwc/pcie-dw-rockchip.c | 1 +
> drivers/pci/controller/dwc/pcie-histb.c | 1 +
> drivers/pci/controller/dwc/pcie-qcom-ep.c | 1 +
> drivers/pci/controller/dwc/pcie-spacemit-k1.c | 2 ++
> drivers/pci/controller/dwc/pcie-tegra194.c | 1 +
> drivers/pci/controller/pci-tegra.c | 1 +
> drivers/pci/controller/pcie-rockchip-host.c | 1 +
> drivers/pci/controller/plda/pcie-starfive.c | 1 +
> 9 files changed, 10 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c
> index 20fa4dadb82a..642e4c45eefc 100644
> --- a/drivers/pci/controller/dwc/pci-keystone.c
> +++ b/drivers/pci/controller/dwc/pci-keystone.c
> @@ -24,6 +24,7 @@
> #include <linux/of_pci.h>
> #include <linux/phy/phy.h>
> #include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> #include <linux/regmap.h>
> #include <linux/resource.h>
> #include <linux/signal.h>
> diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> index 5b17da63151d..e0079ec108ab 100644
> --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> @@ -21,6 +21,7 @@
> #include <linux/phy/phy.h>
> #include <linux/platform_device.h>
> #include <linux/regmap.h>
> +#include <linux/regulator/consumer.h>
> #include <linux/reset.h>
>
> #include "../../pci.h"
> diff --git a/drivers/pci/controller/dwc/pcie-histb.c b/drivers/pci/controller/dwc/pcie-histb.c
> index a52071589377..432a54c5bfce 100644
> --- a/drivers/pci/controller/dwc/pcie-histb.c
> +++ b/drivers/pci/controller/dwc/pcie-histb.c
> @@ -18,6 +18,7 @@
> #include <linux/pci.h>
> #include <linux/phy/phy.h>
> #include <linux/platform_device.h>
> +#include <linux/regulator/consumer.h>
> #include <linux/resource.h>
> #include <linux/reset.h>
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
> index 18460f01b2c6..e417122da51d 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
> @@ -19,6 +19,7 @@
> #include <linux/phy/phy.h>
> #include <linux/platform_device.h>
> #include <linux/pm_domain.h>
> +#include <linux/pm_runtime.h>
> #include <linux/regmap.h>
> #include <linux/reset.h>
> #include <linux/module.h>
> diff --git a/drivers/pci/controller/dwc/pcie-spacemit-k1.c b/drivers/pci/controller/dwc/pcie-spacemit-k1.c
> index be20a520255b..dbec159fd458 100644
> --- a/drivers/pci/controller/dwc/pcie-spacemit-k1.c
> +++ b/drivers/pci/controller/dwc/pcie-spacemit-k1.c
> @@ -15,7 +15,9 @@
> #include <linux/mod_devicetable.h>
> #include <linux/phy/phy.h>
> #include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> #include <linux/regmap.h>
> +#include <linux/regulator/consumer.h>
> #include <linux/reset.h>
> #include <linux/types.h>
>
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index 06571d806ab3..3378a89580ab 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -27,6 +27,7 @@
> #include <linux/platform_device.h>
> #include <linux/pm_runtime.h>
> #include <linux/random.h>
> +#include <linux/regulator/consumer.h>
> #include <linux/reset.h>
> #include <linux/resource.h>
> #include <linux/types.h>
> diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c
> index 512309763d1f..a2c1662b6e81 100644
> --- a/drivers/pci/controller/pci-tegra.c
> +++ b/drivers/pci/controller/pci-tegra.c
> @@ -36,6 +36,7 @@
> #include <linux/phy/phy.h>
> #include <linux/pinctrl/consumer.h>
> #include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> #include <linux/reset.h>
> #include <linux/sizes.h>
> #include <linux/slab.h>
> diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/controller/pcie-rockchip-host.c
> index ee1822ca01db..46adb4582fcc 100644
> --- a/drivers/pci/controller/pcie-rockchip-host.c
> +++ b/drivers/pci/controller/pcie-rockchip-host.c
> @@ -24,6 +24,7 @@
> #include <linux/of_pci.h>
> #include <linux/phy/phy.h>
> #include <linux/platform_device.h>
> +#include <linux/regulator/consumer.h>
>
> #include "../pci.h"
> #include "pcie-rockchip.h"
> diff --git a/drivers/pci/controller/plda/pcie-starfive.c b/drivers/pci/controller/plda/pcie-starfive.c
> index 298036c3e7f9..22344cca167b 100644
> --- a/drivers/pci/controller/plda/pcie-starfive.c
> +++ b/drivers/pci/controller/plda/pcie-starfive.c
> @@ -21,6 +21,7 @@
> #include <linux/platform_device.h>
> #include <linux/pm_runtime.h>
> #include <linux/regmap.h>
> +#include <linux/regulator/consumer.h>
> #include <linux/reset.h>
> #include "../../pci.h"
>
> --
> 2.43.0
>
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^ permalink raw reply
* Re: [RESEND 1/1] phy: freescale: imx8qm-hsio: provide regmap names
From: Vladimir Oltean @ 2026-03-04 21:27 UTC (permalink / raw)
To: Alexander Stein
Cc: Vinod Koul, Neil Armstrong, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, linux-phy, imx,
linux-arm-kernel, linux-kernel
In-Reply-To: <20260211144949.1128122-1-alexander.stein@ew.tq-group.com>
On Wed, Feb 11, 2026 at 03:49:48PM +0100, Alexander Stein wrote:
> This driver uses multiple regmaps, which will causes name conflicts
> in debugfs like:
> debugfs: '5f1a0000.phy' already exists in 'regmap'
> Fix this by using a dedicated regmap config for each resource, each
> having a dedicated regmap name.
>
> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> ---
> Same as the one sent in December but with an updated CC list.
>
> drivers/phy/freescale/phy-fsl-imx8qm-hsio.c | 23 +++++++++++++++++----
> 1 file changed, 19 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c b/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
> index 279b8ac7822df..4ab45c9f53dff 100644
> --- a/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
> +++ b/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
> @@ -107,7 +107,22 @@ static const char * const lan2_pcieb_clks[] = {"apb_pclk2", "pclk2", "ctl1_crr",
> static const char * const lan2_sata_clks[] = {"pclk2", "epcs_tx", "epcs_rx",
> "phy1_crr", "misc_crr"};
>
> -static const struct regmap_config regmap_config = {
> +static const struct regmap_config regmap_phy_config = {
> + .name = "phy",
> + .reg_bits = 32,
> + .val_bits = 32,
> + .reg_stride = 4,
> +};
> +
> +static const struct regmap_config regmap_ctrl_config = {
> + .name = "ctrl",
> + .reg_bits = 32,
> + .val_bits = 32,
> + .reg_stride = 4,
> +};
> +
> +static const struct regmap_config regmap_misc_config = {
> + .name = "misc",
Since __regmap_init() doesn't keep a persistent reference to the config,
just performs a deep copy of it (including regmap_set_name() ->
kstrdup_const()), technically you could have gotten away with just a
single on-stack regmap_config whose .name you kept changing for all 3
calls.
But this is perfectly valid as well.
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
I don't think you need to do anything further, just wait for Vinod to
start going through the backlog.
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* Re: [PATCH 2/5] phy: qcom: qmp-pcie: Add multiple power-domains support
From: Bjorn Andersson @ 2026-03-04 20:46 UTC (permalink / raw)
To: Qiang Yu
Cc: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Konrad Dybcio, linux-arm-msm,
linux-phy, devicetree, linux-kernel
In-Reply-To: <20260304-glymur_gen5x8_phy-v1-2-849e9a72e125@oss.qualcomm.com>
On Wed, Mar 04, 2026 at 12:21:56AM -0800, Qiang Yu wrote:
> The Glymur SoC's 3rd PCIe instance supports 8-lane mode using two PHYs in
> a bifurcated configuration. Each PHY has its own power domain (phy_gdsc)
> that must be powered on before initialization per hardware requirements.
>
> Current PHY power management assumes a single power domain per PHY,
> preventing proper setup for this dual-PHY scenario. Add support for
> multiple power domains by using devm_pm_domain_attach_list() to attach
> power domains manually, while maintaining compatibility with single
> power domain PHYs.
>
> Enable runtime PM to allow power domain control when the PCIe driver
> calls phy_power_on/phy_power_off:
>
Enabling runtime PM seems like a separate change that impacts all
existing targets, while adding multiple power domains should only affect
the specific ones.
I'm not sure if it's too picky, but it would be nice to separate this -
so that any issues that might arise can be bisected down to one or the
other of these two changes?
> - Single power domain: QMP PHY platform device directly attaches to
> power domain and controls it during runtime resume/suspend
> - Multiple power domains: devm_pm_domain_attach_list() creates virtual
> devices as power domain suppliers, linked to the QMP PHY platform
> device as consumer
>
> This ensures power domains are properly attached and turned on/off
> for both single and multiple power domain configurations.
>
> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> index fed2fc9bb31108d51f88d34f3379c7744681f485..7369c291be51aa1ad7a330459dcb857f5a1988f6 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> @@ -17,6 +17,7 @@
> #include <linux/phy/pcie.h>
> #include <linux/phy/phy.h>
> #include <linux/platform_device.h>
> +#include <linux/pm_domain.h>
> #include <linux/regmap.h>
> #include <linux/regulator/consumer.h>
> #include <linux/reset.h>
> @@ -3334,6 +3335,8 @@ struct qmp_pcie {
>
> struct clk_fixed_rate pipe_clk_fixed;
> struct clk_fixed_rate aux_clk_fixed;
> +
> + struct dev_pm_domain_list *pd_list;
This is just an pointer to the list allocated inside
devm_pm_domain_attach_list(), as far as I can tell you don't need to
keep this in the qmp_pcie struct - as you're not using it anyways.
Regards,
Bjorn
> };
>
> static bool qphy_checkbits(const void __iomem *base, u32 offset, u32 val)
> @@ -5348,6 +5351,16 @@ static int qmp_pcie_probe(struct platform_device *pdev)
> WARN_ON_ONCE(!qmp->cfg->pwrdn_ctrl);
> WARN_ON_ONCE(!qmp->cfg->phy_status);
>
> + ret = devm_pm_domain_attach_list(dev, NULL, &qmp->pd_list);
> + if (ret < 0 && ret != -EEXIST) {
> + dev_err(dev, "Failed to attach power domain\n");
> + return ret;
> + }
> +
> + ret = devm_pm_runtime_enable(dev);
> + if (ret)
> + return ret;
> +
> ret = qmp_pcie_clk_init(qmp);
> if (ret)
> return ret;
>
> --
> 2.34.1
>
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* Re: [PATCH phy-next 01/22] ata: add <linux/pm_runtime.h> where missing
From: Damien Le Moal @ 2026-03-04 20:14 UTC (permalink / raw)
To: Vladimir Oltean, linux-phy
Cc: Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-sunxi,
linux-tegra, linux-usb, netdev, spacemit, UNGLinuxDriver,
Niklas Cassel
In-Reply-To: <20260304175735.2660419-2-vladimir.oltean@nxp.com>
On 3/5/26 02:57, Vladimir Oltean wrote:
> It appears that libahci.c, ahci.c as well as the ahci_brcm, ahci_ceva
> and ahci_qoriq drivers are using runtime PM operations without including
> <linux/pm_runtime.h>. This header is somehow being indirectly provided
> by <linux/phy/phy.h>, which would like to drop it (none of the functions
> it exports need it).
>
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Damien Le Moal <dlemoal@kernel.org>
--
Damien Le Moal
Western Digital Research
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^ permalink raw reply
* Re: [PATCH v4 1/2] dt-bindings: phy: qcom-edp: Add reference clock for sa8775p eDP PHY
From: Bjorn Andersson @ 2026-03-04 18:57 UTC (permalink / raw)
To: Ritesh Kumar
Cc: robin.clark, lumag, abhinav.kumar, sean, marijn.suijten,
maarten.lankhorst, mripard, tzimmermann, airlied, simona, robh,
krzk+dt, conor+dt, quic_mahap, konradybcio, mani, James.Bottomley,
martin.petersen, vkoul, kishon, cros-qcom-dts-watchers, linux-phy,
linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
linux-scsi, quic_vproddut
In-Reply-To: <20260128114853.2543416-2-quic_riteshk@quicinc.com>
On Wed, Jan 28, 2026 at 05:18:49PM +0530, Ritesh Kumar wrote:
> The initial sa8775p eDP PHY binding contribution missed adding support for
> voting on the eDP reference clock. This went unnoticed because the UFS PHY
> driver happened to enable the same clock.
>
> After commit 77d2fa54a945 ("scsi: ufs: qcom : Refactor phy_power_on/off
> calls"), the eDP reference clock is no longer kept enabled, which results
> in the following PHY power-on failure:
>
> phy phy-aec2a00.phy.10: phy poweron failed --> -110
>
> To fix this, explicit voting for the eDP reference clock is required.
> This patch adds the eDP reference clock for sa8775p eDP PHY and updates
> the corresponding example node.
>
> Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
Is there any reason why you didn't follow up on this patch Ritesh?
Looks like it's ready to be merged.
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Regards,
Bjorn
> ---
> .../devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml | 6 ++++--
> Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml | 1 +
> 2 files changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
> index e2730a2f25cf..6c827cf9692b 100644
> --- a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
> +++ b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
> @@ -200,9 +200,11 @@ examples:
> <0x0aec2000 0x1c8>;
>
> clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
> - <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>;
> + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
> + <&gcc GCC_EDP_REF_CLKREF_EN>;
> clock-names = "aux",
> - "cfg_ahb";
> + "cfg_ahb",
> + "ref";
>
> #clock-cells = <1>;
> #phy-cells = <0>;
> diff --git a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
> index 4a1daae3d8d4..0bf8bf4f66ac 100644
> --- a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
> @@ -74,6 +74,7 @@ allOf:
> compatible:
> enum:
> - qcom,glymur-dp-phy
> + - qcom,sa8775p-edp-phy
> - qcom,x1e80100-dp-phy
> then:
> properties:
> --
> 2.34.1
>
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^ permalink raw reply
* [PATCH phy-next 22/22] MAINTAINERS: add regex for linux-phy
From: Vladimir Oltean @ 2026-03-04 17:57 UTC (permalink / raw)
To: linux-phy
Cc: Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-sunxi,
linux-tegra, linux-usb, netdev, spacemit, UNGLinuxDriver
In-Reply-To: <20260304175735.2660419-1-vladimir.oltean@nxp.com>
Some pragmatic shortcuts are being taken by PHY consumer driver authors,
which put a burden on the framework. A lot of these can be caught during
review.
Make sure the linux-phy list is copied on as many keywords that a regex
can reasonably catch.
For simplicity sake this is not perfect (devm_ and of_ are not valid
prefixes for all function names), but I tried to pay attention on
avoiding false matches on things like:
- drivers/net/vendor/device/phy.h
- include/linux/phy.h - network PHY, not generic PHY
So I used \b to try to match on actual word boundaries and be explicit
about what is matched on.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 55af015174a5..bdfa47d9c774 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10713,6 +10713,7 @@ F: Documentation/devicetree/bindings/phy/
F: drivers/phy/
F: include/dt-bindings/phy/
F: include/linux/phy/
+K: \b(devm_)?(of_)?phy_(create|destroy|init|exit|reset|power_(on|off)|configure|validate|calibrate|(get|set)_(mode|media|speed|bus_width|drvdata)|get_max_link_rate|pm_runtime_(get|put)|notify_(connect|disconnect|state)|get|put|optional_get|provider_(un)?register|simple_xlate|(create|remove)_lookup)\b|(struct\s+)?phy(_ops|_attrs|_lookup|_provider)?\b|linux/phy/phy\.h|phy-props\.h|phy-provider\.h
GENERIC PINCTRL I2C DEMULTIPLEXER DRIVER
M: Wolfram Sang <wsa+renesas@sang-engineering.com>
--
2.43.0
--
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^ permalink raw reply related
* [PATCH phy-next 21/22] phy: remove temporary provider compatibility from consumer header
From: Vladimir Oltean @ 2026-03-04 17:57 UTC (permalink / raw)
To: linux-phy
Cc: Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-sunxi,
linux-tegra, linux-usb, netdev, spacemit, UNGLinuxDriver
In-Reply-To: <20260304175735.2660419-1-vladimir.oltean@nxp.com>
Now that all consumers have been updated to no longer dereference fields
inside struct phy, we can hide its definition altogether from public view.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
include/linux/phy/phy.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index af9c3e795786..f11ffbbfea2c 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -12,8 +12,6 @@
#include <linux/phy/phy-props.h>
-#include "../../drivers/phy/phy-provider.h"
-
struct device;
struct device_node;
struct phy;
--
2.43.0
--
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^ permalink raw reply related
* [PATCH phy-next 19/22] power: supply: cpcap-charger: include missing <linux/property.h>
From: Vladimir Oltean @ 2026-03-04 17:57 UTC (permalink / raw)
To: linux-phy
Cc: Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-sunxi,
linux-tegra, linux-usb, netdev, spacemit, UNGLinuxDriver,
Sebastian Reichel
In-Reply-To: <20260304175735.2660419-1-vladimir.oltean@nxp.com>
This file uses dev_fwnode() without including the proper header for it,
relying on transitive header inclusion from:
drivers/power/supply/cpcap-charger.c
- include/linux/phy/omap_usb.h
- include/linux/usb/phy_companion.h
- include/linux/usb/otg.h
- include/linux/phy/phy.h
- drivers/phy/phy-provider.h
- include/linux/of.h
- include/linux/property.h
With the future removal of drivers/phy/phy-provider.h from
include/linux/phy/phy.h, this transitive inclusion would break.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
Cc: Sebastian Reichel <sre@kernel.org>
---
drivers/power/supply/cpcap-charger.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/power/supply/cpcap-charger.c b/drivers/power/supply/cpcap-charger.c
index d0c3008db534..24221244b45b 100644
--- a/drivers/power/supply/cpcap-charger.c
+++ b/drivers/power/supply/cpcap-charger.c
@@ -21,6 +21,7 @@
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/power_supply.h>
+#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/gpio/consumer.h>
--
2.43.0
--
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^ permalink raw reply related
* [PATCH phy-next 18/22] pinctrl: tegra-xusb: include PHY provider header
From: Vladimir Oltean @ 2026-03-04 17:57 UTC (permalink / raw)
To: linux-phy
Cc: Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-sunxi,
linux-tegra, linux-usb, netdev, spacemit, UNGLinuxDriver,
Linus Walleij, Thierry Reding, Jonathan Hunter,
Krzysztof Kozlowski
In-Reply-To: <20260304175735.2660419-1-vladimir.oltean@nxp.com>
The tegra-xusb pinctrl driver is also a PHY provider (calls
devm_phy_create() for PCIe and SATA). However, according to Vinod Koul,
having PHY provider drivers outside of drivers/phy/ is discouraged,
although it would be difficult for me to address a proper movement here.
Include the private provider API header from drivers/phy/, but leave a
FIXME in place. It will have to be moved, eventually.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
Cc: Linus Walleij <linusw@kernel.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Jonathan Hunter <jonathanh@nvidia.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
drivers/pinctrl/tegra/pinctrl-tegra-xusb.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra-xusb.c b/drivers/pinctrl/tegra/pinctrl-tegra-xusb.c
index c6a51bb21215..6b609bf685c7 100644
--- a/drivers/pinctrl/tegra/pinctrl-tegra-xusb.c
+++ b/drivers/pinctrl/tegra/pinctrl-tegra-xusb.c
@@ -7,7 +7,6 @@
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
#include <linux/seq_file.h>
@@ -19,6 +18,7 @@
#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
+#include "../../phy/phy-provider.h" /* FIXME */
#include "../core.h"
#include "../pinctrl-utils.h"
--
2.43.0
--
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^ permalink raw reply related
* [PATCH phy-next 17/22] net: renesas: rswitch: include PHY provider header
From: Vladimir Oltean @ 2026-03-04 17:57 UTC (permalink / raw)
To: linux-phy
Cc: Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-sunxi,
linux-tegra, linux-usb, netdev, spacemit, UNGLinuxDriver,
Yoshihiro Shimoda, Michael Dege, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Geert Uytterhoeven,
Russell King (Oracle)
In-Reply-To: <20260304175735.2660419-1-vladimir.oltean@nxp.com>
As a PHY consumer driver, the Renesas rswitch dereferences internal
fields of struct phy, something which shouldn't be done, as that is
going to be made an opaque pointer.
It is quite clearly visible that the driver is tightly coupled with the
drivers/phy/renesas/r8a779f0-ether-serdes.c, which puts heavy pressure
on the Generic PHY subsystem.
This was discussed before here:
https://lore.kernel.org/linux-phy/20260211194541.cdmibrpfn6ej6e74@skbuf/
but to summarize, it is generally expected that when a Generic PHY
function is called, it takes effect immediately. When this doesn't
happen, the PHY provider driver must change its implementation rather
than the consumer be made to work around it. PHY providers which rely on
a hardcoded call sequence in the consumer are just lazy and wrong.
The most obvious example is commit 5cb630925b49 ("net: renesas: rswitch:
Add phy_power_{on,off}() calling"). Problem description:
- Ethernet PHYs may change phydev->interface. When this happens, the
SerDes must learn of the new phydev->interface using phy_set_mode_ext().
- drivers/phy/renesas/r8a779f0-ether-serdes.c implements phy_set_mode_ext(),
but this only caches the mode and submode into channel->phy_interface
and applies this to hardware during phy_power_on().
The commit author decided to work around this at the consumer site, by
power cycling the PHY for the configuration to take effect.
This had a worse implication from an API perspective in subsequent
commit 053f13f67be6 ("rswitch: Fix imbalance phy_power_off() calling").
It was observed that phy_power_on() and phy_power_off() calls need to be
balanced, and so, the consumer decided to start looking at the struct
phy :: power_count (the technical reason why I'm making this change).
This is also wrong from an API perspective because
- a consumer should only care about its own vote on the PHY power state.
If this is a multi-port submode like QSGMII, a single phy_power_off()
call will not actually turn the PHY off (nor should it).
- the power_count is written under the &phy->mutex, but read unlocked
here.
The rswitch and r8a779f0-ether-serdes drivers both need to be completely
rethought in terms of Generic PHY API call sequence. There is no quick
fix to apply. Just include the PHY provider API along with the consumer
one, to keep working as before when struct phy will be made an opaque
pointer to normal PHY consumers. But this is a bad offender (and it's
not even a provider) so add a FIXME.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
Cc: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Cc: Michael Dege <michael.dege@renesas.com>
Cc: Andrew Lunn <andrew+netdev@lunn.ch>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Eric Dumazet <edumazet@google.com>
Cc: Jakub Kicinski <kuba@kernel.org>
Cc: Paolo Abeni <pabeni@redhat.com>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
---
drivers/net/ethernet/renesas/rswitch_main.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/ethernet/renesas/rswitch_main.c b/drivers/net/ethernet/renesas/rswitch_main.c
index 6fe964816322..132be5f15073 100644
--- a/drivers/net/ethernet/renesas/rswitch_main.c
+++ b/drivers/net/ethernet/renesas/rswitch_main.c
@@ -27,6 +27,7 @@
#include <linux/spinlock.h>
#include <linux/sys_soc.h>
+#include "../../../phy/phy-provider.h" /* FIXME */
#include "rswitch.h"
#include "rswitch_l2.h"
--
2.43.0
--
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^ permalink raw reply related
* [PATCH phy-next 16/22] media: sunxi: a83-mips-csi2: include PHY provider header
From: Vladimir Oltean @ 2026-03-04 17:57 UTC (permalink / raw)
To: linux-phy
Cc: Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-sunxi,
linux-tegra, linux-usb, netdev, spacemit, UNGLinuxDriver,
Mauro Carvalho Chehab, Chen-Yu Tsai, Jernej Skrabec,
Samuel Holland
In-Reply-To: <20260304175735.2660419-1-vladimir.oltean@nxp.com>
The introduction commit 576d196c522b ("media: sunxi: Add support for the
A83T MIPI CSI-2 controller") says:
This implementation splits the protocol and D-PHY registers and
uses the PHY framework internally. The D-PHY is not registered as a
standalone PHY driver since it cannot be used with any other
controller.
However, this does not matter, and is not the only instance of tight PHY
provider <-> consumer pairing. According to Vinod Koul, having PHY
provider drivers outside of drivers/phy/ is discouraged, although it
would be difficult for me to address a proper movement here.
So just include the private provider API header from drivers/phy/ and
leave a FIXME in place.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: Chen-Yu Tsai <wens@kernel.org>
Cc: Jernej Skrabec <jernej.skrabec@gmail.com>
Cc: Samuel Holland <samuel@sholland.org>
---
.../media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.c b/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.c
index 24bbcc85013d..1143feeb4fcb 100644
--- a/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.c
+++ b/drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.c
@@ -4,9 +4,9 @@
* Author: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
*/
-#include <linux/phy/phy.h>
#include <linux/regmap.h>
+#include "../../../../phy/phy-provider.h" /* FIXME */
#include "sun8i_a83t_dphy.h"
#include "sun8i_a83t_mipi_csi2.h"
--
2.43.0
--
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^ permalink raw reply related
* [PATCH phy-next 15/22] drm: bridge: cdns-mhdp8546: use consumer API for getting PHY bus width
From: Vladimir Oltean @ 2026-03-04 17:57 UTC (permalink / raw)
To: linux-phy
Cc: Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-sunxi,
linux-tegra, linux-usb, netdev, spacemit, UNGLinuxDriver,
Andrzej Hajda, Robert Foss, Laurent Pinchart, Jonas Karlman,
Jernej Skrabec, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter
In-Reply-To: <20260304175735.2660419-1-vladimir.oltean@nxp.com>
The Cadence MHDP8546 DP bridge driver gets the PHY bus_width attribute
(holding number of lanes) directly, but doing this will no longer be
possible after the definition of struct phy is hidden from consumers.
Use the phy_get_bus_width() API function designed specifically for
consumers.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
Cc: Andrzej Hajda <andrzej.hajda@intel.com>
Cc: Neil Armstrong <neil.armstrong@linaro.org>
Cc: Robert Foss <rfoss@kernel.org>
Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
Cc: Jonas Karlman <jonas@kwiboo.se>
Cc: Jernej Skrabec <jernej.skrabec@gmail.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Maxime Ripard <mripard@kernel.org>
Cc: Thomas Zimmermann <tzimmermann@suse.de>
Cc: David Airlie <airlied@gmail.com>
Cc: Simona Vetter <simona@ffwll.ch>
---
drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
index ed7ed82ddb64..e3f8a281f147 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
@@ -1304,7 +1304,7 @@ static void cdns_mhdp_fill_host_caps(struct cdns_mhdp_device *mhdp)
/* Get source capabilities based on PHY attributes */
- mhdp->host.lanes_cnt = mhdp->phy->attrs.bus_width;
+ mhdp->host.lanes_cnt = phy_get_bus_width(mhdp->phy);
if (!mhdp->host.lanes_cnt)
mhdp->host.lanes_cnt = 4;
--
2.43.0
--
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^ permalink raw reply related
* [PATCH phy-next 14/22] drm/rockchip: dsi: include PHY provider header
From: Vladimir Oltean @ 2026-03-04 17:57 UTC (permalink / raw)
To: linux-phy
Cc: Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-sunxi,
linux-tegra, linux-usb, netdev, spacemit, UNGLinuxDriver,
Andrzej Hajda, Robert Foss, Laurent Pinchart, Jonas Karlman,
Jernej Skrabec, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter
In-Reply-To: <20260304175735.2660419-1-vladimir.oltean@nxp.com>
The Rockchip DSI controller is a PHY consumer driver, which is also a
PHY provider (calls devm_phy_create()) that lives out of drivers/phy/.
According to Vinod, this is discouraged, although it would be difficult
for me to address a proper movement here.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
Cc: Andrzej Hajda <andrzej.hajda@intel.com>
Cc: Neil Armstrong <neil.armstrong@linaro.org>
Cc: Robert Foss <rfoss@kernel.org>
Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
Cc: Jonas Karlman <jonas@kwiboo.se>
Cc: Jernej Skrabec <jernej.skrabec@gmail.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Maxime Ripard <mripard@kernel.org>
Cc: Thomas Zimmermann <tzimmermann@suse.de>
Cc: David Airlie <airlied@gmail.com>
Cc: Simona Vetter <simona@ffwll.ch>
---
drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
index 3547d91b25d3..c0aaa51e0237 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
@@ -27,6 +27,7 @@
#include <drm/drm_print.h>
#include <drm/drm_simple_kms_helper.h>
+#include "../../../phy/phy-provider.h" /* FIXME */
#include "rockchip_drm_drv.h"
#define DSI_PHY_RSTZ 0xa0
--
2.43.0
--
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linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
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* [PATCH phy-next 13/22] phy: introduce phy_get_max_link_rate() helper for consumers
From: Vladimir Oltean @ 2026-03-04 17:57 UTC (permalink / raw)
To: linux-phy
Cc: Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-sunxi,
linux-tegra, linux-usb, netdev, spacemit, UNGLinuxDriver,
Andrzej Hajda, Robert Foss, Laurent Pinchart, Jonas Karlman,
Jernej Skrabec, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Andy Yan,
Marc Kleine-Budde, Vincent Mailhol, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Markus Schneider-Pargmann,
Geert Uytterhoeven, Magnus Damm
In-Reply-To: <20260304175735.2660419-1-vladimir.oltean@nxp.com>
Consumer drivers shouldn't dereference struct phy, not even to get to
its attributes.
We have phy_get_bus_width() as a precedent for getting the bus_width
attribute, so let's add phy_get_max_link_rate() and use it in DRM and
CAN drivers.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
Cc: Andrzej Hajda <andrzej.hajda@intel.com>
Cc: Neil Armstrong <neil.armstrong@linaro.org>
Cc: Robert Foss <rfoss@kernel.org>
Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
Cc: Jonas Karlman <jonas@kwiboo.se>
Cc: Jernej Skrabec <jernej.skrabec@gmail.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Maxime Ripard <mripard@kernel.org>
Cc: Thomas Zimmermann <tzimmermann@suse.de>
Cc: David Airlie <airlied@gmail.com>
Cc: Simona Vetter <simona@ffwll.ch>
Cc: Andy Yan <andy.yan@rock-chips.com>
Cc: Marc Kleine-Budde <mkl@pengutronix.de>
Cc: Vincent Mailhol <mailhol@kernel.org>
Cc: Nicolas Ferre <nicolas.ferre@microchip.com>
Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
Cc: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Cc: Markus Schneider-Pargmann <msp@baylibre.com>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Magnus Damm <magnus.damm@gmail.com>
---
drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c | 4 ++--
drivers/gpu/drm/bridge/synopsys/dw-dp.c | 2 +-
drivers/net/can/at91_can.c | 2 +-
drivers/net/can/flexcan/flexcan-core.c | 2 +-
drivers/net/can/m_can/m_can_platform.c | 2 +-
drivers/net/can/rcar/rcar_canfd.c | 2 +-
drivers/phy/phy-core.c | 6 ++++++
include/linux/phy/phy.h | 6 ++++++
8 files changed, 19 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
index a8b6ae58cb0a..ed7ed82ddb64 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
@@ -1300,7 +1300,7 @@ static u32 cdns_mhdp_get_training_interval_us(struct cdns_mhdp_device *mhdp,
static void cdns_mhdp_fill_host_caps(struct cdns_mhdp_device *mhdp)
{
- unsigned int link_rate;
+ u32 link_rate;
/* Get source capabilities based on PHY attributes */
@@ -1308,7 +1308,7 @@ static void cdns_mhdp_fill_host_caps(struct cdns_mhdp_device *mhdp)
if (!mhdp->host.lanes_cnt)
mhdp->host.lanes_cnt = 4;
- link_rate = mhdp->phy->attrs.max_link_rate;
+ link_rate = phy_get_max_link_rate(mhdp->phy);
if (!link_rate)
link_rate = drm_dp_bw_code_to_link_rate(DP_LINK_BW_8_1);
else
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-dp.c b/drivers/gpu/drm/bridge/synopsys/dw-dp.c
index 4ab6922dd79c..79c72ee8e263 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-dp.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-dp.c
@@ -536,7 +536,7 @@ static int dw_dp_link_parse(struct dw_dp *dp, struct drm_connector *connector)
link->revision = link->dpcd[DP_DPCD_REV];
link->rate = min_t(u32, min(dp->plat_data.max_link_rate,
- dp->phy->attrs.max_link_rate * 100),
+ phy_get_max_link_rate(dp->phy) * 100),
drm_dp_max_link_rate(link->dpcd));
link->lanes = min_t(u8, phy_get_bus_width(dp->phy),
drm_dp_max_lane_count(link->dpcd));
diff --git a/drivers/net/can/at91_can.c b/drivers/net/can/at91_can.c
index 58da323f14d7..b56db253f02d 100644
--- a/drivers/net/can/at91_can.c
+++ b/drivers/net/can/at91_can.c
@@ -1126,7 +1126,7 @@ static int at91_can_probe(struct platform_device *pdev)
can_rx_offload_add_timestamp(dev, &priv->offload);
if (transceiver)
- priv->can.bitrate_max = transceiver->attrs.max_link_rate;
+ priv->can.bitrate_max = phy_get_max_link_rate(transceiver);
if (at91_is_sam9263(priv))
dev->sysfs_groups[0] = &at91_sysfs_attr_group;
diff --git a/drivers/net/can/flexcan/flexcan-core.c b/drivers/net/can/flexcan/flexcan-core.c
index f5d22c61503f..3a4307bc1d61 100644
--- a/drivers/net/can/flexcan/flexcan-core.c
+++ b/drivers/net/can/flexcan/flexcan-core.c
@@ -2211,7 +2211,7 @@ static int flexcan_probe(struct platform_device *pdev)
priv->transceiver = transceiver;
if (transceiver)
- priv->can.bitrate_max = transceiver->attrs.max_link_rate;
+ priv->can.bitrate_max = phy_get_max_link_rate(transceiver);
if (priv->devtype_data.quirks & FLEXCAN_QUIRK_NR_IRQ_3) {
priv->irq_boff = platform_get_irq(pdev, 1);
diff --git a/drivers/net/can/m_can/m_can_platform.c b/drivers/net/can/m_can/m_can_platform.c
index 56da411878af..73525be6566b 100644
--- a/drivers/net/can/m_can/m_can_platform.c
+++ b/drivers/net/can/m_can/m_can_platform.c
@@ -132,7 +132,7 @@ static int m_can_plat_probe(struct platform_device *pdev)
}
if (transceiver)
- mcan_class->can.bitrate_max = transceiver->attrs.max_link_rate;
+ mcan_class->can.bitrate_max = phy_get_max_link_rate(transceiver);
priv->base = addr;
priv->mram_base = mram_addr;
diff --git a/drivers/net/can/rcar/rcar_canfd.c b/drivers/net/can/rcar/rcar_canfd.c
index eaf8cac78038..645d5671705d 100644
--- a/drivers/net/can/rcar/rcar_canfd.c
+++ b/drivers/net/can/rcar/rcar_canfd.c
@@ -1885,7 +1885,7 @@ static int rcar_canfd_channel_probe(struct rcar_canfd_global *gpriv, u32 ch,
priv->channel = ch;
priv->gpriv = gpriv;
if (transceiver)
- priv->can.bitrate_max = transceiver->attrs.max_link_rate;
+ priv->can.bitrate_max = phy_get_max_link_rate(transceiver);
priv->can.clock.freq = fcan_freq;
dev_info(dev, "can_clk rate is %u\n", priv->can.clock.freq);
diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c
index a1aff00fba7c..89f7410241aa 100644
--- a/drivers/phy/phy-core.c
+++ b/drivers/phy/phy-core.c
@@ -640,6 +640,12 @@ void phy_set_bus_width(struct phy *phy, int bus_width)
}
EXPORT_SYMBOL_GPL(phy_set_bus_width);
+u32 phy_get_max_link_rate(struct phy *phy)
+{
+ return phy->attrs.max_link_rate;
+}
+EXPORT_SYMBOL_GPL(phy_get_max_link_rate);
+
/**
* _of_phy_get() - lookup and obtain a reference to a phy by phandle
* @np: device_node for which to get the phy
diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index 36307e47760d..af9c3e795786 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -57,6 +57,7 @@ int phy_notify_disconnect(struct phy *phy, int port);
int phy_notify_state(struct phy *phy, union phy_notify state);
int phy_get_bus_width(struct phy *phy);
void phy_set_bus_width(struct phy *phy, int bus_width);
+u32 phy_get_max_link_rate(struct phy *phy);
#else
static inline struct phy *phy_get(struct device *dev, const char *string)
{
@@ -256,6 +257,11 @@ static inline int phy_get_bus_width(struct phy *phy)
static inline void phy_set_bus_width(struct phy *phy, int bus_width)
{
}
+
+static inline u32 phy_get_max_link_rate(struct phy *phy)
+{
+ return 0;
+}
#endif /* IS_ENABLED(CONFIG_GENERIC_PHY) */
#endif /* __PHY_CONSUMER_H */
--
2.43.0
--
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