* Re: [PATCH phy-next 05/22] phy: add <linux/pm_runtime.h> where missing
From: Geert Uytterhoeven @ 2026-03-05 7:45 UTC (permalink / raw)
To: Vladimir Oltean
Cc: linux-phy, Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-sunxi,
linux-tegra, linux-usb, netdev, spacemit, UNGLinuxDriver,
Peter Griffin, André Draszik, Tudor Ambarus,
Geert Uytterhoeven, Magnus Damm, Heiko Stuebner
In-Reply-To: <20260304175735.2660419-6-vladimir.oltean@nxp.com>
On Wed, 4 Mar 2026 at 19:00, Vladimir Oltean <vladimir.oltean@nxp.com> wrote:
> It appears that the phy-mapphone-mdm6600, phy-qcom-snps-femto-v2,
> phy-rcar-gen3-pcie, r8a779f0-ether-serdes and phy-rockchip-typec drivers
> call runtime PM operations without including the proper header.
>
> This was provided by <linux/phy/phy.h> but no function exported by this
> header directly needs it. So we need to drop it from there, and fix up
> drivers that used to depend on that.
>
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> drivers/phy/renesas/phy-rcar-gen3-pcie.c | 1 +
> drivers/phy/renesas/r8a779f0-ether-serdes.c | 1 +
For the Renesas parts:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply
* Re: [PATCH phy-next 13/22] phy: introduce phy_get_max_link_rate() helper for consumers
From: Geert Uytterhoeven @ 2026-03-05 7:47 UTC (permalink / raw)
To: Vladimir Oltean
Cc: linux-phy, Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-sunxi,
linux-tegra, linux-usb, netdev, spacemit, UNGLinuxDriver,
Andrzej Hajda, Robert Foss, Laurent Pinchart, Jonas Karlman,
Jernej Skrabec, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Andy Yan,
Marc Kleine-Budde, Vincent Mailhol, Nicolas Ferre,
Alexandre Belloni, Claudiu Beznea, Markus Schneider-Pargmann,
Magnus Damm
In-Reply-To: <20260304175735.2660419-14-vladimir.oltean@nxp.com>
Hi Vladimir,
On Wed, 4 Mar 2026 at 19:00, Vladimir Oltean <vladimir.oltean@nxp.com> wrote:
> Consumer drivers shouldn't dereference struct phy, not even to get to
> its attributes.
>
> We have phy_get_bus_width() as a precedent for getting the bus_width
> attribute, so let's add phy_get_max_link_rate() and use it in DRM and
> CAN drivers.
>
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Thanks for your patch!
> drivers/net/can/rcar/rcar_canfd.c | 2 +-
For the Renesas part:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> --- a/drivers/phy/phy-core.c
> +++ b/drivers/phy/phy-core.c
> @@ -640,6 +640,12 @@ void phy_set_bus_width(struct phy *phy, int bus_width)
> }
> EXPORT_SYMBOL_GPL(phy_set_bus_width);
>
> +u32 phy_get_max_link_rate(struct phy *phy)
> +{
> + return phy->attrs.max_link_rate;
> +}
> +EXPORT_SYMBOL_GPL(phy_get_max_link_rate);
Any specific reason you are not making this a simple static inline
function, like phy_get_bus_width()?
> +
> /**
> * _of_phy_get() - lookup and obtain a reference to a phy by phandle
> * @np: device_node for which to get the phy
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply
* [PATCH v2] phy: rockchip: naneng-combphy: Consolidate SSC configuration
From: Shawn Lin @ 2026-03-05 7:40 UTC (permalink / raw)
To: Vinod Koul
Cc: linux-rockchip, linux-phy, Heiko Stuebner, Neil Armstrong,
linux-kernel, Shawn Lin
The PCIe SSC configuration for the RK3588 and RK3576 SoCs required
additional tuning which is missing. When adding these same SSC
configurations for both of these two SoCs, as well as upcoming
platforms, it's obvious the SSC setup code was largely duplicated
across the platform-specific configuration functions. This becomes
harder to maintain as more platforms are added.
So extract the common SSC logic into a shared helper function,
rk_combphy_common_cfg_ssc(). This cleans up the per-platform drivers
and centralizes the standard configuration as possible.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---
Changes in v2:
- rework to consolidate more configuration
- reword the commit message
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 173 +++++++++------------
1 file changed, 73 insertions(+), 100 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
index b60d6bf..2b0f152 100644
--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -121,6 +121,7 @@
#define RK3568_PHYREG32_SSC_OFFSET_500PPM 1
#define RK3568_PHYREG33 0x80
+#define RK3568_PHYREG33_PLL_SSC_CTRL BIT(5)
#define RK3568_PHYREG33_PLL_KVCO_MASK GENMASK(4, 2)
#define RK3568_PHYREG33_PLL_KVCO_SHIFT 2
#define RK3568_PHYREG33_PLL_KVCO_VALUE 2
@@ -446,6 +447,74 @@ static int rockchip_combphy_probe(struct platform_device *pdev)
return PTR_ERR_OR_ZERO(phy_provider);
}
+static void rk_combphy_common_cfg_ssc(struct rockchip_combphy_priv *priv, unsigned long rate)
+{
+ struct device_node *np = priv->dev->of_node;
+ u32 val;
+
+ if (!priv->enable_ssc)
+ return;
+
+ /* Set SSC downward spread spectrum for PCIe and USB3 */
+ if (priv->type == PHY_TYPE_PCIE || priv->type == PHY_TYPE_USB3) {
+ val = FIELD_PREP(RK3568_PHYREG32_SSC_MASK, RK3568_PHYREG32_SSC_DOWNWARD);
+ rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32);
+ }
+
+ /* Set SSC downward spread spectrum +500ppm for SATA in 100MHz */
+ if (priv->type == PHY_TYPE_SATA && rate == REF_CLOCK_100MHz) {
+ val = FIELD_PREP(RK3568_PHYREG32_SSC_DIR_MASK,
+ RK3568_PHYREG32_SSC_DOWNWARD);
+ val |= FIELD_PREP(RK3568_PHYREG32_SSC_OFFSET_MASK,
+ RK3568_PHYREG32_SSC_OFFSET_500PPM);
+ rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val,
+ RK3568_PHYREG32);
+ }
+
+ /* Enable SSC */
+ val = readl(priv->mmio + RK3568_PHYREG8);
+ val |= RK3568_PHYREG8_SSC_EN;
+ writel(val, priv->mmio + RK3568_PHYREG8);
+
+ /* Some SoCs need tuning PCIe SSC instead of default configuration in 24MHz */
+ if (!of_device_is_compatible(np, "rockchip,rk3588-naneng-combphy") &&
+ !of_device_is_compatible(np, "rockchip,rk3576-naneng-combphy"))
+ return;
+
+ /* PLL control SSC module period should be set if need tuning */
+ val = readl(priv->mmio + RK3568_PHYREG33);
+ val |= RK3568_PHYREG33_PLL_SSC_CTRL;
+ writel(val, priv->mmio + RK3568_PHYREG33);
+
+ if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_24MHz) {
+ /* Set PLL loop divider */
+ writel(0x00, priv->mmio + RK3576_PHYREG17);
+ writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18);
+
+ /* Set up rx_pck invert and rx msb to disable */
+ writel(0x00, priv->mmio + RK3588_PHYREG27);
+
+ /*
+ * Set up SU adjust signal:
+ * su_trim[7:0], PLL KVCO adjust bits[2:0] to min
+ * su_trim[15:8], PLL LPF R1 adujst bits[9:7]=3'b101
+ * su_trim[23:16], CKRCV adjust
+ * su_trim[31:24], CKDRV adjust
+ */
+ writel(0x90, priv->mmio + RK3568_PHYREG11);
+ writel(0x02, priv->mmio + RK3568_PHYREG12);
+ writel(0x08, priv->mmio + RK3568_PHYREG13);
+ writel(0x57, priv->mmio + RK3568_PHYREG14);
+ writel(0x40, priv->mmio + RK3568_PHYREG15);
+
+ writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16);
+
+ val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK,
+ RK3576_PHYREG33_PLL_KVCO_VALUE);
+ writel(val, priv->mmio + RK3568_PHYREG33);
+ }
+}
+
static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv)
{
const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
@@ -600,21 +669,12 @@ static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv)
switch (priv->type) {
case PHY_TYPE_PCIE:
- /* Set SSC downward spread spectrum */
- val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT;
- rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32);
-
rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
break;
case PHY_TYPE_USB3:
- /* Set SSC downward spread spectrum */
- val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT;
- rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val,
- RK3568_PHYREG32);
-
/* Enable adaptive CTLE for USB3.0 Rx */
rockchip_combphy_updatel(priv, RK3568_PHYREG15_CTLE_EN,
RK3568_PHYREG15_CTLE_EN, RK3568_PHYREG15);
@@ -706,11 +766,7 @@ static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv)
}
}
- if (priv->enable_ssc) {
- val = readl(priv->mmio + RK3568_PHYREG8);
- val |= RK3568_PHYREG8_SSC_EN;
- writel(val, priv->mmio + RK3568_PHYREG8);
- }
+ rk_combphy_common_cfg_ssc(priv, rate);
return 0;
}
@@ -755,11 +811,6 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
switch (priv->type) {
case PHY_TYPE_PCIE:
- /* Set SSC downward spread spectrum. */
- val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT;
-
- rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32);
-
rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
@@ -767,10 +818,6 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
break;
case PHY_TYPE_USB3:
- /* Set SSC downward spread spectrum. */
- val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT,
- rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32);
-
/* Enable adaptive CTLE for USB3.0 Rx. */
val = readl(priv->mmio + RK3568_PHYREG15);
val |= RK3568_PHYREG15_CTLE_EN;
@@ -880,13 +927,6 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18);
writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11);
- } else if (priv->type == PHY_TYPE_SATA) {
- /* downward spread spectrum +500ppm */
- val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT;
- val |= RK3568_PHYREG32_SSC_OFFSET_500PPM <<
- RK3568_PHYREG32_SSC_OFFSET_SHIFT;
- rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val,
- RK3568_PHYREG32);
}
break;
@@ -909,11 +949,7 @@ static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
}
}
- if (priv->enable_ssc) {
- val = readl(priv->mmio + RK3568_PHYREG8);
- val |= RK3568_PHYREG8_SSC_EN;
- writel(val, priv->mmio + RK3568_PHYREG8);
- }
+ rk_combphy_common_cfg_ssc(priv, rate);
return 0;
}
@@ -972,10 +1008,6 @@ static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
switch (priv->type) {
case PHY_TYPE_PCIE:
- /* Set SSC downward spread spectrum */
- val = FIELD_PREP(RK3568_PHYREG32_SSC_MASK, RK3568_PHYREG32_SSC_DOWNWARD);
- rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32);
-
rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
@@ -983,10 +1015,6 @@ static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
break;
case PHY_TYPE_USB3:
- /* Set SSC downward spread spectrum */
- val = FIELD_PREP(RK3568_PHYREG32_SSC_MASK, RK3568_PHYREG32_SSC_DOWNWARD);
- rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32);
-
/* Enable adaptive CTLE for USB3.0 Rx */
val = readl(priv->mmio + RK3568_PHYREG15);
val |= RK3568_PHYREG15_CTLE_EN;
@@ -1110,14 +1138,6 @@ static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
writel(0x88, priv->mmio + RK3568_PHYREG13);
writel(0x56, priv->mmio + RK3568_PHYREG14);
} else if (priv->type == PHY_TYPE_SATA) {
- /* downward spread spectrum +500ppm */
- val = FIELD_PREP(RK3568_PHYREG32_SSC_DIR_MASK,
- RK3568_PHYREG32_SSC_DOWNWARD);
- val |= FIELD_PREP(RK3568_PHYREG32_SSC_OFFSET_MASK,
- RK3568_PHYREG32_SSC_OFFSET_500PPM);
- rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val,
- RK3568_PHYREG32);
-
/* ssc ppm adjust to 3500ppm */
rockchip_combphy_updatel(priv, RK3576_PHYREG10_SSC_PCM_MASK,
RK3576_PHYREG10_SSC_PCM_3500PPM,
@@ -1156,39 +1176,7 @@ static int rk3576_combphy_cfg(struct rockchip_combphy_priv *priv)
}
}
- if (priv->enable_ssc) {
- val = readl(priv->mmio + RK3568_PHYREG8);
- val |= RK3568_PHYREG8_SSC_EN;
- writel(val, priv->mmio + RK3568_PHYREG8);
-
- if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_24MHz) {
- /* Set PLL loop divider */
- writel(0x00, priv->mmio + RK3576_PHYREG17);
- writel(RK3568_PHYREG18_PLL_LOOP, priv->mmio + RK3568_PHYREG18);
-
- /* Set up rx_pck invert and rx msb to disable */
- writel(0x00, priv->mmio + RK3588_PHYREG27);
-
- /*
- * Set up SU adjust signal:
- * su_trim[7:0], PLL KVCO adjust bits[2:0] to min
- * su_trim[15:8], PLL LPF R1 adujst bits[9:7]=3'b101
- * su_trim[23:16], CKRCV adjust
- * su_trim[31:24], CKDRV adjust
- */
- writel(0x90, priv->mmio + RK3568_PHYREG11);
- writel(0x02, priv->mmio + RK3568_PHYREG12);
- writel(0x08, priv->mmio + RK3568_PHYREG13);
- writel(0x57, priv->mmio + RK3568_PHYREG14);
- writel(0x40, priv->mmio + RK3568_PHYREG15);
-
- writel(RK3568_PHYREG16_SSC_CNT_VALUE, priv->mmio + RK3568_PHYREG16);
-
- val = FIELD_PREP(RK3568_PHYREG33_PLL_KVCO_MASK,
- RK3576_PHYREG33_PLL_KVCO_VALUE);
- writel(val, priv->mmio + RK3568_PHYREG33);
- }
- }
+ rk_combphy_common_cfg_ssc(priv, rate);
return 0;
}
@@ -1255,10 +1243,6 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
}
break;
case PHY_TYPE_USB3:
- /* Set SSC downward spread spectrum */
- val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT;
- rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val, RK3568_PHYREG32);
-
/* Enable adaptive CTLE for USB3.0 Rx. */
val = readl(priv->mmio + RK3568_PHYREG15);
val |= RK3568_PHYREG15_CTLE_EN;
@@ -1343,13 +1327,6 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
/* Set up su_trim: */
writel(RK3568_PHYREG11_SU_TRIM_0_7, priv->mmio + RK3568_PHYREG11);
- } else if (priv->type == PHY_TYPE_SATA) {
- /* downward spread spectrum +500ppm */
- val = RK3568_PHYREG32_SSC_DOWNWARD << RK3568_PHYREG32_SSC_DIR_SHIFT;
- val |= RK3568_PHYREG32_SSC_OFFSET_500PPM <<
- RK3568_PHYREG32_SSC_OFFSET_SHIFT;
- rockchip_combphy_updatel(priv, RK3568_PHYREG32_SSC_MASK, val,
- RK3568_PHYREG32);
}
break;
default:
@@ -1371,11 +1348,7 @@ static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
}
}
- if (priv->enable_ssc) {
- val = readl(priv->mmio + RK3568_PHYREG8);
- val |= RK3568_PHYREG8_SSC_EN;
- writel(val, priv->mmio + RK3568_PHYREG8);
- }
+ rk_combphy_common_cfg_ssc(priv, rate);
return 0;
}
--
2.7.4
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* Re: Re: [PATCH v9 1/2] dt-bindings: phy: eswin: Document the EIC7700 SoC SATA PHY
From: Min Lin @ 2026-03-05 3:14 UTC (permalink / raw)
To: Bo Gan
Cc: Yulin Lu, vkoul, neil.armstrong, robh, krzk+dt, conor+dt, p.zabel,
linux-phy, devicetree, linux-kernel, ningyu, fenglin
In-Reply-To: <5116340c-4702-47d0-87f0-9399937f0e64@gmail.com>
Hi Bo Gan,
To make SATA, USB work, the HSP clock&reset driver is needed. We're doing the upstreaming for this driver.
Here is a draft for your reference, it has been verified with latest v15 clock patchset on our site:
[1]HSP clock and reset generator: https://github.com/eswincomputing/linux-next/pull/23
[2]SATA dts node example: https://github.com/eswincomputing/linux-next/pull/24
Regards,
Lin Min
> -----Original Messages-----
> From: "Bo Gan" <ganboing@gmail.com>
> Send time:Tuesday, 03/03/2026 19:46:25
> To: "Yulin Lu" <luyulin@eswincomputing.com>, vkoul@kernel.org, neil.armstrong@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
> Cc: ningyu@eswincomputing.com, linmin@eswincomputing.com, fenglin@eswincomputing.com
> Subject: Re: [PATCH v9 1/2] dt-bindings: phy: eswin: Document the EIC7700 SoC SATA PHY
>
> Hi Yulin,
>
> Can your team share the dt and driver for &hspcrg? I want to do some
> testing with your latest v15 clock patchset on my P550 w/ SATA. W/o
> &hspcrg, the SATA phy can't be enabled, hence SATA drive doesn't work.
>
> Bo
>
> On 2/5/26 00:21, Yulin Lu wrote:
> > Document the SATA PHY on the EIC7700 SoC platform,
> > describing its usage.
> >
> > Signed-off-by: Yulin Lu <luyulin@eswincomputing.com>
> > ---
> > .../bindings/phy/eswin,eic7700-sata-phy.yaml | 92 +++++++++++++++++++
> > 1 file changed, 92 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/phy/eswin,eic7700-sata-phy.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/phy/eswin,eic7700-sata-phy.yaml b/Documentation/devicetree/bindings/phy/eswin,eic7700-sata-phy.yaml
> > new file mode 100644
> > index 000000000000..fc7dbac77acf
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/eswin,eic7700-sata-phy.yaml
> > @@ -0,0 +1,92 @@
> > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/phy/eswin,eic7700-sata-phy.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Eswin EIC7700 SoC SATA PHY
> > +
> > +maintainers:
> > + - Yulin Lu <luyulin@eswincomputing.com>
> > + - Huan He <hehuan1@eswincomputing.com>
> > +
> > +properties:
> > + compatible:
> > + const: eswin,eic7700-sata-phy
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + clocks:
> > + maxItems: 1
> > +
> > + clock-names:
> > + const: phy
> > +
> > + resets:
> > + maxItems: 2
> > +
> > + reset-names:
> > + items:
> > + - const: port
> > + - const: phy
> > +
> > + eswin,tx-amplitude-tuning:
> > + description: This adjusts the transmitter amplitude signal, and its value
> > + is derived from eye diagram tuning. The three values correspond to Gen1,
> > + Gen2, and Gen3 parameters respectively.
> > + $ref: /schemas/types.yaml#/definitions/uint32-array
> > + items:
> > + - description: Gen1 parameter.
> > + minimum: 0
> > + maximum: 0x7f
> > + - description: Gen2 parameter.
> > + minimum: 0
> > + maximum: 0x7f
> > + - description: Gen3 parameter.
> > + minimum: 0
> > + maximum: 0x7f
> > + default: [0, 0, 0]
> > +
> > + eswin,tx-preemph-tuning:
> > + description: This adjusts the transmitter de-emphasis signal, and its value
> > + is derived from eye diagram tuning. The three values correspond to Gen1,
> > + Gen2, and Gen3 parameters respectively.
> > + $ref: /schemas/types.yaml#/definitions/uint32-array
> > + items:
> > + - description: Gen1 parameter.
> > + minimum: 0
> > + maximum: 0x3f
> > + - description: Gen2 parameter.
> > + minimum: 0
> > + maximum: 0x3f
> > + - description: Gen3 parameter.
> > + minimum: 0
> > + maximum: 0x3f
> > + default: [0, 0, 0]
> > +
> > + "#phy-cells":
> > + const: 0
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - clocks
> > + - clock-names
> > + - resets
> > + - reset-names
> > + - "#phy-cells"
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + sata-phy@50440300 {
> > + compatible = "eswin,eic7700-sata-phy";
> > + reg = <0x50440300 0x40>;
> > + clocks = <&hspcrg 17>;
> > + clock-names = "phy";
> > + resets = <&hspcrg 0>, <&hspcrg 1>;
> > + reset-names = "port", "phy";
> > + #phy-cells = <0>;
> > + };
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^ permalink raw reply
* Re: [PATCH phy-next 03/22] usb: add missing headers transitively included by <linux/phy/phy.h>
From: Thinh Nguyen @ 2026-03-05 2:43 UTC (permalink / raw)
To: Vladimir Oltean
Cc: linux-phy@lists.infradead.org, Vinod Koul, Neil Armstrong,
dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org,
linux-arm-kernel@lists.infradead.org,
linux-arm-msm@vger.kernel.org, linux-can@vger.kernel.org,
linux-gpio@vger.kernel.org, linux-ide@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-media@vger.kernel.org,
linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
linux-riscv@lists.infradead.org,
linux-rockchip@lists.infradead.org,
linux-samsung-soc@vger.kernel.org, linux-sunxi@lists.linux.dev,
linux-tegra@vger.kernel.org, linux-usb@vger.kernel.org,
netdev@vger.kernel.org, spacemit@lists.linux.dev,
UNGLinuxDriver@microchip.com, Peter Chen, Greg Kroah-Hartman,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Thinh Nguyen
In-Reply-To: <20260304175735.2660419-4-vladimir.oltean@nxp.com>
On Wed, Mar 04, 2026, Vladimir Oltean wrote:
> The chipidea ci_hdrc_imx driver uses regulator consumer API like
> regulator_enable() but does not include <linux/regulator/consumer.h>.
>
> The core USB HCD driver calls invalidate_kernel_vmap_range() and
> flush_kernel_vmap_range(), but does not include <linux/highmem.h>.
>
> The DWC3 gadget driver calls:
> - device_property_present()
> - device_property_count_u8()
> - device_property_read_u8_array()
> but does not include <linux/property.h>
>
> The dwc3-generic-plat driver uses of_device_get_match_data() but does
> not include <linux/of.h>.
>
> In all these cases, the necessary includes were still provided somehow,
> directly or indirectly, through <linux/phy/phy.h>. The latter header
> wants to drop those includes, so fill in the required headers to avoid
> any breakage.
>
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> ---
> Cc: Peter Chen <peter.chen@kernel.org>
> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Cc: Frank Li <Frank.Li@nxp.com>
> Cc: Sascha Hauer <s.hauer@pengutronix.de>
> Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
> ---
> drivers/usb/chipidea/ci_hdrc_imx.c | 1 +
> drivers/usb/core/hcd.c | 1 +
> drivers/usb/dwc3/dwc3-generic-plat.c | 1 +
> drivers/usb/dwc3/gadget.c | 1 +
> 4 files changed, 4 insertions(+)
>
> diff --git a/drivers/usb/chipidea/ci_hdrc_imx.c b/drivers/usb/chipidea/ci_hdrc_imx.c
> index 56d2ba824a0b..0a21d7cc5f5a 100644
> --- a/drivers/usb/chipidea/ci_hdrc_imx.c
> +++ b/drivers/usb/chipidea/ci_hdrc_imx.c
> @@ -17,6 +17,7 @@
> #include <linux/clk.h>
> #include <linux/pinctrl/consumer.h>
> #include <linux/pm_qos.h>
> +#include <linux/regulator/consumer.h>
>
> #include "ci.h"
> #include "ci_hdrc_imx.h"
> diff --git a/drivers/usb/core/hcd.c b/drivers/usb/core/hcd.c
> index dee842ea6931..7a3261f72463 100644
> --- a/drivers/usb/core/hcd.c
> +++ b/drivers/usb/core/hcd.c
> @@ -10,6 +10,7 @@
> */
>
> #include <linux/bcd.h>
> +#include <linux/highmem.h>
> #include <linux/module.h>
> #include <linux/version.h>
> #include <linux/kernel.h>
> diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-generic-plat.c
> index e846844e0023..2ee1bb9d7199 100644
> --- a/drivers/usb/dwc3/dwc3-generic-plat.c
> +++ b/drivers/usb/dwc3/dwc3-generic-plat.c
> @@ -8,6 +8,7 @@
> */
>
> #include <linux/clk.h>
> +#include <linux/of.h>
> #include <linux/platform_device.h>
> #include <linux/reset.h>
> #include <linux/regmap.h>
> diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
> index 0a688904ce8c..d06171af6870 100644
> --- a/drivers/usb/dwc3/gadget.c
> +++ b/drivers/usb/dwc3/gadget.c
> @@ -10,6 +10,7 @@
>
> #include <linux/kernel.h>
> #include <linux/delay.h>
> +#include <linux/property.h>
> #include <linux/slab.h>
> #include <linux/spinlock.h>
> #include <linux/platform_device.h>
> --
> 2.43.0
>
For dwc3 related changes:
Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
Thanks,
Thinh
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^ permalink raw reply
* Re: [PATCH net-next v2 0/7] net: stmmac: qcom-ethqos: further serdes reorganisation
From: Jakub Kicinski @ 2026-03-05 1:56 UTC (permalink / raw)
To: Vinod Koul
Cc: Russell King (Oracle), Andrew Lunn, Alexandre Torgue, Andrew Lunn,
David S. Miller, Eric Dumazet, linux-arm-kernel, linux-arm-msm,
linux-phy, linux-stm32, Mohd Ayaan Anwar, Neil Armstrong, netdev,
Paolo Abeni
In-Reply-To: <aacD3osfaZkLsGxm@shell.armlinux.org.uk>
On Tue, 3 Mar 2026 15:53:02 +0000 Russell King (Oracle) wrote:
> This part of the series focuses on the generic PHY driver, but these
> changes have dependencies on the ethernet driver, hence why
> it will need to go via net-next. Furthermore, subsequent changes
> depend on these patches.
Hi Vinod, given the dependency on the existing stuff in net-next
are you okay with patches 3-6 going to net-next without at tag
you can pull?
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^ permalink raw reply
* [PATCH v4 2/2] phy: k1-usb: k3: add USB2 PHY support
From: Yixun Lan @ 2026-03-05 1:00 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Ze Huang
Cc: Junzhong Pan, linux-phy, devicetree, linux-riscv, spacemit,
linux-kernel, Yixun Lan, Yao Zi
In-Reply-To: <20260305-11-k3-usb2-phy-v4-0-15554fb933bc@kernel.org>
Add USB2 PHY support for SpacemiT K3 SoC.
Register layout of handling USB disconnect operation has been changed,
So introducing a platform data to distinguish the different SoCs.
Reviewed-by: Yao Zi <me@ziyao.cc>
Signed-off-by: Yixun Lan <dlan@kernel.org>
---
drivers/phy/spacemit/phy-k1-usb2.c | 34 +++++++++++++++++++++++++++++-----
1 file changed, 29 insertions(+), 5 deletions(-)
diff --git a/drivers/phy/spacemit/phy-k1-usb2.c b/drivers/phy/spacemit/phy-k1-usb2.c
index 9215d0b223b2..87b943d9111f 100644
--- a/drivers/phy/spacemit/phy-k1-usb2.c
+++ b/drivers/phy/spacemit/phy-k1-usb2.c
@@ -51,6 +51,9 @@
#define PHY_K1_HS_HOST_DISC 0x40
#define PHY_K1_HS_HOST_DISC_CLR BIT(0)
+#define PHY_K3_HS_HOST_DISC 0x20
+#define PHY_K3_HS_HOST_DISC_CLR BIT(8)
+
#define PHY_PLL_DIV_CFG 0x98
#define PHY_FDIV_FRACT_8_15 GENMASK(7, 0)
#define PHY_FDIV_FRACT_16_19 GENMASK(11, 8)
@@ -145,7 +148,7 @@ static int spacemit_usb2phy_exit(struct phy *phy)
return 0;
}
-static int spacemit_usb2phy_disconnect(struct phy *phy, int port)
+static int spacemit_k1_usb2phy_disconnect(struct phy *phy, int port)
{
struct spacemit_usb2phy *sphy = phy_get_drvdata(phy);
@@ -155,10 +158,27 @@ static int spacemit_usb2phy_disconnect(struct phy *phy, int port)
return 0;
}
-static const struct phy_ops spacemit_usb2phy_ops = {
+static int spacemit_k3_usb2phy_disconnect(struct phy *phy, int port)
+{
+ struct spacemit_usb2phy *sphy = phy_get_drvdata(phy);
+
+ regmap_update_bits(sphy->regmap_base, PHY_K3_HS_HOST_DISC,
+ PHY_K3_HS_HOST_DISC_CLR, PHY_K3_HS_HOST_DISC_CLR);
+
+ return 0;
+}
+
+static const struct phy_ops spacemit_k1_usb2phy_ops = {
.init = spacemit_usb2phy_init,
.exit = spacemit_usb2phy_exit,
- .disconnect = spacemit_usb2phy_disconnect,
+ .disconnect = spacemit_k1_usb2phy_disconnect,
+ .owner = THIS_MODULE,
+};
+
+static const struct phy_ops spacemit_k3_usb2phy_ops = {
+ .init = spacemit_usb2phy_init,
+ .exit = spacemit_usb2phy_exit,
+ .disconnect = spacemit_k3_usb2phy_disconnect,
.owner = THIS_MODULE,
};
@@ -167,12 +187,15 @@ static int spacemit_usb2phy_probe(struct platform_device *pdev)
struct phy_provider *phy_provider;
struct device *dev = &pdev->dev;
struct spacemit_usb2phy *sphy;
+ const struct phy_ops *ops;
void __iomem *base;
sphy = devm_kzalloc(dev, sizeof(*sphy), GFP_KERNEL);
if (!sphy)
return -ENOMEM;
+ ops = device_get_match_data(dev);
+
sphy->clk = devm_clk_get_prepared(&pdev->dev, NULL);
if (IS_ERR(sphy->clk))
return dev_err_probe(dev, PTR_ERR(sphy->clk), "Failed to get clock\n");
@@ -185,7 +208,7 @@ static int spacemit_usb2phy_probe(struct platform_device *pdev)
if (IS_ERR(sphy->regmap_base))
return dev_err_probe(dev, PTR_ERR(sphy->regmap_base), "Failed to init regmap\n");
- sphy->phy = devm_phy_create(dev, NULL, &spacemit_usb2phy_ops);
+ sphy->phy = devm_phy_create(dev, NULL, ops);
if (IS_ERR(sphy->phy))
return dev_err_probe(dev, PTR_ERR(sphy->phy), "Failed to create phy\n");
@@ -196,7 +219,8 @@ static int spacemit_usb2phy_probe(struct platform_device *pdev)
}
static const struct of_device_id spacemit_usb2phy_dt_match[] = {
- { .compatible = "spacemit,k1-usb2-phy", },
+ { .compatible = "spacemit,k1-usb2-phy", .data = &spacemit_k1_usb2phy_ops },
+ { .compatible = "spacemit,k3-usb2-phy", .data = &spacemit_k3_usb2phy_ops },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, spacemit_usb2phy_dt_match);
--
2.53.0
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^ permalink raw reply related
* [PATCH v4 1/2] dt-bindings: phy: spacemit: k3: add USB2 PHY support
From: Yixun Lan @ 2026-03-05 1:00 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Ze Huang
Cc: Junzhong Pan, linux-phy, devicetree, linux-riscv, spacemit,
linux-kernel, Yixun Lan, Krzysztof Kozlowski
In-Reply-To: <20260305-11-k3-usb2-phy-v4-0-15554fb933bc@kernel.org>
Introduce a compatible string for the USB2 PHY in SpacemiT K3 SoC. The IP
of USB2 PHY mostly shares the same functionalities with K1 SoC, while has
some register layout changes.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Yixun Lan <dlan@kernel.org>
---
Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml
index 43eaca90d88c..18025e5f60d6 100644
--- a/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml
@@ -4,14 +4,16 @@
$id: http://devicetree.org/schemas/phy/spacemit,usb2-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: SpacemiT K1 SoC USB 2.0 PHY
+title: SpacemiT K1/K3 SoC USB 2.0 PHY
maintainers:
- Ze Huang <huang.ze@linux.dev>
properties:
compatible:
- const: spacemit,k1-usb2-phy
+ enum:
+ - spacemit,k1-usb2-phy
+ - spacemit,k3-usb2-phy
reg:
maxItems: 1
--
2.53.0
--
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^ permalink raw reply related
* [PATCH v4 0/2] phy: spacemit: Add USB2 PHY support for K3 SoC
From: Yixun Lan @ 2026-03-05 1:00 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Ze Huang
Cc: Junzhong Pan, linux-phy, devicetree, linux-riscv, spacemit,
linux-kernel, Yixun Lan, Krzysztof Kozlowski, Yao Zi
The series trys to add USB2 PHY support for SpacemiT K3 SoC, while
patch [1/2] implement a disconnect function which is needed during
next connection.
No DTS part has been inclueded in this series, instead I plan to
submit them later while adding USB host support.
I've collected all patches and pushed a complete review branch here[1],
for people who interested to test easily, which include DTS and necessary
changes, other patches may still need to improve, but sufficient for
verifying the functionality.
Link: https://github.com/spacemit-com/linux/tree/WIP/k3/usb2 [1]
To: Vinod Koul <vkoul@kernel.org>
To: Neil Armstrong <neil.armstrong@linaro.org>
To: Rob Herring <robh@kernel.org>
To: Krzysztof Kozlowski <krzk+dt@kernel.org>
To: Conor Dooley <conor+dt@kernel.org>
To: Ze Huang <huang.ze@linux.dev>
Cc: Junzhong Pan <panjunzhong@linux.spacemit.com>
Cc: linux-phy@lists.infradead.org
Cc: devicetree@vger.kernel.org
Cc: linux-riscv@lists.infradead.org
Cc: spacemit@lists.linux.dev
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Yixun Lan <dlan@kernel.org>
Changes in v4:
- rebase to v7.0-rc1
- fix preceding open parenthesis
- drop patch 1 which already merged
- publish a test branch
- Link to v3: https://lore.kernel.org/r/20260216152653.25244-1-dlan@kernel.org
Change in v3:
- split from v2 as bug fix
- fix alignment to open parenthesis
- http://lore.kernel.org/r/20260216090112.n5jjpui3luqsybb5@skbuf
- Link to v2: https://lore.kernel.org/r/20260214-11-k3-usb2-phy-v2-0-6ed31e031ab4@kernel.org
Changes in v2:
- collect ACK
- add Fixes tag
- implement separate phy_ops
- Link to v1: https://lore.kernel.org/r/20260212-11-k3-usb2-phy-v1-0-43578592405d@kernel.org
---
Yixun Lan (2):
dt-bindings: phy: spacemit: k3: add USB2 PHY support
phy: k1-usb: k3: add USB2 PHY support
.../devicetree/bindings/phy/spacemit,usb2-phy.yaml | 6 ++--
drivers/phy/spacemit/phy-k1-usb2.c | 34 ++++++++++++++++++----
2 files changed, 33 insertions(+), 7 deletions(-)
---
base-commit: d2625d793eefe7dff154361ec66fed7886781d73
change-id: 20260124-11-k3-usb2-phy-c4630b990b1f
Best regards,
--
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^ permalink raw reply
* Re: [PATCH 5/5] arch: arm64: dts: qcom: Add support for PCIe3a
From: Dmitry Baryshkov @ 2026-03-05 0:02 UTC (permalink / raw)
To: Qiang Yu
Cc: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Bjorn Andersson, Konrad Dybcio,
linux-arm-msm, linux-phy, devicetree, linux-kernel
In-Reply-To: <20260304-glymur_gen5x8_phy-v1-5-849e9a72e125@oss.qualcomm.com>
On Wed, Mar 04, 2026 at 12:21:59AM -0800, Qiang Yu wrote:
> Describe PCIe3a controller and PHY. Also add required system resources
> like regulators, clocks, interrupts and registers configuration for PCIe3a.
>
> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/glymur.dtsi | 314 ++++++++++++++++++++++++++++++++++-
> 1 file changed, 313 insertions(+), 1 deletion(-)
>
> + pcie3a_phy: phy@f00000 {
> + compatible = "qcom,glymur-qmp-gen5x8-pcie-phy";
> + reg = <0 0x00f00000 0 0x10000>;
> +
> + clocks = <&gcc GCC_PCIE_PHY_3A_AUX_CLK>,
> + <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
> + <&tcsr TCSR_PCIE_3_CLKREF_EN>,
> + <&gcc GCC_PCIE_3A_PHY_RCHNG_CLK>,
> + <&gcc GCC_PCIE_3A_PIPE_CLK>,
> + <&gcc GCC_PCIE_PHY_3B_AUX_CLK>;
> + clock-names = "aux",
> + "cfg_ahb",
> + "ref",
> + "rchng",
Please align on "
> + "pipe",
> + "phy_b_aux";
> +
> + resets = <&gcc GCC_PCIE_3A_PHY_BCR>,
> + <&gcc GCC_PCIE_3A_NOCSR_COM_PHY_BCR>,
> + <&gcc GCC_PCIE_3B_PHY_BCR>,
> + <&gcc GCC_PCIE_3B_NOCSR_COM_PHY_BCR>;
> + reset-names = "phy",
> + "phy_nocsr",
> + "phy_b",
> + "phy_b_nocsr";
Should we be supplying _b components by default? What about the
platforms which might use separate 3a and 3b?
> +
> + assigned-clocks = <&gcc GCC_PCIE_3A_PHY_RCHNG_CLK>;
> + assigned-clock-rates = <100000000>;
> +
> + power-domains = <&gcc GCC_PCIE_3A_PHY_GDSC>,
> + <&gcc GCC_PCIE_3B_PHY_GDSC>;
> +
> + #clock-cells = <0>;
> + clock-output-names = "pcie3a_pipe_clk";
> +
> + #phy-cells = <0>;
> +
> + status = "disabled";
> + };
> +
> pcie4: pci@1bf0000 {
> device_type = "pci";
> compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100";
>
> --
> 2.34.1
>
--
With best wishes
Dmitry
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^ permalink raw reply
* Re: [PATCH 2/5] phy: qcom: qmp-pcie: Add multiple power-domains support
From: Dmitry Baryshkov @ 2026-03-04 23:58 UTC (permalink / raw)
To: Qiang Yu
Cc: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Bjorn Andersson, Konrad Dybcio,
linux-arm-msm, linux-phy, devicetree, linux-kernel
In-Reply-To: <20260304-glymur_gen5x8_phy-v1-2-849e9a72e125@oss.qualcomm.com>
On Wed, Mar 04, 2026 at 12:21:56AM -0800, Qiang Yu wrote:
> The Glymur SoC's 3rd PCIe instance supports 8-lane mode using two PHYs in
> a bifurcated configuration. Each PHY has its own power domain (phy_gdsc)
> that must be powered on before initialization per hardware requirements.
>
> Current PHY power management assumes a single power domain per PHY,
> preventing proper setup for this dual-PHY scenario. Add support for
> multiple power domains by using devm_pm_domain_attach_list() to attach
> power domains manually, while maintaining compatibility with single
> power domain PHYs.
>
> Enable runtime PM to allow power domain control when the PCIe driver
> calls phy_power_on/phy_power_off:
>
> - Single power domain: QMP PHY platform device directly attaches to
> power domain and controls it during runtime resume/suspend
> - Multiple power domains: devm_pm_domain_attach_list() creates virtual
> devices as power domain suppliers, linked to the QMP PHY platform
> device as consumer
>
> This ensures power domains are properly attached and turned on/off
> for both single and multiple power domain configurations.
>
> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> index fed2fc9bb31108d51f88d34f3379c7744681f485..7369c291be51aa1ad7a330459dcb857f5a1988f6 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> @@ -17,6 +17,7 @@
> #include <linux/phy/pcie.h>
> #include <linux/phy/phy.h>
> #include <linux/platform_device.h>
> +#include <linux/pm_domain.h>
> #include <linux/regmap.h>
> #include <linux/regulator/consumer.h>
> #include <linux/reset.h>
> @@ -3334,6 +3335,8 @@ struct qmp_pcie {
>
> struct clk_fixed_rate pipe_clk_fixed;
> struct clk_fixed_rate aux_clk_fixed;
> +
> + struct dev_pm_domain_list *pd_list;
> };
>
> static bool qphy_checkbits(const void __iomem *base, u32 offset, u32 val)
> @@ -5348,6 +5351,16 @@ static int qmp_pcie_probe(struct platform_device *pdev)
> WARN_ON_ONCE(!qmp->cfg->pwrdn_ctrl);
> WARN_ON_ONCE(!qmp->cfg->phy_status);
>
> + ret = devm_pm_domain_attach_list(dev, NULL, &qmp->pd_list);
> + if (ret < 0 && ret != -EEXIST) {
> + dev_err(dev, "Failed to attach power domain\n");
> + return ret;
> + }
> +
> + ret = devm_pm_runtime_enable(dev);
> + if (ret)
> + return ret;
These two should be separate commits.
> +
> ret = qmp_pcie_clk_init(qmp);
> if (ret)
> return ret;
>
> --
> 2.34.1
>
--
With best wishes
Dmitry
--
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^ permalink raw reply
* Re: [PATCH phy-next 21/22] phy: remove temporary provider compatibility from consumer header
From: Dmitry Baryshkov @ 2026-03-04 23:56 UTC (permalink / raw)
To: Vladimir Oltean
Cc: linux-phy, Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-sunxi,
linux-tegra, linux-usb, netdev, spacemit, UNGLinuxDriver
In-Reply-To: <20260304175735.2660419-22-vladimir.oltean@nxp.com>
On Wed, Mar 04, 2026 at 07:57:34PM +0200, Vladimir Oltean wrote:
> Now that all consumers have been updated to no longer dereference fields
> inside struct phy, we can hide its definition altogether from public view.
>
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> ---
> include/linux/phy/phy.h | 2 --
> 1 file changed, 2 deletions(-)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
--
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^ permalink raw reply
* Re: [PATCH phy-next 20/22] phy: include PHY provider header
From: Dmitry Baryshkov @ 2026-03-04 23:56 UTC (permalink / raw)
To: Vladimir Oltean
Cc: linux-phy, Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-sunxi,
linux-tegra, linux-usb, netdev, spacemit, UNGLinuxDriver
In-Reply-To: <20260304175735.2660419-21-vladimir.oltean@nxp.com>
On Wed, Mar 04, 2026 at 07:57:33PM +0200, Vladimir Oltean wrote:
> The majority of PHY drivers are PHY providers (obviously).
>
> Some are providers *and* consumers (phy-meson-axg-mipi-dphy,
> phy-meson-axg-pcie). These are the Amlogic AXG SoCs, which split the
> physical layer into two chained PHYs: the digital layer and the analog
> layer. The DSI or PCIe controller interacts only with the digital PHY,
> presumably for simplicity.
>
> The rest of PHY drivers which include <linux/phy/phy.h> do so because
> they call phy_set_bus_width(), a consumer function.
>
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> ---
> drivers/phy/allwinner/phy-sun4i-usb.c | 3 ++-
> drivers/phy/allwinner/phy-sun50i-usb3.c | 3 ++-
> drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 4 ++--
> drivers/phy/allwinner/phy-sun9i-usb.c | 3 ++-
> drivers/phy/amlogic/phy-meson-axg-mipi-dphy.c | 2 ++
> drivers/phy/amlogic/phy-meson-axg-mipi-pcie-analog.c | 3 ++-
> drivers/phy/amlogic/phy-meson-axg-pcie.c | 2 ++
> drivers/phy/amlogic/phy-meson-g12a-mipi-dphy-analog.c | 3 ++-
> drivers/phy/amlogic/phy-meson-g12a-usb2.c | 2 ++
> drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c | 3 ++-
> drivers/phy/amlogic/phy-meson-gxl-usb2.c | 3 ++-
> drivers/phy/amlogic/phy-meson8-hdmi-tx.c | 3 ++-
> drivers/phy/amlogic/phy-meson8b-usb2.c | 3 ++-
> drivers/phy/apple/atc.c | 3 ++-
> drivers/phy/broadcom/phy-bcm-cygnus-pcie.c | 3 ++-
> drivers/phy/broadcom/phy-bcm-kona-usb2.c | 4 +++-
> drivers/phy/broadcom/phy-bcm-ns-usb2.c | 3 ++-
> drivers/phy/broadcom/phy-bcm-ns-usb3.c | 3 ++-
> drivers/phy/broadcom/phy-bcm-ns2-pcie.c | 3 ++-
> drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c | 3 ++-
> drivers/phy/broadcom/phy-bcm-sr-pcie.c | 3 ++-
> drivers/phy/broadcom/phy-bcm-sr-usb.c | 3 ++-
> drivers/phy/broadcom/phy-bcm63xx-usbh.c | 3 ++-
> drivers/phy/broadcom/phy-brcm-sata.c | 3 ++-
> drivers/phy/broadcom/phy-brcm-usb.c | 2 +-
> drivers/phy/cadence/cdns-dphy-rx.c | 3 ++-
> drivers/phy/cadence/cdns-dphy.c | 4 ++--
> drivers/phy/cadence/phy-cadence-salvo.c | 3 ++-
> drivers/phy/cadence/phy-cadence-sierra.c | 3 ++-
> drivers/phy/cadence/phy-cadence-torrent.c | 3 ++-
> drivers/phy/canaan/phy-k230-usb.c | 3 ++-
> drivers/phy/eswin/phy-eic7700-sata.c | 3 ++-
> drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c | 3 ++-
> drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 4 ++--
> drivers/phy/freescale/phy-fsl-imx8mq-usb.c | 3 ++-
> drivers/phy/freescale/phy-fsl-imx8qm-hsio.c | 6 +++---
> drivers/phy/freescale/phy-fsl-imx8qm-lvds-phy.c | 3 ++-
> drivers/phy/freescale/phy-fsl-lynx-28g.c | 3 ++-
> drivers/phy/hisilicon/phy-hi3660-usb3.c | 3 ++-
> drivers/phy/hisilicon/phy-hi3670-pcie.c | 3 ++-
> drivers/phy/hisilicon/phy-hi3670-usb3.c | 3 ++-
> drivers/phy/hisilicon/phy-hi6220-usb.c | 3 ++-
> drivers/phy/hisilicon/phy-hisi-inno-usb2.c | 4 +++-
> drivers/phy/hisilicon/phy-histb-combphy.c | 3 ++-
> drivers/phy/hisilicon/phy-hix5hd2-sata.c | 3 ++-
> drivers/phy/ingenic/phy-ingenic-usb.c | 3 ++-
> drivers/phy/intel/phy-intel-keembay-emmc.c | 3 ++-
> drivers/phy/intel/phy-intel-keembay-usb.c | 3 ++-
> drivers/phy/intel/phy-intel-lgm-combo.c | 4 ++--
> drivers/phy/intel/phy-intel-lgm-emmc.c | 3 ++-
> drivers/phy/lantiq/phy-lantiq-rcu-usb2.c | 3 ++-
> drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c | 4 ++--
> drivers/phy/marvell/phy-armada375-usb2.c | 3 ++-
> drivers/phy/marvell/phy-armada38x-comphy.c | 3 ++-
> drivers/phy/marvell/phy-berlin-sata.c | 3 ++-
> drivers/phy/marvell/phy-berlin-usb.c | 3 ++-
> drivers/phy/marvell/phy-mmp3-hsic.c | 3 ++-
> drivers/phy/marvell/phy-mmp3-usb.c | 3 ++-
> drivers/phy/marvell/phy-mvebu-a3700-comphy.c | 3 ++-
> drivers/phy/marvell/phy-mvebu-a3700-utmi.c | 3 ++-
> drivers/phy/marvell/phy-mvebu-cp110-comphy.c | 3 ++-
> drivers/phy/marvell/phy-mvebu-cp110-utmi.c | 3 ++-
> drivers/phy/marvell/phy-mvebu-sata.c | 3 ++-
> drivers/phy/marvell/phy-pxa-28nm-hsic.c | 3 ++-
> drivers/phy/marvell/phy-pxa-28nm-usb2.c | 3 ++-
> drivers/phy/marvell/phy-pxa-usb.c | 3 ++-
> drivers/phy/mediatek/phy-mtk-dp.c | 3 ++-
> drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c | 1 -
> drivers/phy/mediatek/phy-mtk-hdmi.h | 3 ++-
> drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c | 2 +-
> drivers/phy/mediatek/phy-mtk-mipi-dsi.h | 3 ++-
> drivers/phy/mediatek/phy-mtk-pcie.c | 2 +-
> drivers/phy/mediatek/phy-mtk-tphy.c | 2 +-
> drivers/phy/mediatek/phy-mtk-ufs.c | 2 +-
> drivers/phy/mediatek/phy-mtk-xfi-tphy.c | 2 +-
> drivers/phy/mediatek/phy-mtk-xsphy.c | 2 +-
> drivers/phy/microchip/lan966x_serdes.c | 4 ++--
> drivers/phy/microchip/sparx5_serdes.c | 2 +-
> drivers/phy/motorola/phy-cpcap-usb.c | 3 ++-
> drivers/phy/motorola/phy-mapphone-mdm6600.c | 4 +++-
> drivers/phy/mscc/phy-ocelot-serdes.c | 3 ++-
> drivers/phy/nuvoton/phy-ma35d1-usb2.c | 3 ++-
> drivers/phy/phy-airoha-pcie.c | 2 +-
> drivers/phy/phy-can-transceiver.c | 3 ++-
> drivers/phy/phy-core-mipi-dphy.c | 4 ++--
> drivers/phy/phy-core.c | 2 ++
> drivers/phy/phy-google-usb.c | 3 ++-
> drivers/phy/phy-lpc18xx-usb-otg.c | 3 ++-
> drivers/phy/phy-nxp-ptn3222.c | 3 ++-
> drivers/phy/phy-pistachio-usb.c | 4 ++--
> drivers/phy/phy-snps-eusb2.c | 2 ++
> drivers/phy/phy-xgene.c | 3 ++-
> drivers/phy/qualcomm/phy-ath79-usb.c | 3 ++-
> drivers/phy/qualcomm/phy-qcom-apq8064-sata.c | 3 ++-
> drivers/phy/qualcomm/phy-qcom-edp.c | 3 ++-
> drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c | 3 ++-
> drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c | 3 ++-
> drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c | 3 ++-
> drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c | 3 ++-
> drivers/phy/qualcomm/phy-qcom-m31-eusb2.c | 2 ++
> drivers/phy/qualcomm/phy-qcom-m31.c | 3 ++-
> drivers/phy/qualcomm/phy-qcom-pcie2.c | 3 ++-
> drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 3 ++-
> drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 3 ++-
> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 3 ++-
> drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 3 ++-
> drivers/phy/qualcomm/phy-qcom-qmp-usb-legacy.c | 3 ++-
> drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 3 ++-
> drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 3 ++-
> drivers/phy/qualcomm/phy-qcom-qusb2.c | 4 ++--
> drivers/phy/qualcomm/phy-qcom-sgmii-eth.c | 3 ++-
> drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c | 3 ++-
> drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c | 3 ++-
> drivers/phy/qualcomm/phy-qcom-usb-hs-28nm.c | 3 ++-
> drivers/phy/qualcomm/phy-qcom-usb-hs.c | 3 ++-
> drivers/phy/qualcomm/phy-qcom-usb-hsic.c | 3 ++-
> drivers/phy/qualcomm/phy-qcom-usb-ss.c | 3 ++-
> drivers/phy/ralink/phy-mt7621-pci.c | 3 ++-
> drivers/phy/ralink/phy-ralink-usb.c | 3 ++-
> drivers/phy/realtek/phy-rtk-usb2.c | 3 ++-
> drivers/phy/realtek/phy-rtk-usb3.c | 3 ++-
> drivers/phy/renesas/phy-rcar-gen2.c | 3 ++-
> drivers/phy/renesas/phy-rcar-gen3-pcie.c | 3 ++-
> drivers/phy/renesas/phy-rcar-gen3-usb2.c | 3 ++-
> drivers/phy/renesas/phy-rcar-gen3-usb3.c | 3 ++-
> drivers/phy/renesas/phy-rzg3e-usb3.c | 3 ++-
> drivers/phy/renesas/r8a779f0-ether-serdes.c | 3 ++-
> drivers/phy/rockchip/phy-rockchip-dp.c | 3 ++-
> drivers/phy/rockchip/phy-rockchip-dphy-rx0.c | 3 ++-
> drivers/phy/rockchip/phy-rockchip-emmc.c | 3 ++-
> drivers/phy/rockchip/phy-rockchip-inno-csidphy.c | 3 ++-
> drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c | 4 ++--
> drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 2 ++
> drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 3 ++-
> drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 3 ++-
> drivers/phy/rockchip/phy-rockchip-pcie.c | 2 +-
> drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c | 3 ++-
> drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 2 ++
> drivers/phy/rockchip/phy-rockchip-snps-pcie3.c | 3 ++-
> drivers/phy/rockchip/phy-rockchip-typec.c | 4 ++--
> drivers/phy/rockchip/phy-rockchip-usb.c | 3 ++-
> drivers/phy/rockchip/phy-rockchip-usbdp.c | 2 ++
> drivers/phy/samsung/phy-exynos-dp-video.c | 3 ++-
> drivers/phy/samsung/phy-exynos-mipi-video.c | 3 ++-
> drivers/phy/samsung/phy-exynos-pcie.c | 3 ++-
> drivers/phy/samsung/phy-exynos4210-usb2.c | 3 ++-
> drivers/phy/samsung/phy-exynos4x12-usb2.c | 3 ++-
> drivers/phy/samsung/phy-exynos5-usbdrd.c | 2 ++
> drivers/phy/samsung/phy-exynos5250-sata.c | 3 ++-
> drivers/phy/samsung/phy-exynos5250-usb2.c | 3 ++-
> drivers/phy/samsung/phy-s5pv210-usb2.c | 3 ++-
> drivers/phy/samsung/phy-samsung-ufs.c | 2 +-
> drivers/phy/samsung/phy-samsung-ufs.h | 3 ++-
> drivers/phy/samsung/phy-samsung-usb2.c | 2 ++
> drivers/phy/samsung/phy-samsung-usb2.h | 3 ++-
> drivers/phy/socionext/phy-uniphier-ahci.c | 3 ++-
> drivers/phy/socionext/phy-uniphier-pcie.c | 3 ++-
> drivers/phy/socionext/phy-uniphier-usb2.c | 3 ++-
> drivers/phy/socionext/phy-uniphier-usb3hs.c | 3 ++-
> drivers/phy/socionext/phy-uniphier-usb3ss.c | 3 ++-
> drivers/phy/sophgo/phy-cv1800-usb2.c | 3 ++-
> drivers/phy/spacemit/phy-k1-pcie.c | 4 ++--
> drivers/phy/spacemit/phy-k1-usb2.c | 3 ++-
> drivers/phy/st/phy-miphy28lp.c | 4 ++--
> drivers/phy/st/phy-spear1310-miphy.c | 3 ++-
> drivers/phy/st/phy-spear1340-miphy.c | 3 ++-
> drivers/phy/st/phy-stih407-usb.c | 3 ++-
> drivers/phy/st/phy-stm32-combophy.c | 3 ++-
> drivers/phy/st/phy-stm32-usbphyc.c | 2 ++
> drivers/phy/starfive/phy-jh7110-dphy-rx.c | 3 ++-
> drivers/phy/starfive/phy-jh7110-dphy-tx.c | 3 ++-
> drivers/phy/starfive/phy-jh7110-pcie.c | 3 ++-
> drivers/phy/starfive/phy-jh7110-usb.c | 3 ++-
> drivers/phy/sunplus/phy-sunplus-usb2.c | 3 ++-
> drivers/phy/tegra/phy-tegra194-p2u.c | 3 ++-
> drivers/phy/tegra/xusb-tegra124.c | 2 +-
> drivers/phy/tegra/xusb-tegra186.c | 2 +-
> drivers/phy/tegra/xusb-tegra210.c | 2 +-
> drivers/phy/tegra/xusb.c | 2 +-
> drivers/phy/ti/phy-am654-serdes.c | 3 ++-
> drivers/phy/ti/phy-da8xx-usb.c | 3 ++-
> drivers/phy/ti/phy-dm816x-usb.c | 3 ++-
> drivers/phy/ti/phy-gmii-sel.c | 3 ++-
> drivers/phy/ti/phy-omap-usb2.c | 3 ++-
> drivers/phy/ti/phy-ti-pipe3.c | 3 ++-
> drivers/phy/ti/phy-twl4030-usb.c | 3 ++-
> drivers/phy/xilinx/phy-zynqmp.c | 4 ++--
> include/linux/phy/phy-sun4i-usb.h | 2 +-
> include/linux/phy/ulpi_phy.h | 2 +-
> 189 files changed, 363 insertions(+), 193 deletions(-)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> #phy/qualcomm
--
With best wishes
Dmitry
--
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^ permalink raw reply
* Re: [PATCH phy-next 12/22] phy: move provider API out of public <linux/phy/phy.h>
From: Dmitry Baryshkov @ 2026-03-04 23:54 UTC (permalink / raw)
To: Vladimir Oltean
Cc: linux-phy, Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-sunxi,
linux-tegra, linux-usb, netdev, spacemit, UNGLinuxDriver
In-Reply-To: <20260304175735.2660419-13-vladimir.oltean@nxp.com>
On Wed, Mar 04, 2026 at 07:57:25PM +0200, Vladimir Oltean wrote:
> The major goal is to hide the contents of struct phy from consumer
> drivers.
>
> The idea with "phy-props.h" is that both consumers and providers make
> use of some data types. So both headers include "phy-props.h".
>
> Two slight points of contention.
>
> 1. phy_set_bus_width(): Vinod explains that despite the current caller
> situation (9 providers, 1 consumer), it is a consumer API function.
>
> The use case is that the controller (for example UFS) may have
> limitations and should set the expected lanes to be used and width on
> those lanes. A number of Generic PHYs can support multiple lanes and
> multiple width so this is way for controller telling I am using this
> configuration.
>
> 2. phy-provider.h should go to include/linux/phy/ or to drivers/phy/?
> We do have 3 PHY providers outside of drivers/phy/:
>
> drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/sun8i_a83t_dphy.c
> drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
> drivers/pinctrl/tegra/pinctrl-tegra-xusb.c
>
> but the practice is not encouraged, and with time, these should be
> moved to the subsystem. This is not something that I can do now.
>
> For temporary compatibility, keep including the provider header. This
> will be removed when abuses are all gotten rid of.
>
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> ---
> drivers/phy/phy-core.c | 34 +++
> drivers/phy/phy-provider.h | 256 +++++++++++++++++
> include/linux/phy/phy-props.h | 75 +++++
> include/linux/phy/phy.h | 499 +++++++---------------------------
> 4 files changed, 458 insertions(+), 406 deletions(-)
> create mode 100644 drivers/phy/phy-provider.h
> create mode 100644 include/linux/phy/phy-props.h
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
--
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^ permalink raw reply
* Re: [PATCH phy-next 11/22] drm/msm/dp: remove debugging prints with internal struct phy state
From: Dmitry Baryshkov @ 2026-03-04 23:53 UTC (permalink / raw)
To: Vladimir Oltean
Cc: linux-phy, Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-sunxi,
linux-tegra, linux-usb, netdev, spacemit, UNGLinuxDriver,
Rob Clark, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang,
Sean Paul, Marijn Suijten, David Airlie, Simona Vetter
In-Reply-To: <20260304175735.2660419-12-vladimir.oltean@nxp.com>
On Wed, Mar 04, 2026 at 07:57:24PM +0200, Vladimir Oltean wrote:
> These do not provide much value, and will become hard to maintain once
> the Generic PHY framework starts hiding the contents of struct phy from
> consumers.
>
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> ---
> Cc: Rob Clark <robin.clark@oss.qualcomm.com>
> Cc: Dmitry Baryshkov <lumag@kernel.org>
> Cc: Abhinav Kumar <abhinav.kumar@linux.dev>
> Cc: Jessica Zhang <jesszhan0024@gmail.com>
> Cc: Sean Paul <sean@poorly.run>
> Cc: Marijn Suijten <marijn.suijten@somainline.org>
> Cc: David Airlie <airlied@gmail.com>
> Cc: Simona Vetter <simona@ffwll.ch>
> ---
> drivers/gpu/drm/msm/dp/dp_ctrl.c | 18 ------------------
> 1 file changed, 18 deletions(-)
>
Acked-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
--
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^ permalink raw reply
* [PATCH] dt-bindings: display/msm: move DSI PHY bindings to phy/ subdir
From: Dmitry Baryshkov @ 2026-03-04 23:47 UTC (permalink / raw)
To: Rob Clark, Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang,
Sean Paul, Marijn Suijten, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Vinod Koul, Neil Armstrong,
Krishna Manikandan, Jonathan Marek
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
linux-phy
Historically DSI PHY bindings landed to the display/msm subdir, however
they describe PHYs and as such they should be in the phy/ subdir.
Follow the example of other Qualcomm display-related PHYs (HDMI, eDP)
and move bindings for the Qualcomm DSI PHYs to the correct subdir.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
---
Merge strategy: I'd ask to merge bindings through the msm tree, reducing
the conflicts for the current kernel development cycle. Starting from
the cycle after this patch is merged, DSI PHY bindings should go through
the PHY tree.
---
.../{display/msm/dsi-phy-10nm.yaml => phy/qcom,dsi-phy-10nm.yaml} | 4 ++--
.../{display/msm/dsi-phy-14nm.yaml => phy/qcom,dsi-phy-14nm.yaml} | 4 ++--
.../{display/msm/dsi-phy-20nm.yaml => phy/qcom,dsi-phy-20nm.yaml} | 4 ++--
.../{display/msm/dsi-phy-28nm.yaml => phy/qcom,dsi-phy-28nm.yaml} | 4 ++--
.../{display/msm/dsi-phy-7nm.yaml => phy/qcom,dsi-phy-7nm.yaml} | 4 ++--
.../{display/msm/dsi-phy-common.yaml => phy/qcom,dsi-phy-common.yaml} | 2 +-
6 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml b/Documentation/devicetree/bindings/phy/qcom,dsi-phy-10nm.yaml
similarity index 96%
rename from Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml
rename to Documentation/devicetree/bindings/phy/qcom,dsi-phy-10nm.yaml
index fc9abf090f0d..d98217747ad1 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,dsi-phy-10nm.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
-$id: http://devicetree.org/schemas/display/msm/dsi-phy-10nm.yaml#
+$id: http://devicetree.org/schemas/phy/qcom,dsi-phy-10nm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display DSI 10nm PHY
@@ -10,7 +10,7 @@ maintainers:
- Krishna Manikandan <quic_mkrishn@quicinc.com>
allOf:
- - $ref: dsi-phy-common.yaml#
+ - $ref: qcom,dsi-phy-common.yaml#
properties:
compatible:
diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml b/Documentation/devicetree/bindings/phy/qcom,dsi-phy-14nm.yaml
similarity index 94%
rename from Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
rename to Documentation/devicetree/bindings/phy/qcom,dsi-phy-14nm.yaml
index 206a9a4b3845..be31b9bac9d5 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,dsi-phy-14nm.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
-$id: http://devicetree.org/schemas/display/msm/dsi-phy-14nm.yaml#
+$id: http://devicetree.org/schemas/phy/qcom,dsi-phy-14nm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display DSI 14nm PHY
@@ -10,7 +10,7 @@ maintainers:
- Krishna Manikandan <quic_mkrishn@quicinc.com>
allOf:
- - $ref: dsi-phy-common.yaml#
+ - $ref: qcom,dsi-phy-common.yaml#
properties:
compatible:
diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml b/Documentation/devicetree/bindings/phy/qcom,dsi-phy-20nm.yaml
similarity index 93%
rename from Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml
rename to Documentation/devicetree/bindings/phy/qcom,dsi-phy-20nm.yaml
index 93570052992a..1d135419d015 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,dsi-phy-20nm.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
-$id: http://devicetree.org/schemas/display/msm/dsi-phy-20nm.yaml#
+$id: http://devicetree.org/schemas/phy/qcom,dsi-phy-20nm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display DSI 20nm PHY
@@ -10,7 +10,7 @@ maintainers:
- Krishna Manikandan <quic_mkrishn@quicinc.com>
allOf:
- - $ref: dsi-phy-common.yaml#
+ - $ref: qcom,dsi-phy-common.yaml#
properties:
compatible:
diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml b/Documentation/devicetree/bindings/phy/qcom,dsi-phy-28nm.yaml
similarity index 94%
rename from Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml
rename to Documentation/devicetree/bindings/phy/qcom,dsi-phy-28nm.yaml
index 371befa9f9d2..f8fe75fa29d7 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,dsi-phy-28nm.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
-$id: http://devicetree.org/schemas/display/msm/dsi-phy-28nm.yaml#
+$id: http://devicetree.org/schemas/phy/qcom,dsi-phy-28nm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display DSI 28nm PHY
@@ -10,7 +10,7 @@ maintainers:
- Krishna Manikandan <quic_mkrishn@quicinc.com>
allOf:
- - $ref: dsi-phy-common.yaml#
+ - $ref: qcom,dsi-phy-common.yaml#
properties:
compatible:
diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml b/Documentation/devicetree/bindings/phy/qcom,dsi-phy-7nm.yaml
similarity index 95%
rename from Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml
rename to Documentation/devicetree/bindings/phy/qcom,dsi-phy-7nm.yaml
index 9a9a6c4abf43..d45015e24639 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,dsi-phy-7nm.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
-$id: http://devicetree.org/schemas/display/msm/dsi-phy-7nm.yaml#
+$id: http://devicetree.org/schemas/phy/qcom,dsi-phy-7nm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display DSI 7nm PHY
@@ -10,7 +10,7 @@ maintainers:
- Jonathan Marek <jonathan@marek.ca>
allOf:
- - $ref: dsi-phy-common.yaml#
+ - $ref: qcom,dsi-phy-common.yaml#
properties:
compatible:
diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-common.yaml b/Documentation/devicetree/bindings/phy/qcom,dsi-phy-common.yaml
similarity index 91%
rename from Documentation/devicetree/bindings/display/msm/dsi-phy-common.yaml
rename to Documentation/devicetree/bindings/phy/qcom,dsi-phy-common.yaml
index d0ce85a08b6d..849321e56b2f 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi-phy-common.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,dsi-phy-common.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
-$id: http://devicetree.org/schemas/display/msm/dsi-phy-common.yaml#
+$id: http://devicetree.org/schemas/phy/qcom,dsi-phy-common.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display DSI PHY Common Properties
---
base-commit: ac47870fd795549f03d57e0879fc730c79119f4b
change-id: 20260305-msm-dsi-phy-96b063cce7b5
Best regards,
--
With best wishes
Dmitry
--
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linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH] phy: miphy28lp: kzalloc + kcalloc to single kzalloc
From: Rosen Penev @ 2026-03-04 23:28 UTC (permalink / raw)
To: linux-phy
Cc: Patrice Chotard, Vinod Koul, Neil Armstrong, Kees Cook,
Gustavo A. R. Silva, moderated list:ARM/STI ARCHITECTURE,
open list,
open list:KERNEL HARDENING (not covered by other areas):Keyword:b__counted_by(_le|_be)?b
Use flex array to simplify allocation.
Allows using __counted_by for extra runtime analysis.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
---
drivers/phy/st/phy-miphy28lp.c | 12 +++++-------
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/drivers/phy/st/phy-miphy28lp.c b/drivers/phy/st/phy-miphy28lp.c
index 43cef89af55e..fd931ede7162 100644
--- a/drivers/phy/st/phy-miphy28lp.c
+++ b/drivers/phy/st/phy-miphy28lp.c
@@ -224,8 +224,8 @@ struct miphy28lp_dev {
struct device *dev;
struct regmap *regmap;
struct mutex miphy_mutex;
- struct miphy28lp_phy **phys;
int nphys;
+ struct miphy28lp_phy *phys[] __counted_by(nphys);
};
enum miphy_sata_gen { SATA_GEN1, SATA_GEN2, SATA_GEN3 };
@@ -1168,16 +1168,14 @@ static int miphy28lp_probe(struct platform_device *pdev)
struct phy_provider *provider;
struct phy *phy;
int ret, port = 0;
+ size_t nphys;
- miphy_dev = devm_kzalloc(&pdev->dev, sizeof(*miphy_dev), GFP_KERNEL);
+ nphys = of_get_child_count(np);
+ miphy_dev = devm_kzalloc(&pdev->dev, struct_size(wiphy_dev, phys, nphys) ,GFP_KERNEL);
if (!miphy_dev)
return -ENOMEM;
- miphy_dev->nphys = of_get_child_count(np);
- miphy_dev->phys = devm_kcalloc(&pdev->dev, miphy_dev->nphys,
- sizeof(*miphy_dev->phys), GFP_KERNEL);
- if (!miphy_dev->phys)
- return -ENOMEM;
+ miphy_dev->nphys = nphys;
miphy_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
if (IS_ERR(miphy_dev->regmap)) {
--
2.53.0
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH] phy: qualcomm: usb-hs-28nm: use flex array
From: Rosen Penev @ 2026-03-04 23:06 UTC (permalink / raw)
To: linux-phy
Cc: Vinod Koul, Neil Armstrong, Kees Cook, Gustavo A. R. Silva,
open list:ARM/QUALCOMM MAILING LIST, open list,
open list:KERNEL HARDENING (not covered by other areas):Keyword:b__counted_by(_le|_be)?b
Allows simplifying allocation to a single kzalloc call.
Also allows using __counted_by for extra runtime analysis.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
---
drivers/phy/qualcomm/phy-qcom-usb-hs-28nm.c | 14 ++++++--------
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-usb-hs-28nm.c b/drivers/phy/qualcomm/phy-qcom-usb-hs-28nm.c
index a52a9bf13b75..b2ea038a8f25 100644
--- a/drivers/phy/qualcomm/phy-qcom-usb-hs-28nm.c
+++ b/drivers/phy/qualcomm/phy-qcom-usb-hs-28nm.c
@@ -56,13 +56,13 @@ struct hsphy_data {
struct hsphy_priv {
void __iomem *base;
- struct clk_bulk_data *clks;
int num_clks;
struct reset_control *phy_reset;
struct reset_control *por_reset;
struct regulator_bulk_data vregs[VREG_NUM];
const struct hsphy_data *data;
enum phy_mode mode;
+ struct clk_bulk_data clks[] __counted_by(num_clks);
};
static int qcom_snps_hsphy_set_mode(struct phy *phy, enum phy_mode mode,
@@ -309,23 +309,21 @@ static int qcom_snps_hsphy_probe(struct platform_device *pdev)
struct phy_provider *provider;
struct hsphy_priv *priv;
struct phy *phy;
+ size_t size;
int ret;
int i;
- priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ size = ARRAY_SIZE(qcom_snps_hsphy_clks);
+ priv = devm_kzalloc(dev, struct_size(priv, clks, size), GFP_KERNEL);
if (!priv)
return -ENOMEM;
+ priv->num_clks = size;
+
priv->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
- priv->num_clks = ARRAY_SIZE(qcom_snps_hsphy_clks);
- priv->clks = devm_kcalloc(dev, priv->num_clks, sizeof(*priv->clks),
- GFP_KERNEL);
- if (!priv->clks)
- return -ENOMEM;
-
for (i = 0; i < priv->num_clks; i++)
priv->clks[i].id = qcom_snps_hsphy_clks[i];
--
2.53.0
--
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https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* Re: [PATCH phy-next 02/22] PCI: add missing headers transitively included by <linux/phy/phy.h>
From: Vladimir Oltean @ 2026-03-04 22:34 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: linux-phy, Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-sunxi,
linux-tegra, linux-usb, netdev, spacemit, UNGLinuxDriver,
Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas, Heiko Stuebner,
Shawn Guo, Yixun Lan, Thierry Reding, Jonathan Hunter, Shawn Lin,
Kevin Xie
In-Reply-To: <20260304222408.GA40990@bhelgaas>
On Wed, Mar 04, 2026 at 04:24:08PM -0600, Bjorn Helgaas wrote:
> Update subject line to match history:
>
> PCI: Add missing headers transitively included by <linux/phy/phy.h>
My case-insensitive brain didn't understand what you mean by this.
I had to power on my case-sensitive part :-/
> On Wed, Mar 04, 2026 at 07:57:15PM +0200, Vladimir Oltean wrote:
> > The tegra as well as a few dwc PCI controller drivers uses PM runtime
> > operations without including the required <linux/pm_runtime.h> header.
> >
> > Similarly, pcie-rockchip-host, pcie-starfive as well as a few dwc PCI
> > controllers use the regulator consumer API without including
> > <linux/regulator/consumer.h>.
> >
> > It seems these function prototypes were indirectly provided by
> > <linux/phy/phy.h>, mostly by mistake (none of the functions it exports
> > need it).
> >
> > Before the PHY header can drop the unnecessary includes, make sure the
> > PCI controller drivers include what they use.
> >
> > Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
>
> With the subject line update:
>
> Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Thanks for looking!
--
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^ permalink raw reply
* Re: [PATCH phy-next 08/22] PCI: remove device links to PHY
From: Bjorn Helgaas @ 2026-03-04 22:28 UTC (permalink / raw)
To: Vladimir Oltean
Cc: linux-phy, Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-sunxi,
linux-tegra, linux-usb, netdev, spacemit, UNGLinuxDriver,
Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas,
Vignesh Raghavendra, Siddharth Vadapalli
In-Reply-To: <20260304175735.2660419-9-vladimir.oltean@nxp.com>
Update subject line to:
PCI: Remove redundant device links to PHY
On Wed, Mar 04, 2026 at 07:57:21PM +0200, Vladimir Oltean wrote:
> This is practically a full revert of commit
> 7a4db656a635 ("PCI: dra7xx: Create functional dependency between PCIe and PHY")
> and a partial revert of the device link pieces from commits
> dfb80534692d ("PCI: cadence: Add generic PHY support to host and EP drivers")
> 49229238ab47 ("PCI: keystone: Cleanup PHY handling")
>
> The trouble with these commits is that they dereference fields inside
> struct phy from a consumer driver, which will become no longer possible.
>
> Since commit 987351e1ea77 ("phy: core: Add consumer device link
> support") from 2019, the PHY core also adds a device link to order PHY
> provider and consumer suspend/resume operations. All reverted commits
> are from 2017-2018, and what they do should actually be redundant now.
>
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
With subject line update:
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Thanks for doing this; it's great to get rid of all that code.
> ---
> Cc: Lorenzo Pieralisi <lpieralisi@kernel.org>
> Cc: "Krzysztof Wilczyński" <kwilczynski@kernel.org>
> Cc: Manivannan Sadhasivam <mani@kernel.org>
> Cc: Rob Herring <robh@kernel.org>
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Cc: Vignesh Raghavendra <vigneshr@ti.com>
> Cc: Siddharth Vadapalli <s-vadapalli@ti.com>
> ---
> drivers/pci/controller/cadence/pcie-cadence.c | 16 +---------
> drivers/pci/controller/dwc/pci-dra7xx.c | 16 ----------
> drivers/pci/controller/dwc/pci-keystone.c | 31 +++----------------
> 3 files changed, 5 insertions(+), 58 deletions(-)
>
> diff --git a/drivers/pci/controller/cadence/pcie-cadence.c b/drivers/pci/controller/cadence/pcie-cadence.c
> index a1eada56edba..0ac980249941 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence.c
> +++ b/drivers/pci/controller/cadence/pcie-cadence.c
> @@ -222,7 +222,6 @@ int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie)
> struct device_node *np = dev->of_node;
> int phy_count;
> struct phy **phy;
> - struct device_link **link;
> int i;
> int ret;
> const char *name;
> @@ -238,10 +237,6 @@ int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie)
> if (!phy)
> return -ENOMEM;
>
> - link = devm_kcalloc(dev, phy_count, sizeof(*link), GFP_KERNEL);
> - if (!link)
> - return -ENOMEM;
> -
> for (i = 0; i < phy_count; i++) {
> of_property_read_string_index(np, "phy-names", i, &name);
> phy[i] = devm_phy_get(dev, name);
> @@ -249,17 +244,10 @@ int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie)
> ret = PTR_ERR(phy[i]);
> goto err_phy;
> }
> - link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS);
> - if (!link[i]) {
> - devm_phy_put(dev, phy[i]);
> - ret = -EINVAL;
> - goto err_phy;
> - }
> }
>
> pcie->phy_count = phy_count;
> pcie->phy = phy;
> - pcie->link = link;
>
> ret = cdns_pcie_enable_phy(pcie);
> if (ret)
> @@ -268,10 +256,8 @@ int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie)
> return 0;
>
> err_phy:
> - while (--i >= 0) {
> - device_link_del(link[i]);
> + while (--i >= 0)
> devm_phy_put(dev, phy[i]);
> - }
>
> return ret;
> }
> diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c
> index d5d26229063f..b91ab37845c9 100644
> --- a/drivers/pci/controller/dwc/pci-dra7xx.c
> +++ b/drivers/pci/controller/dwc/pci-dra7xx.c
> @@ -9,7 +9,6 @@
>
> #include <linux/clk.h>
> #include <linux/delay.h>
> -#include <linux/device.h>
> #include <linux/err.h>
> #include <linux/interrupt.h>
> #include <linux/irq.h>
> @@ -683,7 +682,6 @@ static int dra7xx_pcie_probe(struct platform_device *pdev)
> int i;
> int phy_count;
> struct phy **phy;
> - struct device_link **link;
> void __iomem *base;
> struct dw_pcie *pci;
> struct dra7xx_pcie *dra7xx;
> @@ -731,10 +729,6 @@ static int dra7xx_pcie_probe(struct platform_device *pdev)
> if (!phy)
> return -ENOMEM;
>
> - link = devm_kcalloc(dev, phy_count, sizeof(*link), GFP_KERNEL);
> - if (!link)
> - return -ENOMEM;
> -
> dra7xx->clk = devm_clk_get_optional(dev, NULL);
> if (IS_ERR(dra7xx->clk))
> return dev_err_probe(dev, PTR_ERR(dra7xx->clk),
> @@ -749,12 +743,6 @@ static int dra7xx_pcie_probe(struct platform_device *pdev)
> phy[i] = devm_phy_get(dev, name);
> if (IS_ERR(phy[i]))
> return PTR_ERR(phy[i]);
> -
> - link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS);
> - if (!link[i]) {
> - ret = -EINVAL;
> - goto err_link;
> - }
> }
>
> dra7xx->base = base;
> @@ -856,10 +844,6 @@ static int dra7xx_pcie_probe(struct platform_device *pdev)
> pm_runtime_disable(dev);
> dra7xx_pcie_disable_phy(dra7xx);
>
> -err_link:
> - while (--i >= 0)
> - device_link_del(link[i]);
> -
> return ret;
> }
>
> diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c
> index 642e4c45eefc..07698c645e02 100644
> --- a/drivers/pci/controller/dwc/pci-keystone.c
> +++ b/drivers/pci/controller/dwc/pci-keystone.c
> @@ -130,7 +130,6 @@ struct keystone_pcie {
> int num_lanes;
> u32 num_viewport;
> struct phy **phy;
> - struct device_link **link;
> struct device_node *msi_intc_np;
> struct irq_domain *intx_irq_domain;
> struct device_node *np;
> @@ -1118,7 +1117,6 @@ static int ks_pcie_probe(struct platform_device *pdev)
> enum dw_pcie_device_mode mode;
> struct dw_pcie *pci;
> struct keystone_pcie *ks_pcie;
> - struct device_link **link;
> struct gpio_desc *gpiod;
> struct resource *res;
> void __iomem *base;
> @@ -1189,31 +1187,17 @@ static int ks_pcie_probe(struct platform_device *pdev)
> if (!phy)
> return -ENOMEM;
>
> - link = devm_kcalloc(dev, num_lanes, sizeof(*link), GFP_KERNEL);
> - if (!link)
> - return -ENOMEM;
> -
> for (i = 0; i < num_lanes; i++) {
> snprintf(name, sizeof(name), "pcie-phy%d", i);
> phy[i] = devm_phy_optional_get(dev, name);
> if (IS_ERR(phy[i])) {
> ret = PTR_ERR(phy[i]);
> - goto err_link;
> - }
> -
> - if (!phy[i])
> - continue;
> -
> - link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS);
> - if (!link[i]) {
> - ret = -EINVAL;
> - goto err_link;
> + goto err;
> }
> }
>
> ks_pcie->np = np;
> ks_pcie->pci = pci;
> - ks_pcie->link = link;
> ks_pcie->num_lanes = num_lanes;
> ks_pcie->phy = phy;
>
> @@ -1223,7 +1207,7 @@ static int ks_pcie_probe(struct platform_device *pdev)
> ret = PTR_ERR(gpiod);
> if (ret != -EPROBE_DEFER)
> dev_err(dev, "Failed to get reset GPIO\n");
> - goto err_link;
> + goto err;
> }
>
> /* Obtain references to the PHYs */
> @@ -1238,7 +1222,7 @@ static int ks_pcie_probe(struct platform_device *pdev)
>
> if (ret) {
> dev_err(dev, "failed to enable phy\n");
> - goto err_link;
> + goto err;
> }
>
> platform_set_drvdata(pdev, ks_pcie);
> @@ -1325,25 +1309,18 @@ static int ks_pcie_probe(struct platform_device *pdev)
> pm_runtime_disable(dev);
> ks_pcie_disable_phy(ks_pcie);
>
> -err_link:
> - while (--i >= 0 && link[i])
> - device_link_del(link[i]);
> -
> +err:
> return ret;
> }
>
> static void ks_pcie_remove(struct platform_device *pdev)
> {
> struct keystone_pcie *ks_pcie = platform_get_drvdata(pdev);
> - struct device_link **link = ks_pcie->link;
> - int num_lanes = ks_pcie->num_lanes;
> struct device *dev = &pdev->dev;
>
> pm_runtime_put(dev);
> pm_runtime_disable(dev);
> ks_pcie_disable_phy(ks_pcie);
> - while (num_lanes--)
> - device_link_del(link[num_lanes]);
> }
>
> static struct platform_driver ks_pcie_driver = {
> --
> 2.43.0
>
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^ permalink raw reply
* Re: [PATCH phy-next 02/22] PCI: add missing headers transitively included by <linux/phy/phy.h>
From: Bjorn Helgaas @ 2026-03-04 22:24 UTC (permalink / raw)
To: Vladimir Oltean
Cc: linux-phy, Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-sunxi,
linux-tegra, linux-usb, netdev, spacemit, UNGLinuxDriver,
Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas, Heiko Stuebner,
Shawn Guo, Yixun Lan, Thierry Reding, Jonathan Hunter, Shawn Lin,
Kevin Xie
In-Reply-To: <20260304175735.2660419-3-vladimir.oltean@nxp.com>
Update subject line to match history:
PCI: Add missing headers transitively included by <linux/phy/phy.h>
On Wed, Mar 04, 2026 at 07:57:15PM +0200, Vladimir Oltean wrote:
> The tegra as well as a few dwc PCI controller drivers uses PM runtime
> operations without including the required <linux/pm_runtime.h> header.
>
> Similarly, pcie-rockchip-host, pcie-starfive as well as a few dwc PCI
> controllers use the regulator consumer API without including
> <linux/regulator/consumer.h>.
>
> It seems these function prototypes were indirectly provided by
> <linux/phy/phy.h>, mostly by mistake (none of the functions it exports
> need it).
>
> Before the PHY header can drop the unnecessary includes, make sure the
> PCI controller drivers include what they use.
>
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
With the subject line update:
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
> ---
> Cc: Lorenzo Pieralisi <lpieralisi@kernel.org>
> Cc: "Krzysztof Wilczyński" <kwilczynski@kernel.org>
> Cc: Manivannan Sadhasivam <mani@kernel.org>
> Cc: Rob Herring <robh@kernel.org>
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Cc: Heiko Stuebner <heiko@sntech.de>
> Cc: Shawn Guo <shawn.guo@linaro.org>
> Cc: Yixun Lan <dlan@kernel.org>
> Cc: Thierry Reding <thierry.reding@gmail.com>
> Cc: Jonathan Hunter <jonathanh@nvidia.com>
> Cc: Shawn Lin <shawn.lin@rock-chips.com>
> Cc: Kevin Xie <kevin.xie@starfivetech.com>
> ---
> drivers/pci/controller/dwc/pci-keystone.c | 1 +
> drivers/pci/controller/dwc/pcie-dw-rockchip.c | 1 +
> drivers/pci/controller/dwc/pcie-histb.c | 1 +
> drivers/pci/controller/dwc/pcie-qcom-ep.c | 1 +
> drivers/pci/controller/dwc/pcie-spacemit-k1.c | 2 ++
> drivers/pci/controller/dwc/pcie-tegra194.c | 1 +
> drivers/pci/controller/pci-tegra.c | 1 +
> drivers/pci/controller/pcie-rockchip-host.c | 1 +
> drivers/pci/controller/plda/pcie-starfive.c | 1 +
> 9 files changed, 10 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c
> index 20fa4dadb82a..642e4c45eefc 100644
> --- a/drivers/pci/controller/dwc/pci-keystone.c
> +++ b/drivers/pci/controller/dwc/pci-keystone.c
> @@ -24,6 +24,7 @@
> #include <linux/of_pci.h>
> #include <linux/phy/phy.h>
> #include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> #include <linux/regmap.h>
> #include <linux/resource.h>
> #include <linux/signal.h>
> diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> index 5b17da63151d..e0079ec108ab 100644
> --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> @@ -21,6 +21,7 @@
> #include <linux/phy/phy.h>
> #include <linux/platform_device.h>
> #include <linux/regmap.h>
> +#include <linux/regulator/consumer.h>
> #include <linux/reset.h>
>
> #include "../../pci.h"
> diff --git a/drivers/pci/controller/dwc/pcie-histb.c b/drivers/pci/controller/dwc/pcie-histb.c
> index a52071589377..432a54c5bfce 100644
> --- a/drivers/pci/controller/dwc/pcie-histb.c
> +++ b/drivers/pci/controller/dwc/pcie-histb.c
> @@ -18,6 +18,7 @@
> #include <linux/pci.h>
> #include <linux/phy/phy.h>
> #include <linux/platform_device.h>
> +#include <linux/regulator/consumer.h>
> #include <linux/resource.h>
> #include <linux/reset.h>
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
> index 18460f01b2c6..e417122da51d 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
> @@ -19,6 +19,7 @@
> #include <linux/phy/phy.h>
> #include <linux/platform_device.h>
> #include <linux/pm_domain.h>
> +#include <linux/pm_runtime.h>
> #include <linux/regmap.h>
> #include <linux/reset.h>
> #include <linux/module.h>
> diff --git a/drivers/pci/controller/dwc/pcie-spacemit-k1.c b/drivers/pci/controller/dwc/pcie-spacemit-k1.c
> index be20a520255b..dbec159fd458 100644
> --- a/drivers/pci/controller/dwc/pcie-spacemit-k1.c
> +++ b/drivers/pci/controller/dwc/pcie-spacemit-k1.c
> @@ -15,7 +15,9 @@
> #include <linux/mod_devicetable.h>
> #include <linux/phy/phy.h>
> #include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> #include <linux/regmap.h>
> +#include <linux/regulator/consumer.h>
> #include <linux/reset.h>
> #include <linux/types.h>
>
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index 06571d806ab3..3378a89580ab 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -27,6 +27,7 @@
> #include <linux/platform_device.h>
> #include <linux/pm_runtime.h>
> #include <linux/random.h>
> +#include <linux/regulator/consumer.h>
> #include <linux/reset.h>
> #include <linux/resource.h>
> #include <linux/types.h>
> diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c
> index 512309763d1f..a2c1662b6e81 100644
> --- a/drivers/pci/controller/pci-tegra.c
> +++ b/drivers/pci/controller/pci-tegra.c
> @@ -36,6 +36,7 @@
> #include <linux/phy/phy.h>
> #include <linux/pinctrl/consumer.h>
> #include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> #include <linux/reset.h>
> #include <linux/sizes.h>
> #include <linux/slab.h>
> diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/controller/pcie-rockchip-host.c
> index ee1822ca01db..46adb4582fcc 100644
> --- a/drivers/pci/controller/pcie-rockchip-host.c
> +++ b/drivers/pci/controller/pcie-rockchip-host.c
> @@ -24,6 +24,7 @@
> #include <linux/of_pci.h>
> #include <linux/phy/phy.h>
> #include <linux/platform_device.h>
> +#include <linux/regulator/consumer.h>
>
> #include "../pci.h"
> #include "pcie-rockchip.h"
> diff --git a/drivers/pci/controller/plda/pcie-starfive.c b/drivers/pci/controller/plda/pcie-starfive.c
> index 298036c3e7f9..22344cca167b 100644
> --- a/drivers/pci/controller/plda/pcie-starfive.c
> +++ b/drivers/pci/controller/plda/pcie-starfive.c
> @@ -21,6 +21,7 @@
> #include <linux/platform_device.h>
> #include <linux/pm_runtime.h>
> #include <linux/regmap.h>
> +#include <linux/regulator/consumer.h>
> #include <linux/reset.h>
> #include "../../pci.h"
>
> --
> 2.43.0
>
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^ permalink raw reply
* Re: [RESEND 1/1] phy: freescale: imx8qm-hsio: provide regmap names
From: Vladimir Oltean @ 2026-03-04 21:27 UTC (permalink / raw)
To: Alexander Stein
Cc: Vinod Koul, Neil Armstrong, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, linux-phy, imx,
linux-arm-kernel, linux-kernel
In-Reply-To: <20260211144949.1128122-1-alexander.stein@ew.tq-group.com>
On Wed, Feb 11, 2026 at 03:49:48PM +0100, Alexander Stein wrote:
> This driver uses multiple regmaps, which will causes name conflicts
> in debugfs like:
> debugfs: '5f1a0000.phy' already exists in 'regmap'
> Fix this by using a dedicated regmap config for each resource, each
> having a dedicated regmap name.
>
> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> ---
> Same as the one sent in December but with an updated CC list.
>
> drivers/phy/freescale/phy-fsl-imx8qm-hsio.c | 23 +++++++++++++++++----
> 1 file changed, 19 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c b/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
> index 279b8ac7822df..4ab45c9f53dff 100644
> --- a/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
> +++ b/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
> @@ -107,7 +107,22 @@ static const char * const lan2_pcieb_clks[] = {"apb_pclk2", "pclk2", "ctl1_crr",
> static const char * const lan2_sata_clks[] = {"pclk2", "epcs_tx", "epcs_rx",
> "phy1_crr", "misc_crr"};
>
> -static const struct regmap_config regmap_config = {
> +static const struct regmap_config regmap_phy_config = {
> + .name = "phy",
> + .reg_bits = 32,
> + .val_bits = 32,
> + .reg_stride = 4,
> +};
> +
> +static const struct regmap_config regmap_ctrl_config = {
> + .name = "ctrl",
> + .reg_bits = 32,
> + .val_bits = 32,
> + .reg_stride = 4,
> +};
> +
> +static const struct regmap_config regmap_misc_config = {
> + .name = "misc",
Since __regmap_init() doesn't keep a persistent reference to the config,
just performs a deep copy of it (including regmap_set_name() ->
kstrdup_const()), technically you could have gotten away with just a
single on-stack regmap_config whose .name you kept changing for all 3
calls.
But this is perfectly valid as well.
Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
I don't think you need to do anything further, just wait for Vinod to
start going through the backlog.
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^ permalink raw reply
* Re: [PATCH 2/5] phy: qcom: qmp-pcie: Add multiple power-domains support
From: Bjorn Andersson @ 2026-03-04 20:46 UTC (permalink / raw)
To: Qiang Yu
Cc: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Konrad Dybcio, linux-arm-msm,
linux-phy, devicetree, linux-kernel
In-Reply-To: <20260304-glymur_gen5x8_phy-v1-2-849e9a72e125@oss.qualcomm.com>
On Wed, Mar 04, 2026 at 12:21:56AM -0800, Qiang Yu wrote:
> The Glymur SoC's 3rd PCIe instance supports 8-lane mode using two PHYs in
> a bifurcated configuration. Each PHY has its own power domain (phy_gdsc)
> that must be powered on before initialization per hardware requirements.
>
> Current PHY power management assumes a single power domain per PHY,
> preventing proper setup for this dual-PHY scenario. Add support for
> multiple power domains by using devm_pm_domain_attach_list() to attach
> power domains manually, while maintaining compatibility with single
> power domain PHYs.
>
> Enable runtime PM to allow power domain control when the PCIe driver
> calls phy_power_on/phy_power_off:
>
Enabling runtime PM seems like a separate change that impacts all
existing targets, while adding multiple power domains should only affect
the specific ones.
I'm not sure if it's too picky, but it would be nice to separate this -
so that any issues that might arise can be bisected down to one or the
other of these two changes?
> - Single power domain: QMP PHY platform device directly attaches to
> power domain and controls it during runtime resume/suspend
> - Multiple power domains: devm_pm_domain_attach_list() creates virtual
> devices as power domain suppliers, linked to the QMP PHY platform
> device as consumer
>
> This ensures power domains are properly attached and turned on/off
> for both single and multiple power domain configurations.
>
> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> index fed2fc9bb31108d51f88d34f3379c7744681f485..7369c291be51aa1ad7a330459dcb857f5a1988f6 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> @@ -17,6 +17,7 @@
> #include <linux/phy/pcie.h>
> #include <linux/phy/phy.h>
> #include <linux/platform_device.h>
> +#include <linux/pm_domain.h>
> #include <linux/regmap.h>
> #include <linux/regulator/consumer.h>
> #include <linux/reset.h>
> @@ -3334,6 +3335,8 @@ struct qmp_pcie {
>
> struct clk_fixed_rate pipe_clk_fixed;
> struct clk_fixed_rate aux_clk_fixed;
> +
> + struct dev_pm_domain_list *pd_list;
This is just an pointer to the list allocated inside
devm_pm_domain_attach_list(), as far as I can tell you don't need to
keep this in the qmp_pcie struct - as you're not using it anyways.
Regards,
Bjorn
> };
>
> static bool qphy_checkbits(const void __iomem *base, u32 offset, u32 val)
> @@ -5348,6 +5351,16 @@ static int qmp_pcie_probe(struct platform_device *pdev)
> WARN_ON_ONCE(!qmp->cfg->pwrdn_ctrl);
> WARN_ON_ONCE(!qmp->cfg->phy_status);
>
> + ret = devm_pm_domain_attach_list(dev, NULL, &qmp->pd_list);
> + if (ret < 0 && ret != -EEXIST) {
> + dev_err(dev, "Failed to attach power domain\n");
> + return ret;
> + }
> +
> + ret = devm_pm_runtime_enable(dev);
> + if (ret)
> + return ret;
> +
> ret = qmp_pcie_clk_init(qmp);
> if (ret)
> return ret;
>
> --
> 2.34.1
>
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^ permalink raw reply
* Re: [PATCH phy-next 01/22] ata: add <linux/pm_runtime.h> where missing
From: Damien Le Moal @ 2026-03-04 20:14 UTC (permalink / raw)
To: Vladimir Oltean, linux-phy
Cc: Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-sunxi,
linux-tegra, linux-usb, netdev, spacemit, UNGLinuxDriver,
Niklas Cassel
In-Reply-To: <20260304175735.2660419-2-vladimir.oltean@nxp.com>
On 3/5/26 02:57, Vladimir Oltean wrote:
> It appears that libahci.c, ahci.c as well as the ahci_brcm, ahci_ceva
> and ahci_qoriq drivers are using runtime PM operations without including
> <linux/pm_runtime.h>. This header is somehow being indirectly provided
> by <linux/phy/phy.h>, which would like to drop it (none of the functions
> it exports need it).
>
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Damien Le Moal <dlemoal@kernel.org>
--
Damien Le Moal
Western Digital Research
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^ permalink raw reply
* Re: [PATCH v4 1/2] dt-bindings: phy: qcom-edp: Add reference clock for sa8775p eDP PHY
From: Bjorn Andersson @ 2026-03-04 18:57 UTC (permalink / raw)
To: Ritesh Kumar
Cc: robin.clark, lumag, abhinav.kumar, sean, marijn.suijten,
maarten.lankhorst, mripard, tzimmermann, airlied, simona, robh,
krzk+dt, conor+dt, quic_mahap, konradybcio, mani, James.Bottomley,
martin.petersen, vkoul, kishon, cros-qcom-dts-watchers, linux-phy,
linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
linux-scsi, quic_vproddut
In-Reply-To: <20260128114853.2543416-2-quic_riteshk@quicinc.com>
On Wed, Jan 28, 2026 at 05:18:49PM +0530, Ritesh Kumar wrote:
> The initial sa8775p eDP PHY binding contribution missed adding support for
> voting on the eDP reference clock. This went unnoticed because the UFS PHY
> driver happened to enable the same clock.
>
> After commit 77d2fa54a945 ("scsi: ufs: qcom : Refactor phy_power_on/off
> calls"), the eDP reference clock is no longer kept enabled, which results
> in the following PHY power-on failure:
>
> phy phy-aec2a00.phy.10: phy poweron failed --> -110
>
> To fix this, explicit voting for the eDP reference clock is required.
> This patch adds the eDP reference clock for sa8775p eDP PHY and updates
> the corresponding example node.
>
> Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
Is there any reason why you didn't follow up on this patch Ritesh?
Looks like it's ready to be merged.
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Regards,
Bjorn
> ---
> .../devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml | 6 ++++--
> Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml | 1 +
> 2 files changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
> index e2730a2f25cf..6c827cf9692b 100644
> --- a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
> +++ b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
> @@ -200,9 +200,11 @@ examples:
> <0x0aec2000 0x1c8>;
>
> clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
> - <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>;
> + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
> + <&gcc GCC_EDP_REF_CLKREF_EN>;
> clock-names = "aux",
> - "cfg_ahb";
> + "cfg_ahb",
> + "ref";
>
> #clock-cells = <1>;
> #phy-cells = <0>;
> diff --git a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
> index 4a1daae3d8d4..0bf8bf4f66ac 100644
> --- a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
> @@ -74,6 +74,7 @@ allOf:
> compatible:
> enum:
> - qcom,glymur-dp-phy
> + - qcom,sa8775p-edp-phy
> - qcom,x1e80100-dp-phy
> then:
> properties:
> --
> 2.34.1
>
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