* [PATCH v9 06/23] scsi: ufs: mediatek: Rework resets
From: Nicolas Frattaroli @ 2026-03-06 13:24 UTC (permalink / raw)
To: Alim Akhtar, Avri Altman, Bart Van Assche, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chunfeng Yun, Vinod Koul,
Kishon Vijay Abraham I, Peter Wang, Stanley Jhu,
James E.J. Bottomley, Martin K. Petersen, Philipp Zabel,
Liam Girdwood, Mark Brown, Chaotian Jing, Neil Armstrong
Cc: Louis-Alexis Eyraud, kernel, linux-scsi, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-phy, Nicolas Frattaroli
In-Reply-To: <20260306-mt8196-ufs-v9-0-55b073f7a830@collabora.com>
Rework the reset control getting in the driver's probe function to use
the bulk reset APIs. Use the optional variant instead of defaulting to
NULL if the resets fail, so that absent resets can be distinguished from
erroneous resets.
Also remove all remnants of the MPHY reset ever having lived in this
driver.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Peter Wang <peter.wang@mediatek.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
drivers/ufs/host/ufs-mediatek-sip.h | 8 ----
drivers/ufs/host/ufs-mediatek.c | 78 ++++++++++++++++++-------------------
drivers/ufs/host/ufs-mediatek.h | 7 ++--
3 files changed, 42 insertions(+), 51 deletions(-)
diff --git a/drivers/ufs/host/ufs-mediatek-sip.h b/drivers/ufs/host/ufs-mediatek-sip.h
index d627dfb4a766..256598cc3b5b 100644
--- a/drivers/ufs/host/ufs-mediatek-sip.h
+++ b/drivers/ufs/host/ufs-mediatek-sip.h
@@ -31,11 +31,6 @@ enum ufs_mtk_vcc_num {
UFS_VCC_MAX
};
-enum ufs_mtk_mphy_op {
- UFS_MPHY_BACKUP = 0,
- UFS_MPHY_RESTORE
-};
-
/*
* SMC call wrapper function
*/
@@ -84,9 +79,6 @@ static inline void _ufs_mtk_smc(struct ufs_mtk_smc_arg s)
#define ufs_mtk_device_pwr_ctrl(on, ufs_version, res) \
ufs_mtk_smc(UFS_MTK_SIP_DEVICE_PWR_CTRL, &(res), on, ufs_version)
-#define ufs_mtk_mphy_ctrl(op, res) \
- ufs_mtk_smc(UFS_MTK_SIP_MPHY_CTRL, &(res), op)
-
#define ufs_mtk_mtcmos_ctrl(op, res) \
ufs_mtk_smc(UFS_MTK_SIP_MTCMOS_CTRL, &(res), op)
diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index b3daaa07e925..206794ce46c8 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -93,6 +93,12 @@ static const char *const ufs_uic_dl_err_str[] = {
"PA_INIT"
};
+static const char *const ufs_reset_names[] = {
+ "unipro",
+ "crypto",
+ "hci",
+};
+
static bool ufs_mtk_is_boost_crypt_enabled(struct ufs_hba *hba)
{
struct ufs_mtk_host *host = ufshcd_get_variant(hba);
@@ -203,49 +209,45 @@ static void ufs_mtk_crypto_enable(struct ufs_hba *hba)
static void ufs_mtk_host_reset(struct ufs_hba *hba)
{
struct ufs_mtk_host *host = ufshcd_get_variant(hba);
- struct arm_smccc_res res;
-
- reset_control_assert(host->hci_reset);
- reset_control_assert(host->crypto_reset);
- reset_control_assert(host->unipro_reset);
- reset_control_assert(host->mphy_reset);
-
- usleep_range(100, 110);
+ int ret;
- reset_control_deassert(host->unipro_reset);
- reset_control_deassert(host->crypto_reset);
- reset_control_deassert(host->hci_reset);
- reset_control_deassert(host->mphy_reset);
+ ret = reset_control_bulk_assert(MTK_UFS_NUM_RESETS, host->resets);
+ if (ret)
+ dev_warn(hba->dev, "Host reset assert failed: %pe\n", ERR_PTR(ret));
- /* restore mphy setting aftre mphy reset */
- if (host->mphy_reset)
- ufs_mtk_mphy_ctrl(UFS_MPHY_RESTORE, res);
-}
+ ret = phy_reset(host->mphy);
-static void ufs_mtk_init_reset_control(struct ufs_hba *hba,
- struct reset_control **rc,
- char *str)
-{
- *rc = devm_reset_control_get(hba->dev, str);
- if (IS_ERR(*rc)) {
- dev_info(hba->dev, "Failed to get reset control %s: %ld\n",
- str, PTR_ERR(*rc));
- *rc = NULL;
+ /*
+ * Only sleep if MPHY doesn't have a reset implemented (which already
+ * sleeps) or the PHY reset function failed somehow, just to be safe
+ */
+ if (ret) {
+ usleep_range(100, 110);
+ if (ret != -EOPNOTSUPP)
+ dev_warn(hba->dev, "PHY reset failed: %pe\n", ERR_PTR(ret));
}
+
+ ret = reset_control_bulk_deassert(MTK_UFS_NUM_RESETS, host->resets);
+ if (ret)
+ dev_warn(hba->dev, "Host reset deassert failed: %pe\n", ERR_PTR(ret));
}
-static void ufs_mtk_init_reset(struct ufs_hba *hba)
+static int ufs_mtk_init_reset(struct ufs_hba *hba)
{
struct ufs_mtk_host *host = ufshcd_get_variant(hba);
+ int ret, i;
+
+ for (i = 0; i < MTK_UFS_NUM_RESETS; i++)
+ host->resets[i].id = ufs_reset_names[i];
- ufs_mtk_init_reset_control(hba, &host->hci_reset,
- "hci_rst");
- ufs_mtk_init_reset_control(hba, &host->unipro_reset,
- "unipro_rst");
- ufs_mtk_init_reset_control(hba, &host->crypto_reset,
- "crypto_rst");
- ufs_mtk_init_reset_control(hba, &host->mphy_reset,
- "mphy_rst");
+ ret = devm_reset_control_bulk_get_optional_exclusive(hba->dev, MTK_UFS_NUM_RESETS,
+ host->resets);
+ if (ret) {
+ dev_err(hba->dev, "Failed to get resets: %pe\n", ERR_PTR(ret));
+ return ret;
+ }
+
+ return 0;
}
static int ufs_mtk_hce_enable_notify(struct ufs_hba *hba,
@@ -1247,11 +1249,9 @@ static int ufs_mtk_init(struct ufs_hba *hba)
if (err)
goto out_variant_clear;
- ufs_mtk_init_reset(hba);
-
- /* backup mphy setting if mphy can reset */
- if (host->mphy_reset)
- ufs_mtk_mphy_ctrl(UFS_MPHY_BACKUP, res);
+ err = ufs_mtk_init_reset(hba);
+ if (err)
+ goto out_variant_clear;
/* Enable runtime autosuspend */
hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND;
diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediatek.h
index 9747277f11e8..4fce29d131d1 100644
--- a/drivers/ufs/host/ufs-mediatek.h
+++ b/drivers/ufs/host/ufs-mediatek.h
@@ -7,12 +7,14 @@
#define _UFS_MEDIATEK_H
#include <linux/bitops.h>
+#include <linux/reset.h>
/*
* MCQ define and struct
*/
#define UFSHCD_MAX_Q_NR 8
#define MTK_MCQ_INVALID_IRQ 0xFFFF
+#define MTK_UFS_NUM_RESETS 3
/* REG_UFS_MMIO_OPT_CTRL_0 160h */
#define EHS_EN BIT(0)
@@ -175,10 +177,7 @@ struct ufs_mtk_mcq_intr_info {
struct ufs_mtk_host {
struct phy *mphy;
struct regulator *reg_va09;
- struct reset_control *hci_reset;
- struct reset_control *unipro_reset;
- struct reset_control *crypto_reset;
- struct reset_control *mphy_reset;
+ struct reset_control_bulk_data resets[MTK_UFS_NUM_RESETS];
struct ufs_hba *hba;
struct ufs_mtk_crypt_cfg *crypt;
struct ufs_mtk_clk mclk;
--
2.53.0
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH v9 07/23] scsi: ufs: mediatek: Rework 0.9V regulator
From: Nicolas Frattaroli @ 2026-03-06 13:24 UTC (permalink / raw)
To: Alim Akhtar, Avri Altman, Bart Van Assche, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chunfeng Yun, Vinod Koul,
Kishon Vijay Abraham I, Peter Wang, Stanley Jhu,
James E.J. Bottomley, Martin K. Petersen, Philipp Zabel,
Liam Girdwood, Mark Brown, Chaotian Jing, Neil Armstrong
Cc: Louis-Alexis Eyraud, kernel, linux-scsi, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-phy, Nicolas Frattaroli
In-Reply-To: <20260306-mt8196-ufs-v9-0-55b073f7a830@collabora.com>
The mediatek UFS host driver does some pretty bad stuff with regards to
the 0.9V regulator. Instead of just checking for the presence of the
regulator, it adds a cap if it's there, and then checks for the cap. It
also sleeps to stabilise the supply after enabling the regulator, which
is something that should be done by the regulator framework with the
appropriate delay properties in the DTS instead of random sleeps in the
driver code.
Rework this code and rename it to the avdd09 name I've chosen in the
binding for this supply name, instead of the downstream "va09" name that
isn't used by the datasheets for any of these chips.
Reviewed-by: Peter Wang <peter.wang@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
drivers/ufs/host/ufs-mediatek.c | 153 ++++++++++++++++++++++++++--------------
drivers/ufs/host/ufs-mediatek.h | 3 +-
2 files changed, 101 insertions(+), 55 deletions(-)
diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index 206794ce46c8..0d22ac4c925c 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -38,6 +38,10 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba, bool scale_up);
#define MAX_SUPP_MAC 64
#define MCQ_QUEUE_OFFSET(c) ((((c) >> 16) & 0xFF) * 0x200)
+struct ufs_mtk_soc_data {
+ bool has_avdd09;
+};
+
static const struct ufs_dev_quirk ufs_mtk_dev_fixups[] = {
{ .wmanufacturerid = UFS_ANY_VENDOR,
.model = UFS_ANY_MODEL,
@@ -48,13 +52,6 @@ static const struct ufs_dev_quirk ufs_mtk_dev_fixups[] = {
{}
};
-static const struct of_device_id ufs_mtk_of_match[] = {
- { .compatible = "mediatek,mt8183-ufshci" },
- { .compatible = "mediatek,mt8195-ufshci" },
- {},
-};
-MODULE_DEVICE_TABLE(of, ufs_mtk_of_match);
-
/*
* Details of UIC Errors
*/
@@ -106,13 +103,6 @@ static bool ufs_mtk_is_boost_crypt_enabled(struct ufs_hba *hba)
return host->caps & UFS_MTK_CAP_BOOST_CRYPT_ENGINE;
}
-static bool ufs_mtk_is_va09_supported(struct ufs_hba *hba)
-{
- struct ufs_mtk_host *host = ufshcd_get_variant(hba);
-
- return host->caps & UFS_MTK_CAP_VA09_PWR_CTRL;
-}
-
static bool ufs_mtk_is_broken_vcc(struct ufs_hba *hba)
{
struct ufs_mtk_host *host = ufshcd_get_variant(hba);
@@ -506,44 +496,70 @@ static int ufs_mtk_wait_link_state(struct ufs_hba *hba, u32 state,
return -ETIMEDOUT;
}
+static int ufs_mtk_09v_off(struct ufs_mtk_host *host)
+{
+ struct arm_smccc_res res;
+ int ret;
+
+ if (!host->reg_avdd09)
+ return 0;
+
+ ufs_mtk_va09_pwr_ctrl(res, 0);
+ ret = regulator_disable(host->reg_avdd09);
+ if (ret) {
+ dev_err(host->hba->dev, "Failed to disable avdd09-supply: %pe\n",
+ ERR_PTR(ret));
+ ufs_mtk_va09_pwr_ctrl(res, 1);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int ufs_mtk_09v_on(struct ufs_mtk_host *host)
+{
+ struct arm_smccc_res res;
+ int ret;
+
+ if (!host->reg_avdd09)
+ return 0;
+
+ ret = regulator_enable(host->reg_avdd09);
+ if (ret) {
+ dev_err(host->hba->dev, "Failed to enable avdd09-supply: %pe\n",
+ ERR_PTR(ret));
+ return ret;
+ }
+
+ ufs_mtk_va09_pwr_ctrl(res, 1);
+
+ return 0;
+}
+
static int ufs_mtk_mphy_power_on(struct ufs_hba *hba, bool on)
{
struct ufs_mtk_host *host = ufshcd_get_variant(hba);
struct phy *mphy = host->mphy;
- struct arm_smccc_res res;
- int ret = 0;
+ int ret;
- if (!mphy || !(on ^ host->mphy_powered_on))
+ if (!mphy || on == host->mphy_powered_on)
return 0;
if (on) {
- if (ufs_mtk_is_va09_supported(hba)) {
- ret = regulator_enable(host->reg_va09);
- if (ret < 0)
- goto out;
- /* wait 200 us to stablize VA09 */
- usleep_range(200, 210);
- ufs_mtk_va09_pwr_ctrl(res, 1);
- }
+ ret = ufs_mtk_09v_on(host);
+ if (ret)
+ return ret;
phy_power_on(mphy);
} else {
phy_power_off(mphy);
- if (ufs_mtk_is_va09_supported(hba)) {
- ufs_mtk_va09_pwr_ctrl(res, 0);
- ret = regulator_disable(host->reg_va09);
- }
- }
-out:
- if (ret) {
- dev_info(hba->dev,
- "failed to %s va09: %d\n",
- on ? "enable" : "disable",
- ret);
- } else {
- host->mphy_powered_on = on;
+ ret = ufs_mtk_09v_off(host);
+ if (ret)
+ return ret;
}
- return ret;
+ host->mphy_powered_on = on;
+
+ return 0;
}
static int ufs_mtk_get_host_clk(struct device *dev, const char *name,
@@ -678,17 +694,6 @@ static void ufs_mtk_init_boost_crypt(struct ufs_hba *hba)
return;
}
-static void ufs_mtk_init_va09_pwr_ctrl(struct ufs_hba *hba)
-{
- struct ufs_mtk_host *host = ufshcd_get_variant(hba);
-
- host->reg_va09 = regulator_get(hba->dev, "va09");
- if (IS_ERR(host->reg_va09))
- dev_info(hba->dev, "failed to get va09");
- else
- host->caps |= UFS_MTK_CAP_VA09_PWR_CTRL;
-}
-
static void ufs_mtk_init_host_caps(struct ufs_hba *hba)
{
struct ufs_mtk_host *host = ufshcd_get_variant(hba);
@@ -697,9 +702,6 @@ static void ufs_mtk_init_host_caps(struct ufs_hba *hba)
if (of_property_read_bool(np, "mediatek,ufs-boost-crypt"))
ufs_mtk_init_boost_crypt(hba);
- if (of_property_read_bool(np, "mediatek,ufs-support-va09"))
- ufs_mtk_init_va09_pwr_ctrl(hba);
-
if (of_property_read_bool(np, "mediatek,ufs-disable-ah8"))
host->caps |= UFS_MTK_CAP_DISABLE_AH8;
@@ -1205,6 +1207,35 @@ static void ufs_mtk_init_mcq_irq(struct ufs_hba *hba)
host->mcq_nr_intr = 0;
}
+/**
+ * ufs_mtk_get_supplies - acquire variant-specific supplies
+ * @host: pointer to driver's private &struct ufs_mtk_host instance
+ *
+ * Returns 0 on success, negative errno on error.
+ */
+static int ufs_mtk_get_supplies(struct ufs_mtk_host *host)
+{
+ struct device *dev = host->hba->dev;
+ const struct ufs_mtk_soc_data *data = of_device_get_match_data(dev);
+
+ if (!data || !data->has_avdd09)
+ return 0;
+
+ host->reg_avdd09 = devm_regulator_get_optional(dev, "avdd09");
+ if (IS_ERR(host->reg_avdd09)) {
+ if (PTR_ERR(host->reg_avdd09) == -ENODEV) {
+ host->reg_avdd09 = NULL;
+ return 0;
+ }
+
+ dev_err(dev, "Failed to get avdd09 regulator: %pe\n",
+ host->reg_avdd09);
+ return PTR_ERR(host->reg_avdd09);
+ }
+
+ return 0;
+}
+
/**
* ufs_mtk_init - find other essential mmio bases
* @hba: host controller instance
@@ -1288,6 +1319,10 @@ static int ufs_mtk_init(struct ufs_hba *hba)
ufs_mtk_init_clocks(hba);
+ err = ufs_mtk_get_supplies(host);
+ if (err)
+ goto out_variant_clear;
+
/*
* ufshcd_vops_init() is invoked after
* ufshcd_setup_clock(true) in ufshcd_hba_init() thus
@@ -2336,6 +2371,18 @@ static const struct ufs_hba_variant_ops ufs_hba_mtk_vops = {
.config_scsi_dev = ufs_mtk_config_scsi_dev,
};
+static const struct ufs_mtk_soc_data mt8183_data = {
+ .has_avdd09 = true,
+};
+
+static const struct of_device_id ufs_mtk_of_match[] = {
+ { .compatible = "mediatek,mt8183-ufshci", .data = &mt8183_data },
+ { .compatible = "mediatek,mt8192-ufshci" },
+ { .compatible = "mediatek,mt8195-ufshci" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, ufs_mtk_of_match);
+
/**
* ufs_mtk_probe - probe routine of the driver
* @pdev: pointer to Platform device handle
diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediatek.h
index 4fce29d131d1..24c8941f6b86 100644
--- a/drivers/ufs/host/ufs-mediatek.h
+++ b/drivers/ufs/host/ufs-mediatek.h
@@ -125,7 +125,6 @@ enum {
*/
enum ufs_mtk_host_caps {
UFS_MTK_CAP_BOOST_CRYPT_ENGINE = 1 << 0,
- UFS_MTK_CAP_VA09_PWR_CTRL = 1 << 1,
UFS_MTK_CAP_DISABLE_AH8 = 1 << 2,
UFS_MTK_CAP_BROKEN_VCC = 1 << 3,
@@ -176,7 +175,7 @@ struct ufs_mtk_mcq_intr_info {
struct ufs_mtk_host {
struct phy *mphy;
- struct regulator *reg_va09;
+ struct regulator *reg_avdd09;
struct reset_control_bulk_data resets[MTK_UFS_NUM_RESETS];
struct ufs_hba *hba;
struct ufs_mtk_crypt_cfg *crypt;
--
2.53.0
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH v9 08/23] scsi: ufs: mediatek: Rework init function
From: Nicolas Frattaroli @ 2026-03-06 13:24 UTC (permalink / raw)
To: Alim Akhtar, Avri Altman, Bart Van Assche, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chunfeng Yun, Vinod Koul,
Kishon Vijay Abraham I, Peter Wang, Stanley Jhu,
James E.J. Bottomley, Martin K. Petersen, Philipp Zabel,
Liam Girdwood, Mark Brown, Chaotian Jing, Neil Armstrong
Cc: Louis-Alexis Eyraud, kernel, linux-scsi, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-phy, Nicolas Frattaroli
In-Reply-To: <20260306-mt8196-ufs-v9-0-55b073f7a830@collabora.com>
Printing an error message on ENOMEM is pointless. The print will not
work because there is no memory.
Adding an of_match_device to the init function is pointless. Why would a
different device with a different probe function ever use the same init
function? Get rid of it.
zero-initialising an error variable just so you can then goto a bare
return statement with that error variable to signal success is also
pointless, just return directly, there's no unwind being done.
Reviewed-by: Peter Wang <peter.wang@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
drivers/ufs/host/ufs-mediatek.c | 19 ++++---------------
1 file changed, 4 insertions(+), 15 deletions(-)
diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index 0d22ac4c925c..392383e03ab0 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -1248,29 +1248,19 @@ static int ufs_mtk_get_supplies(struct ufs_mtk_host *host)
*/
static int ufs_mtk_init(struct ufs_hba *hba)
{
- const struct of_device_id *id;
struct device *dev = hba->dev;
struct ufs_mtk_host *host;
struct Scsi_Host *shost = hba->host;
- int err = 0;
+ int err;
struct arm_smccc_res res;
host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
- if (!host) {
- err = -ENOMEM;
- dev_info(dev, "%s: no memory for mtk ufs host\n", __func__);
- goto out;
- }
+ if (!host)
+ return -ENOMEM;
host->hba = hba;
ufshcd_set_variant(hba, host);
- id = of_match_device(ufs_mtk_of_match, dev);
- if (!id) {
- err = -EINVAL;
- goto out;
- }
-
/* Initialize host capability */
ufs_mtk_init_host_caps(hba);
@@ -1344,11 +1334,10 @@ static int ufs_mtk_init(struct ufs_hba *hba)
ufs_mtk_get_hw_ip_version(hba);
- goto out;
+ return 0;
out_variant_clear:
ufshcd_set_variant(hba, NULL);
-out:
return err;
}
--
2.53.0
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH v9 09/23] scsi: ufs: mediatek: Rework the crypt-boost stuff
From: Nicolas Frattaroli @ 2026-03-06 13:24 UTC (permalink / raw)
To: Alim Akhtar, Avri Altman, Bart Van Assche, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chunfeng Yun, Vinod Koul,
Kishon Vijay Abraham I, Peter Wang, Stanley Jhu,
James E.J. Bottomley, Martin K. Petersen, Philipp Zabel,
Liam Girdwood, Mark Brown, Chaotian Jing, Neil Armstrong
Cc: Louis-Alexis Eyraud, kernel, linux-scsi, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-phy, Nicolas Frattaroli
In-Reply-To: <20260306-mt8196-ufs-v9-0-55b073f7a830@collabora.com>
I don't know whether the crypt-boost functionality as it is currently
implemented is even appropriate for mainline. It might be better done in
some generic way. But what I do know is that I can rework the code to
make it less obtuse.
Prefix the boost stuff with the appropriate vendor prefix, remove the
pointless clock wrappers, and rework the function.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Peter Wang (王信友) <peter.wang@mediatek.com>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
drivers/ufs/host/ufs-mediatek.c | 89 ++++++++++++++---------------------------
1 file changed, 30 insertions(+), 59 deletions(-)
diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index 392383e03ab0..9b7d7e4ba4ba 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -562,21 +562,6 @@ static int ufs_mtk_mphy_power_on(struct ufs_hba *hba, bool on)
return 0;
}
-static int ufs_mtk_get_host_clk(struct device *dev, const char *name,
- struct clk **clk_out)
-{
- struct clk *clk;
- int err = 0;
-
- clk = devm_clk_get(dev, name);
- if (IS_ERR(clk))
- err = PTR_ERR(clk);
- else
- *clk_out = clk;
-
- return err;
-}
-
static void ufs_mtk_boost_crypt(struct ufs_hba *hba, bool boost)
{
struct ufs_mtk_host *host = ufshcd_get_variant(hba);
@@ -633,65 +618,51 @@ static void ufs_mtk_boost_crypt(struct ufs_hba *hba, bool boost)
clk_disable_unprepare(cfg->clk_crypt_mux);
}
-static int ufs_mtk_init_host_clk(struct ufs_hba *hba, const char *name,
- struct clk **clk)
-{
- int ret;
-
- ret = ufs_mtk_get_host_clk(hba->dev, name, clk);
- if (ret) {
- dev_info(hba->dev, "%s: failed to get %s: %d", __func__,
- name, ret);
- }
-
- return ret;
-}
-
static void ufs_mtk_init_boost_crypt(struct ufs_hba *hba)
{
struct ufs_mtk_host *host = ufshcd_get_variant(hba);
struct ufs_mtk_crypt_cfg *cfg;
struct device *dev = hba->dev;
- struct regulator *reg;
- u32 volt;
+ int ret;
- host->crypt = devm_kzalloc(dev, sizeof(*(host->crypt)),
- GFP_KERNEL);
- if (!host->crypt)
- goto disable_caps;
+ cfg = devm_kzalloc(dev, sizeof(*cfg), GFP_KERNEL);
+ if (!cfg)
+ return;
- reg = devm_regulator_get_optional(dev, "dvfsrc-vcore");
- if (IS_ERR(reg)) {
- dev_info(dev, "failed to get dvfsrc-vcore: %ld",
- PTR_ERR(reg));
- goto disable_caps;
+ cfg->reg_vcore = devm_regulator_get_optional(dev, "dvfsrc-vcore");
+ if (IS_ERR(cfg->reg_vcore)) {
+ dev_err(dev, "Failed to get dvfsrc-vcore: %pe", cfg->reg_vcore);
+ return;
}
- if (of_property_read_u32(dev->of_node, "boost-crypt-vcore-min",
- &volt)) {
- dev_info(dev, "failed to get boost-crypt-vcore-min");
- goto disable_caps;
+ ret = of_property_read_u32(dev->of_node, "mediatek,boost-crypt-vcore-min",
+ &cfg->vcore_volt);
+ if (ret) {
+ dev_err(dev, "Failed to get mediatek,boost-crypt-vcore-min: %pe\n",
+ ERR_PTR(ret));
+ return;
}
- cfg = host->crypt;
- if (ufs_mtk_init_host_clk(hba, "crypt_mux",
- &cfg->clk_crypt_mux))
- goto disable_caps;
+ cfg->clk_crypt_mux = devm_clk_get(dev, "crypt_mux");
+ if (IS_ERR(cfg->clk_crypt_mux)) {
+ dev_err(dev, "Failed to get clock crypt_mux: %pe\n", cfg->clk_crypt_mux);
+ return;
+ }
- if (ufs_mtk_init_host_clk(hba, "crypt_lp",
- &cfg->clk_crypt_lp))
- goto disable_caps;
+ cfg->clk_crypt_lp = devm_clk_get(dev, "crypt_lp");
+ if (IS_ERR(cfg->clk_crypt_lp)) {
+ dev_err(dev, "Failed to get clock crypt_lp: %pe\n", cfg->clk_crypt_lp);
+ return;
+ }
- if (ufs_mtk_init_host_clk(hba, "crypt_perf",
- &cfg->clk_crypt_perf))
- goto disable_caps;
+ cfg->clk_crypt_perf = devm_clk_get(dev, "crypt_perf");
+ if (IS_ERR(cfg->clk_crypt_perf)) {
+ dev_err(dev, "Failed to get clock crypt_perf: %pe\n", cfg->clk_crypt_perf);
+ return;
+ }
- cfg->reg_vcore = reg;
- cfg->vcore_volt = volt;
+ host->crypt = cfg;
host->caps |= UFS_MTK_CAP_BOOST_CRYPT_ENGINE;
-
-disable_caps:
- return;
}
static void ufs_mtk_init_host_caps(struct ufs_hba *hba)
--
2.53.0
--
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* [PATCH v9 10/23] scsi: ufs: mediatek: Handle misc host voltage regulators
From: Nicolas Frattaroli @ 2026-03-06 13:24 UTC (permalink / raw)
To: Alim Akhtar, Avri Altman, Bart Van Assche, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chunfeng Yun, Vinod Koul,
Kishon Vijay Abraham I, Peter Wang, Stanley Jhu,
James E.J. Bottomley, Martin K. Petersen, Philipp Zabel,
Liam Girdwood, Mark Brown, Chaotian Jing, Neil Armstrong
Cc: Louis-Alexis Eyraud, kernel, linux-scsi, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-phy, Nicolas Frattaroli
In-Reply-To: <20260306-mt8196-ufs-v9-0-55b073f7a830@collabora.com>
MediaTek SoCs handled by this driver contain a per-SoC specific set of
miscellaneous supplies. These feed parts of the UFS controller silicon
inside the SoC, as opposed to the UFS card.
Add the necessary driver code to acquire these supplies using the
regulator bulk API. They should be kept on during suspend, so enable
them when acquiring.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Peter Wang <peter.wang@mediatek.com>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
drivers/ufs/host/ufs-mediatek.c | 37 ++++++++++++++++++++++++++++++++++---
1 file changed, 34 insertions(+), 3 deletions(-)
diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index 9b7d7e4ba4ba..3282b2d2d498 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -40,6 +40,8 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba, bool scale_up);
struct ufs_mtk_soc_data {
bool has_avdd09;
+ u8 num_reg_names;
+ const char *const *reg_names;
};
static const struct ufs_dev_quirk ufs_mtk_dev_fixups[] = {
@@ -1188,8 +1190,21 @@ static int ufs_mtk_get_supplies(struct ufs_mtk_host *host)
{
struct device *dev = host->hba->dev;
const struct ufs_mtk_soc_data *data = of_device_get_match_data(dev);
+ int ret;
+
+ if (!data)
+ return 0;
+
+ if (data->num_reg_names) {
+ ret = devm_regulator_bulk_get_enable(dev, data->num_reg_names,
+ data->reg_names);
+ if (ret) {
+ dev_err(dev, "Failed to get misc regulators: %pe\n", ERR_PTR(ret));
+ return ret;
+ }
+ }
- if (!data || !data->has_avdd09)
+ if (!data->has_avdd09)
return 0;
host->reg_avdd09 = devm_regulator_get_optional(dev, "avdd09");
@@ -2331,14 +2346,30 @@ static const struct ufs_hba_variant_ops ufs_hba_mtk_vops = {
.config_scsi_dev = ufs_mtk_config_scsi_dev,
};
+static const char *const ufs_mtk_regs_avdd12_avdd18[] = {
+ "avdd12", "avdd18"
+};
+
+static const char *const ufs_mtk_regs_avdd12_ckbuf_avdd18[] = {
+ "avdd12", "avdd12-ckbuf", "avdd18"
+};
+
static const struct ufs_mtk_soc_data mt8183_data = {
.has_avdd09 = true,
+ .reg_names = ufs_mtk_regs_avdd12_avdd18,
+ .num_reg_names = ARRAY_SIZE(ufs_mtk_regs_avdd12_avdd18),
+};
+
+static const struct ufs_mtk_soc_data mt8192_8195_data = {
+ .has_avdd09 = false,
+ .reg_names = ufs_mtk_regs_avdd12_ckbuf_avdd18,
+ .num_reg_names = ARRAY_SIZE(ufs_mtk_regs_avdd12_ckbuf_avdd18),
};
static const struct of_device_id ufs_mtk_of_match[] = {
{ .compatible = "mediatek,mt8183-ufshci", .data = &mt8183_data },
- { .compatible = "mediatek,mt8192-ufshci" },
- { .compatible = "mediatek,mt8195-ufshci" },
+ { .compatible = "mediatek,mt8192-ufshci", .data = &mt8192_8195_data },
+ { .compatible = "mediatek,mt8195-ufshci", .data = &mt8192_8195_data },
{},
};
MODULE_DEVICE_TABLE(of, ufs_mtk_of_match);
--
2.53.0
--
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* [PATCH v9 11/23] scsi: ufs: mediatek: Remove undocumented downstream reset cruft
From: Nicolas Frattaroli @ 2026-03-06 13:24 UTC (permalink / raw)
To: Alim Akhtar, Avri Altman, Bart Van Assche, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chunfeng Yun, Vinod Koul,
Kishon Vijay Abraham I, Peter Wang, Stanley Jhu,
James E.J. Bottomley, Martin K. Petersen, Philipp Zabel,
Liam Girdwood, Mark Brown, Chaotian Jing, Neil Armstrong
Cc: Louis-Alexis Eyraud, kernel, linux-scsi, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-phy, Nicolas Frattaroli
In-Reply-To: <20260306-mt8196-ufs-v9-0-55b073f7a830@collabora.com>
The MediaTek UFS host driver's probe function allows using a
ti,syscon-reset as a reset, without going through the appropriate
abstractions, or by documenting this in the binding at all.
Remove this, it's downstream code and does not belong here.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
drivers/ufs/host/ufs-mediatek.c | 33 +++------------------------------
1 file changed, 3 insertions(+), 30 deletions(-)
diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index 3282b2d2d498..6b4db7c09bbc 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -2383,38 +2383,12 @@ MODULE_DEVICE_TABLE(of, ufs_mtk_of_match);
static int ufs_mtk_probe(struct platform_device *pdev)
{
int err;
- struct device *dev = &pdev->dev, *phy_dev = NULL;
- struct device_node *reset_node, *phy_node = NULL;
- struct platform_device *reset_pdev, *phy_pdev = NULL;
- struct device_link *link;
struct ufs_hba *hba;
+ struct platform_device *phy_pdev = NULL;
+ struct device *dev = &pdev->dev, *phy_dev = NULL;
+ struct device_node *phy_node = NULL;
struct ufs_mtk_host *host;
- reset_node = of_find_compatible_node(NULL, NULL,
- "ti,syscon-reset");
- if (!reset_node) {
- dev_notice(dev, "find ti,syscon-reset fail\n");
- goto skip_reset;
- }
- reset_pdev = of_find_device_by_node(reset_node);
- if (!reset_pdev) {
- dev_notice(dev, "find reset_pdev fail\n");
- goto skip_reset;
- }
- link = device_link_add(dev, &reset_pdev->dev,
- DL_FLAG_AUTOPROBE_CONSUMER);
- put_device(&reset_pdev->dev);
- if (!link) {
- dev_notice(dev, "add reset device_link fail\n");
- goto skip_reset;
- }
- /* supplier is not probed */
- if (link->status == DL_STATE_DORMANT) {
- err = -EPROBE_DEFER;
- goto out;
- }
-
-skip_reset:
/* find phy node */
phy_node = of_parse_phandle(dev->of_node, "phys", 0);
@@ -2460,7 +2434,6 @@ static int ufs_mtk_probe(struct platform_device *pdev)
out:
of_node_put(phy_node);
- of_node_put(reset_node);
return err;
}
--
2.53.0
--
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* [PATCH v9 13/23] scsi: ufs: mediatek: Use the common PHY framework
From: Nicolas Frattaroli @ 2026-03-06 13:24 UTC (permalink / raw)
To: Alim Akhtar, Avri Altman, Bart Van Assche, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chunfeng Yun, Vinod Koul,
Kishon Vijay Abraham I, Peter Wang, Stanley Jhu,
James E.J. Bottomley, Martin K. Petersen, Philipp Zabel,
Liam Girdwood, Mark Brown, Chaotian Jing, Neil Armstrong
Cc: Louis-Alexis Eyraud, kernel, linux-scsi, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-phy, Nicolas Frattaroli
In-Reply-To: <20260306-mt8196-ufs-v9-0-55b073f7a830@collabora.com>
There is no need to reinvent the PHY framework, especially not its OF
parsing.
Change the code to simply use the PHY framework to acquire the device's
PHY in the ufshcd init, so that it's device linked to the right device.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
drivers/ufs/host/ufs-mediatek.c | 134 +++++++++++++---------------------------
drivers/ufs/host/ufs-mediatek.h | 1 -
2 files changed, 42 insertions(+), 93 deletions(-)
diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index cb120dd52fb8..e7948fad2e39 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -293,44 +293,6 @@ static int ufs_mtk_hce_enable_notify(struct ufs_hba *hba,
return 0;
}
-static int ufs_mtk_bind_mphy(struct ufs_hba *hba)
-{
- struct ufs_mtk_host *host = ufshcd_get_variant(hba);
- struct device *dev = hba->dev;
- struct device_node *np = dev->of_node;
- int err = 0;
-
- host->mphy = devm_of_phy_get_by_index(dev, np, 0);
-
- if (host->mphy == ERR_PTR(-EPROBE_DEFER)) {
- /*
- * UFS driver might be probed before the phy driver does.
- * In that case we would like to return EPROBE_DEFER code.
- */
- err = -EPROBE_DEFER;
- dev_info(dev,
- "%s: required phy hasn't probed yet. err = %d\n",
- __func__, err);
- } else if (IS_ERR(host->mphy)) {
- err = PTR_ERR(host->mphy);
- if (err != -ENODEV) {
- dev_info(dev, "%s: PHY get failed %d\n", __func__,
- err);
- }
- }
-
- if (err)
- host->mphy = NULL;
- /*
- * Allow unbound mphy because not every platform needs specific
- * mphy control.
- */
- if (err == -ENODEV)
- err = 0;
-
- return err;
-}
-
static int ufs_mtk_setup_ref_clk(struct ufs_hba *hba, bool on)
{
struct ufs_mtk_host *host = ufshcd_get_variant(hba);
@@ -1185,13 +1147,21 @@ static int ufs_mtk_init(struct ufs_hba *hba)
ufs_mtk_init_mcq_irq(hba);
- err = ufs_mtk_bind_mphy(hba);
- if (err)
+ host->mphy = devm_phy_get(dev, NULL);
+ if (IS_ERR(host->mphy)) {
+ err = dev_err_probe(dev, PTR_ERR(host->mphy), "Failed to get PHY\n");
+ goto out_variant_clear;
+ }
+
+ err = phy_init(host->mphy);
+ if (err) {
+ dev_err_probe(dev, err, "Failed to initialize PHY\n");
goto out_variant_clear;
+ }
err = ufs_mtk_init_reset(hba);
if (err)
- goto out_variant_clear;
+ goto out_phy_exit;
/* Enable runtime autosuspend */
hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND;
@@ -1230,7 +1200,7 @@ static int ufs_mtk_init(struct ufs_hba *hba)
err = ufs_mtk_get_supplies(host);
if (err)
- goto out_variant_clear;
+ goto out_phy_exit;
/*
* ufshcd_vops_init() is invoked after
@@ -1255,11 +1225,22 @@ static int ufs_mtk_init(struct ufs_hba *hba)
return 0;
+out_phy_exit:
+ phy_exit(host->mphy);
out_variant_clear:
ufshcd_set_variant(hba, NULL);
return err;
}
+static void ufs_mtk_exit(struct ufs_hba *hba)
+{
+ struct ufs_mtk_host *host = ufshcd_get_variant(hba);
+
+ ufs_mtk_mphy_power_on(hba, false);
+
+ phy_exit(host->mphy);
+}
+
static bool ufs_mtk_pmc_via_fastauto(struct ufs_hba *hba,
struct ufs_pa_layer_attr *dev_req_params)
{
@@ -2255,6 +2236,7 @@ static const struct ufs_hba_variant_ops ufs_hba_mtk_vops = {
.name = "mediatek.ufshci",
.max_num_rtt = MTK_MAX_NUM_RTT,
.init = ufs_mtk_init,
+ .exit = ufs_mtk_exit,
.get_ufs_hci_version = ufs_mtk_get_ufs_hci_version,
.setup_clocks = ufs_mtk_setup_clocks,
.hce_enable_notify = ufs_mtk_hce_enable_notify,
@@ -2313,48 +2295,15 @@ MODULE_DEVICE_TABLE(of, ufs_mtk_of_match);
*/
static int ufs_mtk_probe(struct platform_device *pdev)
{
- int err;
+ struct device *dev = &pdev->dev;
struct ufs_hba *hba;
- struct platform_device *phy_pdev = NULL;
- struct device *dev = &pdev->dev, *phy_dev = NULL;
- struct device_node *phy_node = NULL;
- struct ufs_mtk_host *host;
-
- /* find phy node */
- phy_node = of_parse_phandle(dev->of_node, "phys", 0);
-
- if (phy_node) {
- phy_pdev = of_find_device_by_node(phy_node);
- if (!phy_pdev)
- goto skip_phy;
- phy_dev = &phy_pdev->dev;
-
- pm_runtime_set_active(phy_dev);
- pm_runtime_enable(phy_dev);
- pm_runtime_get_sync(phy_dev);
-
- put_device(phy_dev);
- dev_info(dev, "phys node found\n");
- } else {
- dev_notice(dev, "phys node not found\n");
- }
+ int ret;
-skip_phy:
- /* perform generic probe */
- err = ufshcd_pltfrm_init(pdev, &ufs_hba_mtk_vops);
- if (err) {
- dev_err(dev, "probe failed %d\n", err);
- goto out;
- }
+ ret = ufshcd_pltfrm_init(pdev, &ufs_hba_mtk_vops);
+ if (ret)
+ return dev_err_probe(dev, ret, "Generic platform probe failed\n");
hba = platform_get_drvdata(pdev);
- if (!hba)
- goto out;
-
- if (phy_node && phy_dev) {
- host = ufshcd_get_variant(hba);
- host->phy_dev = phy_dev;
- }
/*
* Because the default power setting of VSx (the upper layer of
@@ -2363,16 +2312,12 @@ static int ufs_mtk_probe(struct platform_device *pdev)
*/
ufs_mtk_dev_vreg_set_lpm(hba, false);
-out:
- of_node_put(phy_node);
- return err;
+ return 0;
}
/**
* ufs_mtk_remove - set driver_data of the device to NULL
* @pdev: pointer to platform device handle
- *
- * Always return 0
*/
static void ufs_mtk_remove(struct platform_device *pdev)
{
@@ -2429,9 +2374,8 @@ static int ufs_mtk_system_resume(struct device *dev)
static int ufs_mtk_runtime_suspend(struct device *dev)
{
struct ufs_hba *hba = dev_get_drvdata(dev);
- struct ufs_mtk_host *host = ufshcd_get_variant(hba);
struct arm_smccc_res res;
- int ret = 0;
+ int ret;
ret = ufshcd_runtime_suspend(dev);
if (ret)
@@ -2442,8 +2386,11 @@ static int ufs_mtk_runtime_suspend(struct device *dev)
if (ufs_mtk_is_rtff_mtcmos(hba))
ufs_mtk_mtcmos_ctrl(false, res);
- if (host->phy_dev)
- pm_runtime_put_sync(host->phy_dev);
+ ret = ufs_mtk_mphy_power_on(hba, false);
+ if (ret) {
+ dev_err(dev, "Failed to power off PHY: %pe\n", ERR_PTR(ret));
+ return ret;
+ }
return 0;
}
@@ -2451,14 +2398,17 @@ static int ufs_mtk_runtime_suspend(struct device *dev)
static int ufs_mtk_runtime_resume(struct device *dev)
{
struct ufs_hba *hba = dev_get_drvdata(dev);
- struct ufs_mtk_host *host = ufshcd_get_variant(hba);
struct arm_smccc_res res;
+ int ret;
if (ufs_mtk_is_rtff_mtcmos(hba))
ufs_mtk_mtcmos_ctrl(true, res);
- if (host->phy_dev)
- pm_runtime_get_sync(host->phy_dev);
+ ret = ufs_mtk_mphy_power_on(hba, true);
+ if (ret) {
+ dev_err(dev, "Failed to power on PHY: %pe\n", ERR_PTR(ret));
+ return ret;
+ }
ufs_mtk_dev_vreg_set_lpm(hba, false);
diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediatek.h
index 24c8941f6b86..4e6a34f4ac39 100644
--- a/drivers/ufs/host/ufs-mediatek.h
+++ b/drivers/ufs/host/ufs-mediatek.h
@@ -195,7 +195,6 @@ struct ufs_mtk_host {
bool is_mcq_intr_enabled;
int mcq_nr_intr;
struct ufs_mtk_mcq_intr_info mcq_intr_info[UFSHCD_MAX_Q_NR];
- struct device *phy_dev;
};
/* MTK delay of autosuspend: 500 ms */
--
2.53.0
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* [PATCH v9 12/23] scsi: ufs: mediatek: Remove vendor kernel quirks cruft
From: Nicolas Frattaroli @ 2026-03-06 13:24 UTC (permalink / raw)
To: Alim Akhtar, Avri Altman, Bart Van Assche, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chunfeng Yun, Vinod Koul,
Kishon Vijay Abraham I, Peter Wang, Stanley Jhu,
James E.J. Bottomley, Martin K. Petersen, Philipp Zabel,
Liam Girdwood, Mark Brown, Chaotian Jing, Neil Armstrong
Cc: Louis-Alexis Eyraud, kernel, linux-scsi, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-phy, Nicolas Frattaroli,
Krzysztof Kozlowski
In-Reply-To: <20260306-mt8196-ufs-v9-0-55b073f7a830@collabora.com>
Both ufs_mtk_vreg_fix_vcc and ufs_mtk_vreg_fix_vccqx look like they are
vendor kernel hacks to work around existing downstream device trees.
Mainline does not need or want them, so remove them.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Peter Wang <peter.wang@mediatek.com>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
drivers/ufs/host/ufs-mediatek.c | 69 -----------------------------------------
1 file changed, 69 deletions(-)
diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index 6b4db7c09bbc..cb120dd52fb8 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -1017,73 +1017,6 @@ static void ufs_mtk_init_clocks(struct ufs_hba *hba)
}
}
-#define MAX_VCC_NAME 30
-static int ufs_mtk_vreg_fix_vcc(struct ufs_hba *hba)
-{
- struct ufs_vreg_info *info = &hba->vreg_info;
- struct device_node *np = hba->dev->of_node;
- struct device *dev = hba->dev;
- char vcc_name[MAX_VCC_NAME];
- struct arm_smccc_res res;
- int err, ver;
-
- if (info->vcc)
- return 0;
-
- if (of_property_read_bool(np, "mediatek,ufs-vcc-by-num")) {
- ufs_mtk_get_vcc_num(res);
- if (res.a1 > UFS_VCC_NONE && res.a1 < UFS_VCC_MAX)
- snprintf(vcc_name, MAX_VCC_NAME, "vcc-opt%lu", res.a1);
- else
- return -ENODEV;
- } else if (of_property_read_bool(np, "mediatek,ufs-vcc-by-ver")) {
- ver = (hba->dev_info.wspecversion & 0xF00) >> 8;
- snprintf(vcc_name, MAX_VCC_NAME, "vcc-ufs%u", ver);
- } else {
- return 0;
- }
-
- err = ufshcd_populate_vreg(dev, vcc_name, &info->vcc, false);
- if (err)
- return err;
-
- err = ufshcd_get_vreg(dev, info->vcc);
- if (err)
- return err;
-
- err = regulator_enable(info->vcc->reg);
- if (!err) {
- info->vcc->enabled = true;
- dev_info(dev, "%s: %s enabled\n", __func__, vcc_name);
- }
-
- return err;
-}
-
-static void ufs_mtk_vreg_fix_vccqx(struct ufs_hba *hba)
-{
- struct ufs_vreg_info *info = &hba->vreg_info;
- struct ufs_vreg **vreg_on, **vreg_off;
-
- if (hba->dev_info.wspecversion >= 0x0300) {
- vreg_on = &info->vccq;
- vreg_off = &info->vccq2;
- } else {
- vreg_on = &info->vccq2;
- vreg_off = &info->vccq;
- }
-
- if (*vreg_on)
- (*vreg_on)->always_on = true;
-
- if (*vreg_off) {
- regulator_disable((*vreg_off)->reg);
- devm_kfree(hba->dev, (*vreg_off)->name);
- devm_kfree(hba->dev, *vreg_off);
- *vreg_off = NULL;
- }
-}
-
static void ufs_mtk_setup_clk_gating(struct ufs_hba *hba)
{
unsigned long flags;
@@ -1981,8 +1914,6 @@ static void ufs_mtk_fixup_dev_quirks(struct ufs_hba *hba)
hba->dev_quirks &= ~UFS_DEVICE_QUIRK_DELAY_BEFORE_LPM;
}
- ufs_mtk_vreg_fix_vcc(hba);
- ufs_mtk_vreg_fix_vccqx(hba);
ufs_mtk_fix_ahit(hba);
ufs_mtk_fix_clock_scaling(hba);
}
--
2.53.0
--
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* [PATCH v9 15/23] scsi: ufs: mediatek: Rework _ufs_mtk_clk_scale error paths
From: Nicolas Frattaroli @ 2026-03-06 13:24 UTC (permalink / raw)
To: Alim Akhtar, Avri Altman, Bart Van Assche, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chunfeng Yun, Vinod Koul,
Kishon Vijay Abraham I, Peter Wang, Stanley Jhu,
James E.J. Bottomley, Martin K. Petersen, Philipp Zabel,
Liam Girdwood, Mark Brown, Chaotian Jing, Neil Armstrong
Cc: Louis-Alexis Eyraud, kernel, linux-scsi, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-phy, Nicolas Frattaroli
In-Reply-To: <20260306-mt8196-ufs-v9-0-55b073f7a830@collabora.com>
Errors should be printed at the correct log level. Additionally, it
looks like some "goto out"'s were omitted in the scale up case, which
looks like a mistake, as the scale down branch of the code does use
them.
Rework the error messages to make them nicer and at the correct
verbosity, and add the missing gotos.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Peter Wang <peter.wang@mediatek.com>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
drivers/ufs/host/ufs-mediatek.c | 41 +++++++++++++++++++----------------------
1 file changed, 19 insertions(+), 22 deletions(-)
diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index 909e4ea2d92c..c236a833fe9a 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -1961,16 +1961,16 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba, bool scale_up)
ret = clk_prepare_enable(clki->clk);
if (ret) {
- dev_info(hba->dev,
- "clk_prepare_enable() fail, ret: %d\n", ret);
+ dev_err(hba->dev, "%s: Failed to enable clock: %pe\n", __func__, ERR_PTR(ret));
return;
}
if (clk_fde_scale) {
ret = clk_prepare_enable(fde_clki->clk);
if (ret) {
- dev_info(hba->dev,
- "fde clk_prepare_enable() fail, ret: %d\n", ret);
+ dev_err(hba->dev, "%s: Failed to enable FDE clock: %pe\n",
+ __func__, ERR_PTR(ret));
+ clk_disable_unprepare(clki->clk);
return;
}
}
@@ -1979,51 +1979,48 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba, bool scale_up)
if (clk_bind_vcore) {
ret = regulator_set_voltage(reg, volt, INT_MAX);
if (ret) {
- dev_info(hba->dev,
- "Failed to set vcore to %d\n", volt);
+ dev_err(hba->dev, "Failed to set vcore to %d\n", volt);
goto out;
}
}
ret = clk_set_parent(clki->clk, mclk->ufs_sel_max_clki->clk);
if (ret) {
- dev_info(hba->dev, "Failed to set clk mux, ret = %d\n",
- ret);
+ dev_err(hba->dev, "%s: Failed to set clock mux: %pe\n",
+ __func__, ERR_PTR(ret));
+ goto out;
}
if (clk_fde_scale) {
- ret = clk_set_parent(fde_clki->clk,
- mclk->ufs_fde_max_clki->clk);
+ ret = clk_set_parent(fde_clki->clk, mclk->ufs_fde_max_clki->clk);
if (ret) {
- dev_info(hba->dev,
- "Failed to set fde clk mux, ret = %d\n",
- ret);
+ dev_err(hba->dev, "%s: Failed to set fde clock mux: %pe\n",
+ __func__, ERR_PTR(ret));
+ goto out;
}
}
} else {
if (clk_fde_scale) {
- ret = clk_set_parent(fde_clki->clk,
- mclk->ufs_fde_min_clki->clk);
+ ret = clk_set_parent(fde_clki->clk, mclk->ufs_fde_min_clki->clk);
if (ret) {
- dev_info(hba->dev,
- "Failed to set fde clk mux, ret = %d\n",
- ret);
+ dev_err(hba->dev, "%s: Failed to set fde clock mux: %pe\n",
+ __func__, ERR_PTR(ret));
goto out;
}
}
ret = clk_set_parent(clki->clk, mclk->ufs_sel_min_clki->clk);
if (ret) {
- dev_info(hba->dev, "Failed to set clk mux, ret = %d\n",
- ret);
+ dev_err(hba->dev, "%s: Failed to set clock mux: %pe\n",
+ __func__, ERR_PTR(ret));
goto out;
}
if (clk_bind_vcore) {
ret = regulator_set_voltage(reg, 0, INT_MAX);
if (ret) {
- dev_info(hba->dev,
- "failed to set vcore to MIN\n");
+ dev_err(hba->dev, "%s: Failed to set vcore to minimum: %pe\n",
+ __func__, ERR_PTR(ret));
}
}
}
--
2.53.0
--
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* [PATCH v9 14/23] scsi: ufs: mediatek: Remove mediatek,ufs-broken-rtc property
From: Nicolas Frattaroli @ 2026-03-06 13:24 UTC (permalink / raw)
To: Alim Akhtar, Avri Altman, Bart Van Assche, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chunfeng Yun, Vinod Koul,
Kishon Vijay Abraham I, Peter Wang, Stanley Jhu,
James E.J. Bottomley, Martin K. Petersen, Philipp Zabel,
Liam Girdwood, Mark Brown, Chaotian Jing, Neil Armstrong
Cc: Louis-Alexis Eyraud, kernel, linux-scsi, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-phy, Nicolas Frattaroli
In-Reply-To: <20260306-mt8196-ufs-v9-0-55b073f7a830@collabora.com>
This flag property was never described in the binding, and its
capability wrapper seems pointless.
If one of the MediaTek SoCs needs the ufshcd quirk applied, then this
can be done per-compatible, without needing to give the device tree
author the option to forget to set it.
Remove it and the associated capability flag wrapping code.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Peter Wang <peter.wang@mediatek.com>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
drivers/ufs/host/ufs-mediatek.c | 5 -----
drivers/ufs/host/ufs-mediatek.h | 2 --
2 files changed, 7 deletions(-)
diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index e7948fad2e39..909e4ea2d92c 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -655,9 +655,6 @@ static void ufs_mtk_init_host_caps(struct ufs_hba *hba)
if (of_property_read_bool(np, "mediatek,ufs-rtff-mtcmos"))
host->caps |= UFS_MTK_CAP_RTFF_MTCMOS;
- if (of_property_read_bool(np, "mediatek,ufs-broken-rtc"))
- host->caps |= UFS_MTK_CAP_MCQ_BROKEN_RTC;
-
dev_info(hba->dev, "caps: 0x%x", host->caps);
}
@@ -1185,8 +1182,6 @@ static int ufs_mtk_init(struct ufs_hba *hba)
hba->quirks |= UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL;
hba->quirks |= UFSHCD_QUIRK_MCQ_BROKEN_INTR;
- if (host->caps & UFS_MTK_CAP_MCQ_BROKEN_RTC)
- hba->quirks |= UFSHCD_QUIRK_MCQ_BROKEN_RTC;
hba->vps->wb_flush_threshold = UFS_WB_BUF_REMAIN_PERCENT(80);
diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediatek.h
index 4e6a34f4ac39..9c377745f7a0 100644
--- a/drivers/ufs/host/ufs-mediatek.h
+++ b/drivers/ufs/host/ufs-mediatek.h
@@ -138,8 +138,6 @@ enum ufs_mtk_host_caps {
UFS_MTK_CAP_DISABLE_MCQ = 1 << 8,
/* Control MTCMOS with RTFF */
UFS_MTK_CAP_RTFF_MTCMOS = 1 << 9,
-
- UFS_MTK_CAP_MCQ_BROKEN_RTC = 1 << 10,
};
struct ufs_mtk_crypt_cfg {
--
2.53.0
--
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* [PATCH v9 22/23] scsi: ufs: mediatek: Remove undocumented "clk-scale-up-vcore-min"
From: Nicolas Frattaroli @ 2026-03-06 13:25 UTC (permalink / raw)
To: Alim Akhtar, Avri Altman, Bart Van Assche, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chunfeng Yun, Vinod Koul,
Kishon Vijay Abraham I, Peter Wang, Stanley Jhu,
James E.J. Bottomley, Martin K. Petersen, Philipp Zabel,
Liam Girdwood, Mark Brown, Chaotian Jing, Neil Armstrong
Cc: Louis-Alexis Eyraud, kernel, linux-scsi, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-phy, Nicolas Frattaroli
In-Reply-To: <20260306-mt8196-ufs-v9-0-55b073f7a830@collabora.com>
The MediaTek UFS driver contains support for an undocumented,
non-vendor-prefixed u32 property named "clk-scale-up-vcore-min".
Since it is not part of any binding, and would not pass a bindings
review in its current form, remove it.
To return this functionality, it needs to be resubmitted in a series
that also introduces it to the binding, and justifies what it is used
for. Compatibility with downstream device trees is not a valid
justification for its existence.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
drivers/ufs/host/ufs-mediatek.c | 19 -------------------
1 file changed, 19 deletions(-)
diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index ae6735683f76..1dfc299b93b5 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -880,8 +880,6 @@ static void ufs_mtk_init_clocks(struct ufs_hba *hba)
struct ufs_mtk_host *host = ufshcd_get_variant(hba);
struct list_head *head = &hba->clk_list_head;
struct ufs_clk_info *clki, *clki_tmp;
- struct device *dev = hba->dev;
- u32 volt;
/*
* Find private clocks and store them in struct ufs_mtk_clk.
@@ -918,24 +916,7 @@ static void ufs_mtk_init_clocks(struct ufs_hba *hba)
if (!ufs_mtk_is_clk_scale_ready(hba)) {
hba->caps &= ~UFSHCD_CAP_CLK_SCALING;
dev_info(hba->dev, "%s: Clock scaling unavailable", __func__);
- return;
- }
-
- if (!host->reg_vcore)
- return;
-
- if (of_property_read_u32(dev->of_node, "clk-scale-up-vcore-min",
- &volt)) {
- dev_info(dev, "failed to get clk-scale-up-vcore-min");
- return;
}
-
- host->mclk.vcore_volt = volt;
-
- /* If default boot is max gear, request vcore */
- if (volt && host->clk_scale_up)
- if (regulator_set_voltage(host->reg_vcore, volt, INT_MAX))
- dev_err(hba->dev, "Failed to set vcore to %d\n", volt);
}
static void ufs_mtk_setup_clk_gating(struct ufs_hba *hba)
--
2.53.0
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* [PATCH v9 16/23] scsi: ufs: mediatek: Clean up logging prints
From: Nicolas Frattaroli @ 2026-03-06 13:24 UTC (permalink / raw)
To: Alim Akhtar, Avri Altman, Bart Van Assche, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chunfeng Yun, Vinod Koul,
Kishon Vijay Abraham I, Peter Wang, Stanley Jhu,
James E.J. Bottomley, Martin K. Petersen, Philipp Zabel,
Liam Girdwood, Mark Brown, Chaotian Jing, Neil Armstrong
Cc: Louis-Alexis Eyraud, kernel, linux-scsi, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-phy, Nicolas Frattaroli
In-Reply-To: <20260306-mt8196-ufs-v9-0-55b073f7a830@collabora.com>
The Linux kernel's log buffer provides many levels of verbosity,
associated with different semantic meanings. Care should be taken to
only log useful information to the info level, and log errors to the
error level.
The MediaTek UFS driver does not do this. It freely logs verbose debug
information to the info level, errors to the info level, and sometimes
errors to the warning level.
Adjust all the wrapped kprintf invocations to rectify this situation.
Use user-friendly %pe format codes for printing errors where possible.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Peter Wang <peter.wang@mediatek.com>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
drivers/ufs/host/ufs-mediatek.c | 97 ++++++++++++++++++-----------------------
1 file changed, 42 insertions(+), 55 deletions(-)
diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index c236a833fe9a..8d2aa3d9a6e2 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -192,8 +192,8 @@ static void ufs_mtk_crypto_enable(struct ufs_hba *hba)
ufs_mtk_crypto_ctrl(res, 1);
if (res.a0) {
- dev_info(hba->dev, "%s: crypto enable failed, err: %lu\n",
- __func__, res.a0);
+ dev_err(hba->dev, "%s: crypto enable failed with error %lu, disabling\n",
+ __func__, res.a0);
hba->caps &= ~UFSHCD_CAP_CRYPTO;
}
}
@@ -542,40 +542,38 @@ static void ufs_mtk_boost_crypt(struct ufs_hba *hba, bool boost)
ret = clk_prepare_enable(cfg->clk_crypt_mux);
if (ret) {
- dev_info(hba->dev, "clk_prepare_enable(): %d\n",
- ret);
+ dev_err(hba->dev, "%s: Failed to enable clk_crypt_mux: %pe\n",
+ __func__, ERR_PTR(ret));
return;
}
if (boost) {
ret = regulator_set_voltage(reg, volt, INT_MAX);
if (ret) {
- dev_info(hba->dev,
- "failed to set vcore to %d\n", volt);
+ dev_err(hba->dev, "%s: Failed to set vcore to %d: %pe\n",
+ __func__, volt, ERR_PTR(ret));
goto out;
}
- ret = clk_set_parent(cfg->clk_crypt_mux,
- cfg->clk_crypt_perf);
+ ret = clk_set_parent(cfg->clk_crypt_mux, cfg->clk_crypt_perf);
if (ret) {
- dev_info(hba->dev,
- "failed to set clk_crypt_perf\n");
+ dev_err(hba->dev, "%s: Failed to reparent clk_crypt_perf: %pe\n",
+ __func__, ERR_PTR(ret));
regulator_set_voltage(reg, 0, INT_MAX);
goto out;
}
} else {
- ret = clk_set_parent(cfg->clk_crypt_mux,
- cfg->clk_crypt_lp);
+ ret = clk_set_parent(cfg->clk_crypt_mux, cfg->clk_crypt_lp);
if (ret) {
- dev_info(hba->dev,
- "failed to set clk_crypt_lp\n");
+ dev_err(hba->dev, "%s: Failed to reparent clk_crypt_lp: %pe\n",
+ __func__, ERR_PTR(ret));
goto out;
}
ret = regulator_set_voltage(reg, 0, INT_MAX);
if (ret) {
- dev_info(hba->dev,
- "failed to set vcore to MIN\n");
+ dev_err(hba->dev, "%s: Failed to set vcore to minimum: %pe\n",
+ __func__, ERR_PTR(ret));
}
}
out:
@@ -763,10 +761,8 @@ static int ufs_mtk_setup_clocks(struct ufs_hba *hba, bool on,
if (clk_pwr_off) {
ufs_mtk_pwr_ctrl(hba, false);
} else {
- dev_warn(hba->dev, "Clock is not turned off, hba->ahit = 0x%x, AHIT = 0x%x\n",
- hba->ahit,
- ufshcd_readl(hba,
- REG_AUTO_HIBERNATE_IDLE_TIMER));
+ dev_warn(hba->dev, "Clock isn't off, hba->ahit = 0x%x, AHIT = 0x%x\n",
+ hba->ahit, ufshcd_readl(hba, REG_AUTO_HIBERNATE_IDLE_TIMER));
}
ufs_mtk_mcq_disable_irq(hba);
} else if (on && status == POST_CHANGE) {
@@ -810,11 +806,11 @@ static void ufs_mtk_mcq_set_irq_affinity(struct ufs_hba *hba, unsigned int cpu)
_cpu = (cpu == 0) ? 3 : cpu;
ret = irq_set_affinity(irq, cpumask_of(_cpu));
if (ret) {
- dev_err(hba->dev, "set irq %d affinity to CPU %d failed\n",
+ dev_err(hba->dev, "setting irq %d affinity to CPU %d failed\n",
irq, _cpu);
return;
}
- dev_info(hba->dev, "set irq %d affinity to CPU: %d\n", irq, _cpu);
+ dev_dbg(hba->dev, "set irq %d affinity to CPU %d\n", irq, _cpu);
}
static bool ufs_mtk_is_legacy_chipset(struct ufs_hba *hba, u32 hw_ip_ver)
@@ -830,7 +826,8 @@ static bool ufs_mtk_is_legacy_chipset(struct ufs_hba *hba, u32 hw_ip_ver)
default:
break;
}
- dev_info(hba->dev, "legacy IP version - 0x%x, is legacy : %d", hw_ip_ver, is_legacy);
+ dev_dbg(hba->dev, "IP version 0x%x, legacy = %s", hw_ip_ver,
+ str_true_false(is_legacy));
return is_legacy;
}
@@ -935,15 +932,12 @@ static void ufs_mtk_init_clocks(struct ufs_hba *hba)
}
}
- list_for_each_entry(clki, head, list) {
- dev_info(hba->dev, "clk \"%s\" present", clki->name);
- }
+ list_for_each_entry(clki, head, list)
+ dev_dbg(hba->dev, "clk \"%s\" present", clki->name);
if (!ufs_mtk_is_clk_scale_ready(hba)) {
hba->caps &= ~UFSHCD_CAP_CLK_SCALING;
- dev_info(hba->dev,
- "%s: Clk-scaling not ready. Feature disabled.",
- __func__);
+ dev_info(hba->dev, "%s: Clock scaling unavailable", __func__);
return;
}
@@ -953,8 +947,8 @@ static void ufs_mtk_init_clocks(struct ufs_hba *hba)
*/
reg = devm_regulator_get_optional(dev, "dvfsrc-vcore");
if (IS_ERR(reg)) {
- dev_info(dev, "failed to get dvfsrc-vcore: %ld",
- PTR_ERR(reg));
+ if (PTR_ERR(reg) != -ENODEV)
+ dev_err(dev, "Failed to get dvfsrc-vcore: %pe\n", reg);
return;
}
@@ -968,12 +962,9 @@ static void ufs_mtk_init_clocks(struct ufs_hba *hba)
host->mclk.vcore_volt = volt;
/* If default boot is max gear, request vcore */
- if (reg && volt && host->clk_scale_up) {
- if (regulator_set_voltage(reg, volt, INT_MAX)) {
- dev_info(hba->dev,
- "Failed to set vcore to %d\n", volt);
- }
- }
+ if (reg && volt && host->clk_scale_up)
+ if (regulator_set_voltage(reg, volt, INT_MAX))
+ dev_err(hba->dev, "Failed to set vcore to %d\n", volt);
}
static void ufs_mtk_setup_clk_gating(struct ufs_hba *hba)
@@ -1060,7 +1051,7 @@ static void ufs_mtk_init_mcq_irq(struct ufs_hba *hba)
}
host->mcq_intr_info[i].hba = hba;
host->mcq_intr_info[i].irq = irq;
- dev_info(hba->dev, "get platform mcq irq: %d, %d\n", i, irq);
+ dev_dbg(hba->dev, "get platform mcq irq: %d, %d\n", i, irq);
}
return;
@@ -1307,10 +1298,8 @@ static int ufs_mtk_pre_pwr_change(struct ufs_hba *hba,
host_params.desired_working_mode = UFS_PWM_MODE;
ret = ufshcd_negotiate_pwr_params(&host_params, dev_max_params, dev_req_params);
- if (ret) {
- pr_info("%s: failed to determine capabilities\n",
- __func__);
- }
+ if (ret)
+ dev_warn(hba->dev, "%s: failed to determine capabilities\n", __func__);
if (ufs_mtk_pmc_via_fastauto(hba, dev_req_params)) {
ufs_mtk_adjust_sync_length(hba);
@@ -1356,10 +1345,9 @@ static int ufs_mtk_pre_pwr_change(struct ufs_hba *hba,
ret = ufshcd_uic_change_pwr_mode(hba,
FASTAUTO_MODE << 4 | FASTAUTO_MODE);
- if (ret) {
- dev_err(hba->dev, "%s: HSG1B FASTAUTO failed ret=%d\n",
- __func__, ret);
- }
+ if (ret)
+ dev_err(hba->dev, "%s: HSG1B FASTAUTO failed: %pe\n",
+ __func__, ERR_PTR(ret));
}
/* if already configured to the requested pwr_mode, skip adapt */
@@ -1409,7 +1397,7 @@ static int ufs_mtk_auto_hibern8_disable(struct ufs_hba *hba)
out:
if (ret) {
- dev_warn(hba->dev, "exit h8 state fail, ret=%d\n", ret);
+ dev_err(hba->dev, "Failed to exit h8 state: %pe\n", ERR_PTR(ret));
ufshcd_force_error_recovery(hba);
@@ -1607,12 +1595,12 @@ static int ufs_mtk_link_set_hpm(struct ufs_hba *hba)
/* Check link state to make sure exit h8 success */
err = ufs_mtk_wait_idle_state(hba, 5);
if (err) {
- dev_warn(hba->dev, "wait idle fail, err=%d\n", err);
+ dev_err(hba->dev, "Failed to wait for idle: %pe\n", ERR_PTR(err));
return err;
}
err = ufs_mtk_wait_link_state(hba, VS_LINK_UP, 100);
if (err) {
- dev_warn(hba->dev, "exit h8 state fail, err=%d\n", err);
+ dev_err(hba->dev, "Failed to wait for link to be up: %pe\n", ERR_PTR(err));
return err;
}
ufshcd_set_link_active(hba);
@@ -1905,20 +1893,19 @@ static void ufs_mtk_event_notify(struct ufs_hba *hba,
/* Print details of UIC Errors */
if (evt <= UFS_EVT_DME_ERR) {
- dev_info(hba->dev,
- "Host UIC Error Code (%s): %08x\n",
- ufs_uic_err_str[evt], val);
+ dev_err(hba->dev, "Host UIC Error Code (%s): %08x\n",
+ ufs_uic_err_str[evt], val);
reg = val;
}
if (evt == UFS_EVT_PA_ERR) {
for_each_set_bit(bit, ®, ARRAY_SIZE(ufs_uic_pa_err_str))
- dev_info(hba->dev, "%s\n", ufs_uic_pa_err_str[bit]);
+ dev_err(hba->dev, "%s\n", ufs_uic_pa_err_str[bit]);
}
if (evt == UFS_EVT_DL_ERR) {
for_each_set_bit(bit, ®, ARRAY_SIZE(ufs_uic_dl_err_str))
- dev_info(hba->dev, "%s\n", ufs_uic_dl_err_str[bit]);
+ dev_err(hba->dev, "%s\n", ufs_uic_dl_err_str[bit]);
}
}
@@ -2123,7 +2110,7 @@ static int ufs_mtk_mcq_config_resource(struct ufs_hba *hba)
/* fail mcq initialization if interrupt is not filled properly */
if (!host->mcq_nr_intr) {
- dev_info(hba->dev, "IRQs not ready. MCQ disabled.");
+ dev_err(hba->dev, "IRQs not ready. MCQ disabled.");
return -EINVAL;
}
--
2.53.0
--
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^ permalink raw reply related
* [PATCH v9 17/23] scsi: ufs: mediatek: Rework ufs_mtk_wait_idle_state
From: Nicolas Frattaroli @ 2026-03-06 13:24 UTC (permalink / raw)
To: Alim Akhtar, Avri Altman, Bart Van Assche, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chunfeng Yun, Vinod Koul,
Kishon Vijay Abraham I, Peter Wang, Stanley Jhu,
James E.J. Bottomley, Martin K. Petersen, Philipp Zabel,
Liam Girdwood, Mark Brown, Chaotian Jing, Neil Armstrong
Cc: Louis-Alexis Eyraud, kernel, linux-scsi, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-phy, Nicolas Frattaroli
In-Reply-To: <20260306-mt8196-ufs-v9-0-55b073f7a830@collabora.com>
While ufs_mtk_wait_idle state has some code smells for me (the
VS_HCE_BASE early exit seems racey at best), it can still benefit from
some general cleanup to make the code flow less convoluted.
Use the iopoll helpers, for one, and specifically the one that sleeps
and does not busy delay, as it's being done for up to 5ms.
The register read is split out to a helper function that branches
between new and old style flow.
Every called uses the same 5ms timeout value, so there is no point in
making this a parameter. Just assume a 5ms timeout in the function.
Reviewed-by: Peter Wang <peter.wang@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
drivers/ufs/host/ufs-mediatek.c | 71 +++++++++++++++++------------------------
1 file changed, 30 insertions(+), 41 deletions(-)
diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index 8d2aa3d9a6e2..c2a044a70466 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -10,6 +10,7 @@
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/delay.h>
+#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
@@ -380,51 +381,39 @@ static void ufs_mtk_dbg_sel(struct ufs_hba *hba)
}
}
-static int ufs_mtk_wait_idle_state(struct ufs_hba *hba,
- unsigned long retry_ms)
+static u32 ufs_mtk_read_state(struct ufs_hba *hba, bool old_style)
{
- u64 timeout, time_checked;
- u32 val, sm;
- bool wait_idle;
- struct ufs_mtk_host *host = ufshcd_get_variant(hba);
-
- /* cannot use plain ktime_get() in suspend */
- timeout = ktime_get_mono_fast_ns() + retry_ms * 1000000UL;
-
- /* wait a specific time after check base */
- udelay(10);
- wait_idle = false;
+ u32 val;
- do {
- time_checked = ktime_get_mono_fast_ns();
- if (host->legacy_ip_ver || host->ip_ver < IP_VER_MT6899) {
- ufs_mtk_dbg_sel(hba);
- val = ufshcd_readl(hba, REG_UFS_PROBE);
- } else {
- val = ufshcd_readl(hba, REG_UFS_UFS_MMIO_OTSD_CTRL);
- val = val >> 16;
- }
+ if (old_style) {
+ ufs_mtk_dbg_sel(hba);
+ val = ufshcd_readl(hba, REG_UFS_PROBE);
+ } else {
+ val = ufshcd_readl(hba, REG_UFS_UFS_MMIO_OTSD_CTRL) >> 16;
+ }
- sm = val & 0x1f;
+ return FIELD_GET(0x1f, val);
+}
- /*
- * if state is in H8 enter and H8 enter confirm
- * wait until return to idle state.
- */
- if ((sm >= VS_HIB_ENTER) && (sm <= VS_HIB_EXIT)) {
- wait_idle = true;
- udelay(50);
- continue;
- } else if (!wait_idle)
- break;
+static int ufs_mtk_wait_idle_state(struct ufs_hba *hba)
+{
+ struct ufs_mtk_host *host = ufshcd_get_variant(hba);
+ bool old_style = (host->legacy_ip_ver || host->ip_ver < IP_VER_MT6899);
+ u32 val;
+ int ret;
- if (wait_idle && (sm == VS_HCE_BASE))
- break;
- } while (time_checked < timeout);
+ /* If the device isn't in a hibernate state after 10us, don't wait. */
+ udelay(10);
+ val = ufs_mtk_read_state(hba, old_style);
+ if (val < VS_HIB_ENTER || val > VS_HIB_EXIT)
+ return 0;
- if (wait_idle && sm != VS_HCE_BASE) {
- dev_info(hba->dev, "wait idle tmo: 0x%x\n", val);
- return -ETIMEDOUT;
+ /* Poll to wait for idle */
+ ret = read_poll_timeout(ufs_mtk_read_state, val, (val == VS_HCE_BASE),
+ 50, 5 * USEC_PER_MSEC, false, hba, old_style);
+ if (ret) {
+ dev_err(hba->dev, "Timed out waiting for idle state, val = 0x%x\n", val);
+ return ret;
}
return 0;
@@ -1389,7 +1378,7 @@ static int ufs_mtk_auto_hibern8_disable(struct ufs_hba *hba)
ufshcd_writel(hba, 0, REG_AUTO_HIBERNATE_IDLE_TIMER);
/* wait host return to idle state when auto-hibern8 off */
- ret = ufs_mtk_wait_idle_state(hba, 5);
+ ret = ufs_mtk_wait_idle_state(hba);
if (ret)
goto out;
@@ -1593,7 +1582,7 @@ static int ufs_mtk_link_set_hpm(struct ufs_hba *hba)
return err;
/* Check link state to make sure exit h8 success */
- err = ufs_mtk_wait_idle_state(hba, 5);
+ err = ufs_mtk_wait_idle_state(hba);
if (err) {
dev_err(hba->dev, "Failed to wait for idle: %pe\n", ERR_PTR(err));
return err;
--
2.53.0
--
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linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH v9 18/23] scsi: ufs: mediatek: Don't acquire dvfsrc-vcore twice
From: Nicolas Frattaroli @ 2026-03-06 13:24 UTC (permalink / raw)
To: Alim Akhtar, Avri Altman, Bart Van Assche, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chunfeng Yun, Vinod Koul,
Kishon Vijay Abraham I, Peter Wang, Stanley Jhu,
James E.J. Bottomley, Martin K. Petersen, Philipp Zabel,
Liam Girdwood, Mark Brown, Chaotian Jing, Neil Armstrong
Cc: Louis-Alexis Eyraud, kernel, linux-scsi, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-phy, Nicolas Frattaroli
In-Reply-To: <20260306-mt8196-ufs-v9-0-55b073f7a830@collabora.com>
As part of its featureset, the ufs-mediatek driver needs to play with an
optional dvfsrc-vcore regulator for some of them.
However, it currently does this by acquiring two different references to
it in two different places, needlessly duplicating logic.
Move reg_vcore to the host struct, acquire it in the same function as
avdd09 is acquired, and rework the users of reg_vcore.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Peter Wang <peter.wang@mediatek.com>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
drivers/ufs/host/ufs-mediatek.c | 71 +++++++++++++++++++----------------------
drivers/ufs/host/ufs-mediatek.h | 3 +-
2 files changed, 33 insertions(+), 41 deletions(-)
diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index c2a044a70466..5573e7f8bd13 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -519,7 +519,6 @@ static void ufs_mtk_boost_crypt(struct ufs_hba *hba, bool boost)
{
struct ufs_mtk_host *host = ufshcd_get_variant(hba);
struct ufs_mtk_crypt_cfg *cfg;
- struct regulator *reg;
int volt, ret;
if (!ufs_mtk_is_boost_crypt_enabled(hba))
@@ -527,7 +526,6 @@ static void ufs_mtk_boost_crypt(struct ufs_hba *hba, bool boost)
cfg = host->crypt;
volt = cfg->vcore_volt;
- reg = cfg->reg_vcore;
ret = clk_prepare_enable(cfg->clk_crypt_mux);
if (ret) {
@@ -537,7 +535,7 @@ static void ufs_mtk_boost_crypt(struct ufs_hba *hba, bool boost)
}
if (boost) {
- ret = regulator_set_voltage(reg, volt, INT_MAX);
+ ret = regulator_set_voltage(host->reg_vcore, volt, INT_MAX);
if (ret) {
dev_err(hba->dev, "%s: Failed to set vcore to %d: %pe\n",
__func__, volt, ERR_PTR(ret));
@@ -548,7 +546,7 @@ static void ufs_mtk_boost_crypt(struct ufs_hba *hba, bool boost)
if (ret) {
dev_err(hba->dev, "%s: Failed to reparent clk_crypt_perf: %pe\n",
__func__, ERR_PTR(ret));
- regulator_set_voltage(reg, 0, INT_MAX);
+ regulator_set_voltage(host->reg_vcore, 0, INT_MAX);
goto out;
}
} else {
@@ -559,7 +557,7 @@ static void ufs_mtk_boost_crypt(struct ufs_hba *hba, bool boost)
goto out;
}
- ret = regulator_set_voltage(reg, 0, INT_MAX);
+ ret = regulator_set_voltage(host->reg_vcore, 0, INT_MAX);
if (ret) {
dev_err(hba->dev, "%s: Failed to set vcore to minimum: %pe\n",
__func__, ERR_PTR(ret));
@@ -576,15 +574,12 @@ static void ufs_mtk_init_boost_crypt(struct ufs_hba *hba)
struct device *dev = hba->dev;
int ret;
- cfg = devm_kzalloc(dev, sizeof(*cfg), GFP_KERNEL);
- if (!cfg)
+ if (!host->reg_vcore)
return;
- cfg->reg_vcore = devm_regulator_get_optional(dev, "dvfsrc-vcore");
- if (IS_ERR(cfg->reg_vcore)) {
- dev_err(dev, "Failed to get dvfsrc-vcore: %pe", cfg->reg_vcore);
+ cfg = devm_kzalloc(dev, sizeof(*cfg), GFP_KERNEL);
+ if (!cfg)
return;
- }
ret = of_property_read_u32(dev->of_node, "mediatek,boost-crypt-vcore-min",
&cfg->vcore_volt);
@@ -889,7 +884,6 @@ static void ufs_mtk_init_clocks(struct ufs_hba *hba)
struct list_head *head = &hba->clk_list_head;
struct ufs_clk_info *clki, *clki_tmp;
struct device *dev = hba->dev;
- struct regulator *reg;
u32 volt;
/*
@@ -930,16 +924,8 @@ static void ufs_mtk_init_clocks(struct ufs_hba *hba)
return;
}
- /*
- * Default get vcore if dts have these settings.
- * No matter clock scaling support or not. (may disable by customer)
- */
- reg = devm_regulator_get_optional(dev, "dvfsrc-vcore");
- if (IS_ERR(reg)) {
- if (PTR_ERR(reg) != -ENODEV)
- dev_err(dev, "Failed to get dvfsrc-vcore: %pe\n", reg);
+ if (!host->reg_vcore)
return;
- }
if (of_property_read_u32(dev->of_node, "clk-scale-up-vcore-min",
&volt)) {
@@ -947,12 +933,11 @@ static void ufs_mtk_init_clocks(struct ufs_hba *hba)
return;
}
- host->mclk.reg_vcore = reg;
host->mclk.vcore_volt = volt;
/* If default boot is max gear, request vcore */
- if (reg && volt && host->clk_scale_up)
- if (regulator_set_voltage(reg, volt, INT_MAX))
+ if (volt && host->clk_scale_up)
+ if (regulator_set_voltage(host->reg_vcore, volt, INT_MAX))
dev_err(hba->dev, "Failed to set vcore to %d\n", volt);
}
@@ -1064,6 +1049,17 @@ static int ufs_mtk_get_supplies(struct ufs_mtk_host *host)
const struct ufs_mtk_soc_data *data = of_device_get_match_data(dev);
int ret;
+ host->reg_vcore = devm_regulator_get_optional(dev, "dvfsrc-vcore");
+ if (IS_ERR(host->reg_vcore)) {
+ if (PTR_ERR(host->reg_vcore) != -ENODEV) {
+ dev_err(dev, "Failed to get dvfsrc-vcore supply: %pe\n",
+ host->reg_vcore);
+ return PTR_ERR(host->reg_vcore);
+ }
+
+ host->reg_vcore = NULL;
+ }
+
if (!data)
return 0;
@@ -1081,14 +1077,13 @@ static int ufs_mtk_get_supplies(struct ufs_mtk_host *host)
host->reg_avdd09 = devm_regulator_get_optional(dev, "avdd09");
if (IS_ERR(host->reg_avdd09)) {
- if (PTR_ERR(host->reg_avdd09) == -ENODEV) {
- host->reg_avdd09 = NULL;
- return 0;
+ if (PTR_ERR(host->reg_avdd09) != -ENODEV) {
+ dev_err(dev, "Failed to get avdd09 regulator: %pe\n",
+ host->reg_avdd09);
+ return PTR_ERR(host->reg_avdd09);
}
- dev_err(dev, "Failed to get avdd09 regulator: %pe\n",
- host->reg_avdd09);
- return PTR_ERR(host->reg_avdd09);
+ host->reg_avdd09 = NULL;
}
return 0;
@@ -1119,6 +1114,10 @@ static int ufs_mtk_init(struct ufs_hba *hba)
host->hba = hba;
ufshcd_set_variant(hba, host);
+ err = ufs_mtk_get_supplies(host);
+ if (err)
+ goto out_variant_clear;
+
/* Initialize host capability */
ufs_mtk_init_host_caps(hba);
@@ -1173,10 +1172,6 @@ static int ufs_mtk_init(struct ufs_hba *hba)
ufs_mtk_init_clocks(hba);
- err = ufs_mtk_get_supplies(host);
- if (err)
- goto out_phy_exit;
-
/*
* ufshcd_vops_init() is invoked after
* ufshcd_setup_clock(true) in ufshcd_hba_init() thus
@@ -1916,7 +1911,6 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba, bool scale_up)
struct ufs_mtk_clk *mclk = &host->mclk;
struct ufs_clk_info *clki = mclk->ufs_sel_clki;
struct ufs_clk_info *fde_clki = mclk->ufs_fde_clki;
- struct regulator *reg;
int volt, ret = 0;
bool clk_bind_vcore = false;
bool clk_fde_scale = false;
@@ -1927,9 +1921,8 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba, bool scale_up)
if (!clki || !fde_clki)
return;
- reg = host->mclk.reg_vcore;
volt = host->mclk.vcore_volt;
- if (reg && volt != 0)
+ if (host->reg_vcore && volt)
clk_bind_vcore = true;
if (mclk->ufs_fde_max_clki && mclk->ufs_fde_min_clki)
@@ -1953,7 +1946,7 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba, bool scale_up)
if (scale_up) {
if (clk_bind_vcore) {
- ret = regulator_set_voltage(reg, volt, INT_MAX);
+ ret = regulator_set_voltage(host->reg_vcore, volt, INT_MAX);
if (ret) {
dev_err(hba->dev, "Failed to set vcore to %d\n", volt);
goto out;
@@ -1993,7 +1986,7 @@ static void _ufs_mtk_clk_scale(struct ufs_hba *hba, bool scale_up)
}
if (clk_bind_vcore) {
- ret = regulator_set_voltage(reg, 0, INT_MAX);
+ ret = regulator_set_voltage(host->reg_vcore, 0, INT_MAX);
if (ret) {
dev_err(hba->dev, "%s: Failed to set vcore to minimum: %pe\n",
__func__, ERR_PTR(ret));
diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediatek.h
index 9c377745f7a0..fa27ab4d6d6c 100644
--- a/drivers/ufs/host/ufs-mediatek.h
+++ b/drivers/ufs/host/ufs-mediatek.h
@@ -141,7 +141,6 @@ enum ufs_mtk_host_caps {
};
struct ufs_mtk_crypt_cfg {
- struct regulator *reg_vcore;
struct clk *clk_crypt_perf;
struct clk *clk_crypt_mux;
struct clk *clk_crypt_lp;
@@ -155,7 +154,6 @@ struct ufs_mtk_clk {
struct ufs_clk_info *ufs_fde_clki; /* Mux */
struct ufs_clk_info *ufs_fde_max_clki; /* Max src */
struct ufs_clk_info *ufs_fde_min_clki; /* Min src */
- struct regulator *reg_vcore;
int vcore_volt;
};
@@ -174,6 +172,7 @@ struct ufs_mtk_mcq_intr_info {
struct ufs_mtk_host {
struct phy *mphy;
struct regulator *reg_avdd09;
+ struct regulator *reg_vcore;
struct reset_control_bulk_data resets[MTK_UFS_NUM_RESETS];
struct ufs_hba *hba;
struct ufs_mtk_crypt_cfg *crypt;
--
2.53.0
--
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^ permalink raw reply related
* [PATCH v9 19/23] scsi: ufs: mediatek: Rework hardware version reading
From: Nicolas Frattaroli @ 2026-03-06 13:25 UTC (permalink / raw)
To: Alim Akhtar, Avri Altman, Bart Van Assche, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chunfeng Yun, Vinod Koul,
Kishon Vijay Abraham I, Peter Wang, Stanley Jhu,
James E.J. Bottomley, Martin K. Petersen, Philipp Zabel,
Liam Girdwood, Mark Brown, Chaotian Jing, Neil Armstrong
Cc: Louis-Alexis Eyraud, kernel, linux-scsi, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-phy, Nicolas Frattaroli
In-Reply-To: <20260306-mt8196-ufs-v9-0-55b073f7a830@collabora.com>
Split assignment to the host struct out from the read function, and
utilise bitfield helpers to simplify the code. Also move the debug print
out of the legacy version helper, which means it no longer has to take a
struct ufs_hba as an input, and can be rewritten as a pure function.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Peter Wang <peter.wang@mediatek.com>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
drivers/ufs/host/ufs-mediatek.c | 65 +++++++++++++++++++++--------------------
1 file changed, 33 insertions(+), 32 deletions(-)
diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index 5573e7f8bd13..c4e70fb99e82 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -797,50 +797,47 @@ static void ufs_mtk_mcq_set_irq_affinity(struct ufs_hba *hba, unsigned int cpu)
dev_dbg(hba->dev, "set irq %d affinity to CPU %d\n", irq, _cpu);
}
-static bool ufs_mtk_is_legacy_chipset(struct ufs_hba *hba, u32 hw_ip_ver)
+static bool __pure ufs_mtk_is_legacy_chipset(u32 hw_ip_ver)
{
- bool is_legacy = false;
-
switch (hw_ip_ver) {
case IP_LEGACY_VER_MT6893:
case IP_LEGACY_VER_MT6781:
/* can add other legacy chipset ID here accordingly */
- is_legacy = true;
- break;
- default:
- break;
+ return true;
}
- dev_dbg(hba->dev, "IP version 0x%x, legacy = %s", hw_ip_ver,
- str_true_false(is_legacy));
- return is_legacy;
+ return false;
}
-/*
- * HW version format has been changed from 01MMmmmm to 1MMMmmmm, since
- * project MT6878. In order to perform correct version comparison,
- * version number is changed by SW for the following projects.
- * IP_VER_MT6983 0x00360000 to 0x10360000
- * IP_VER_MT6897 0x01440000 to 0x10440000
- * IP_VER_MT6989 0x01450000 to 0x10450000
- * IP_VER_MT6991 0x01460000 to 0x10460000
+#define MTK_UFS_VER_PREFIX_M (0xFF << 24)
+
+/**
+ * ufs_mtk_get_hw_ip_version - read and return adjusted hardware version
+ * @hba: pointer to this device's &struct ufs_hba
+ *
+ * Reads, transforms and returns the hardware version.
+ *
+ * Since MT6878, the versioning scheme was changed from 01MMmmmm to 1MMMmmmm.
+ * In order to support version comparisons across these different versioning
+ * schemes, this function transforms the older style to the newer one.
+ *
+ * For example:
+ * MT6983 is transformed from 0x00360000 to 0x10360000
+ * MT6897 is transformed from 0x01440000 to 0x10440000
+ * MT6989 is transformed from 0x01450000 to 0x10450000
+ * MT6991 is transformed from 0x01460000 to 0x10460000
+ *
+ * Returns a u32 representing the hardware version.
*/
-static void ufs_mtk_get_hw_ip_version(struct ufs_hba *hba)
+static u32 ufs_mtk_get_hw_ip_version(struct ufs_hba *hba)
{
- struct ufs_mtk_host *host = ufshcd_get_variant(hba);
- u32 hw_ip_ver;
+ u32 version = ufshcd_readl(hba, REG_UFS_MTK_IP_VER);
+ u32 prefix = FIELD_GET(MTK_UFS_VER_PREFIX_M, version);
- hw_ip_ver = ufshcd_readl(hba, REG_UFS_MTK_IP_VER);
+ if (prefix <= 1)
+ FIELD_MODIFY(MTK_UFS_VER_PREFIX_M, &version, BIT(28));
- if (((hw_ip_ver & (0xFF << 24)) == (0x1 << 24)) ||
- ((hw_ip_ver & (0xFF << 24)) == 0)) {
- hw_ip_ver &= ~(0xFF << 24);
- hw_ip_ver |= (0x1 << 28);
- }
-
- host->ip_ver = hw_ip_ver;
-
- host->legacy_ip_ver = ufs_mtk_is_legacy_chipset(hba, hw_ip_ver);
+ return version;
}
static void ufs_mtk_get_controller_version(struct ufs_hba *hba)
@@ -1191,7 +1188,11 @@ static int ufs_mtk_init(struct ufs_hba *hba)
ufs_mtk_setup_clocks(hba, true, POST_CHANGE);
- ufs_mtk_get_hw_ip_version(hba);
+ host->ip_ver = ufs_mtk_get_hw_ip_version(hba);
+ host->legacy_ip_ver = ufs_mtk_is_legacy_chipset(host->ip_ver);
+
+ dev_dbg(hba->dev, "IP version 0x%x, legacy = %s", host->ip_ver,
+ str_true_false(host->legacy_ip_ver));
return 0;
--
2.53.0
--
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https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH v9 21/23] scsi: ufs: mediatek: Remove ret local from link_startup_notify
From: Nicolas Frattaroli @ 2026-03-06 13:25 UTC (permalink / raw)
To: Alim Akhtar, Avri Altman, Bart Van Assche, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chunfeng Yun, Vinod Koul,
Kishon Vijay Abraham I, Peter Wang, Stanley Jhu,
James E.J. Bottomley, Martin K. Petersen, Philipp Zabel,
Liam Girdwood, Mark Brown, Chaotian Jing, Neil Armstrong
Cc: Louis-Alexis Eyraud, kernel, linux-scsi, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-phy, Nicolas Frattaroli
In-Reply-To: <20260306-mt8196-ufs-v9-0-55b073f7a830@collabora.com>
Remove the "ret" local variable from ufs_mtk_link_startup_notify, as
it's pointless; in all cases it is assigned, it is returned right after
without being read first.
Rework the code to just return directly, and get rid of the default
branch while at it.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Peter Wang <peter.wang@mediatek.com>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
drivers/ufs/host/ufs-mediatek.c | 12 +++---------
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index 2198271a269a..ae6735683f76 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -1500,21 +1500,15 @@ static void ufs_mtk_post_link(struct ufs_hba *hba)
static int ufs_mtk_link_startup_notify(struct ufs_hba *hba,
enum ufs_notify_change_status stage)
{
- int ret = 0;
-
switch (stage) {
case PRE_CHANGE:
- ret = ufs_mtk_pre_link(hba);
- break;
+ return ufs_mtk_pre_link(hba);
case POST_CHANGE:
ufs_mtk_post_link(hba);
- break;
- default:
- ret = -EINVAL;
- break;
+ return 0;
}
- return ret;
+ return -EINVAL;
}
static int ufs_mtk_device_reset(struct ufs_hba *hba)
--
2.53.0
--
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* [PATCH v9 20/23] scsi: ufs: mediatek: Back up idle timer in per-instance struct
From: Nicolas Frattaroli @ 2026-03-06 13:25 UTC (permalink / raw)
To: Alim Akhtar, Avri Altman, Bart Van Assche, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chunfeng Yun, Vinod Koul,
Kishon Vijay Abraham I, Peter Wang, Stanley Jhu,
James E.J. Bottomley, Martin K. Petersen, Philipp Zabel,
Liam Girdwood, Mark Brown, Chaotian Jing, Neil Armstrong
Cc: Louis-Alexis Eyraud, kernel, linux-scsi, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-phy, Nicolas Frattaroli
In-Reply-To: <20260306-mt8196-ufs-v9-0-55b073f7a830@collabora.com>
The MediaTek UFS driver uses a function-scope static variable to back up
a hardware register across a power change in the
ufs_mtk_pwr_change_notify function. This is dangerous, as it's only
correct if only ever one instance of the driver is loaded, which isn't
true if there's more than one device on a SoC that needs it, or it
otherwise gets loaded a second time.
Back it up into a member of the host struct instead, as this struct is
per-instance. Rework the function to not use a pointless "ret" local as
well.
Fixes: f5ca8d0c7a63 ("scsi: ufs: host: mediatek: Disable auto-hibern8 during power mode changes")
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
drivers/ufs/host/ufs-mediatek.c | 20 ++++++++------------
drivers/ufs/host/ufs-mediatek.h | 1 +
2 files changed, 9 insertions(+), 12 deletions(-)
diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index c4e70fb99e82..2198271a269a 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -1398,28 +1398,24 @@ static int ufs_mtk_pwr_change_notify(struct ufs_hba *hba,
const struct ufs_pa_layer_attr *dev_max_params,
struct ufs_pa_layer_attr *dev_req_params)
{
- int ret = 0;
- static u32 reg;
+ struct ufs_mtk_host *host = ufshcd_get_variant(hba);
switch (stage) {
case PRE_CHANGE:
if (ufshcd_is_auto_hibern8_supported(hba)) {
- reg = ufshcd_readl(hba, REG_AUTO_HIBERNATE_IDLE_TIMER);
+ host->ahit = ufshcd_readl(
+ hba, REG_AUTO_HIBERNATE_IDLE_TIMER);
ufs_mtk_auto_hibern8_disable(hba);
}
- ret = ufs_mtk_pre_pwr_change(hba, dev_max_params,
- dev_req_params);
- break;
+ return ufs_mtk_pre_pwr_change(hba, dev_max_params, dev_req_params);
case POST_CHANGE:
if (ufshcd_is_auto_hibern8_supported(hba))
- ufshcd_writel(hba, reg, REG_AUTO_HIBERNATE_IDLE_TIMER);
- break;
- default:
- ret = -EINVAL;
- break;
+ ufshcd_writel(hba, host->ahit,
+ REG_AUTO_HIBERNATE_IDLE_TIMER);
+ return 0;
}
- return ret;
+ return -EINVAL;
}
static int ufs_mtk_unipro_set_lpm(struct ufs_hba *hba, bool lpm)
diff --git a/drivers/ufs/host/ufs-mediatek.h b/drivers/ufs/host/ufs-mediatek.h
index fa27ab4d6d6c..2349d9b9375c 100644
--- a/drivers/ufs/host/ufs-mediatek.h
+++ b/drivers/ufs/host/ufs-mediatek.h
@@ -187,6 +187,7 @@ struct ufs_mtk_host {
u16 ref_clk_gating_wait_us;
u32 ip_ver;
bool legacy_ip_ver;
+ u32 ahit;
bool mcq_set_intr;
bool is_mcq_intr_enabled;
--
2.53.0
--
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https://lists.infradead.org/mailman/listinfo/linux-phy
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* [PATCH v9 23/23] scsi: ufs: mediatek: Add MT8196 compatible, update copyright
From: Nicolas Frattaroli @ 2026-03-06 13:25 UTC (permalink / raw)
To: Alim Akhtar, Avri Altman, Bart Van Assche, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chunfeng Yun, Vinod Koul,
Kishon Vijay Abraham I, Peter Wang, Stanley Jhu,
James E.J. Bottomley, Martin K. Petersen, Philipp Zabel,
Liam Girdwood, Mark Brown, Chaotian Jing, Neil Armstrong
Cc: Louis-Alexis Eyraud, kernel, linux-scsi, devicetree, linux-kernel,
linux-arm-kernel, linux-mediatek, linux-phy, Nicolas Frattaroli
In-Reply-To: <20260306-mt8196-ufs-v9-0-55b073f7a830@collabora.com>
THe MT8196's UFS controller has a new compatible. Add the necessary
struct definitions to support it.
Also update the copyrights and authors, without tabs following spaces to
avoid checkpatch errors, to list myself as having contributed to this
driver after the preceding rework patches.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Peter Wang <peter.wang@mediatek.com>
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
drivers/ufs/host/ufs-mediatek.c | 17 +++++++++++++++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index 1dfc299b93b5..cc9357e90958 100644
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -1,9 +1,11 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 MediaTek Inc.
+ * Copyright (C) 2025 Collabora Ltd.
* Authors:
- * Stanley Chu <stanley.chu@mediatek.com>
- * Peter Wang <peter.wang@mediatek.com>
+ * Stanley Chu <stanley.chu@mediatek.com>
+ * Peter Wang <peter.wang@mediatek.com>
+ * Nicolas Frattaroli <nicolas.frattaroli@collabora.com> (Major cleanups)
*/
#include <linux/arm-smccc.h>
@@ -2200,6 +2202,10 @@ static const char *const ufs_mtk_regs_avdd12_ckbuf_avdd18[] = {
"avdd12", "avdd12-ckbuf", "avdd18"
};
+static const char *const ufs_mtk_regs_avdd12_ckbuf[] = {
+ "avdd12", "avdd12-ckbuf"
+};
+
static const struct ufs_mtk_soc_data mt8183_data = {
.has_avdd09 = true,
.reg_names = ufs_mtk_regs_avdd12_avdd18,
@@ -2212,10 +2218,17 @@ static const struct ufs_mtk_soc_data mt8192_8195_data = {
.num_reg_names = ARRAY_SIZE(ufs_mtk_regs_avdd12_ckbuf_avdd18),
};
+static const struct ufs_mtk_soc_data mt8196_data = {
+ .has_avdd09 = true,
+ .reg_names = ufs_mtk_regs_avdd12_ckbuf,
+ .num_reg_names = ARRAY_SIZE(ufs_mtk_regs_avdd12_ckbuf),
+};
+
static const struct of_device_id ufs_mtk_of_match[] = {
{ .compatible = "mediatek,mt8183-ufshci", .data = &mt8183_data },
{ .compatible = "mediatek,mt8192-ufshci", .data = &mt8192_8195_data },
{ .compatible = "mediatek,mt8195-ufshci", .data = &mt8192_8195_data },
+ { .compatible = "mediatek,mt8196-ufshci", .data = &mt8196_data },
{},
};
MODULE_DEVICE_TABLE(of, ufs_mtk_of_match);
--
2.53.0
--
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* [PATCH v8] phy: Add generic PHY driver used by MACB/GEM on EyeQ5
From: Théo Lebrun @ 2026-03-06 14:29 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong
Cc: linux-phy, linux-kernel, linux-mips, Vladimir Kondratiev,
Gregory CLEMENT, Benoît Monin, Tawfik Bayouk,
Thomas Petazzoni, Luca Ceresoli, Théo Lebrun
EyeQ5 SoCs integrate two GEM instances. A system-controller register
region named "OLB" has some control over the Ethernet PHY integration.
Extend the current OLB ecosystem with a new generic PHY driver.
- OLB is carried by one main platform driver: clk-eyeq.
- It instantiates auxiliary devices: reset-eyeq & pinctrl-eyeq5.
- We add a new one: phy-eyeq5-eth.
About related patches:
- The MACB series [1] has been merged in v6.19-rc1. It makes MACB
consume a generic PHY from devicetree with the EyeQ5 compatible.
- clk patches are on the lkml [3]; they make clk-eyeq instantiate this
new auxiliary device. They also ensure we get a dev->of_node
assigned. Patches used to be [2] in the same series.
- MIPS patches are on the lkml [4]; they add MACB/GEM instances in
devicetree and their associated PHYs. They also update dt-bindings
to reflect this new feature OLB provides. Patches used to be [2] in
the same series.
Have a nice day,
Thanks!
Théo
[0]: https://lore.kernel.org/lkml/20250627-macb-v2-15-ff8207d0bb77@bootlin.com/
[1]: https://lore.kernel.org/lkml/20251022-macb-eyeq5-v2-0-7c140abb0581@bootlin.com/
[2]: https://lore.kernel.org/all/20260127-macb-phy-v6-0-cdd840588188@bootlin.com/
[3]: https://lore.kernel.org/all/20260225-macb-phy-v7-0-665bd8619d51@bootlin.com/
[4]: https://lore.kernel.org/all/20260225-macb-phy-v7-0-d3c9842ec931@bootlin.com/
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
---
Changes in v8:
- Rebase upon linux-phy/next. Drop sorting Kconfig/Makefile patch
because one exists upstream.
- Instead of storing a phy_interface_t to know which submode to target,
store a custom enum with two states (RGMII/SGMII). Ignore RGMII
timings in this generic PHY driver because they are handled by the
net PHY.
- eq5_phy_set_mode() calls into eq5_phy_validate() and now propagates
its error return value. Previously it shadowed EINVAL with EOPNOTSUPP.
- Link to v7: https://lore.kernel.org/r/20260225-macb-phy-v7-0-e5211a61db56@bootlin.com
Changes in v7:
- Separate PHY / clk / MIPS patches into three series.
- Implement phy_validate().
- phy_power_on() now supports being called without a prior
phy_set_mode() because at probe we read the hardware state to
initialise inst->phy_instance.
- phy_set_mode() now support being called while the PHY is powered on.
- Add sgmii_support bool for each PHY instance to reject SGMII
configuration on PHY 1 which only supports RGMII.
- Drop dev_dbg() calls.
- Drop readl(gp) in phy_init().
- Replace inst->priv field by inst->dev; that is the only value we need
from the driver private data. Drop priv->dev field that is unused.
- Call into phy_exit() from phy_init() as the sequence is the same.
Add comment to explain the reasoning.
- Take Reviewed-by: Luca on "phy: sort Kconfig and Makefile".
- Rebase onto v7.0-rc1 and test on EyeQ5. Only diff to report:
PHY_COMMON_PROPS and PHY_COMMON_PROPS_TEST are kept at the top in the
sorting patch; we do not strictly respect an alphabetical ordering.
- Link to v6: https://lore.kernel.org/r/20260127-macb-phy-v6-0-cdd840588188@bootlin.com
Changes in v6:
- Rebase upon v6.19-rc7; nothing to report.
- Add new patch "phy: sort Kconfig and Makefile".
- phy-eyeq5-eth: drop useless explicit __iomem cast to
dev_get_platdata() return value.
- I did *not* drop the Kconfig `default MACH_EYEQ5` nor driver
`dev_dbg()`. I think both are useful and should be kept. See
last revision discussion here:
https://lore.kernel.org/lkml/DFGSMN8268O0.33TYCQDBVHUHZ@bootlin.com/
- Link to v5: https://lore.kernel.org/r/20251215-macb-phy-v5-0-a9dfea39da34@bootlin.com
Changes in v5:
- phy-eyeq5-eth:
- fix #includes: add delay, gfp_types, module and drop array_size,
bug, cleanup, container_of, lockdep, mutex.
- eq5_phy_xlate(): avoid magic value, use EQ5_PHY_COUNT.
- use dev_err_probe() in error cases of devm_phy_create() and
devm_of_phy_provider_register().
- 3x Reviewed-by: Luca Ceresoli.
- Add Neil Armstrong to Cc as new PHY subsystem reviewer.
- Rebase on v6.19-rc1, tested on hardware, no changes.
- Link to v4: https://lore.kernel.org/r/20251124-macb-phy-v4-0-955c625a81a7@bootlin.com
Changes in v4:
- Append my SoB to Jerome's patch:
[PATCH v4 3/7] clk: eyeq: use the auxiliary device creation helper
- Rebase on net-next & linux-{clk,mips,phy}. Nothing to report.
- Link to v3: https://lore.kernel.org/r/20251119-macb-phy-v3-0-e9a7be186a33@bootlin.com
Changes in v3:
- Take Philipp Zabel's Reviewed-by & Acked-by trailers on reset patch.
- Take Thomas Bogendoerfer's two Acked-by trailers on DT patches.
- Rebase on net-next & test on target. Nothing to report.
- Link to v2: https://lore.kernel.org/r/20251101-macb-phy-v2-0-c1519eef16d3@bootlin.com
Changes in v2:
- Take Acked-by: Conor Dooley on dt-bindings-patch.
- s/%ld/%tu/ for printing ptrdiff_t; warnings on 32-bit archs.
Reported by NIPA's netdev/build_32bit test.
https://patchwork.kernel.org/project/netdevbpf/patch/20251021-macb-eyeq5-v1-7-3b0b5a9d2f85@bootlin.com/
https://netdev.bots.linux.dev/static/nipa/1014126/14277857/build_32bit/stderr
- Link to v1: https://lore.kernel.org/r/20251022-macb-phy-v1-0-f29f28fae721@bootlin.com
Changes since MACB V1:
- Drop the old "mobileye,olb" properties from DT patches; found while
running dtbs_check and dt_binding_check.
- Drop all patches targeting net-next. That is MACB dt-bindings patch
and MACB driver code. See there here [1].
- Link to v1: https://lore.kernel.org/lkml/20251021-macb-eyeq5-v1-0-3b0b5a9d2f85@bootlin.com/
Past versions of MACB patches:
- March 2025: [PATCH net-next 00/13] Support the Cadence MACB/GEM
instances on Mobileye EyeQ5 SoCs
https://lore.kernel.org/lkml/20250321-macb-v1-0-537b7e37971d@bootlin.com/
- June 2025: [PATCH net-next v2 00/18] Support the Cadence MACB/GEM
instances on Mobileye EyeQ5 SoCs
https://lore.kernel.org/lkml/20250627-macb-v2-0-ff8207d0bb77@bootlin.com/
- August 2025: [PATCH net v3 00/16] net: macb: various fixes & cleanup
https://lore.kernel.org/lkml/20250808-macb-fixes-v3-0-08f1fcb5179f@bootlin.com/
---
Théo Lebrun (1):
phy: Add driver for EyeQ5 Ethernet PHY wrapper
MAINTAINERS | 1 +
drivers/phy/Kconfig | 13 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-eyeq5-eth.c | 280 ++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 295 insertions(+)
---
base-commit: caf08514bbee0736c31d8d4f406e3415cdf726bb
change-id: 20251022-macb-phy-21bc4e1dfbb7
Best regards,
--
Théo Lebrun <theo.lebrun@bootlin.com>
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* [PATCH v8] phy: Add driver for EyeQ5 Ethernet PHY wrapper
From: Théo Lebrun @ 2026-03-06 14:29 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong
Cc: linux-phy, linux-kernel, linux-mips, Vladimir Kondratiev,
Gregory CLEMENT, Benoît Monin, Tawfik Bayouk,
Thomas Petazzoni, Luca Ceresoli, Théo Lebrun
In-Reply-To: <20260306-macb-phy-v8-0-b5c48ee61402@bootlin.com>
EyeQ5 embeds a system-controller called OLB. It features many unrelated
registers, and some of those are registers used to configure the
integration of the RGMII/SGMII Cadence PHY used by MACB/GEM instances.
Wrap in a neat generic PHY provider, exposing two PHYs with standard
phy_init() / phy_set_mode() / phy_power_on() operations.
Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
---
MAINTAINERS | 1 +
drivers/phy/Kconfig | 13 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-eyeq5-eth.c | 280 ++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 295 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 55af015174a5..6bc2ae3bbd4b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17812,6 +17812,7 @@ F: arch/mips/boot/dts/mobileye/
F: arch/mips/configs/eyeq5_defconfig
F: arch/mips/mobileye/board-epm5.its.S
F: drivers/clk/clk-eyeq.c
+F: drivers/phy/phy-eyeq5-eth.c
F: drivers/pinctrl/pinctrl-eyeq5.c
F: drivers/reset/reset-eyeq.c
F: include/dt-bindings/clock/mobileye,eyeq5-clk.h
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 3970aa1f300f..cb973a5c0d28 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -67,6 +67,19 @@ config PHY_CAN_TRANSCEIVER
functional modes using gpios and sets the attribute max link
rate, for CAN drivers.
+config PHY_EYEQ5_ETH
+ tristate "Ethernet PHY Driver on EyeQ5"
+ depends on OF
+ depends on MACH_EYEQ5 || COMPILE_TEST
+ select AUXILIARY_BUS
+ select GENERIC_PHY
+ default MACH_EYEQ5
+ help
+ Enable this to support the Ethernet PHY integrated on EyeQ5.
+ It supports both RGMII and SGMII. Registers are located in a
+ shared register region called OLB. If M is selected, the
+ module will be called phy-eyeq5-eth.
+
config PHY_GOOGLE_USB
tristate "Google Tensor SoC USB PHY driver"
select GENERIC_PHY
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index f49d83f00a3d..05be5759cd10 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_GENERIC_PHY) += phy-core.o
obj-$(CONFIG_GENERIC_PHY_MIPI_DPHY) += phy-core-mipi-dphy.o
obj-$(CONFIG_PHY_AIROHA_PCIE) += phy-airoha-pcie.o
obj-$(CONFIG_PHY_CAN_TRANSCEIVER) += phy-can-transceiver.o
+obj-$(CONFIG_PHY_EYEQ5_ETH) += phy-eyeq5-eth.o
obj-$(CONFIG_PHY_GOOGLE_USB) += phy-google-usb.o
obj-$(CONFIG_USB_LGM_PHY) += phy-lgm-usb.o
obj-$(CONFIG_PHY_LPC18XX_USB_OTG) += phy-lpc18xx-usb-otg.o
diff --git a/drivers/phy/phy-eyeq5-eth.c b/drivers/phy/phy-eyeq5-eth.c
new file mode 100644
index 000000000000..a5ba1bf8c475
--- /dev/null
+++ b/drivers/phy/phy-eyeq5-eth.c
@@ -0,0 +1,280 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <linux/auxiliary_bus.h>
+#include <linux/bitfield.h>
+#include <linux/bits.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/gfp_types.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/phy.h>
+#include <linux/phy/phy.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+
+#define EQ5_PHY_COUNT 2
+
+#define EQ5_PHY0_GP 0x128
+#define EQ5_PHY1_GP 0x12c
+#define EQ5_PHY0_SGMII 0x134
+#define EQ5_PHY1_SGMII 0x138
+
+#define EQ5_GP_TX_SWRST_DIS BIT(0) // Tx SW reset
+#define EQ5_GP_TX_M_CLKE BIT(1) // Tx M clock enable
+#define EQ5_GP_SYS_SWRST_DIS BIT(2) // Sys SW reset
+#define EQ5_GP_SYS_M_CLKE BIT(3) // Sys clock enable
+#define EQ5_GP_SGMII_MODE BIT(4) // SGMII mode
+#define EQ5_GP_RGMII_DRV GENMASK(8, 5) // RGMII drive strength
+
+#define EQ5_SGMII_PWR_EN BIT(0)
+#define EQ5_SGMII_RST_DIS BIT(1)
+#define EQ5_SGMII_PLL_EN BIT(2)
+#define EQ5_SGMII_SIG_DET_SW BIT(3)
+#define EQ5_SGMII_PWR_STATE BIT(4)
+#define EQ5_SGMII_PLL_ACK BIT(18)
+#define EQ5_SGMII_PWR_STATE_ACK GENMASK(24, 20)
+
+/*
+ * Instead of storing a phy_interface_t, we store this enum.
+ *
+ * We do not deal with RGMII timings in this generic PHY driver,
+ * it is all handled inside the net PHY.
+ */
+enum eq5_phy_submode {
+ EQ5_PHY_SUBMODE_SGMII,
+ EQ5_PHY_SUBMODE_RGMII,
+};
+
+struct eq5_phy_inst {
+ struct device *dev;
+ struct phy *phy;
+ void __iomem *gp, *sgmii;
+ enum eq5_phy_submode submode;
+ bool sgmii_support;
+};
+
+struct eq5_phy_private {
+ struct eq5_phy_inst phys[EQ5_PHY_COUNT];
+};
+
+static int eq5_phy_exit(struct phy *phy)
+{
+ struct eq5_phy_inst *inst = phy_get_drvdata(phy);
+
+ writel(0, inst->gp);
+ writel(0, inst->sgmii);
+ udelay(5); /* settling time */
+ return 0;
+}
+
+static int eq5_phy_init(struct phy *phy)
+{
+ struct eq5_phy_inst *inst = phy_get_drvdata(phy);
+ u32 reg;
+
+ /*
+ * Hardware stops listening to our instructions once it is started.
+ * It must be reset to reconfigure it.
+ */
+ eq5_phy_exit(phy);
+
+ reg = EQ5_GP_TX_SWRST_DIS | EQ5_GP_TX_M_CLKE |
+ EQ5_GP_SYS_SWRST_DIS | EQ5_GP_SYS_M_CLKE |
+ FIELD_PREP(EQ5_GP_RGMII_DRV, 0x9);
+ writel(reg, inst->gp);
+
+ return 0;
+}
+
+static int eq5_phy_power_on(struct phy *phy)
+{
+ struct eq5_phy_inst *inst = phy_get_drvdata(phy);
+ u32 reg;
+
+ if (inst->submode == EQ5_PHY_SUBMODE_SGMII) {
+ writel(readl(inst->gp) | EQ5_GP_SGMII_MODE, inst->gp);
+
+ reg = EQ5_SGMII_PWR_EN | EQ5_SGMII_RST_DIS | EQ5_SGMII_PLL_EN;
+ writel(reg, inst->sgmii);
+
+ if (readl_poll_timeout(inst->sgmii, reg,
+ reg & EQ5_SGMII_PLL_ACK, 1, 100)) {
+ dev_err(inst->dev, "PLL timeout\n");
+ return -ETIMEDOUT;
+ }
+
+ reg = readl(inst->sgmii);
+ reg |= EQ5_SGMII_PWR_STATE | EQ5_SGMII_SIG_DET_SW;
+ writel(reg, inst->sgmii);
+ } else {
+ writel(readl(inst->gp) & ~EQ5_GP_SGMII_MODE, inst->gp);
+ writel(0, inst->sgmii);
+ }
+
+ return 0;
+}
+
+static int eq5_phy_power_off(struct phy *phy)
+{
+ struct eq5_phy_inst *inst = phy_get_drvdata(phy);
+
+ writel(readl(inst->gp) & ~EQ5_GP_SGMII_MODE, inst->gp);
+ writel(0, inst->sgmii);
+
+ return 0;
+}
+
+static int eq5_phy_validate(struct phy *phy, enum phy_mode mode, int submode,
+ union phy_configure_opts *opts)
+{
+ struct eq5_phy_inst *inst = phy_get_drvdata(phy);
+
+ if (mode != PHY_MODE_ETHERNET)
+ return -EINVAL;
+
+ if (phy_interface_mode_is_rgmii(submode))
+ return 0;
+
+ if (inst->sgmii_support && submode == PHY_INTERFACE_MODE_SGMII)
+ return 0;
+
+ return -EINVAL;
+}
+
+static int eq5_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
+{
+ struct eq5_phy_inst *inst = phy_get_drvdata(phy);
+ enum eq5_phy_submode target_submode;
+ int ret;
+
+ ret = eq5_phy_validate(phy, mode, submode, NULL);
+ if (ret)
+ return ret;
+
+ if (submode == PHY_INTERFACE_MODE_SGMII)
+ target_submode = EQ5_PHY_SUBMODE_SGMII;
+ else
+ target_submode = EQ5_PHY_SUBMODE_RGMII;
+
+ if (target_submode == inst->submode)
+ return 0;
+
+ inst->submode = target_submode;
+
+ if (phy->power_count) {
+ eq5_phy_init(phy);
+ return eq5_phy_power_on(phy);
+ }
+
+ return 0;
+}
+
+static const struct phy_ops eq5_phy_ops = {
+ .init = eq5_phy_init,
+ .exit = eq5_phy_exit,
+ .power_on = eq5_phy_power_on,
+ .power_off = eq5_phy_power_off,
+ .set_mode = eq5_phy_set_mode,
+ .validate = eq5_phy_validate,
+};
+
+static struct phy *eq5_phy_xlate(struct device *dev,
+ const struct of_phandle_args *args)
+{
+ struct eq5_phy_private *priv = dev_get_drvdata(dev);
+
+ if (args->args_count != 1 || args->args[0] >= EQ5_PHY_COUNT)
+ return ERR_PTR(-EINVAL);
+
+ return priv->phys[args->args[0]].phy;
+}
+
+static int eq5_phy_probe_phy(struct device *dev, struct eq5_phy_private *priv,
+ unsigned int index, void __iomem *base,
+ unsigned int gp, unsigned int sgmii,
+ bool sgmii_support)
+{
+ struct eq5_phy_inst *inst = &priv->phys[index];
+ struct phy *phy;
+
+ phy = devm_phy_create(dev, dev->of_node, &eq5_phy_ops);
+ if (IS_ERR(phy))
+ return dev_err_probe(dev, PTR_ERR(phy),
+ "failed to create PHY %u\n", index);
+
+ inst->dev = dev;
+ inst->phy = phy;
+ inst->gp = base + gp;
+ inst->sgmii = base + sgmii;
+ inst->sgmii_support = sgmii_support;
+ phy_set_drvdata(phy, inst);
+
+ /*
+ * Init inst->submode based on probe hardware state, allowing
+ * consumers to power us on without first setting the mode.
+ */
+ if (sgmii_support && (readl(inst->gp) & EQ5_GP_SGMII_MODE))
+ inst->submode = EQ5_PHY_SUBMODE_SGMII;
+ else
+ inst->submode = EQ5_PHY_SUBMODE_RGMII;
+
+ return 0;
+}
+
+static int eq5_phy_probe(struct auxiliary_device *adev,
+ const struct auxiliary_device_id *id)
+{
+ struct device *dev = &adev->dev;
+ struct phy_provider *provider;
+ struct eq5_phy_private *priv;
+ void __iomem *base;
+ int ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ dev_set_drvdata(dev, priv);
+
+ base = dev_get_platdata(dev);
+
+ ret = eq5_phy_probe_phy(dev, priv, 0, base, EQ5_PHY0_GP,
+ EQ5_PHY0_SGMII, true);
+ if (ret)
+ return ret;
+
+ ret = eq5_phy_probe_phy(dev, priv, 1, base, EQ5_PHY1_GP,
+ EQ5_PHY1_SGMII, false);
+ if (ret)
+ return ret;
+
+ provider = devm_of_phy_provider_register(dev, eq5_phy_xlate);
+ if (IS_ERR(provider))
+ return dev_err_probe(dev, PTR_ERR(provider),
+ "registering provider failed\n");
+
+ return 0;
+}
+
+static const struct auxiliary_device_id eq5_phy_id_table[] = {
+ { .name = "clk_eyeq.phy" },
+ {}
+};
+MODULE_DEVICE_TABLE(auxiliary, eq5_phy_id_table);
+
+static struct auxiliary_driver eq5_phy_driver = {
+ .probe = eq5_phy_probe,
+ .id_table = eq5_phy_id_table,
+};
+module_auxiliary_driver(eq5_phy_driver);
+
+MODULE_DESCRIPTION("EyeQ5 Ethernet PHY driver");
+MODULE_AUTHOR("Théo Lebrun <theo.lebrun@bootlin.com>");
+MODULE_LICENSE("GPL");
--
2.53.0
--
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https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* Re: [PATCH v11 1/9] phy: can-transceiver: rename temporary helper function to avoid conflict
From: Wolfram Sang @ 2026-03-06 15:30 UTC (permalink / raw)
To: Josua Mayer
Cc: Marc Kleine-Budde, Vincent Mailhol, Vinod Koul, Neil Armstrong,
Peter Rosin, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Janusz Krzysztofik, Vignesh R,
Andi Shyti, Ulf Hansson, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Geert Uytterhoeven, Magnus Damm, Yoshihiro Shimoda,
Yazan Shhady, Jon Nettleton, Vladimir Oltean, Mikhail Anikin,
linux-can, linux-phy, linux-kernel, linux-omap, linux-i2c,
linux-mmc, devicetree, linux-renesas-soc
In-Reply-To: <20260226-rz-sdio-mux-v11-1-c2a350f9bbd3@solid-run.com>
On Thu, Feb 26, 2026 at 03:21:09PM +0200, Josua Mayer wrote:
> Rename the temporary devm_mux_state_get_optional function to avoid
> conflict with upcoming implementation in multiplexer subsystem.
>
> Signed-off-by: Josua Mayer <josua@solid-run.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
--
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^ permalink raw reply
* Re: [PATCH v11 2/9] phy: renesas: rcar-gen3-usb2: rename local mux helper to avoid conflict
From: Wolfram Sang @ 2026-03-06 15:32 UTC (permalink / raw)
To: Josua Mayer
Cc: Marc Kleine-Budde, Vincent Mailhol, Vinod Koul, Neil Armstrong,
Peter Rosin, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Janusz Krzysztofik, Vignesh R,
Andi Shyti, Ulf Hansson, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Geert Uytterhoeven, Magnus Damm, Yoshihiro Shimoda,
Yazan Shhady, Jon Nettleton, Vladimir Oltean, Mikhail Anikin,
linux-can, linux-phy, linux-kernel, linux-omap, linux-i2c,
linux-mmc, devicetree, linux-renesas-soc
In-Reply-To: <20260226-rz-sdio-mux-v11-2-c2a350f9bbd3@solid-run.com>
On Thu, Feb 26, 2026 at 03:21:10PM +0200, Josua Mayer wrote:
> Rename the temporary devm_mux_state_get_optional function to avoid
> conflict with upcoming implementation in multiplexer subsystem.
>
> Signed-off-by: Josua Mayer <josua@solid-run.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
--
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^ permalink raw reply
* Re: [PATCH v11 5/9] phy: renesas: rcar-gen3-usb2: drop helper getting optional mux-state
From: Wolfram Sang @ 2026-03-06 15:33 UTC (permalink / raw)
To: Josua Mayer
Cc: Marc Kleine-Budde, Vincent Mailhol, Vinod Koul, Neil Armstrong,
Peter Rosin, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Janusz Krzysztofik, Vignesh R,
Andi Shyti, Ulf Hansson, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Geert Uytterhoeven, Magnus Damm, Yoshihiro Shimoda,
Yazan Shhady, Jon Nettleton, Vladimir Oltean, Mikhail Anikin,
linux-can, linux-phy, linux-kernel, linux-omap, linux-i2c,
linux-mmc, devicetree, linux-renesas-soc
In-Reply-To: <20260226-rz-sdio-mux-v11-5-c2a350f9bbd3@solid-run.com>
On Thu, Feb 26, 2026 at 03:21:13PM +0200, Josua Mayer wrote:
> Multiplexer subsystem has now added helpers for getting managed optional
> mux-state.
>
> Switch to the new devm_mux_state_get_optional_selected helper.
>
> This change is only compile-tested.
>
> Signed-off-by: Josua Mayer <josua@solid-run.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
--
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^ permalink raw reply
* Re: [PATCH v11 9/9] mmc: host: renesas_sdhi_core: support selecting an optional mux
From: Wolfram Sang @ 2026-03-06 15:33 UTC (permalink / raw)
To: Josua Mayer
Cc: Marc Kleine-Budde, Vincent Mailhol, Vinod Koul, Neil Armstrong,
Peter Rosin, Aaro Koskinen, Andreas Kemnade, Kevin Hilman,
Roger Quadros, Tony Lindgren, Janusz Krzysztofik, Vignesh R,
Andi Shyti, Ulf Hansson, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Geert Uytterhoeven, Magnus Damm, Yoshihiro Shimoda,
Yazan Shhady, Jon Nettleton, Vladimir Oltean, Mikhail Anikin,
linux-can, linux-phy, linux-kernel, linux-omap, linux-i2c,
linux-mmc, devicetree, linux-renesas-soc
In-Reply-To: <20260226-rz-sdio-mux-v11-9-c2a350f9bbd3@solid-run.com>
On Thu, Feb 26, 2026 at 03:21:17PM +0200, Josua Mayer wrote:
> Some hardware designs route data or control signals through a mux to
> support multiple devices on a single sdhi controller.
>
> In particular SolidRun RZ/G2L/G2LC/V2L System on Module use a mux for
> switching between soldered eMMC and an optional microSD on a carrier
> board, e.g. for development or provisioning.
>
> SD/SDIO/eMMC are not well suited for runtime switching between different
> cards, however boot-time selection is possible and useful - in
> particular considering dt overlays.
>
> Add support for an optional SD/SDIO/eMMC mux defined in dt, and select
> it during probe.
>
> Similar functionality already exists in other places, e.g. i2c-omap.
>
> Signed-off-by: Josua Mayer <josua@solid-run.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
--
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^ permalink raw reply
* [PATCH phy-next 20/22] phy: include PHY provider header
From: Vladimir Oltean @ 2026-03-04 17:57 UTC (permalink / raw)
To: linux-phy
Cc: Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-sunxi,
linux-tegra, linux-usb, netdev, spacemit, UNGLinuxDriver
In-Reply-To: <20260304175735.2660419-1-vladimir.oltean@nxp.com>
The majority of PHY drivers are PHY providers (obviously).
Some are providers *and* consumers (phy-meson-axg-mipi-dphy,
phy-meson-axg-pcie). These are the Amlogic AXG SoCs, which split the
physical layer into two chained PHYs: the digital layer and the analog
layer. The DSI or PCIe controller interacts only with the digital PHY,
presumably for simplicity.
The rest of PHY drivers which include <linux/phy/phy.h> do so because
they call phy_set_bus_width(), a consumer function.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
drivers/phy/allwinner/phy-sun4i-usb.c | 3 ++-
drivers/phy/allwinner/phy-sun50i-usb3.c | 3 ++-
drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 4 ++--
drivers/phy/allwinner/phy-sun9i-usb.c | 3 ++-
drivers/phy/amlogic/phy-meson-axg-mipi-dphy.c | 2 ++
drivers/phy/amlogic/phy-meson-axg-mipi-pcie-analog.c | 3 ++-
drivers/phy/amlogic/phy-meson-axg-pcie.c | 2 ++
drivers/phy/amlogic/phy-meson-g12a-mipi-dphy-analog.c | 3 ++-
drivers/phy/amlogic/phy-meson-g12a-usb2.c | 2 ++
drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c | 3 ++-
drivers/phy/amlogic/phy-meson-gxl-usb2.c | 3 ++-
drivers/phy/amlogic/phy-meson8-hdmi-tx.c | 3 ++-
drivers/phy/amlogic/phy-meson8b-usb2.c | 3 ++-
drivers/phy/apple/atc.c | 3 ++-
drivers/phy/broadcom/phy-bcm-cygnus-pcie.c | 3 ++-
drivers/phy/broadcom/phy-bcm-kona-usb2.c | 4 +++-
drivers/phy/broadcom/phy-bcm-ns-usb2.c | 3 ++-
drivers/phy/broadcom/phy-bcm-ns-usb3.c | 3 ++-
drivers/phy/broadcom/phy-bcm-ns2-pcie.c | 3 ++-
drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c | 3 ++-
drivers/phy/broadcom/phy-bcm-sr-pcie.c | 3 ++-
drivers/phy/broadcom/phy-bcm-sr-usb.c | 3 ++-
drivers/phy/broadcom/phy-bcm63xx-usbh.c | 3 ++-
drivers/phy/broadcom/phy-brcm-sata.c | 3 ++-
drivers/phy/broadcom/phy-brcm-usb.c | 2 +-
drivers/phy/cadence/cdns-dphy-rx.c | 3 ++-
drivers/phy/cadence/cdns-dphy.c | 4 ++--
drivers/phy/cadence/phy-cadence-salvo.c | 3 ++-
drivers/phy/cadence/phy-cadence-sierra.c | 3 ++-
drivers/phy/cadence/phy-cadence-torrent.c | 3 ++-
drivers/phy/canaan/phy-k230-usb.c | 3 ++-
drivers/phy/eswin/phy-eic7700-sata.c | 3 ++-
drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c | 3 ++-
drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 4 ++--
drivers/phy/freescale/phy-fsl-imx8mq-usb.c | 3 ++-
drivers/phy/freescale/phy-fsl-imx8qm-hsio.c | 6 +++---
drivers/phy/freescale/phy-fsl-imx8qm-lvds-phy.c | 3 ++-
drivers/phy/freescale/phy-fsl-lynx-28g.c | 3 ++-
drivers/phy/hisilicon/phy-hi3660-usb3.c | 3 ++-
drivers/phy/hisilicon/phy-hi3670-pcie.c | 3 ++-
drivers/phy/hisilicon/phy-hi3670-usb3.c | 3 ++-
drivers/phy/hisilicon/phy-hi6220-usb.c | 3 ++-
drivers/phy/hisilicon/phy-hisi-inno-usb2.c | 4 +++-
drivers/phy/hisilicon/phy-histb-combphy.c | 3 ++-
drivers/phy/hisilicon/phy-hix5hd2-sata.c | 3 ++-
drivers/phy/ingenic/phy-ingenic-usb.c | 3 ++-
drivers/phy/intel/phy-intel-keembay-emmc.c | 3 ++-
drivers/phy/intel/phy-intel-keembay-usb.c | 3 ++-
drivers/phy/intel/phy-intel-lgm-combo.c | 4 ++--
drivers/phy/intel/phy-intel-lgm-emmc.c | 3 ++-
drivers/phy/lantiq/phy-lantiq-rcu-usb2.c | 3 ++-
drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c | 4 ++--
drivers/phy/marvell/phy-armada375-usb2.c | 3 ++-
drivers/phy/marvell/phy-armada38x-comphy.c | 3 ++-
drivers/phy/marvell/phy-berlin-sata.c | 3 ++-
drivers/phy/marvell/phy-berlin-usb.c | 3 ++-
drivers/phy/marvell/phy-mmp3-hsic.c | 3 ++-
drivers/phy/marvell/phy-mmp3-usb.c | 3 ++-
drivers/phy/marvell/phy-mvebu-a3700-comphy.c | 3 ++-
drivers/phy/marvell/phy-mvebu-a3700-utmi.c | 3 ++-
drivers/phy/marvell/phy-mvebu-cp110-comphy.c | 3 ++-
drivers/phy/marvell/phy-mvebu-cp110-utmi.c | 3 ++-
drivers/phy/marvell/phy-mvebu-sata.c | 3 ++-
drivers/phy/marvell/phy-pxa-28nm-hsic.c | 3 ++-
drivers/phy/marvell/phy-pxa-28nm-usb2.c | 3 ++-
drivers/phy/marvell/phy-pxa-usb.c | 3 ++-
drivers/phy/mediatek/phy-mtk-dp.c | 3 ++-
drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c | 1 -
drivers/phy/mediatek/phy-mtk-hdmi.h | 3 ++-
drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c | 2 +-
drivers/phy/mediatek/phy-mtk-mipi-dsi.h | 3 ++-
drivers/phy/mediatek/phy-mtk-pcie.c | 2 +-
drivers/phy/mediatek/phy-mtk-tphy.c | 2 +-
drivers/phy/mediatek/phy-mtk-ufs.c | 2 +-
drivers/phy/mediatek/phy-mtk-xfi-tphy.c | 2 +-
drivers/phy/mediatek/phy-mtk-xsphy.c | 2 +-
drivers/phy/microchip/lan966x_serdes.c | 4 ++--
drivers/phy/microchip/sparx5_serdes.c | 2 +-
drivers/phy/motorola/phy-cpcap-usb.c | 3 ++-
drivers/phy/motorola/phy-mapphone-mdm6600.c | 4 +++-
drivers/phy/mscc/phy-ocelot-serdes.c | 3 ++-
drivers/phy/nuvoton/phy-ma35d1-usb2.c | 3 ++-
drivers/phy/phy-airoha-pcie.c | 2 +-
drivers/phy/phy-can-transceiver.c | 3 ++-
drivers/phy/phy-core-mipi-dphy.c | 4 ++--
drivers/phy/phy-core.c | 2 ++
drivers/phy/phy-google-usb.c | 3 ++-
drivers/phy/phy-lpc18xx-usb-otg.c | 3 ++-
drivers/phy/phy-nxp-ptn3222.c | 3 ++-
drivers/phy/phy-pistachio-usb.c | 4 ++--
drivers/phy/phy-snps-eusb2.c | 2 ++
drivers/phy/phy-xgene.c | 3 ++-
drivers/phy/qualcomm/phy-ath79-usb.c | 3 ++-
drivers/phy/qualcomm/phy-qcom-apq8064-sata.c | 3 ++-
drivers/phy/qualcomm/phy-qcom-edp.c | 3 ++-
drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c | 3 ++-
drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c | 3 ++-
drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c | 3 ++-
drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c | 3 ++-
drivers/phy/qualcomm/phy-qcom-m31-eusb2.c | 2 ++
drivers/phy/qualcomm/phy-qcom-m31.c | 3 ++-
drivers/phy/qualcomm/phy-qcom-pcie2.c | 3 ++-
drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 3 ++-
drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 3 ++-
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 3 ++-
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 3 ++-
drivers/phy/qualcomm/phy-qcom-qmp-usb-legacy.c | 3 ++-
drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 3 ++-
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 3 ++-
drivers/phy/qualcomm/phy-qcom-qusb2.c | 4 ++--
drivers/phy/qualcomm/phy-qcom-sgmii-eth.c | 3 ++-
drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c | 3 ++-
drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c | 3 ++-
drivers/phy/qualcomm/phy-qcom-usb-hs-28nm.c | 3 ++-
drivers/phy/qualcomm/phy-qcom-usb-hs.c | 3 ++-
drivers/phy/qualcomm/phy-qcom-usb-hsic.c | 3 ++-
drivers/phy/qualcomm/phy-qcom-usb-ss.c | 3 ++-
drivers/phy/ralink/phy-mt7621-pci.c | 3 ++-
drivers/phy/ralink/phy-ralink-usb.c | 3 ++-
drivers/phy/realtek/phy-rtk-usb2.c | 3 ++-
drivers/phy/realtek/phy-rtk-usb3.c | 3 ++-
drivers/phy/renesas/phy-rcar-gen2.c | 3 ++-
drivers/phy/renesas/phy-rcar-gen3-pcie.c | 3 ++-
drivers/phy/renesas/phy-rcar-gen3-usb2.c | 3 ++-
drivers/phy/renesas/phy-rcar-gen3-usb3.c | 3 ++-
drivers/phy/renesas/phy-rzg3e-usb3.c | 3 ++-
drivers/phy/renesas/r8a779f0-ether-serdes.c | 3 ++-
drivers/phy/rockchip/phy-rockchip-dp.c | 3 ++-
drivers/phy/rockchip/phy-rockchip-dphy-rx0.c | 3 ++-
drivers/phy/rockchip/phy-rockchip-emmc.c | 3 ++-
drivers/phy/rockchip/phy-rockchip-inno-csidphy.c | 3 ++-
drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c | 4 ++--
drivers/phy/rockchip/phy-rockchip-inno-hdmi.c | 2 ++
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 3 ++-
drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 3 ++-
drivers/phy/rockchip/phy-rockchip-pcie.c | 2 +-
drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c | 3 ++-
drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 2 ++
drivers/phy/rockchip/phy-rockchip-snps-pcie3.c | 3 ++-
drivers/phy/rockchip/phy-rockchip-typec.c | 4 ++--
drivers/phy/rockchip/phy-rockchip-usb.c | 3 ++-
drivers/phy/rockchip/phy-rockchip-usbdp.c | 2 ++
drivers/phy/samsung/phy-exynos-dp-video.c | 3 ++-
drivers/phy/samsung/phy-exynos-mipi-video.c | 3 ++-
drivers/phy/samsung/phy-exynos-pcie.c | 3 ++-
drivers/phy/samsung/phy-exynos4210-usb2.c | 3 ++-
drivers/phy/samsung/phy-exynos4x12-usb2.c | 3 ++-
drivers/phy/samsung/phy-exynos5-usbdrd.c | 2 ++
drivers/phy/samsung/phy-exynos5250-sata.c | 3 ++-
drivers/phy/samsung/phy-exynos5250-usb2.c | 3 ++-
drivers/phy/samsung/phy-s5pv210-usb2.c | 3 ++-
drivers/phy/samsung/phy-samsung-ufs.c | 2 +-
drivers/phy/samsung/phy-samsung-ufs.h | 3 ++-
drivers/phy/samsung/phy-samsung-usb2.c | 2 ++
drivers/phy/samsung/phy-samsung-usb2.h | 3 ++-
drivers/phy/socionext/phy-uniphier-ahci.c | 3 ++-
drivers/phy/socionext/phy-uniphier-pcie.c | 3 ++-
drivers/phy/socionext/phy-uniphier-usb2.c | 3 ++-
drivers/phy/socionext/phy-uniphier-usb3hs.c | 3 ++-
drivers/phy/socionext/phy-uniphier-usb3ss.c | 3 ++-
drivers/phy/sophgo/phy-cv1800-usb2.c | 3 ++-
drivers/phy/spacemit/phy-k1-pcie.c | 4 ++--
drivers/phy/spacemit/phy-k1-usb2.c | 3 ++-
drivers/phy/st/phy-miphy28lp.c | 4 ++--
drivers/phy/st/phy-spear1310-miphy.c | 3 ++-
drivers/phy/st/phy-spear1340-miphy.c | 3 ++-
drivers/phy/st/phy-stih407-usb.c | 3 ++-
drivers/phy/st/phy-stm32-combophy.c | 3 ++-
drivers/phy/st/phy-stm32-usbphyc.c | 2 ++
drivers/phy/starfive/phy-jh7110-dphy-rx.c | 3 ++-
drivers/phy/starfive/phy-jh7110-dphy-tx.c | 3 ++-
drivers/phy/starfive/phy-jh7110-pcie.c | 3 ++-
drivers/phy/starfive/phy-jh7110-usb.c | 3 ++-
drivers/phy/sunplus/phy-sunplus-usb2.c | 3 ++-
drivers/phy/tegra/phy-tegra194-p2u.c | 3 ++-
drivers/phy/tegra/xusb-tegra124.c | 2 +-
drivers/phy/tegra/xusb-tegra186.c | 2 +-
drivers/phy/tegra/xusb-tegra210.c | 2 +-
drivers/phy/tegra/xusb.c | 2 +-
drivers/phy/ti/phy-am654-serdes.c | 3 ++-
drivers/phy/ti/phy-da8xx-usb.c | 3 ++-
drivers/phy/ti/phy-dm816x-usb.c | 3 ++-
drivers/phy/ti/phy-gmii-sel.c | 3 ++-
drivers/phy/ti/phy-omap-usb2.c | 3 ++-
drivers/phy/ti/phy-ti-pipe3.c | 3 ++-
drivers/phy/ti/phy-twl4030-usb.c | 3 ++-
drivers/phy/xilinx/phy-zynqmp.c | 4 ++--
include/linux/phy/phy-sun4i-usb.h | 2 +-
include/linux/phy/ulpi_phy.h | 2 +-
189 files changed, 363 insertions(+), 193 deletions(-)
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
index e2fbf8ccf99e..9a03b5944b98 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -23,7 +23,6 @@
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/phy/phy-sun4i-usb.h>
#include <linux/platform_device.h>
#include <linux/power_supply.h>
@@ -33,6 +32,8 @@
#include <linux/usb/of.h>
#include <linux/workqueue.h>
+#include "../phy-provider.h"
+
#define REG_ISCR 0x00
#define REG_PHYCTL_A10 0x04
#define REG_PHYBIST 0x08
diff --git a/drivers/phy/allwinner/phy-sun50i-usb3.c b/drivers/phy/allwinner/phy-sun50i-usb3.c
index 363f9a0df503..d38b26e4bf95 100644
--- a/drivers/phy/allwinner/phy-sun50i-usb3.c
+++ b/drivers/phy/allwinner/phy-sun50i-usb3.c
@@ -18,10 +18,11 @@
#include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
+#include "../phy-provider.h"
+
/* Interface Status and Control Registers */
#define SUNXI_ISCR 0x00
#define SUNXI_PIPE_CLOCK_CONTROL 0x14
diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
index 36eab95271b2..e96162d078eb 100644
--- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
+++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
@@ -10,12 +10,12 @@
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/of_address.h>
+#include <linux/phy/phy-mipi-dphy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset.h>
-#include <linux/phy/phy.h>
-#include <linux/phy/phy-mipi-dphy.h>
+#include "../phy-provider.h"
#define SUN6I_DPHY_GCTL_REG 0x00
#define SUN6I_DPHY_GCTL_LANE_NUM(n) ((((n) - 1) & 3) << 4)
diff --git a/drivers/phy/allwinner/phy-sun9i-usb.c b/drivers/phy/allwinner/phy-sun9i-usb.c
index 2f9e60c188b8..f667f3f4b307 100644
--- a/drivers/phy/allwinner/phy-sun9i-usb.c
+++ b/drivers/phy/allwinner/phy-sun9i-usb.c
@@ -15,11 +15,12 @@
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
-#include <linux/phy/phy.h>
#include <linux/usb/of.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
+#include "../phy-provider.h"
+
#define SUNXI_AHB_INCR16_BURST_EN BIT(11)
#define SUNXI_AHB_INCR8_BURST_EN BIT(10)
#define SUNXI_AHB_INCR4_BURST_EN BIT(9)
diff --git a/drivers/phy/amlogic/phy-meson-axg-mipi-dphy.c b/drivers/phy/amlogic/phy-meson-axg-mipi-dphy.c
index c4a56b9d3289..60d17973a38f 100644
--- a/drivers/phy/amlogic/phy-meson-axg-mipi-dphy.c
+++ b/drivers/phy/amlogic/phy-meson-axg-mipi-dphy.c
@@ -20,6 +20,8 @@
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
+#include "../phy-provider.h"
+
/* [31] soft reset for the phy.
* 1: reset. 0: dessert the reset.
* [30] clock lane soft reset.
diff --git a/drivers/phy/amlogic/phy-meson-axg-mipi-pcie-analog.c b/drivers/phy/amlogic/phy-meson-axg-mipi-pcie-analog.c
index c0ba2852dbb8..21e8e2a5563a 100644
--- a/drivers/phy/amlogic/phy-meson-axg-mipi-pcie-analog.c
+++ b/drivers/phy/amlogic/phy-meson-axg-mipi-pcie-analog.c
@@ -7,7 +7,6 @@
#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/module.h>
-#include <linux/phy/phy.h>
#include <linux/regmap.h>
#include <linux/delay.h>
#include <linux/mfd/syscon.h>
@@ -15,6 +14,8 @@
#include <linux/platform_device.h>
#include <dt-bindings/phy/phy.h>
+#include "../phy-provider.h"
+
#define HHI_MIPI_CNTL0 0x00
#define HHI_MIPI_CNTL0_COMMON_BLOCK GENMASK(31, 28)
#define HHI_MIPI_CNTL0_ENABLE BIT(29)
diff --git a/drivers/phy/amlogic/phy-meson-axg-pcie.c b/drivers/phy/amlogic/phy-meson-axg-pcie.c
index 14dee73f9cb5..c4d9faf3a805 100644
--- a/drivers/phy/amlogic/phy-meson-axg-pcie.c
+++ b/drivers/phy/amlogic/phy-meson-axg-pcie.c
@@ -13,6 +13,8 @@
#include <linux/bitfield.h>
#include <dt-bindings/phy/phy.h>
+#include "../phy-provider.h"
+
#define MESON_PCIE_REG0 0x00
#define MESON_PCIE_COMMON_CLK BIT(4)
#define MESON_PCIE_PORT_SEL GENMASK(3, 2)
diff --git a/drivers/phy/amlogic/phy-meson-g12a-mipi-dphy-analog.c b/drivers/phy/amlogic/phy-meson-g12a-mipi-dphy-analog.c
index 46e5f7e7eb6c..11626f4528dd 100644
--- a/drivers/phy/amlogic/phy-meson-g12a-mipi-dphy-analog.c
+++ b/drivers/phy/amlogic/phy-meson-g12a-mipi-dphy-analog.c
@@ -9,7 +9,6 @@
#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/module.h>
-#include <linux/phy/phy.h>
#include <linux/regmap.h>
#include <linux/delay.h>
#include <linux/mfd/syscon.h>
@@ -17,6 +16,8 @@
#include <linux/platform_device.h>
#include <dt-bindings/phy/phy.h>
+#include "../phy-provider.h"
+
#define HHI_MIPI_CNTL0 0x00
#define HHI_MIPI_CNTL0_DIF_REF_CTL1 GENMASK(31, 16)
#define HHI_MIPI_CNTL0_DIF_REF_CTL0 GENMASK(15, 0)
diff --git a/drivers/phy/amlogic/phy-meson-g12a-usb2.c b/drivers/phy/amlogic/phy-meson-g12a-usb2.c
index 66bf0b7ef8ed..6e599b933153 100644
--- a/drivers/phy/amlogic/phy-meson-g12a-usb2.c
+++ b/drivers/phy/amlogic/phy-meson-g12a-usb2.c
@@ -20,6 +20,8 @@
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
+#include "../phy-provider.h"
+
#define PHY_CTRL_R0 0x0
#define PHY_CTRL_R1 0x4
#define PHY_CTRL_R2 0x8
diff --git a/drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c b/drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c
index 5468831d6ab9..60e9c3c1c449 100644
--- a/drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c
+++ b/drivers/phy/amlogic/phy-meson-g12a-usb3-pcie.c
@@ -12,12 +12,13 @@
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/platform_device.h>
#include <dt-bindings/phy/phy.h>
+#include "../phy-provider.h"
+
#define PHY_R0 0x00
#define PHY_R0_PCIE_POWER_STATE GENMASK(4, 0)
#define PHY_R0_PCIE_USB3_SWITCH GENMASK(6, 5)
diff --git a/drivers/phy/amlogic/phy-meson-gxl-usb2.c b/drivers/phy/amlogic/phy-meson-gxl-usb2.c
index 6b390304f723..b8d5b12cffc8 100644
--- a/drivers/phy/amlogic/phy-meson-gxl-usb2.c
+++ b/drivers/phy/amlogic/phy-meson-gxl-usb2.c
@@ -12,9 +12,10 @@
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/reset.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
+#include "../phy-provider.h"
+
/* bits [31:27] are read-only */
#define U2P_R0 0x0
#define U2P_R0_BYPASS_SEL BIT(0)
diff --git a/drivers/phy/amlogic/phy-meson8-hdmi-tx.c b/drivers/phy/amlogic/phy-meson8-hdmi-tx.c
index 2617f7f6c2ec..2a8c93dcda7e 100644
--- a/drivers/phy/amlogic/phy-meson8-hdmi-tx.c
+++ b/drivers/phy/amlogic/phy-meson8-hdmi-tx.c
@@ -11,11 +11,12 @@
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/regmap.h>
+#include "../phy-provider.h"
+
/*
* Unfortunately there is no detailed documentation available for the
* HHI_HDMI_PHY_CNTL0 register. CTL0 and CTL1 is all we know about.
diff --git a/drivers/phy/amlogic/phy-meson8b-usb2.c b/drivers/phy/amlogic/phy-meson8b-usb2.c
index a553231a9f7c..b288868b2d9e 100644
--- a/drivers/phy/amlogic/phy-meson8b-usb2.c
+++ b/drivers/phy/amlogic/phy-meson8b-usb2.c
@@ -14,10 +14,11 @@
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/reset.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/usb/of.h>
+#include "../phy-provider.h"
+
#define REG_CONFIG 0x00
#define REG_CONFIG_CLK_EN BIT(0)
#define REG_CONFIG_CLK_SEL_MASK GENMASK(3, 1)
diff --git a/drivers/phy/apple/atc.c b/drivers/phy/apple/atc.c
index e9d106f135c5..de9453d13c0e 100644
--- a/drivers/phy/apple/atc.c
+++ b/drivers/phy/apple/atc.c
@@ -32,7 +32,6 @@
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/of_device.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/reset-controller.h>
#include <linux/soc/apple/tunable.h>
@@ -44,6 +43,8 @@
#include <linux/usb/typec_mux.h>
#include <linux/usb/typec_tbt.h>
+#include "../phy-provider.h"
+
#define AUSPLL_FSM_CTRL 0x1014
#define AUSPLL_APB_CMD_OVERRIDE 0x2000
diff --git a/drivers/phy/broadcom/phy-bcm-cygnus-pcie.c b/drivers/phy/broadcom/phy-bcm-cygnus-pcie.c
index 462c61a24ec5..e10274f53c10 100644
--- a/drivers/phy/broadcom/phy-bcm-cygnus-pcie.c
+++ b/drivers/phy/broadcom/phy-bcm-cygnus-pcie.c
@@ -5,9 +5,10 @@
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
+#include "../phy-provider.h"
+
#define PCIE_CFG_OFFSET 0x00
#define PCIE1_PHY_IDDQ_SHIFT 10
#define PCIE0_PHY_IDDQ_SHIFT 2
diff --git a/drivers/phy/broadcom/phy-bcm-kona-usb2.c b/drivers/phy/broadcom/phy-bcm-kona-usb2.c
index e9cc5f2cb89a..356f42a08941 100644
--- a/drivers/phy/broadcom/phy-bcm-kona-usb2.c
+++ b/drivers/phy/broadcom/phy-bcm-kona-usb2.c
@@ -12,9 +12,11 @@
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
+#include <linux/phy/phy.h> /* for phy_set_bus_width() */
#include <linux/platform_device.h>
+#include "../phy-provider.h"
+
#define OTGCTL (0)
#define OTGCTL_OTGSTAT2 BIT(31)
#define OTGCTL_OTGSTAT1 BIT(30)
diff --git a/drivers/phy/broadcom/phy-bcm-ns-usb2.c b/drivers/phy/broadcom/phy-bcm-ns-usb2.c
index c5d35031b398..95331d08b367 100644
--- a/drivers/phy/broadcom/phy-bcm-ns-usb2.c
+++ b/drivers/phy/broadcom/phy-bcm-ns-usb2.c
@@ -13,11 +13,12 @@
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>
+#include "../phy-provider.h"
+
struct bcm_ns_usb2 {
struct device *dev;
struct clk *ref_clk;
diff --git a/drivers/phy/broadcom/phy-bcm-ns-usb3.c b/drivers/phy/broadcom/phy-bcm-ns-usb3.c
index 6e56498d0644..f2aa4014f197 100644
--- a/drivers/phy/broadcom/phy-bcm-ns-usb3.c
+++ b/drivers/phy/broadcom/phy-bcm-ns-usb3.c
@@ -19,10 +19,11 @@
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
-#include <linux/phy/phy.h>
#include <linux/property.h>
#include <linux/slab.h>
+#include "../phy-provider.h"
+
#define BCM_NS_USB3_PHY_BASE_ADDR_REG 0x1f
#define BCM_NS_USB3_PHY_PLL30_BLOCK 0x8000
#define BCM_NS_USB3_PHY_TX_PMD_BLOCK 0x8040
diff --git a/drivers/phy/broadcom/phy-bcm-ns2-pcie.c b/drivers/phy/broadcom/phy-bcm-ns2-pcie.c
index 67a6ae5ecba0..9c2c603426ca 100644
--- a/drivers/phy/broadcom/phy-bcm-ns2-pcie.c
+++ b/drivers/phy/broadcom/phy-bcm-ns2-pcie.c
@@ -6,7 +6,8 @@
#include <linux/of_mdio.h>
#include <linux/mdio.h>
#include <linux/phy.h>
-#include <linux/phy/phy.h>
+
+#include "../phy-provider.h"
#define BLK_ADDR_REG_OFFSET 0x1f
#define PLL_AFE1_100MHZ_BLK 0x2100
diff --git a/drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c b/drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c
index 8473fa574529..7543211fb998 100644
--- a/drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c
+++ b/drivers/phy/broadcom/phy-bcm-ns2-usbdrd.c
@@ -14,12 +14,13 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/workqueue.h>
+#include "../phy-provider.h"
+
#define ICFG_DRD_AFE 0x0
#define ICFG_MISC_STAT 0x18
#define ICFG_DRD_P0CTL 0x1C
diff --git a/drivers/phy/broadcom/phy-bcm-sr-pcie.c b/drivers/phy/broadcom/phy-bcm-sr-pcie.c
index 706e1d83b4ce..8f4e44d1dea6 100644
--- a/drivers/phy/broadcom/phy-bcm-sr-pcie.c
+++ b/drivers/phy/broadcom/phy-bcm-sr-pcie.c
@@ -9,10 +9,11 @@
#include <linux/module.h>
#include <linux/mfd/syscon.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
+#include "../phy-provider.h"
+
/* we have up to 8 PAXB based RC. The 9th one is always PAXC */
#define SR_NR_PCIE_PHYS 9
#define SR_PAXC_PHY_IDX (SR_NR_PCIE_PHYS - 1)
diff --git a/drivers/phy/broadcom/phy-bcm-sr-usb.c b/drivers/phy/broadcom/phy-bcm-sr-usb.c
index 6bcfe83609c8..4c863738bdca 100644
--- a/drivers/phy/broadcom/phy-bcm-sr-usb.c
+++ b/drivers/phy/broadcom/phy-bcm-sr-usb.c
@@ -8,9 +8,10 @@
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
+#include "../phy-provider.h"
+
enum bcm_usb_phy_version {
BCM_SR_USB_COMBO_PHY,
BCM_SR_USB_HS_PHY,
diff --git a/drivers/phy/broadcom/phy-bcm63xx-usbh.c b/drivers/phy/broadcom/phy-bcm63xx-usbh.c
index 29fd6791bae6..63099da486c6 100644
--- a/drivers/phy/broadcom/phy-bcm63xx-usbh.c
+++ b/drivers/phy/broadcom/phy-bcm63xx-usbh.c
@@ -18,10 +18,11 @@
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
+#include "../phy-provider.h"
+
/* USBH control register offsets */
enum usbh_regs {
USBH_BRT_CONTROL1 = 0,
diff --git a/drivers/phy/broadcom/phy-brcm-sata.c b/drivers/phy/broadcom/phy-brcm-sata.c
index fb69e21a0292..ab826f9c8678 100644
--- a/drivers/phy/broadcom/phy-brcm-sata.c
+++ b/drivers/phy/broadcom/phy-brcm-sata.c
@@ -13,9 +13,10 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
+#include "../phy-provider.h"
+
#define SATA_PCB_BANK_OFFSET 0x23c
#define SATA_PCB_REG_OFFSET(ofs) ((ofs) * 4)
diff --git a/drivers/phy/broadcom/phy-brcm-usb.c b/drivers/phy/broadcom/phy-brcm-usb.c
index 59d756a10d6c..d660a0ed03ee 100644
--- a/drivers/phy/broadcom/phy-brcm-usb.c
+++ b/drivers/phy/broadcom/phy-brcm-usb.c
@@ -11,7 +11,6 @@
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/soc/brcmstb/brcmstb.h>
@@ -19,6 +18,7 @@
#include <linux/mfd/syscon.h>
#include <linux/suspend.h>
+#include "../phy-provider.h"
#include "phy-brcm-usb-init.h"
static DEFINE_MUTEX(sysfs_lock);
diff --git a/drivers/phy/cadence/cdns-dphy-rx.c b/drivers/phy/cadence/cdns-dphy-rx.c
index 3ac80141189c..7097ac17443f 100644
--- a/drivers/phy/cadence/cdns-dphy-rx.c
+++ b/drivers/phy/cadence/cdns-dphy-rx.c
@@ -9,12 +9,13 @@
#include <linux/iopoll.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
-#include <linux/phy/phy.h>
#include <linux/phy/phy-mipi-dphy.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/sys_soc.h>
+#include "../phy-provider.h"
+
#define DPHY_PMA_CMN(reg) (reg)
#define DPHY_PCS(reg) (0xb00 + (reg))
#define DPHY_ISO(reg) (0xc00 + (reg))
diff --git a/drivers/phy/cadence/cdns-dphy.c b/drivers/phy/cadence/cdns-dphy.c
index d5b0e516b93c..40bc18405082 100644
--- a/drivers/phy/cadence/cdns-dphy.c
+++ b/drivers/phy/cadence/cdns-dphy.c
@@ -10,11 +10,11 @@
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/of.h>
+#include <linux/phy/phy-mipi-dphy.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
-#include <linux/phy/phy.h>
-#include <linux/phy/phy-mipi-dphy.h>
+#include "../phy-provider.h"
#define REG_WAKEUP_TIME_NS 800
#define DPHY_PLL_RATE_HZ 108000000
diff --git a/drivers/phy/cadence/phy-cadence-salvo.c b/drivers/phy/cadence/phy-cadence-salvo.c
index f461585c84c6..8ed74db50dfa 100644
--- a/drivers/phy/cadence/phy-cadence-salvo.c
+++ b/drivers/phy/cadence/phy-cadence-salvo.c
@@ -10,12 +10,13 @@
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/module.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/of.h>
#include <linux/of_platform.h>
+#include "../phy-provider.h"
+
#define USB3_PHY_OFFSET 0x0
#define USB2_PHY_OFFSET 0x38000
/* USB3 PHY register definition */
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c
index 92ab1a31646a..fb44b8fc5e3f 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -12,7 +12,6 @@
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
@@ -23,6 +22,8 @@
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/phy/phy-cadence.h>
+#include "../phy-provider.h"
+
#define NUM_SSC_MODE 3
#define NUM_PHY_TYPE 5
diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
index d446a0f97688..974e12e34ae1 100644
--- a/drivers/phy/cadence/phy-cadence-torrent.c
+++ b/drivers/phy/cadence/phy-cadence-torrent.c
@@ -17,11 +17,12 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
#include <linux/regmap.h>
+#include "../phy-provider.h"
+
#define REF_CLK_19_2MHZ 19200000
#define REF_CLK_25MHZ 25000000
#define REF_CLK_100MHZ 100000000
diff --git a/drivers/phy/canaan/phy-k230-usb.c b/drivers/phy/canaan/phy-k230-usb.c
index 52dad35fc6cf..4305763a5456 100644
--- a/drivers/phy/canaan/phy-k230-usb.c
+++ b/drivers/phy/canaan/phy-k230-usb.c
@@ -8,9 +8,10 @@
#include <linux/bitfield.h>
#include <linux/io.h>
#include <linux/of_address.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
+#include "../phy-provider.h"
+
#define MAX_PHYS 2
/* Register offsets within the HiSysConfig system controller */
diff --git a/drivers/phy/eswin/phy-eic7700-sata.c b/drivers/phy/eswin/phy-eic7700-sata.c
index c33653d48daa..387d5c8c11d9 100644
--- a/drivers/phy/eswin/phy-eic7700-sata.c
+++ b/drivers/phy/eswin/phy-eic7700-sata.c
@@ -14,11 +14,12 @@
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset.h>
+#include "../phy-provider.h"
+
#define SATA_AXI_LP_CTRL 0x08
#define SATA_MPLL_CTRL 0x20
#define SATA_P0_PHY_STAT 0x24
diff --git a/drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c b/drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c
index 0928a526e2ab..314aa227f753 100644
--- a/drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c
+++ b/drivers/phy/freescale/phy-fsl-imx8-mipi-dphy.c
@@ -16,11 +16,12 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/firmware/imx/rsrc.h>
+#include "../phy-provider.h"
+
/* Control and Status Registers(CSR) */
#define PHY_CTRL 0x00
#define CCM_MASK GENMASK(7, 5)
diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
index 7f5600103a00..6197cfc9b9a4 100644
--- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
+++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
@@ -3,6 +3,7 @@
* Copyright 2021 NXP
*/
+#include <dt-bindings/phy/phy-imx8-pcie.h>
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/delay.h>
@@ -12,12 +13,11 @@
#include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset.h>
-#include <dt-bindings/phy/phy-imx8-pcie.h>
+#include "../phy-provider.h"
#define IMX8MM_PCIE_PHY_CMN_REG061 0x184
#define ANA_PLL_CLK_OUT_TO_EXT_IO_EN BIT(0)
diff --git a/drivers/phy/freescale/phy-fsl-imx8mq-usb.c b/drivers/phy/freescale/phy-fsl-imx8mq-usb.c
index b05d80e849a1..9b938b446996 100644
--- a/drivers/phy/freescale/phy-fsl-imx8mq-usb.c
+++ b/drivers/phy/freescale/phy-fsl-imx8mq-usb.c
@@ -7,11 +7,12 @@
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/usb/typec_mux.h>
+#include "../phy-provider.h"
+
#define PHY_CTRL0 0x0
#define PHY_CTRL0_REF_SSP_EN BIT(2)
#define PHY_CTRL0_FSEL_MASK GENMASK(10, 5)
diff --git a/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c b/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
index 279b8ac7822d..b274fd24b59a 100644
--- a/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
+++ b/drivers/phy/freescale/phy-fsl-imx8qm-hsio.c
@@ -3,6 +3,8 @@
* Copyright 2024 NXP
*/
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/phy/phy-imx8-pcie.h>
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/delay.h>
@@ -11,13 +13,11 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/pci_regs.h>
-#include <linux/phy/phy.h>
#include <linux/phy/pcie.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
-#include <dt-bindings/phy/phy.h>
-#include <dt-bindings/phy/phy-imx8-pcie.h>
+#include "../phy-provider.h"
#define MAX_NUM_LANE 3
#define LANE_NUM_CLKS 5
diff --git a/drivers/phy/freescale/phy-fsl-imx8qm-lvds-phy.c b/drivers/phy/freescale/phy-fsl-imx8qm-lvds-phy.c
index ece357443521..55c23bef5121 100644
--- a/drivers/phy/freescale/phy-fsl-imx8qm-lvds-phy.c
+++ b/drivers/phy/freescale/phy-fsl-imx8qm-lvds-phy.c
@@ -9,12 +9,13 @@
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/units.h>
+#include "../phy-provider.h"
+
#define REG_SET 0x4
#define REG_CLR 0x8
diff --git a/drivers/phy/freescale/phy-fsl-lynx-28g.c b/drivers/phy/freescale/phy-fsl-lynx-28g.c
index 2b0fd95ba62f..c4df5966ddfb 100644
--- a/drivers/phy/freescale/phy-fsl-lynx-28g.c
+++ b/drivers/phy/freescale/phy-fsl-lynx-28g.c
@@ -5,10 +5,11 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/phy.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/workqueue.h>
+#include "../phy-provider.h"
+
#define LYNX_28G_NUM_LANE 8
#define LYNX_28G_NUM_PLL 2
diff --git a/drivers/phy/hisilicon/phy-hi3660-usb3.c b/drivers/phy/hisilicon/phy-hi3660-usb3.c
index e2a09d67faed..b66ff3be1aed 100644
--- a/drivers/phy/hisilicon/phy-hi3660-usb3.c
+++ b/drivers/phy/hisilicon/phy-hi3660-usb3.c
@@ -12,10 +12,11 @@
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
+#include "../phy-provider.h"
+
#define PERI_CRG_CLK_EN4 0x40
#define PERI_CRG_CLK_DIS4 0x44
#define GT_CLK_USB3OTG_REF BIT(0)
diff --git a/drivers/phy/hisilicon/phy-hi3670-pcie.c b/drivers/phy/hisilicon/phy-hi3670-pcie.c
index dbc7dcce682b..b7cf44078e0d 100644
--- a/drivers/phy/hisilicon/phy-hi3670-pcie.c
+++ b/drivers/phy/hisilicon/phy-hi3670-pcie.c
@@ -26,11 +26,12 @@
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/types.h>
+#include "../phy-provider.h"
+
#define AXI_CLK_FREQ 207500000
#define REF_CLK_FREQ 100000000
diff --git a/drivers/phy/hisilicon/phy-hi3670-usb3.c b/drivers/phy/hisilicon/phy-hi3670-usb3.c
index 40d3cf128b44..004c51500597 100644
--- a/drivers/phy/hisilicon/phy-hi3670-usb3.c
+++ b/drivers/phy/hisilicon/phy-hi3670-usb3.c
@@ -14,10 +14,11 @@
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
+#include "../phy-provider.h"
+
#define SCTRL_SCDEEPSLEEPED (0x0)
#define USB_CLK_SELECTED BIT(20)
diff --git a/drivers/phy/hisilicon/phy-hi6220-usb.c b/drivers/phy/hisilicon/phy-hi6220-usb.c
index 22d8d8a8dabe..1b5a2d3e3e44 100644
--- a/drivers/phy/hisilicon/phy-hi6220-usb.c
+++ b/drivers/phy/hisilicon/phy-hi6220-usb.c
@@ -8,9 +8,10 @@
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
-#include <linux/phy/phy.h>
#include <linux/regmap.h>
+#include "../phy-provider.h"
+
#define SC_PERIPH_CTRL4 0x00c
#define CTRL4_PICO_SIDDQ BIT(6)
diff --git a/drivers/phy/hisilicon/phy-hisi-inno-usb2.c b/drivers/phy/hisilicon/phy-hisi-inno-usb2.c
index c843923252aa..4a4701d0fc9c 100644
--- a/drivers/phy/hisilicon/phy-hisi-inno-usb2.c
+++ b/drivers/phy/hisilicon/phy-hisi-inno-usb2.c
@@ -10,10 +10,12 @@
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
+#include <linux/phy/phy.h> /* for phy_set_bus_width() */
#include <linux/platform_device.h>
#include <linux/reset.h>
+#include "../phy-provider.h"
+
#define INNO_PHY_PORT_NUM 2
#define REF_CLK_STABLE_TIME 100 /* unit:us */
#define UTMI_CLK_STABLE_TIME 200 /* unit:us */
diff --git a/drivers/phy/hisilicon/phy-histb-combphy.c b/drivers/phy/hisilicon/phy-histb-combphy.c
index 9dd0bd00b4e4..9b6ed1644d74 100644
--- a/drivers/phy/hisilicon/phy-histb-combphy.c
+++ b/drivers/phy/hisilicon/phy-histb-combphy.c
@@ -14,12 +14,13 @@
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <dt-bindings/phy/phy.h>
+#include "../phy-provider.h"
+
#define COMBPHY_MODE_PCIE 0
#define COMBPHY_MODE_USB3 1
#define COMBPHY_MODE_SATA 2
diff --git a/drivers/phy/hisilicon/phy-hix5hd2-sata.c b/drivers/phy/hisilicon/phy-hix5hd2-sata.c
index 1b26ddb4c8a7..57994f69417d 100644
--- a/drivers/phy/hisilicon/phy-hix5hd2-sata.c
+++ b/drivers/phy/hisilicon/phy-hix5hd2-sata.c
@@ -9,10 +9,11 @@
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
+#include "../phy-provider.h"
+
#define SATA_PHY0_CTLL 0xa0
#define MPLL_MULTIPLIER_SHIFT 1
#define MPLL_MULTIPLIER_MASK 0xfe
diff --git a/drivers/phy/ingenic/phy-ingenic-usb.c b/drivers/phy/ingenic/phy-ingenic-usb.c
index 7e62d46850fd..d656f97729c4 100644
--- a/drivers/phy/ingenic/phy-ingenic-usb.c
+++ b/drivers/phy/ingenic/phy-ingenic-usb.c
@@ -12,10 +12,11 @@
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
+#include "../phy-provider.h"
+
/* OTGPHY register offsets */
#define REG_USBPCR_OFFSET 0x00
#define REG_USBRDT_OFFSET 0x04
diff --git a/drivers/phy/intel/phy-intel-keembay-emmc.c b/drivers/phy/intel/phy-intel-keembay-emmc.c
index 0eb11ac7c2e2..fdba1d050439 100644
--- a/drivers/phy/intel/phy-intel-keembay-emmc.c
+++ b/drivers/phy/intel/phy-intel-keembay-emmc.c
@@ -11,10 +11,11 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
+#include "../phy-provider.h"
+
/* eMMC/SD/SDIO core/phy configuration registers */
#define PHY_CFG_0 0x24
#define SEL_DLY_TXCLK_MASK BIT(29)
diff --git a/drivers/phy/intel/phy-intel-keembay-usb.c b/drivers/phy/intel/phy-intel-keembay-usb.c
index c8b05f7b2445..4e690f3eb560 100644
--- a/drivers/phy/intel/phy-intel-keembay-usb.c
+++ b/drivers/phy/intel/phy-intel-keembay-usb.c
@@ -10,10 +10,11 @@
#include <linux/delay.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
+#include "../phy-provider.h"
+
/* USS (USB Subsystem) clock control registers */
#define USS_CPR_CLK_EN 0x00
#define USS_CPR_CLK_SET 0x04
diff --git a/drivers/phy/intel/phy-intel-lgm-combo.c b/drivers/phy/intel/phy-intel-lgm-combo.c
index 9ee3cf61cdd0..2a8b0caa0e59 100644
--- a/drivers/phy/intel/phy-intel-lgm-combo.c
+++ b/drivers/phy/intel/phy-intel-lgm-combo.c
@@ -5,6 +5,7 @@
* Copyright (C) 2019-2020 Intel Corporation.
*/
+#include <dt-bindings/phy/phy.h>
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/iopoll.h>
@@ -12,12 +13,11 @@
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset.h>
-#include <dt-bindings/phy/phy.h>
+#include "../phy-provider.h"
#define PCIE_PHY_GEN_CTRL 0x00
#define PCIE_PHY_CLK_PAD BIT(17)
diff --git a/drivers/phy/intel/phy-intel-lgm-emmc.c b/drivers/phy/intel/phy-intel-lgm-emmc.c
index 703aeb122541..479a530dd630 100644
--- a/drivers/phy/intel/phy-intel-lgm-emmc.c
+++ b/drivers/phy/intel/phy-intel-lgm-emmc.c
@@ -11,10 +11,11 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
+#include "../phy-provider.h"
+
/* eMMC phy register definitions */
#define EMMC_PHYCTRL0_REG 0xa8
#define DR_TY_MASK GENMASK(30, 28)
diff --git a/drivers/phy/lantiq/phy-lantiq-rcu-usb2.c b/drivers/phy/lantiq/phy-lantiq-rcu-usb2.c
index 82f1ffc0b0ad..eb6c201f7c87 100644
--- a/drivers/phy/lantiq/phy-lantiq-rcu-usb2.c
+++ b/drivers/phy/lantiq/phy-lantiq-rcu-usb2.c
@@ -12,12 +12,13 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/reset.h>
+#include "../phy-provider.h"
+
/* Transmitter HS Pre-Emphasis Enable */
#define RCU_CFG1_TX_PEE BIT(0)
/* Disconnect Threshold */
diff --git a/drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c b/drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c
index 406a87c8b759..70da76399e30 100644
--- a/drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c
+++ b/drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c
@@ -11,6 +11,7 @@
* TODO: PHY modes other than 36MHz (without "SSC")
*/
+#include <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
#include <linux/bitfield.h>
#include <linux/bits.h>
#include <linux/clk.h>
@@ -18,13 +19,12 @@
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/reset.h>
-#include <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
+#include "../phy-provider.h"
#define PCIE_PHY_PLL_CTRL1 0x44
diff --git a/drivers/phy/marvell/phy-armada375-usb2.c b/drivers/phy/marvell/phy-armada375-usb2.c
index 3731f9b25655..d5c100096c3d 100644
--- a/drivers/phy/marvell/phy-armada375-usb2.c
+++ b/drivers/phy/marvell/phy-armada375-usb2.c
@@ -16,9 +16,10 @@
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/of_address.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
+#include "../phy-provider.h"
+
#define USB2_PHY_CONFIG_DISABLE BIT(0)
struct armada375_cluster_phy {
diff --git a/drivers/phy/marvell/phy-armada38x-comphy.c b/drivers/phy/marvell/phy-armada38x-comphy.c
index 5063361b0120..9653863f90bb 100644
--- a/drivers/phy/marvell/phy-armada38x-comphy.c
+++ b/drivers/phy/marvell/phy-armada38x-comphy.c
@@ -9,10 +9,11 @@
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/phy.h>
#include <linux/platform_device.h>
+#include "../phy-provider.h"
+
#define MAX_A38X_COMPHY 6
#define MAX_A38X_PORTS 3
diff --git a/drivers/phy/marvell/phy-berlin-sata.c b/drivers/phy/marvell/phy-berlin-sata.c
index c90e2867900c..4d4013d115ca 100644
--- a/drivers/phy/marvell/phy-berlin-sata.c
+++ b/drivers/phy/marvell/phy-berlin-sata.c
@@ -10,10 +10,11 @@
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/io.h>
#include <linux/platform_device.h>
+#include "../phy-provider.h"
+
#define HOST_VSA_ADDR 0x0
#define HOST_VSA_DATA 0x4
#define PORT_SCR_CTL 0x2c
diff --git a/drivers/phy/marvell/phy-berlin-usb.c b/drivers/phy/marvell/phy-berlin-usb.c
index f26bf630da2c..a3e58deaaa74 100644
--- a/drivers/phy/marvell/phy-berlin-usb.c
+++ b/drivers/phy/marvell/phy-berlin-usb.c
@@ -9,11 +9,12 @@
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/reset.h>
+#include "../phy-provider.h"
+
#define USB_PHY_PLL 0x04
#define USB_PHY_PLL_CONTROL 0x08
#define USB_PHY_TX_CTRL0 0x10
diff --git a/drivers/phy/marvell/phy-mmp3-hsic.c b/drivers/phy/marvell/phy-mmp3-hsic.c
index 72ab6da0ebc3..90498211431b 100644
--- a/drivers/phy/marvell/phy-mmp3-hsic.c
+++ b/drivers/phy/marvell/phy-mmp3-hsic.c
@@ -7,9 +7,10 @@
#include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
+#include "../phy-provider.h"
+
#define HSIC_CTRL 0x08
#define HSIC_ENABLE BIT(7)
#define PLL_BYPASS BIT(4)
diff --git a/drivers/phy/marvell/phy-mmp3-usb.c b/drivers/phy/marvell/phy-mmp3-usb.c
index 5b71deb08851..ba67bcc2c3f9 100644
--- a/drivers/phy/marvell/phy-mmp3-usb.c
+++ b/drivers/phy/marvell/phy-mmp3-usb.c
@@ -8,10 +8,11 @@
#include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/soc/mmp/cputype.h>
+#include "../phy-provider.h"
+
#define USB2_PLL_REG0 0x4
#define USB2_PLL_REG1 0x8
#define USB2_TX_REG0 0x10
diff --git a/drivers/phy/marvell/phy-mvebu-a3700-comphy.c b/drivers/phy/marvell/phy-mvebu-a3700-comphy.c
index 1d1db1737422..3acfd74c3eca 100644
--- a/drivers/phy/marvell/phy-mvebu-a3700-comphy.c
+++ b/drivers/phy/marvell/phy-mvebu-a3700-comphy.c
@@ -21,10 +21,11 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/phy.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
+#include "../phy-provider.h"
+
#define PLL_SET_DELAY_US 600
#define COMPHY_PLL_SLEEP 1000
#define COMPHY_PLL_TIMEOUT 150000
diff --git a/drivers/phy/marvell/phy-mvebu-a3700-utmi.c b/drivers/phy/marvell/phy-mvebu-a3700-utmi.c
index 04f4fb4bed70..c17ce28ceb0b 100644
--- a/drivers/phy/marvell/phy-mvebu-a3700-utmi.c
+++ b/drivers/phy/marvell/phy-mvebu-a3700-utmi.c
@@ -14,10 +14,11 @@
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
+#include "../phy-provider.h"
+
/* Armada 3700 UTMI PHY registers */
#define USB2_PHY_PLL_CTRL_REG0 0x0
#define PLL_REF_DIV_OFF 0
diff --git a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
index 71f9c14fb50d..18ad172135ea 100644
--- a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
+++ b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
@@ -13,10 +13,11 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/phy.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
+#include "../phy-provider.h"
+
/* Relative to priv->base */
#define MVEBU_COMPHY_SERDES_CFG0(n) (0x0 + (n) * 0x1000)
#define MVEBU_COMPHY_SERDES_CFG0_PU_PLL BIT(1)
diff --git a/drivers/phy/marvell/phy-mvebu-cp110-utmi.c b/drivers/phy/marvell/phy-mvebu-cp110-utmi.c
index dd3e515a8e86..f3e2ef54c37b 100644
--- a/drivers/phy/marvell/phy-mvebu-cp110-utmi.c
+++ b/drivers/phy/marvell/phy-mvebu-cp110-utmi.c
@@ -13,12 +13,13 @@
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/usb/of.h>
#include <linux/usb/otg.h>
+#include "../phy-provider.h"
+
#define UTMI_PHY_PORTS 2
/* CP110 UTMI register macro definetions */
diff --git a/drivers/phy/marvell/phy-mvebu-sata.c b/drivers/phy/marvell/phy-mvebu-sata.c
index 89a5a2b69d80..b9a9eca74789 100644
--- a/drivers/phy/marvell/phy-mvebu-sata.c
+++ b/drivers/phy/marvell/phy-mvebu-sata.c
@@ -8,11 +8,12 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/clk.h>
-#include <linux/phy/phy.h>
#include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
+#include "../phy-provider.h"
+
struct priv {
struct clk *clk;
void __iomem *base;
diff --git a/drivers/phy/marvell/phy-pxa-28nm-hsic.c b/drivers/phy/marvell/phy-pxa-28nm-hsic.c
index eff6dd6b2dd0..6feee8d1ca70 100644
--- a/drivers/phy/marvell/phy-pxa-28nm-hsic.c
+++ b/drivers/phy/marvell/phy-pxa-28nm-hsic.c
@@ -17,7 +17,8 @@
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/platform_device.h>
-#include <linux/phy/phy.h>
+
+#include "../phy-provider.h"
#define PHY_28NM_HSIC_CTRL 0x08
#define PHY_28NM_HSIC_IMPCAL_CAL 0x18
diff --git a/drivers/phy/marvell/phy-pxa-28nm-usb2.c b/drivers/phy/marvell/phy-pxa-28nm-usb2.c
index 64afb82cf70e..39b8344803cb 100644
--- a/drivers/phy/marvell/phy-pxa-28nm-usb2.c
+++ b/drivers/phy/marvell/phy-pxa-28nm-usb2.c
@@ -17,7 +17,8 @@
#include <linux/clk.h>
#include <linux/module.h>
#include <linux/platform_device.h>
-#include <linux/phy/phy.h>
+
+#include "../phy-provider.h"
/* USB PXA1928 PHY mapping */
#define PHY_28NM_PLL_REG0 0x0
diff --git a/drivers/phy/marvell/phy-pxa-usb.c b/drivers/phy/marvell/phy-pxa-usb.c
index c0bb71f80c04..9a8ab813d001 100644
--- a/drivers/phy/marvell/phy-pxa-usb.c
+++ b/drivers/phy/marvell/phy-pxa-usb.c
@@ -10,9 +10,10 @@
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_address.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
+#include "../phy-provider.h"
+
/* phy regs */
#define UTMI_REVISION 0x0
#define UTMI_CTRL 0x4
diff --git a/drivers/phy/mediatek/phy-mtk-dp.c b/drivers/phy/mediatek/phy-mtk-dp.c
index d7024a144335..ab3778447570 100644
--- a/drivers/phy/mediatek/phy-mtk-dp.c
+++ b/drivers/phy/mediatek/phy-mtk-dp.c
@@ -10,10 +10,11 @@
#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
+#include "../phy-provider.h"
+
#define PHY_OFFSET 0x1000
#define MTK_DP_PHY_DIG_PLL_CTL_1 (PHY_OFFSET + 0x14)
diff --git a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
index 1426a2db984d..30015bac3f73 100644
--- a/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
+++ b/drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c
@@ -7,7 +7,6 @@
#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regulator/driver.h>
#include <linux/regulator/of_regulator.h>
diff --git a/drivers/phy/mediatek/phy-mtk-hdmi.h b/drivers/phy/mediatek/phy-mtk-hdmi.h
index 99d917e0036a..bfddd8dbe9dd 100644
--- a/drivers/phy/mediatek/phy-mtk-hdmi.h
+++ b/drivers/phy/mediatek/phy-mtk-hdmi.h
@@ -11,12 +11,13 @@
#include <linux/delay.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regulator/driver.h>
#include <linux/regulator/machine.h>
#include <linux/types.h>
+#include "../phy-provider.h"
+
struct mtk_hdmi_phy;
struct mtk_hdmi_phy_conf {
diff --git a/drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c b/drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c
index 058e1d926630..5e008204ecca 100644
--- a/drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c
+++ b/drivers/phy/mediatek/phy-mtk-mipi-csi-0-5.c
@@ -12,10 +12,10 @@
#include <linux/io.h>
#include <linux/module.h>
#include <linux/mutex.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
+#include "../phy-provider.h"
#include "phy-mtk-io.h"
#include "phy-mtk-mipi-csi-0-5-rx-reg.h"
diff --git a/drivers/phy/mediatek/phy-mtk-mipi-dsi.h b/drivers/phy/mediatek/phy-mtk-mipi-dsi.h
index 5d4876f1dc95..676c8f78d9d6 100644
--- a/drivers/phy/mediatek/phy-mtk-mipi-dsi.h
+++ b/drivers/phy/mediatek/phy-mtk-mipi-dsi.h
@@ -13,9 +13,10 @@
#include <linux/module.h>
#include <linux/nvmem-consumer.h>
#include <linux/platform_device.h>
-#include <linux/phy/phy.h>
#include <linux/slab.h>
+#include "../phy-provider.h"
+
struct mtk_mipitx_data {
const u32 mppll_preserve;
const struct clk_ops *mipi_tx_clk_ops;
diff --git a/drivers/phy/mediatek/phy-mtk-pcie.c b/drivers/phy/mediatek/phy-mtk-pcie.c
index a2f69d6c72f0..1ab7c1dc2753 100644
--- a/drivers/phy/mediatek/phy-mtk-pcie.c
+++ b/drivers/phy/mediatek/phy-mtk-pcie.c
@@ -8,10 +8,10 @@
#include <linux/module.h>
#include <linux/nvmem-consumer.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
+#include "../phy-provider.h"
#include "phy-mtk-io.h"
#define PEXTP_ANA_GLB_00_REG 0x9000
diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c
index acf506529507..6f98de067327 100644
--- a/drivers/phy/mediatek/phy-mtk-tphy.c
+++ b/drivers/phy/mediatek/phy-mtk-tphy.c
@@ -15,10 +15,10 @@
#include <linux/nvmem-consumer.h>
#include <linux/of.h>
#include <linux/of_address.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
+#include "../phy-provider.h"
#include "phy-mtk-io.h"
/* version V1 sub-banks offset base address */
diff --git a/drivers/phy/mediatek/phy-mtk-ufs.c b/drivers/phy/mediatek/phy-mtk-ufs.c
index 0cb5a25b1b7a..de517fcc4f3e 100644
--- a/drivers/phy/mediatek/phy-mtk-ufs.c
+++ b/drivers/phy/mediatek/phy-mtk-ufs.c
@@ -9,9 +9,9 @@
#include <linux/io.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
+#include "../phy-provider.h"
#include "phy-mtk-io.h"
/* mphy register and offsets */
diff --git a/drivers/phy/mediatek/phy-mtk-xfi-tphy.c b/drivers/phy/mediatek/phy-mtk-xfi-tphy.c
index 100a50d0e861..036a4bb58dcf 100644
--- a/drivers/phy/mediatek/phy-mtk-xfi-tphy.c
+++ b/drivers/phy/mediatek/phy-mtk-xfi-tphy.c
@@ -17,8 +17,8 @@
#include <linux/clk.h>
#include <linux/reset.h>
#include <linux/phy.h>
-#include <linux/phy/phy.h>
+#include "../phy-provider.h"
#include "phy-mtk-io.h"
#define MTK_XFI_TPHY_NUM_CLOCKS 2
diff --git a/drivers/phy/mediatek/phy-mtk-xsphy.c b/drivers/phy/mediatek/phy-mtk-xsphy.c
index c0ddb9273cc3..5e61abddaf54 100644
--- a/drivers/phy/mediatek/phy-mtk-xsphy.c
+++ b/drivers/phy/mediatek/phy-mtk-xsphy.c
@@ -14,10 +14,10 @@
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of_address.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
+#include "../phy-provider.h"
#include "phy-mtk-io.h"
/* u2 phy banks */
diff --git a/drivers/phy/microchip/lan966x_serdes.c b/drivers/phy/microchip/lan966x_serdes.c
index 835e369cdfc5..8769518f9708 100644
--- a/drivers/phy/microchip/lan966x_serdes.c
+++ b/drivers/phy/microchip/lan966x_serdes.c
@@ -1,15 +1,15 @@
// SPDX-License-Identifier: GPL-2.0-or-later
+#include <dt-bindings/phy/phy-lan966x-serdes.h>
#include <linux/err.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/phy.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
-#include <dt-bindings/phy/phy-lan966x-serdes.h>
#include "lan966x_serdes_regs.h"
+#include "../phy-provider.h"
#define PLL_CONF_MASK GENMASK(4, 3)
#define PLL_CONF_25MHZ 0
diff --git a/drivers/phy/microchip/sparx5_serdes.c b/drivers/phy/microchip/sparx5_serdes.c
index 320cf5b50a8c..09c22a6a2639 100644
--- a/drivers/phy/microchip/sparx5_serdes.c
+++ b/drivers/phy/microchip/sparx5_serdes.c
@@ -17,8 +17,8 @@
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/phy.h>
-#include <linux/phy/phy.h>
+#include "../phy-provider.h"
#include "sparx5_serdes.h"
#define SPX5_SERDES_10G_START 13
diff --git a/drivers/phy/motorola/phy-cpcap-usb.c b/drivers/phy/motorola/phy-cpcap-usb.c
index 7cb020dd3423..66a834c208fc 100644
--- a/drivers/phy/motorola/phy-cpcap-usb.c
+++ b/drivers/phy/motorola/phy-cpcap-usb.c
@@ -24,10 +24,11 @@
#include <linux/gpio/consumer.h>
#include <linux/mfd/motorola-cpcap.h>
#include <linux/phy/omap_usb.h>
-#include <linux/phy/phy.h>
#include <linux/regulator/consumer.h>
#include <linux/usb/musb.h>
+#include "../phy-provider.h"
+
/* CPCAP_REG_USBC1 register bits */
#define CPCAP_BIT_IDPULSE BIT(15)
#define CPCAP_BIT_ID100KPU BIT(14)
diff --git a/drivers/phy/motorola/phy-mapphone-mdm6600.c b/drivers/phy/motorola/phy-mapphone-mdm6600.c
index ce1dad8c438d..92f63e52bd1d 100644
--- a/drivers/phy/motorola/phy-mapphone-mdm6600.c
+++ b/drivers/phy/motorola/phy-mapphone-mdm6600.c
@@ -15,10 +15,12 @@
#include <linux/gpio/consumer.h>
#include <linux/of_platform.h>
-#include <linux/phy/phy.h>
+#include <linux/phy/phy.h> /* for phy_pm_runtime_*() */
#include <linux/pinctrl/consumer.h>
#include <linux/pm_runtime.h>
+#include "../phy-provider.h"
+
#define PHY_MDM6600_PHY_DELAY_MS 4000 /* PHY enable 2.2s to 3.5s */
#define PHY_MDM6600_ENABLED_DELAY_MS 8000 /* 8s more total for MDM6600 */
#define PHY_MDM6600_WAKE_KICK_MS 600 /* time on after GPIO toggle */
diff --git a/drivers/phy/mscc/phy-ocelot-serdes.c b/drivers/phy/mscc/phy-ocelot-serdes.c
index 1cd1b5db2ad7..13f83876d954 100644
--- a/drivers/phy/mscc/phy-ocelot-serdes.c
+++ b/drivers/phy/mscc/phy-ocelot-serdes.c
@@ -12,12 +12,13 @@
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/phy.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <soc/mscc/ocelot_hsio.h>
#include <dt-bindings/phy/phy-ocelot-serdes.h>
+#include "../phy-provider.h"
+
struct serdes_ctrl {
struct regmap *regs;
struct device *dev;
diff --git a/drivers/phy/nuvoton/phy-ma35d1-usb2.c b/drivers/phy/nuvoton/phy-ma35d1-usb2.c
index 9a459b700ed4..520c86188fe2 100644
--- a/drivers/phy/nuvoton/phy-ma35d1-usb2.c
+++ b/drivers/phy/nuvoton/phy-ma35d1-usb2.c
@@ -10,10 +10,11 @@
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
+#include "../phy-provider.h"
+
/* USB PHY Miscellaneous Control Register */
#define MA35_SYS_REG_USBPMISCR 0x60
#define PHY0POR BIT(0) /* PHY Power-On Reset Control Bit */
diff --git a/drivers/phy/phy-airoha-pcie.c b/drivers/phy/phy-airoha-pcie.c
index 56e9ade8a9fd..d9817eed2631 100644
--- a/drivers/phy/phy-airoha-pcie.c
+++ b/drivers/phy/phy-airoha-pcie.c
@@ -9,11 +9,11 @@
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include "phy-airoha-pcie-regs.h"
+#include "phy-provider.h"
#define LEQ_LEN_CTRL_MAX_VAL 7
#define FREQ_LOCK_MAX_ATTEMPT 10
diff --git a/drivers/phy/phy-can-transceiver.c b/drivers/phy/phy-can-transceiver.c
index 330356706ad7..d1e90fe6b68b 100644
--- a/drivers/phy/phy-can-transceiver.c
+++ b/drivers/phy/phy-can-transceiver.c
@@ -6,13 +6,14 @@
*
*/
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/mux/consumer.h>
+#include "phy-provider.h"
+
struct can_transceiver_data {
u32 flags;
#define CAN_TRANSCEIVER_STB_PRESENT BIT(0)
diff --git a/drivers/phy/phy-core-mipi-dphy.c b/drivers/phy/phy-core-mipi-dphy.c
index f4956a417a47..770cfe2a2279 100644
--- a/drivers/phy/phy-core-mipi-dphy.c
+++ b/drivers/phy/phy-core-mipi-dphy.c
@@ -4,13 +4,13 @@
* Copyright (C) 2018 Cadence Design Systems Inc.
*/
+#include <linux/phy/phy-mipi-dphy.h>
#include <linux/errno.h>
#include <linux/export.h>
#include <linux/kernel.h>
#include <linux/time64.h>
-#include <linux/phy/phy.h>
-#include <linux/phy/phy-mipi-dphy.h>
+#include "phy-provider.h"
/*
* Minimum D-PHY timings based on MIPI D-PHY specification. Derived
diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c
index 89f7410241aa..a092c6290545 100644
--- a/drivers/phy/phy-core.c
+++ b/drivers/phy/phy-core.c
@@ -20,6 +20,8 @@
#include <linux/pm_runtime.h>
#include <linux/regulator/consumer.h>
+#include "phy-provider.h"
+
#define to_phy(a) (container_of((a), struct phy, dev))
/**
diff --git a/drivers/phy/phy-google-usb.c b/drivers/phy/phy-google-usb.c
index 48cfa2e28347..539732f4869e 100644
--- a/drivers/phy/phy-google-usb.c
+++ b/drivers/phy/phy-google-usb.c
@@ -14,13 +14,14 @@
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/usb/typec_mux.h>
+#include "phy-provider.h"
+
#define USBCS_USB2PHY_CFG19_OFFSET 0x0
#define USBCS_USB2PHY_CFG19_PHY_CFG_PLL_FB_DIV GENMASK(19, 8)
diff --git a/drivers/phy/phy-lpc18xx-usb-otg.c b/drivers/phy/phy-lpc18xx-usb-otg.c
index f905d3c64584..554dfa55fe7e 100644
--- a/drivers/phy/phy-lpc18xx-usb-otg.c
+++ b/drivers/phy/phy-lpc18xx-usb-otg.c
@@ -10,10 +10,11 @@
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
+#include "phy-provider.h"
+
/* USB OTG PHY register offset and bit in CREG */
#define LPC18XX_CREG_CREG0 0x004
#define LPC18XX_CREG_CREG0_USB0PHY BIT(5)
diff --git a/drivers/phy/phy-nxp-ptn3222.c b/drivers/phy/phy-nxp-ptn3222.c
index c6179d8701e6..ae75b760a30d 100644
--- a/drivers/phy/phy-nxp-ptn3222.c
+++ b/drivers/phy/phy-nxp-ptn3222.c
@@ -7,10 +7,11 @@
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
+#include "phy-provider.h"
+
#define NUM_SUPPLIES 2
struct ptn3222 {
diff --git a/drivers/phy/phy-pistachio-usb.c b/drivers/phy/phy-pistachio-usb.c
index 231792f48ced..8eed6f505a31 100644
--- a/drivers/phy/phy-pistachio-usb.c
+++ b/drivers/phy/phy-pistachio-usb.c
@@ -5,6 +5,7 @@
* Copyright (C) 2015 Google, Inc.
*/
+#include <dt-bindings/phy/phy-pistachio-usb.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h>
@@ -12,11 +13,10 @@
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
-#include <dt-bindings/phy/phy-pistachio-usb.h>
+#include "phy-provider.h"
#define USB_PHY_CONTROL1 0x04
#define USB_PHY_CONTROL1_FSEL_SHIFT 2
diff --git a/drivers/phy/phy-snps-eusb2.c b/drivers/phy/phy-snps-eusb2.c
index f90bf7e95463..9062737bfad4 100644
--- a/drivers/phy/phy-snps-eusb2.c
+++ b/drivers/phy/phy-snps-eusb2.c
@@ -13,6 +13,8 @@
#include <linux/regulator/consumer.h>
#include <linux/reset.h>
+#include "phy-provider.h"
+
#define EXYNOS_USB_PHY_HS_PHY_CTRL_RST (0x0)
#define USB_PHY_RST_MASK GENMASK(1, 0)
#define UTMI_PORT_RST_MASK GENMASK(5, 4)
diff --git a/drivers/phy/phy-xgene.c b/drivers/phy/phy-xgene.c
index 5007dc7a357c..90a00498ec0a 100644
--- a/drivers/phy/phy-xgene.c
+++ b/drivers/phy/phy-xgene.c
@@ -43,9 +43,10 @@
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/delay.h>
-#include <linux/phy/phy.h>
#include <linux/clk.h>
+#include "phy-provider.h"
+
/* Max 2 lanes per a PHY unit */
#define MAX_LANE 2
diff --git a/drivers/phy/qualcomm/phy-ath79-usb.c b/drivers/phy/qualcomm/phy-ath79-usb.c
index f8d0199c6e78..2f07241be600 100644
--- a/drivers/phy/qualcomm/phy-ath79-usb.c
+++ b/drivers/phy/qualcomm/phy-ath79-usb.c
@@ -8,9 +8,10 @@
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
-#include <linux/phy/phy.h>
#include <linux/reset.h>
+#include "../phy-provider.h"
+
struct ath79_usb_phy {
struct reset_control *reset;
/* The suspend override logic is inverted, hence the no prefix
diff --git a/drivers/phy/qualcomm/phy-qcom-apq8064-sata.c b/drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
index cae290a6e19f..dd73ecbb6c1e 100644
--- a/drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
+++ b/drivers/phy/qualcomm/phy-qcom-apq8064-sata.c
@@ -13,7 +13,8 @@
#include <linux/clk.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
-#include <linux/phy/phy.h>
+
+#include "../phy-provider.h"
/* PHY registers */
#define UNIPHY_PLL_REFCLK_CFG 0x000
diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy-qcom-edp.c
index 7372de05a0b8..faddba0f20c7 100644
--- a/drivers/phy/qualcomm/phy-qcom-edp.c
+++ b/drivers/phy/qualcomm/phy-qcom-edp.c
@@ -13,7 +13,6 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/phy/phy-dp.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
@@ -22,6 +21,8 @@
#include <dt-bindings/phy/phy.h>
+#include "../phy-provider.h"
+
#include "phy-qcom-qmp-dp-phy.h"
#include "phy-qcom-qmp-qserdes-com-v4.h"
#include "phy-qcom-qmp-qserdes-com-v6.h"
diff --git a/drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c b/drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c
index efeec4709a15..5783bdabc287 100644
--- a/drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c
+++ b/drivers/phy/qualcomm/phy-qcom-eusb2-repeater.c
@@ -8,7 +8,8 @@
#include <linux/regulator/consumer.h>
#include <linux/regmap.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
+
+#include "../phy-provider.h"
/* eUSB2 status registers */
#define EUSB2_RPTR_STATUS 0x08
diff --git a/drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c b/drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c
index da6f290af722..f1c1c2969e37 100644
--- a/drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c
+++ b/drivers/phy/qualcomm/phy-qcom-ipq4019-usb.c
@@ -14,10 +14,11 @@
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
+#include "../phy-provider.h"
+
struct ipq4019_usb_phy {
struct device *dev;
struct phy *phy;
diff --git a/drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c b/drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c
index f5eb0bdac418..1a9d4dae6a33 100644
--- a/drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c
+++ b/drivers/phy/qualcomm/phy-qcom-ipq806x-sata.c
@@ -13,7 +13,8 @@
#include <linux/clk.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
-#include <linux/phy/phy.h>
+
+#include "phy-provider.h"
struct qcom_ipq806x_sata_phy {
void __iomem *mmio;
diff --git a/drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c b/drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c
index f22c0000479f..54144f0547f0 100644
--- a/drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c
+++ b/drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c
@@ -5,13 +5,14 @@
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>
#include <linux/bitfield.h>
+#include "../phy-provider.h"
+
/* USB QSCRATCH Hardware registers */
#define QSCRATCH_GENERAL_CFG (0x08)
#define HSUSB_PHY_CTRL_REG (0x10)
diff --git a/drivers/phy/qualcomm/phy-qcom-m31-eusb2.c b/drivers/phy/qualcomm/phy-qcom-m31-eusb2.c
index 68f1ba8fec4a..9e3a911023cd 100644
--- a/drivers/phy/qualcomm/phy-qcom-m31-eusb2.c
+++ b/drivers/phy/qualcomm/phy-qcom-m31-eusb2.c
@@ -18,6 +18,8 @@
#include <linux/regulator/consumer.h>
+#include "../phy-provider.h"
+
#define USB_PHY_UTMI_CTRL0 (0x3c)
#define SLEEPM BIT(0)
diff --git a/drivers/phy/qualcomm/phy-qcom-m31.c b/drivers/phy/qualcomm/phy-qcom-m31.c
index 168ea980fda0..1a63a5807d37 100644
--- a/drivers/phy/qualcomm/phy-qcom-m31.c
+++ b/drivers/phy/qualcomm/phy-qcom-m31.c
@@ -10,11 +10,12 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
#include <linux/slab.h>
+#include "../phy-provider.h"
+
#define USB2PHY_PORT_UTMI_CTRL1 0x40
#define USB2PHY_PORT_UTMI_CTRL2 0x44
diff --git a/drivers/phy/qualcomm/phy-qcom-pcie2.c b/drivers/phy/qualcomm/phy-qcom-pcie2.c
index 11a2bb958681..4c74d8e7722d 100644
--- a/drivers/phy/qualcomm/phy-qcom-pcie2.c
+++ b/drivers/phy/qualcomm/phy-qcom-pcie2.c
@@ -8,11 +8,12 @@
#include <linux/clk.h>
#include <linux/iopoll.h>
#include <linux/module.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
#include <linux/slab.h>
+#include "../phy-provider.h"
+
#include <dt-bindings/phy/phy.h>
#define PCIE20_PARF_PHY_STTS 0x3c
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
index b9ea7d058e93..04c54c229f08 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
@@ -14,7 +14,6 @@
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_graph.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regulator/consumer.h>
@@ -28,6 +27,8 @@
#include <dt-bindings/phy/phy-qcom-qmp.h>
+#include "../phy-provider.h"
+
#include "phy-qcom-qmp-common.h"
#include "phy-qcom-qmp.h"
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
index a7c65cfe31df..df38d5b6d5be 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
@@ -13,12 +13,13 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/reset.h>
#include <linux/slab.h>
+#include "../phy-provider.h"
+
#include "phy-qcom-qmp-common.h"
#include "phy-qcom-qmp.h"
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index fed2fc9bb311..06680151360e 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -15,7 +15,6 @@
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/phy/pcie.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
@@ -24,6 +23,8 @@
#include <dt-bindings/phy/phy-qcom-qmp.h>
+#include "../phy-provider.h"
+
#include "phy-qcom-qmp-common.h"
#include "phy-qcom-qmp.h"
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index df138a5442eb..75cd5b10fdb2 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -13,7 +13,6 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/reset.h>
@@ -21,6 +20,8 @@
#include <ufs/unipro.h>
+#include "../phy-provider.h"
+
#include "phy-qcom-qmp-common.h"
#include "phy-qcom-qmp.h"
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb-legacy.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb-legacy.c
index 2bd5862c5ba8..a682b30db03e 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb-legacy.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb-legacy.c
@@ -14,13 +14,14 @@
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/of_address.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regulator/consumer.h>
#include <linux/reset.h>
#include <linux/slab.h>
+#include "../phy-provider.h"
+
#include "phy-qcom-qmp.h"
#include "phy-qcom-qmp-pcs-misc-v3.h"
#include "phy-qcom-qmp-pcs-usb-v4.h"
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
index d88b8a415e85..3db0a5282dbf 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
@@ -13,13 +13,14 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regulator/consumer.h>
#include <linux/reset.h>
#include <linux/slab.h>
+#include "../phy-provider.h"
+
#include "phy-qcom-qmp-common.h"
#include "phy-qcom-qmp.h"
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
index f62e1f6ecc07..b77007f8fee3 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
@@ -14,7 +14,6 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
@@ -25,6 +24,8 @@
#include <linux/usb/typec_mux.h>
#include <dt-bindings/phy/phy-qcom-qmp.h>
+#include "../phy-provider.h"
+
#include "phy-qcom-qmp-common.h"
#include "phy-qcom-qmp.h"
diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c
index 191040f6d60f..e5516099b911 100644
--- a/drivers/phy/qualcomm/phy-qcom-qusb2.c
+++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c
@@ -3,6 +3,7 @@
* Copyright (c) 2017, 2019, The Linux Foundation. All rights reserved.
*/
+#include <dt-bindings/phy/phy-qcom-qusb2.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/err.h>
@@ -12,7 +13,6 @@
#include <linux/module.h>
#include <linux/nvmem-consumer.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
@@ -20,7 +20,7 @@
#include <linux/reset.h>
#include <linux/slab.h>
-#include <dt-bindings/phy/phy-qcom-qusb2.h>
+#include "../phy-provider.h"
#define QUSB2PHY_PLL 0x0
#define QUSB2PHY_PLL_TEST 0x04
diff --git a/drivers/phy/qualcomm/phy-qcom-sgmii-eth.c b/drivers/phy/qualcomm/phy-qcom-sgmii-eth.c
index 5b1c82459c12..4f8ffc6524ab 100644
--- a/drivers/phy/qualcomm/phy-qcom-sgmii-eth.c
+++ b/drivers/phy/qualcomm/phy-qcom-sgmii-eth.c
@@ -7,10 +7,11 @@
#include <linux/ethtool.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
+#include "../phy-provider.h"
+
#include "phy-qcom-qmp-pcs-sgmii.h"
#include "phy-qcom-qmp-qserdes-com-v5.h"
#include "phy-qcom-qmp-qserdes-txrx-v5.h"
diff --git a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c b/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c
index 8915fa250e81..17a33e545008 100644
--- a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c
+++ b/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c
@@ -10,7 +10,6 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
@@ -18,6 +17,8 @@
#include <linux/reset.h>
#include <linux/slab.h>
+#include "../phy-provider.h"
+
#define USB2_PHY_USB_PHY_UTMI_CTRL0 (0x3c)
#define SLEEPM BIT(0)
#define OPMODE_MASK GENMASK(4, 3)
diff --git a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c
index 324c0a5d658e..13828d4f788e 100644
--- a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c
+++ b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c
@@ -12,12 +12,13 @@
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/units.h>
+#include "../phy-provider.h"
+
#define RST_ASSERT_DELAY_MIN_US 100
#define RST_ASSERT_DELAY_MAX_US 150
#define PIPE_CLK_DELAY_MIN_US 5000
diff --git a/drivers/phy/qualcomm/phy-qcom-usb-hs-28nm.c b/drivers/phy/qualcomm/phy-qcom-usb-hs-28nm.c
index a52a9bf13b75..ce317deaeacb 100644
--- a/drivers/phy/qualcomm/phy-qcom-usb-hs-28nm.c
+++ b/drivers/phy/qualcomm/phy-qcom-usb-hs-28nm.c
@@ -11,12 +11,13 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_graph.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/reset.h>
#include <linux/slab.h>
+#include "../phy-provider.h"
+
/* PHY register and bit definitions */
#define PHY_CTRL_COMMON0 0x078
#define SIDDQ BIT(2)
diff --git a/drivers/phy/qualcomm/phy-qcom-usb-hs.c b/drivers/phy/qualcomm/phy-qcom-usb-hs.c
index 98a18987f1be..95581926023f 100644
--- a/drivers/phy/qualcomm/phy-qcom-usb-hs.c
+++ b/drivers/phy/qualcomm/phy-qcom-usb-hs.c
@@ -8,11 +8,12 @@
#include <linux/clk.h>
#include <linux/regulator/consumer.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/reset.h>
#include <linux/extcon.h>
#include <linux/notifier.h>
+#include "../phy-provider.h"
+
#define ULPI_PWR_CLK_MNG_REG 0x88
# define ULPI_PWR_OTG_COMP_DISABLE BIT(0)
diff --git a/drivers/phy/qualcomm/phy-qcom-usb-hsic.c b/drivers/phy/qualcomm/phy-qcom-usb-hsic.c
index 20f6dd37c7c1..fe9315a2f207 100644
--- a/drivers/phy/qualcomm/phy-qcom-usb-hsic.c
+++ b/drivers/phy/qualcomm/phy-qcom-usb-hsic.c
@@ -5,12 +5,13 @@
#include <linux/module.h>
#include <linux/ulpi/driver.h>
#include <linux/ulpi/regs.h>
-#include <linux/phy/phy.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/pinctrl-state.h>
#include <linux/delay.h>
#include <linux/clk.h>
+#include "../phy-provider.h"
+
#define ULPI_HSIC_CFG 0x30
#define ULPI_HSIC_IO_CAL 0x33
diff --git a/drivers/phy/qualcomm/phy-qcom-usb-ss.c b/drivers/phy/qualcomm/phy-qcom-usb-ss.c
index a3a6d3ce7ea1..17ca14a0b34d 100644
--- a/drivers/phy/qualcomm/phy-qcom-usb-ss.c
+++ b/drivers/phy/qualcomm/phy-qcom-usb-ss.c
@@ -11,12 +11,13 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/reset.h>
#include <linux/slab.h>
+#include "../phy-provider.h"
+
#define PHY_CTRL0 0x6C
#define PHY_CTRL1 0x70
#define PHY_CTRL2 0x74
diff --git a/drivers/phy/ralink/phy-mt7621-pci.c b/drivers/phy/ralink/phy-mt7621-pci.c
index a591ad95347c..4865a264136d 100644
--- a/drivers/phy/ralink/phy-mt7621-pci.c
+++ b/drivers/phy/ralink/phy-mt7621-pci.c
@@ -10,11 +10,12 @@
#include <linux/bitops.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/sys_soc.h>
+#include "../phy-provider.h"
+
#define RG_PE1_PIPE_REG 0x02c
#define RG_PE1_PIPE_RST BIT(12)
#define RG_PE1_PIPE_CMD_FRC BIT(4)
diff --git a/drivers/phy/ralink/phy-ralink-usb.c b/drivers/phy/ralink/phy-ralink-usb.c
index 0ff07e210769..cc61139ce157 100644
--- a/drivers/phy/ralink/phy-ralink-usb.c
+++ b/drivers/phy/ralink/phy-ralink-usb.c
@@ -14,11 +14,12 @@
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset.h>
+#include "../phy-provider.h"
+
#define RT_SYSC_REG_SYSCFG1 0x014
#define RT_SYSC_REG_CLKCFG1 0x030
#define RT_SYSC_REG_USB_PHY_CFG 0x05c
diff --git a/drivers/phy/realtek/phy-rtk-usb2.c b/drivers/phy/realtek/phy-rtk-usb2.c
index 248550ef98ca..a0431f11972e 100644
--- a/drivers/phy/realtek/phy-rtk-usb2.c
+++ b/drivers/phy/realtek/phy-rtk-usb2.c
@@ -16,9 +16,10 @@
#include <linux/regmap.h>
#include <linux/sys_soc.h>
#include <linux/mfd/syscon.h>
-#include <linux/phy/phy.h>
#include <linux/usb.h>
+#include "../phy-provider.h"
+
/* GUSB2PHYACCn register */
#define PHY_NEW_REG_REQ BIT(25)
#define PHY_VSTS_BUSY BIT(23)
diff --git a/drivers/phy/realtek/phy-rtk-usb3.c b/drivers/phy/realtek/phy-rtk-usb3.c
index cce453686db2..3f565c4d96be 100644
--- a/drivers/phy/realtek/phy-rtk-usb3.c
+++ b/drivers/phy/realtek/phy-rtk-usb3.c
@@ -16,9 +16,10 @@
#include <linux/regmap.h>
#include <linux/sys_soc.h>
#include <linux/mfd/syscon.h>
-#include <linux/phy/phy.h>
#include <linux/usb.h>
+#include "../phy-provider.h"
+
#define USB_MDIO_CTRL_PHY_BUSY BIT(7)
#define USB_MDIO_CTRL_PHY_WRITE BIT(0)
#define USB_MDIO_CTRL_PHY_ADDR_SHIFT 8
diff --git a/drivers/phy/renesas/phy-rcar-gen2.c b/drivers/phy/renesas/phy-rcar-gen2.c
index 6c671254c625..ca5498986120 100644
--- a/drivers/phy/renesas/phy-rcar-gen2.c
+++ b/drivers/phy/renesas/phy-rcar-gen2.c
@@ -12,11 +12,12 @@
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/atomic.h>
+#include "../phy-provider.h"
+
#define USBHS_LPSTS 0x02
#define USBHS_UGCTRL 0x80
#define USBHS_UGCTRL2 0x84
diff --git a/drivers/phy/renesas/phy-rcar-gen3-pcie.c b/drivers/phy/renesas/phy-rcar-gen3-pcie.c
index 3e2cf59ad480..747a1cd74639 100644
--- a/drivers/phy/renesas/phy-rcar-gen3-pcie.c
+++ b/drivers/phy/renesas/phy-rcar-gen3-pcie.c
@@ -9,11 +9,12 @@
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/spinlock.h>
+#include "../phy-provider.h"
+
#define PHY_CTRL 0x4000 /* R8A77980 only */
/* PHY control register (PHY_CTRL) */
diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb2.c b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
index cfc2a8d9028d..48ae5a507752 100644
--- a/drivers/phy/renesas/phy-rcar-gen3-usb2.c
+++ b/drivers/phy/renesas/phy-rcar-gen3-usb2.c
@@ -19,7 +19,6 @@
#include <linux/mutex.h>
#include <linux/mux/consumer.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regulator/consumer.h>
@@ -29,6 +28,8 @@
#include <linux/usb/of.h>
#include <linux/workqueue.h>
+#include "../phy-provider.h"
+
/******* USB2.0 Host registers (original offset is +0x200) *******/
#define USB2_INT_ENABLE 0x000
#define USB2_AHB_BUS_CTR 0x008
diff --git a/drivers/phy/renesas/phy-rcar-gen3-usb3.c b/drivers/phy/renesas/phy-rcar-gen3-usb3.c
index 0420f5b283ce..3511831e95d2 100644
--- a/drivers/phy/renesas/phy-rcar-gen3-usb3.c
+++ b/drivers/phy/renesas/phy-rcar-gen3-usb3.c
@@ -10,10 +10,11 @@
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
+#include "../phy-provider.h"
+
#define USB30_CLKSET0 0x034
#define USB30_CLKSET1 0x036
#define USB30_SSC_SET 0x038
diff --git a/drivers/phy/renesas/phy-rzg3e-usb3.c b/drivers/phy/renesas/phy-rzg3e-usb3.c
index 6b3453ea0004..1c9e2276bb73 100644
--- a/drivers/phy/renesas/phy-rzg3e-usb3.c
+++ b/drivers/phy/renesas/phy-rzg3e-usb3.c
@@ -11,11 +11,12 @@
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/reset.h>
+#include "../phy-provider.h"
+
#define USB3_TEST_RESET 0x0000
#define USB3_TEST_UTMICTRL2 0x0b04
#define USB3_TEST_PRMCTRL5_R 0x0c10
diff --git a/drivers/phy/renesas/r8a779f0-ether-serdes.c b/drivers/phy/renesas/r8a779f0-ether-serdes.c
index c34427ac4fdb..807af518aeda 100644
--- a/drivers/phy/renesas/r8a779f0-ether-serdes.c
+++ b/drivers/phy/renesas/r8a779f0-ether-serdes.c
@@ -10,11 +10,12 @@
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/phy.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/reset.h>
+#include "../phy-provider.h"
+
#define R8A779F0_ETH_SERDES_NUM 3
#define R8A779F0_ETH_SERDES_OFFSET 0x0400
#define R8A779F0_ETH_SERDES_BANK_SELECT 0x03fc
diff --git a/drivers/phy/rockchip/phy-rockchip-dp.c b/drivers/phy/rockchip/phy-rockchip-dp.c
index 592aa956eead..63e972969379 100644
--- a/drivers/phy/rockchip/phy-rockchip-dp.c
+++ b/drivers/phy/rockchip/phy-rockchip-dp.c
@@ -10,10 +10,11 @@
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
+#include "../phy-provider.h"
+
#define GRF_SOC_CON12 0x0274
#define GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK BIT(20)
diff --git a/drivers/phy/rockchip/phy-rockchip-dphy-rx0.c b/drivers/phy/rockchip/phy-rockchip-dphy-rx0.c
index e6a768bbb9b3..de7e00580e20 100644
--- a/drivers/phy/rockchip/phy-rockchip-dphy-rx0.c
+++ b/drivers/phy/rockchip/phy-rockchip-dphy-rx0.c
@@ -21,11 +21,12 @@
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/phy/phy-mipi-dphy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
+#include "../phy-provider.h"
+
#define RK3399_GRF_SOC_CON9 0x6224
#define RK3399_GRF_SOC_CON21 0x6254
#define RK3399_GRF_SOC_CON22 0x6258
diff --git a/drivers/phy/rockchip/phy-rockchip-emmc.c b/drivers/phy/rockchip/phy-rockchip-emmc.c
index 5187983c58e5..fd292f063f48 100644
--- a/drivers/phy/rockchip/phy-rockchip-emmc.c
+++ b/drivers/phy/rockchip/phy-rockchip-emmc.c
@@ -13,10 +13,11 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
+#include "../phy-provider.h"
+
/*
* The higher 16-bit of this register is used for write protection
* only if BIT(x + 16) set to 1 the BIT(x) can be written.
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c b/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c
index c79fb53d8ee5..3b5d86b07564 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-csidphy.c
@@ -13,13 +13,14 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
-#include <linux/phy/phy.h>
#include <linux/phy/phy-mipi-dphy.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/reset.h>
+#include "../phy-provider.h"
+
/* GRF */
#define RK1808_GRF_PD_VI_CON_OFFSET 0x0430
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
index 30d5e5ddff4a..5613b34958fe 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
@@ -15,13 +15,13 @@
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
+#include <linux/phy/phy-mipi-dphy.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/reset.h>
#include <linux/time64.h>
-#include <linux/phy/phy.h>
-#include <linux/phy/phy-mipi-dphy.h>
+#include "../phy-provider.h"
#define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l)))
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
index 1483907413fa..82b5e7434f83 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
@@ -20,6 +20,8 @@
#include <linux/phy/phy.h>
#include <linux/slab.h>
+#include "../phy-provider.h"
+
#define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l)))
/* REG: 0x00 */
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
index 8f4c08e599aa..f88e09f61994 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -18,7 +18,6 @@
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/of_irq.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/power_supply.h>
#include <linux/regmap.h>
@@ -27,6 +26,8 @@
#include <linux/usb/of.h>
#include <linux/usb/otg.h>
+#include "../phy-provider.h"
+
#define BIT_WRITEABLE_SHIFT 16
#define SCHEDULE_DELAY (60 * HZ)
#define OTG_SCHEDULE_DELAY (2 * HZ)
diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
index b60d6bf3f33c..2deb2666acb1 100644
--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
@@ -9,12 +9,13 @@
#include <linux/clk.h>
#include <linux/mfd/syscon.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/units.h>
+#include "../phy-provider.h"
+
#define BIT_WRITEABLE_SHIFT 16
#define REF_CLOCK_24MHz (24 * HZ_PER_MHZ)
#define REF_CLOCK_25MHz (25 * HZ_PER_MHZ)
diff --git a/drivers/phy/rockchip/phy-rockchip-pcie.c b/drivers/phy/rockchip/phy-rockchip-pcie.c
index 126306c01454..604ff00653b0 100644
--- a/drivers/phy/rockchip/phy-rockchip-pcie.c
+++ b/drivers/phy/rockchip/phy-rockchip-pcie.c
@@ -13,12 +13,12 @@
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/reset.h>
+#include "../phy-provider.h"
#define PHY_MAX_LANE_NUM 4
#define PHY_CFG_DATA_MASK GENMASK(10, 7)
diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c b/drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
index 0f69060aa5d5..78a0446b81df 100644
--- a/drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
+++ b/drivers/phy/rockchip/phy-rockchip-samsung-dcphy.c
@@ -15,12 +15,13 @@
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/reset.h>
+#include "../phy-provider.h"
+
#define BIAS_CON0 0x0000
#define I_RES_CNTL_MASK GENMASK(6, 4)
#define I_RES_CNTL(x) FIELD_PREP(I_RES_CNTL_MASK, x)
diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
index 2d973bc37f07..01801a4dc436 100644
--- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
+++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
@@ -21,6 +21,8 @@
#include <linux/regmap.h>
#include <linux/reset.h>
+#include "../phy-provider.h"
+
#define GRF_HDPTX_CON0 0x00
#define LC_REF_CLK_SEL BIT(11)
#define HDPTX_I_PLL_EN BIT(7)
diff --git a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
index 4e8ffd173096..029566330aa0 100644
--- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
+++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
@@ -14,11 +14,12 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/phy/pcie.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset.h>
+#include "../phy-provider.h"
+
/* Register for RK3568 */
#define GRF_PCIE30PHY_CON1 0x4
#define GRF_PCIE30PHY_CON6 0x18
diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c b/drivers/phy/rockchip/phy-rockchip-typec.c
index 0a318ccf1bbf..4a9756ca4f68 100644
--- a/drivers/phy/rockchip/phy-rockchip-typec.c
+++ b/drivers/phy/rockchip/phy-rockchip-typec.c
@@ -43,6 +43,7 @@
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
@@ -53,8 +54,7 @@
#include <linux/regmap.h>
#include <linux/reset.h>
-#include <linux/mfd/syscon.h>
-#include <linux/phy/phy.h>
+#include "../phy-provider.h"
#define CMN_SSM_BANDGAP (0x21 << 2)
#define CMN_SSM_BIAS (0x22 << 2)
diff --git a/drivers/phy/rockchip/phy-rockchip-usb.c b/drivers/phy/rockchip/phy-rockchip-usb.c
index cef96739cf3f..0652f821332b 100644
--- a/drivers/phy/rockchip/phy-rockchip-usb.c
+++ b/drivers/phy/rockchip/phy-rockchip-usb.c
@@ -14,7 +14,6 @@
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/regulator/consumer.h>
@@ -23,6 +22,8 @@
#include <linux/mfd/syscon.h>
#include <linux/delay.h>
+#include "../phy-provider.h"
+
static int enable_usb_uart;
#define UOC_CON0 0x00
diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c
index fba35510d88c..cf2abf29512f 100644
--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
@@ -25,6 +25,8 @@
#include <linux/usb/typec_dp.h>
#include <linux/usb/typec_mux.h>
+#include "../phy-provider.h"
+
/* USBDP PHY Register Definitions */
#define UDPHY_PCS 0x4000
#define UDPHY_PMA 0x8000
diff --git a/drivers/phy/samsung/phy-exynos-dp-video.c b/drivers/phy/samsung/phy-exynos-dp-video.c
index a636dee07585..00d0ed82a620 100644
--- a/drivers/phy/samsung/phy-exynos-dp-video.c
+++ b/drivers/phy/samsung/phy-exynos-dp-video.c
@@ -12,11 +12,12 @@
#include <linux/module.h>
#include <linux/mfd/syscon.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/soc/samsung/exynos-regs-pmu.h>
+#include "../phy-provider.h"
+
struct exynos_dp_video_phy_drvdata {
u32 phy_ctrl_offset;
};
diff --git a/drivers/phy/samsung/phy-exynos-mipi-video.c b/drivers/phy/samsung/phy-exynos-mipi-video.c
index be925508ed97..ce8a258a104e 100644
--- a/drivers/phy/samsung/phy-exynos-mipi-video.c
+++ b/drivers/phy/samsung/phy-exynos-mipi-video.c
@@ -11,13 +11,14 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/spinlock.h>
#include <linux/soc/samsung/exynos-regs-pmu.h>
#include <linux/mfd/syscon.h>
+#include "../phy-provider.h"
+
enum exynos_mipi_phy_id {
EXYNOS_MIPI_PHY_ID_NONE = -1,
EXYNOS_MIPI_PHY_ID_CSIS0,
diff --git a/drivers/phy/samsung/phy-exynos-pcie.c b/drivers/phy/samsung/phy-exynos-pcie.c
index 53c9230c2907..9dd3a4a90fa7 100644
--- a/drivers/phy/samsung/phy-exynos-pcie.c
+++ b/drivers/phy/samsung/phy-exynos-pcie.c
@@ -12,9 +12,10 @@
#include <linux/mfd/syscon.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
-#include <linux/phy/phy.h>
#include <linux/regmap.h>
+#include "../phy-provider.h"
+
#define PCIE_PHY_OFFSET(x) ((x) * 0x4)
/* Sysreg FSYS register offsets and bits for Exynos5433 */
diff --git a/drivers/phy/samsung/phy-exynos4210-usb2.c b/drivers/phy/samsung/phy-exynos4210-usb2.c
index 3898a7f58217..beb2f96bebbf 100644
--- a/drivers/phy/samsung/phy-exynos4210-usb2.c
+++ b/drivers/phy/samsung/phy-exynos4210-usb2.c
@@ -8,8 +8,9 @@
#include <linux/delay.h>
#include <linux/io.h>
-#include <linux/phy/phy.h>
#include <linux/regmap.h>
+
+#include "../phy-provider.h"
#include "phy-samsung-usb2.h"
/* Exynos USB PHY registers */
diff --git a/drivers/phy/samsung/phy-exynos4x12-usb2.c b/drivers/phy/samsung/phy-exynos4x12-usb2.c
index b528a5d037fe..a402f80d0aab 100644
--- a/drivers/phy/samsung/phy-exynos4x12-usb2.c
+++ b/drivers/phy/samsung/phy-exynos4x12-usb2.c
@@ -8,8 +8,9 @@
#include <linux/delay.h>
#include <linux/io.h>
-#include <linux/phy/phy.h>
#include <linux/regmap.h>
+
+#include "../phy-provider.h"
#include "phy-samsung-usb2.h"
/* Exynos USB PHY registers */
diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c
index 5a181cb4597e..cb476d007e3f 100644
--- a/drivers/phy/samsung/phy-exynos5-usbdrd.c
+++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c
@@ -26,6 +26,8 @@
#include <linux/usb/typec.h>
#include <linux/usb/typec_mux.h>
+#include "../phy-provider.h"
+
/* Exynos USB PHY registers */
#define EXYNOS5_FSEL_9MHZ6 0x0
#define EXYNOS5_FSEL_10MHZ 0x1
diff --git a/drivers/phy/samsung/phy-exynos5250-sata.c b/drivers/phy/samsung/phy-exynos5250-sata.c
index 595adba5fb8f..0f85ae0a5901 100644
--- a/drivers/phy/samsung/phy-exynos5250-sata.c
+++ b/drivers/phy/samsung/phy-exynos5250-sata.c
@@ -15,12 +15,13 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/spinlock.h>
#include <linux/mfd/syscon.h>
+#include "../phy-provider.h"
+
#define SATAPHY_CONTROL_OFFSET 0x0724
#define EXYNOS5_SATAPHY_PMU_ENABLE BIT(0)
#define EXYNOS5_SATA_RESET 0x4
diff --git a/drivers/phy/samsung/phy-exynos5250-usb2.c b/drivers/phy/samsung/phy-exynos5250-usb2.c
index 21b06072f866..04815633f290 100644
--- a/drivers/phy/samsung/phy-exynos5250-usb2.c
+++ b/drivers/phy/samsung/phy-exynos5250-usb2.c
@@ -8,8 +8,9 @@
#include <linux/delay.h>
#include <linux/io.h>
-#include <linux/phy/phy.h>
#include <linux/regmap.h>
+
+#include "../phy-provider.h"
#include "phy-samsung-usb2.h"
/* Exynos USB PHY registers */
diff --git a/drivers/phy/samsung/phy-s5pv210-usb2.c b/drivers/phy/samsung/phy-s5pv210-usb2.c
index 32be62e49804..4d72559d29a9 100644
--- a/drivers/phy/samsung/phy-s5pv210-usb2.c
+++ b/drivers/phy/samsung/phy-s5pv210-usb2.c
@@ -8,7 +8,8 @@
#include <linux/delay.h>
#include <linux/io.h>
-#include <linux/phy/phy.h>
+
+#include "../phy-provider.h"
#include "phy-samsung-usb2.h"
/* Exynos USB PHY registers */
diff --git a/drivers/phy/samsung/phy-samsung-ufs.c b/drivers/phy/samsung/phy-samsung-ufs.c
index ee665f26c236..b55a726cd44e 100644
--- a/drivers/phy/samsung/phy-samsung-ufs.c
+++ b/drivers/phy/samsung/phy-samsung-ufs.c
@@ -15,10 +15,10 @@
#include <linux/iopoll.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
+#include "../phy-provider.h"
#include "phy-samsung-ufs.h"
#define for_each_phy_lane(phy, i) \
diff --git a/drivers/phy/samsung/phy-samsung-ufs.h b/drivers/phy/samsung/phy-samsung-ufs.h
index f2c2e744e5ba..90f4d4cef631 100644
--- a/drivers/phy/samsung/phy-samsung-ufs.h
+++ b/drivers/phy/samsung/phy-samsung-ufs.h
@@ -10,9 +10,10 @@
#ifndef _PHY_SAMSUNG_UFS_
#define _PHY_SAMSUNG_UFS_
-#include <linux/phy/phy.h>
#include <linux/regmap.h>
+#include "../phy-provider.h"
+
#define PHY_COMN_BLK 1
#define PHY_TRSV_BLK 2
#define END_UFS_PHY_CFG { 0 }
diff --git a/drivers/phy/samsung/phy-samsung-usb2.c b/drivers/phy/samsung/phy-samsung-usb2.c
index d2749b67cf8f..362dd4ae3cab 100644
--- a/drivers/phy/samsung/phy-samsung-usb2.c
+++ b/drivers/phy/samsung/phy-samsung-usb2.c
@@ -13,6 +13,8 @@
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
+
+#include "../phy-provider.h"
#include "phy-samsung-usb2.h"
static int samsung_usb2_phy_power_on(struct phy *phy)
diff --git a/drivers/phy/samsung/phy-samsung-usb2.h b/drivers/phy/samsung/phy-samsung-usb2.h
index ebaf43bfc5a2..515c7938fccd 100644
--- a/drivers/phy/samsung/phy-samsung-usb2.h
+++ b/drivers/phy/samsung/phy-samsung-usb2.h
@@ -10,12 +10,13 @@
#define _PHY_EXYNOS_USB2_H
#include <linux/clk.h>
-#include <linux/phy/phy.h>
#include <linux/device.h>
#include <linux/regmap.h>
#include <linux/spinlock.h>
#include <linux/regulator/consumer.h>
+#include "../phy-provider.h"
+
#define KHZ 1000
#define MHZ (KHZ * KHZ)
diff --git a/drivers/phy/socionext/phy-uniphier-ahci.c b/drivers/phy/socionext/phy-uniphier-ahci.c
index 28cf3efe0695..6b3ce56c7f0c 100644
--- a/drivers/phy/socionext/phy-uniphier-ahci.c
+++ b/drivers/phy/socionext/phy-uniphier-ahci.c
@@ -12,10 +12,11 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
+#include "../phy-provider.h"
+
struct uniphier_ahciphy_priv {
struct device *dev;
void __iomem *base;
diff --git a/drivers/phy/socionext/phy-uniphier-pcie.c b/drivers/phy/socionext/phy-uniphier-pcie.c
index c19173492b79..00f6cdf846f1 100644
--- a/drivers/phy/socionext/phy-uniphier-pcie.c
+++ b/drivers/phy/socionext/phy-uniphier-pcie.c
@@ -12,12 +12,13 @@
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/resource.h>
+#include "../phy-provider.h"
+
/* PHY */
#define PCL_PHY_CLKCTRL 0x0000
#define PORT_SEL_MASK GENMASK(11, 9)
diff --git a/drivers/phy/socionext/phy-uniphier-usb2.c b/drivers/phy/socionext/phy-uniphier-usb2.c
index c49d432e526b..6ee566478be0 100644
--- a/drivers/phy/socionext/phy-uniphier-usb2.c
+++ b/drivers/phy/socionext/phy-uniphier-usb2.c
@@ -10,11 +10,12 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
+#include "../phy-provider.h"
+
#define SG_USBPHY1CTRL 0x500
#define SG_USBPHY1CTRL2 0x504
#define SG_USBPHY2CTRL 0x508
diff --git a/drivers/phy/socionext/phy-uniphier-usb3hs.c b/drivers/phy/socionext/phy-uniphier-usb3hs.c
index 8c8673df0084..a08db863223f 100644
--- a/drivers/phy/socionext/phy-uniphier-usb3hs.c
+++ b/drivers/phy/socionext/phy-uniphier-usb3hs.c
@@ -17,12 +17,13 @@
#include <linux/nvmem-consumer.h>
#include <linux/of.h>
#include <linux/of_platform.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/reset.h>
#include <linux/slab.h>
+#include "../phy-provider.h"
+
#define HSPHY_CFG0 0x0
#define HSPHY_CFG0_HS_I_MASK GENMASK(31, 28)
#define HSPHY_CFG0_HSDISC_MASK GENMASK(27, 26)
diff --git a/drivers/phy/socionext/phy-uniphier-usb3ss.c b/drivers/phy/socionext/phy-uniphier-usb3ss.c
index f402ed8732fd..8829305e9d4c 100644
--- a/drivers/phy/socionext/phy-uniphier-usb3ss.c
+++ b/drivers/phy/socionext/phy-uniphier-usb3ss.c
@@ -16,11 +16,12 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/reset.h>
+#include "../phy-provider.h"
+
#define SSPHY_TESTI 0x0
#define TESTI_DAT_MASK GENMASK(13, 6)
#define TESTI_ADR_MASK GENMASK(5, 1)
diff --git a/drivers/phy/sophgo/phy-cv1800-usb2.c b/drivers/phy/sophgo/phy-cv1800-usb2.c
index 6fe846534e9c..1fd7bba498ad 100644
--- a/drivers/phy/sophgo/phy-cv1800-usb2.c
+++ b/drivers/phy/sophgo/phy-cv1800-usb2.c
@@ -12,10 +12,11 @@
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
-#include <linux/phy/phy.h>
#include <linux/regmap.h>
#include <linux/spinlock.h>
+#include "../phy-provider.h"
+
#define REG_USB_PHY_CTRL 0x048
#define PHY_VBUS_POWER_EN BIT(0)
diff --git a/drivers/phy/spacemit/phy-k1-pcie.c b/drivers/phy/spacemit/phy-k1-pcie.c
index 75477bea7f70..6f8f2f39f7f8 100644
--- a/drivers/phy/spacemit/phy-k1-pcie.c
+++ b/drivers/phy/spacemit/phy-k1-pcie.c
@@ -5,6 +5,7 @@
* Copyright (C) 2025 by RISCstar Solutions Corporation. All rights reserved.
*/
+#include <dt-bindings/phy/phy.h>
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
@@ -12,12 +13,11 @@
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset.h>
-#include <dt-bindings/phy/phy.h>
+#include "../phy-provider.h"
/*
* Three PCIe ports are supported in the SpacemiT K1 SoC, and this driver
diff --git a/drivers/phy/spacemit/phy-k1-usb2.c b/drivers/phy/spacemit/phy-k1-usb2.c
index 14a02f554810..f482b6c9b6d4 100644
--- a/drivers/phy/spacemit/phy-k1-usb2.c
+++ b/drivers/phy/spacemit/phy-k1-usb2.c
@@ -9,11 +9,12 @@
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/iopoll.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/usb/of.h>
+#include "../phy-provider.h"
+
#define PHY_RST_MODE_CTRL 0x04
#define PHY_PLL_RDY BIT(0)
#define PHY_CLK_CDR_EN BIT(1)
diff --git a/drivers/phy/st/phy-miphy28lp.c b/drivers/phy/st/phy-miphy28lp.c
index 43cef89af55e..e9792deb629a 100644
--- a/drivers/phy/st/phy-miphy28lp.c
+++ b/drivers/phy/st/phy-miphy28lp.c
@@ -7,6 +7,7 @@
* Author: Alexandre Torgue <alexandre.torgue@st.com>
*/
+#include <dt-bindings/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/iopoll.h>
@@ -16,13 +17,12 @@
#include <linux/of_platform.h>
#include <linux/of_address.h>
#include <linux/clk.h>
-#include <linux/phy/phy.h>
#include <linux/delay.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>
#include <linux/reset.h>
-#include <dt-bindings/phy/phy.h>
+#include "../phy-provider.h"
/* MiPHY registers */
#define MIPHY_CONF_RESET 0x00
diff --git a/drivers/phy/st/phy-spear1310-miphy.c b/drivers/phy/st/phy-spear1310-miphy.c
index c661ab63505f..86acc2412c46 100644
--- a/drivers/phy/st/phy-spear1310-miphy.c
+++ b/drivers/phy/st/phy-spear1310-miphy.c
@@ -14,10 +14,11 @@
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
+#include "../phy-provider.h"
+
/* SPEAr1310 Registers */
#define SPEAR1310_PCIE_SATA_CFG 0x3A4
#define SPEAR1310_PCIE_SATA2_SEL_PCIE (0 << 31)
diff --git a/drivers/phy/st/phy-spear1340-miphy.c b/drivers/phy/st/phy-spear1340-miphy.c
index 85a60d64ebb7..4dbd3158c060 100644
--- a/drivers/phy/st/phy-spear1340-miphy.c
+++ b/drivers/phy/st/phy-spear1340-miphy.c
@@ -14,10 +14,11 @@
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
+#include "../phy-provider.h"
+
/* SPEAr1340 Registers */
/* Power Management Registers */
#define SPEAR1340_PCM_CFG 0x100
diff --git a/drivers/phy/st/phy-stih407-usb.c b/drivers/phy/st/phy-stih407-usb.c
index 7a3e4584895c..497f9aa4139d 100644
--- a/drivers/phy/st/phy-stih407-usb.c
+++ b/drivers/phy/st/phy-stih407-usb.c
@@ -16,7 +16,8 @@
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/mfd/syscon.h>
-#include <linux/phy/phy.h>
+
+#include "../phy-provider.h"
#define PHYPARAM_REG 0
#define PHYCTRL_REG 1
diff --git a/drivers/phy/st/phy-stm32-combophy.c b/drivers/phy/st/phy-stm32-combophy.c
index 607b4d607eb5..8757b1993e90 100644
--- a/drivers/phy/st/phy-stm32-combophy.c
+++ b/drivers/phy/st/phy-stm32-combophy.c
@@ -10,12 +10,13 @@
#include <linux/clk.h>
#include <linux/mfd/syscon.h>
#include <linux/platform_device.h>
-#include <linux/phy/phy.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <dt-bindings/phy/phy.h>
+#include "../phy-provider.h"
+
#define SYSCFG_COMBOPHY_CR1 0x4c00
#define SYSCFG_COMBOPHY_CR2 0x4c04
#define SYSCFG_COMBOPHY_CR4 0x4c0c
diff --git a/drivers/phy/st/phy-stm32-usbphyc.c b/drivers/phy/st/phy-stm32-usbphyc.c
index b44afbff8616..647fbbe5c734 100644
--- a/drivers/phy/st/phy-stm32-usbphyc.c
+++ b/drivers/phy/st/phy-stm32-usbphyc.c
@@ -18,6 +18,8 @@
#include <linux/reset.h>
#include <linux/units.h>
+#include "../phy-provider.h"
+
#define STM32_USBPHYC_PLL 0x0
#define STM32_USBPHYC_MISC 0x8
#define STM32_USBPHYC_MONITOR(X) (0x108 + ((X) * 0x100))
diff --git a/drivers/phy/starfive/phy-jh7110-dphy-rx.c b/drivers/phy/starfive/phy-jh7110-dphy-rx.c
index 0b039e1f71c5..099a1ebf6194 100644
--- a/drivers/phy/starfive/phy-jh7110-dphy-rx.c
+++ b/drivers/phy/starfive/phy-jh7110-dphy-rx.c
@@ -13,11 +13,12 @@
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/reset.h>
+#include "../phy-provider.h"
+
#define STF_DPHY_APBCFGSAIF_SYSCFG(x) (x)
#define STF_DPHY_ENABLE_CLK BIT(6)
diff --git a/drivers/phy/starfive/phy-jh7110-dphy-tx.c b/drivers/phy/starfive/phy-jh7110-dphy-tx.c
index c64d1c91b130..a5faf06b6d14 100644
--- a/drivers/phy/starfive/phy-jh7110-dphy-tx.c
+++ b/drivers/phy/starfive/phy-jh7110-dphy-tx.c
@@ -15,12 +15,13 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
-#include <linux/phy/phy.h>
#include <linux/phy/phy-mipi-dphy.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/reset.h>
+#include "../phy-provider.h"
+
#define STF_DPHY_APBIFSAIF_SYSCFG(x) (x)
#define STF_DPHY_AON_POWER_READY_N_ACTIVE 0
diff --git a/drivers/phy/starfive/phy-jh7110-pcie.c b/drivers/phy/starfive/phy-jh7110-pcie.c
index 734c8e007727..d68d396ac3cc 100644
--- a/drivers/phy/starfive/phy-jh7110-pcie.c
+++ b/drivers/phy/starfive/phy-jh7110-pcie.c
@@ -12,10 +12,11 @@
#include <linux/io.h>
#include <linux/module.h>
#include <linux/mfd/syscon.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
+#include "../phy-provider.h"
+
#define PCIE_KVCO_LEVEL_OFF 0x28
#define PCIE_USB3_PHY_PLL_CTL_OFF 0x7c
#define PCIE_KVCO_TUNE_SIGNAL_OFF 0x80
diff --git a/drivers/phy/starfive/phy-jh7110-usb.c b/drivers/phy/starfive/phy-jh7110-usb.c
index b505d89860b4..5762586e5c7d 100644
--- a/drivers/phy/starfive/phy-jh7110-usb.c
+++ b/drivers/phy/starfive/phy-jh7110-usb.c
@@ -12,11 +12,12 @@
#include <linux/io.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/usb/of.h>
+#include "../phy-provider.h"
+
#define USB_125M_CLK_RATE 125000000
#define USB_CLK_MODE_OFF 0x0
#define USB_CLK_MODE_RX_NORMAL_PWR BIT(1)
diff --git a/drivers/phy/sunplus/phy-sunplus-usb2.c b/drivers/phy/sunplus/phy-sunplus-usb2.c
index 637a5fbae6d9..2ddbc37d09ee 100644
--- a/drivers/phy/sunplus/phy-sunplus-usb2.c
+++ b/drivers/phy/sunplus/phy-sunplus-usb2.c
@@ -17,10 +17,11 @@
#include <linux/module.h>
#include <linux/nvmem-consumer.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
+#include "../phy-provider.h"
+
#define HIGH_MASK_BITS GENMASK(31, 16)
#define LOW_MASK_BITS GENMASK(15, 0)
#define OTP_DISC_LEVEL_DEFAULT 0xd
diff --git a/drivers/phy/tegra/phy-tegra194-p2u.c b/drivers/phy/tegra/phy-tegra194-p2u.c
index f49b417c9eb6..467b6b97e53d 100644
--- a/drivers/phy/tegra/phy-tegra194-p2u.c
+++ b/drivers/phy/tegra/phy-tegra194-p2u.c
@@ -11,9 +11,10 @@
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
+#include "../phy-provider.h"
+
#define P2U_CONTROL_CMN 0x74
#define P2U_CONTROL_CMN_ENABLE_L2_EXIT_RATE_CHANGE BIT(13)
#define P2U_CONTROL_CMN_SKP_SIZE_PROTECTION_EN BIT(20)
diff --git a/drivers/phy/tegra/xusb-tegra124.c b/drivers/phy/tegra/xusb-tegra124.c
index 70b6213370a8..21686c6fb2d7 100644
--- a/drivers/phy/tegra/xusb-tegra124.c
+++ b/drivers/phy/tegra/xusb-tegra124.c
@@ -8,7 +8,6 @@
#include <linux/mailbox_client.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/reset.h>
@@ -16,6 +15,7 @@
#include <soc/tegra/fuse.h>
+#include "../phy-provider.h"
#include "xusb.h"
#define FUSE_SKU_CALIB_HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? 15 : 0)
diff --git a/drivers/phy/tegra/xusb-tegra186.c b/drivers/phy/tegra/xusb-tegra186.c
index 1ddf11265974..e017cb1ff484 100644
--- a/drivers/phy/tegra/xusb-tegra186.c
+++ b/drivers/phy/tegra/xusb-tegra186.c
@@ -7,7 +7,6 @@
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/regulator/consumer.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
@@ -15,6 +14,7 @@
#include <soc/tegra/fuse.h>
+#include "../phy-provider.h"
#include "xusb.h"
/* FUSE USB_CALIB registers */
diff --git a/drivers/phy/tegra/xusb-tegra210.c b/drivers/phy/tegra/xusb-tegra210.c
index 1abc5913ec49..006aba47b93d 100644
--- a/drivers/phy/tegra/xusb-tegra210.c
+++ b/drivers/phy/tegra/xusb-tegra210.c
@@ -12,7 +12,6 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
@@ -21,6 +20,7 @@
#include <soc/tegra/fuse.h>
+#include "../phy-provider.h"
#include "xusb.h"
#define FUSE_SKU_CALIB_HS_CURR_LEVEL_PADX_SHIFT(x) \
diff --git a/drivers/phy/tegra/xusb.c b/drivers/phy/tegra/xusb.c
index 9d74c0ecc31b..07a2f5a4dbee 100644
--- a/drivers/phy/tegra/xusb.c
+++ b/drivers/phy/tegra/xusb.c
@@ -9,7 +9,6 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
-#include <linux/phy/phy.h>
#include <linux/phy/tegra/xusb.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
@@ -19,6 +18,7 @@
#include <soc/tegra/fuse.h>
+#include "../phy-provider.h"
#include "xusb.h"
static struct phy *tegra_xusb_pad_of_xlate(struct device *dev,
diff --git a/drivers/phy/ti/phy-am654-serdes.c b/drivers/phy/ti/phy-am654-serdes.c
index 5b6c27aa7e8b..8990b715525e 100644
--- a/drivers/phy/ti/phy-am654-serdes.c
+++ b/drivers/phy/ti/phy-am654-serdes.c
@@ -15,11 +15,12 @@
#include <linux/mfd/syscon.h>
#include <linux/mux/consumer.h>
#include <linux/of_address.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
+#include "../phy-provider.h"
+
#define CMU_R004 0x4
#define CMU_R060 0x60
#define CMU_R07C 0x7c
diff --git a/drivers/phy/ti/phy-da8xx-usb.c b/drivers/phy/ti/phy-da8xx-usb.c
index 62fa6f89c0e6..261b65abd38b 100644
--- a/drivers/phy/ti/phy-da8xx-usb.c
+++ b/drivers/phy/ti/phy-da8xx-usb.c
@@ -11,12 +11,13 @@
#include <linux/mfd/da8xx-cfgchip.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
-#include <linux/phy/phy.h>
#include <linux/platform_data/phy-da8xx-usb.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
+#include "../phy-provider.h"
+
#define PHY_INIT_BITS (CFGCHIP2_SESENDEN | CFGCHIP2_VBDTCTEN)
struct da8xx_usb_phy {
diff --git a/drivers/phy/ti/phy-dm816x-usb.c b/drivers/phy/ti/phy-dm816x-usb.c
index d274831b731c..515ef7812bde 100644
--- a/drivers/phy/ti/phy-dm816x-usb.c
+++ b/drivers/phy/ti/phy-dm816x-usb.c
@@ -12,10 +12,11 @@
#include <linux/err.h>
#include <linux/pm_runtime.h>
#include <linux/delay.h>
-#include <linux/phy/phy.h>
#include <linux/mfd/syscon.h>
+#include "../phy-provider.h"
+
/*
* TRM has two sets of USB_CTRL registers.. The correct register bits
* are in TRM section 24.9.8.2 USB_CTRL Register. The TRM documents the
diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c
index 6213c2b6005a..ce7dc692d7be 100644
--- a/drivers/phy/ti/phy-gmii-sel.c
+++ b/drivers/phy/ti/phy-gmii-sel.c
@@ -14,9 +14,10 @@
#include <linux/of_address.h>
#include <linux/of_net.h>
#include <linux/phy.h>
-#include <linux/phy/phy.h>
#include <linux/regmap.h>
+#include "../phy-provider.h"
+
/* AM33xx SoC specific definitions for the CONTROL port */
#define AM33XX_GMII_SEL_MODE_MII 0
#define AM33XX_GMII_SEL_MODE_RMII 1
diff --git a/drivers/phy/ti/phy-omap-usb2.c b/drivers/phy/ti/phy-omap-usb2.c
index 1eb252604441..318f51d09c28 100644
--- a/drivers/phy/ti/phy-omap-usb2.c
+++ b/drivers/phy/ti/phy-omap-usb2.c
@@ -16,7 +16,6 @@
#include <linux/of_platform.h>
#include <linux/phy/omap_control_phy.h>
#include <linux/phy/omap_usb.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/property.h>
@@ -25,6 +24,8 @@
#include <linux/sys_soc.h>
#include <linux/usb/phy_companion.h>
+#include "../phy-provider.h"
+
#define USB2PHY_ANA_CONFIG1 0x4c
#define USB2PHY_DISCON_BYP_LATCH BIT(31)
diff --git a/drivers/phy/ti/phy-ti-pipe3.c b/drivers/phy/ti/phy-ti-pipe3.c
index b5543b5c674c..d63c8e872d5b 100644
--- a/drivers/phy/ti/phy-ti-pipe3.c
+++ b/drivers/phy/ti/phy-ti-pipe3.c
@@ -10,7 +10,6 @@
#include <linux/platform_device.h>
#include <linux/property.h>
#include <linux/slab.h>
-#include <linux/phy/phy.h>
#include <linux/of.h>
#include <linux/clk.h>
#include <linux/err.h>
@@ -22,6 +21,8 @@
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>
+#include "../phy-provider.h"
+
#define PLL_STATUS 0x00000004
#define PLL_GO 0x00000008
#define PLL_CONFIGURATION1 0x0000000C
diff --git a/drivers/phy/ti/phy-twl4030-usb.c b/drivers/phy/ti/phy-twl4030-usb.c
index a26aec3ab29e..67c9883691fc 100644
--- a/drivers/phy/ti/phy-twl4030-usb.c
+++ b/drivers/phy/ti/phy-twl4030-usb.c
@@ -20,7 +20,6 @@
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/usb/otg.h>
-#include <linux/phy/phy.h>
#include <linux/pm_runtime.h>
#include <linux/usb/musb.h>
#include <linux/usb/ulpi.h>
@@ -29,6 +28,8 @@
#include <linux/err.h>
#include <linux/slab.h>
+#include "../phy-provider.h"
+
/* Register defines */
#define MCPC_CTRL 0x30
diff --git a/drivers/phy/xilinx/phy-zynqmp.c b/drivers/phy/xilinx/phy-zynqmp.c
index fe6b4925d166..db40594622da 100644
--- a/drivers/phy/xilinx/phy-zynqmp.c
+++ b/drivers/phy/xilinx/phy-zynqmp.c
@@ -12,6 +12,7 @@
* PCIe should also work but that is experimental as of now.
*/
+#include <dt-bindings/phy/phy.h>
#include <linux/clk.h>
#include <linux/debugfs.h>
#include <linux/delay.h>
@@ -19,12 +20,11 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
-#include <dt-bindings/phy/phy.h>
+#include "../phy-provider.h"
/*
* Lane Registers
diff --git a/include/linux/phy/phy-sun4i-usb.h b/include/linux/phy/phy-sun4i-usb.h
index f3e7b13608e4..66612be0dac5 100644
--- a/include/linux/phy/phy-sun4i-usb.h
+++ b/include/linux/phy/phy-sun4i-usb.h
@@ -6,7 +6,7 @@
#ifndef PHY_SUN4I_USB_H_
#define PHY_SUN4I_USB_H_
-#include "phy.h"
+struct phy;
/**
* sun4i_usb_phy_set_squelch_detect() - Enable/disable squelch detect
diff --git a/include/linux/phy/ulpi_phy.h b/include/linux/phy/ulpi_phy.h
index 7054b440347c..0f9e8430d398 100644
--- a/include/linux/phy/ulpi_phy.h
+++ b/include/linux/phy/ulpi_phy.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0 */
-#include <linux/phy/phy.h>
+#include "../../drivers/phy/phy-provider.h"
/**
* Helper that registers PHY for a ULPI device and adds a lookup for binding it
--
2.43.0
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