* [PATCH v3 04/12] phy: rockchip: usbdp: Amend SSC modulation deviation
From: Sebastian Reichel @ 2026-03-13 17:57 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Heiko Stuebner, Frank Wang,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Andy Yan, Dmitry Baryshkov, Yubing Zhang, Alexey Charkov,
linux-phy, linux-arm-kernel, linux-rockchip, linux-kernel, kernel,
devicetree, Sebastian Reichel
In-Reply-To: <20260313-rockchip-usbdp-cleanup-v3-0-3e8fe89a35b5@collabora.com>
From: Frank Wang <frank.wang@rock-chips.com>
Move SSC modulation deviation into private config of clock
- 24M: 0x00d4[5:0] = 0x30
- 26M: 0x00d4[5:0] = 0x33
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
[Taken over from rockchip's kernel tree; register 0x00d4 is not
described in the TRM]
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/phy/rockchip/phy-rockchip-usbdp.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c
index 98562a888b42..1f686844c337 100644
--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
@@ -350,7 +350,8 @@ static const struct reg_sequence rk_udphy_24m_refclk_cfg[] = {
{0x0a64, 0xa8}, {0x1a3c, 0xd0},
{0x1a44, 0xd0}, {0x1a48, 0x01},
{0x1a4c, 0x0d}, {0x1a54, 0xe0},
- {0x1a5c, 0xe0}, {0x1a64, 0xa8}
+ {0x1a5c, 0xe0}, {0x1a64, 0xa8},
+ {0x00d4, 0x30}
};
static const struct reg_sequence rk_udphy_26m_refclk_cfg[] = {
@@ -377,7 +378,7 @@ static const struct reg_sequence rk_udphy_26m_refclk_cfg[] = {
{0x0c30, 0x0e}, {0x0c48, 0x06},
{0x1c30, 0x0e}, {0x1c48, 0x06},
{0x028c, 0x18}, {0x0af0, 0x00},
- {0x1af0, 0x00}
+ {0x1af0, 0x00}, {0x00d4, 0x33}
};
static const struct reg_sequence rk_udphy_init_sequence[] = {
@@ -412,8 +413,7 @@ static const struct reg_sequence rk_udphy_init_sequence[] = {
{0x0070, 0x7d}, {0x0074, 0x68},
{0x0af4, 0x1a}, {0x1af4, 0x1a},
{0x0440, 0x3f}, {0x10d4, 0x08},
- {0x20d4, 0x08}, {0x00d4, 0x30},
- {0x0024, 0x6e},
+ {0x20d4, 0x08}, {0x0024, 0x6e}
};
static inline int rk_udphy_grfreg_write(struct regmap *base,
--
2.51.0
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* [PATCH v3 03/12] phy: rockchip: usbdp: Keep clocks running on PHY re-init
From: Sebastian Reichel @ 2026-03-13 17:57 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Heiko Stuebner, Frank Wang,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Andy Yan, Dmitry Baryshkov, Yubing Zhang, Alexey Charkov,
linux-phy, linux-arm-kernel, linux-rockchip, linux-kernel, kernel,
devicetree, Sebastian Reichel
In-Reply-To: <20260313-rockchip-usbdp-cleanup-v3-0-3e8fe89a35b5@collabora.com>
When a mode change is required rk_udphy_power_on() disables
the clocks and then calls rk_udphy_setup(), which then enables
all the clocks again before continuing with rk_udphy_init().
Considering that rk_udphy_init() does assert the reset lines,
re-enabling the clocks is just delaying things. Avoid it by
directly calling rk_udphy_init().
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/phy/rockchip/phy-rockchip-usbdp.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c
index 744cc7c642f4..98562a888b42 100644
--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
@@ -1012,8 +1012,7 @@ static int rk_udphy_power_on(struct rk_udphy *udphy, u8 mode)
if (udphy->mode == UDPHY_MODE_DP)
rk_udphy_u3_port_disable(udphy, true);
- rk_udphy_disable(udphy);
- ret = rk_udphy_setup(udphy);
+ ret = rk_udphy_init(udphy);
if (ret)
return ret;
}
--
2.51.0
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* [PATCH v3 01/12] dt-bindings: phy: rockchip-usbdp: add improved ports scheme
From: Sebastian Reichel @ 2026-03-13 17:57 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Heiko Stuebner, Frank Wang,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Andy Yan, Dmitry Baryshkov, Yubing Zhang, Alexey Charkov,
linux-phy, linux-arm-kernel, linux-rockchip, linux-kernel, kernel,
devicetree, Sebastian Reichel
In-Reply-To: <20260313-rockchip-usbdp-cleanup-v3-0-3e8fe89a35b5@collabora.com>
Currently the Rockchip USBDP PHY is missing a documented port scheme.
Meanwhile upstream RK3588 DTS files are a bit messy and use different
port schemes. The upstream USBDP PHY Linux kernel driver does not yet
parse the ports at all and thus does not create any implicit ABI either.
But with the current mess it is not possible to properly support USB-C
DP AltMode. Thus this introduces a proper port scheme following roughly
the ports design of the Qualcomm QMP USB4-USB3-DP PHY controller binding
with a slight difference that there is an additional port for the
USB-C SBU port as the Rockchip USB-DP PHY also contains the SBU mux.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
.../bindings/phy/phy-rockchip-usbdp.yaml | 23 ++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml b/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml
index 8b7059d5b182..f728acf057e4 100644
--- a/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml
+++ b/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml
@@ -114,6 +114,29 @@ properties:
A port node to link the PHY to a TypeC controller for the purpose of
handling orientation switching.
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ Output endpoint of the PHY for USB (or DP when configured into 4 lane
+ mode), which should point to the superspeed port of a USB connector.
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Incoming endpoint from the USB controller
+
+ port@2:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Incoming endpoint from the DisplayPort controller
+
+ port@3:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ Output endpoint of the PHY for DP, which should either point to the
+ SBU port of a USB-C connector or a DisplayPort connector input port.
+
required:
- compatible
- reg
--
2.51.0
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* [PATCH v3 00/12] phy: rockchip: usbdp: Fixes, DP 1-lane support and cleanups
From: Sebastian Reichel @ 2026-03-13 17:57 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Heiko Stuebner, Frank Wang,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Andy Yan, Dmitry Baryshkov, Yubing Zhang, Alexey Charkov,
linux-phy, linux-arm-kernel, linux-rockchip, linux-kernel, kernel,
devicetree, Sebastian Reichel, William Wu
This series overhauls the Rockchip USBDP driver; apart from a
a bunch of cleanups and small improvements the main goal is to
get the driver ready for proper USB-C DP AltMode support.
Once this series has landed, it unblocks enabling proper USB-C
DP AltMode on the RK3588 and RK3576 platforms incl. runtime PM
for the Synopsys DesignWare DisplayPort controller.
Apart from this series, further changes are required on the
DRM side. There are no compile-time dependencies between the
DRM side and the PHY side, but the PHY side must be applied
to avoid SErrors once runtime PM is added to the DisplayPort
controller driver. Thus it would be really good to land this
series in the next merge window.
Changes in v3:
- Link to v2: https://lore.kernel.org/r/20260213-rockchip-usbdp-cleanup-v2-0-b67ec225f96e@collabora.com
- Add patch to register the USBDP PHY as DRM bridge
- Add patch to describe ports in DT binding (used by the DRM bridge)
- Add patch to drop HPD handling from the PHY
Changes in v2:
- Link to v1: https://lore.kernel.org/r/20260203-rockchip-usbdp-cleanup-v1-0-16a6f92ed176@collabora.com
- Added new patches to fix USB3 SError
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
Frank Wang (1):
phy: rockchip: usbdp: Amend SSC modulation deviation
Sebastian Reichel (9):
dt-bindings: phy: rockchip-usbdp: add improved ports scheme
phy: rockchip: usbdp: Do not loose USB3 PHY status
phy: rockchip: usbdp: Keep clocks running on PHY re-init
phy: rockchip: usbdp: Add missing mode_change update
phy: rockchip: usbdp: Rename DP lane functions
phy: rockchip: usbdp: Use FIELD_PREP_WM16_CONST
phy: rockchip: usbdp: Cleanup DP lane selection function
phy: rockchip: usbdp: Register DP aux bridge
phy: rockchip: usbdp: Drop DP HPD handling
William Wu (1):
phy: rockchip: usbdp: Fix LFPS detect threshold control
Zhang Yubing (1):
phy: rockchip: usbdp: Support single-lane DP
.../bindings/phy/phy-rockchip-usbdp.yaml | 23 +++
drivers/phy/rockchip/Kconfig | 2 +
drivers/phy/rockchip/phy-rockchip-usbdp.c | 158 +++++++--------------
3 files changed, 74 insertions(+), 109 deletions(-)
---
base-commit: 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f
change-id: 20260203-rockchip-usbdp-cleanup-5b59dfb561a3
Best regards,
--
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* [PATCH v3 02/12] phy: rockchip: usbdp: Do not loose USB3 PHY status
From: Sebastian Reichel @ 2026-03-13 17:57 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Heiko Stuebner, Frank Wang,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Andy Yan, Dmitry Baryshkov, Yubing Zhang, Alexey Charkov,
linux-phy, linux-arm-kernel, linux-rockchip, linux-kernel, kernel,
devicetree, Sebastian Reichel
In-Reply-To: <20260313-rockchip-usbdp-cleanup-v3-0-3e8fe89a35b5@collabora.com>
By default (i.e. without manually enabling runtime PM) DWC3 requests the
USB3 PHY once and keeps it enabled all the time. When DisplayPort is
being requested later on, a mode change is needed. This re-initializes
the PHY. During re-initialization the status variable has incorrectly
been cleared, which means the tracking information for USB3 ist lost.
This is not an immediate problem, since the DP side keeps the PHY
enabled. But once DP is toggled off, the whole PHY will be disabled.
This is a problem, because the USB side still needs it powered.
Fix things by not clearing the status flags.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/phy/rockchip/phy-rockchip-usbdp.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c
index fba35510d88c..744cc7c642f4 100644
--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
@@ -1009,7 +1009,6 @@ static int rk_udphy_power_on(struct rk_udphy *udphy, u8 mode)
rk_udphy_u3_port_disable(udphy, false);
} else if (udphy->mode_change) {
udphy->mode_change = false;
- udphy->status = UDPHY_MODE_NONE;
if (udphy->mode == UDPHY_MODE_DP)
rk_udphy_u3_port_disable(udphy, true);
--
2.51.0
--
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* Re: [PATCH v1 1/1] arm64: dts: qcom: hamoa: Move PCIe PERST and Wake GPIOs to port nodes
From: Bjorn Helgaas @ 2026-03-13 16:45 UTC (permalink / raw)
To: Ziyue Zhang
Cc: andersson, konradybcio, robh, krzk+dt, conor+dt, jingoohan1, mani,
lpieralisi, kwilczynski, bhelgaas, johan+linaro, vkoul, kishon,
neil.armstrong, abel.vesa, kw, linux-arm-msm, devicetree,
linux-kernel, linux-pci, linux-phy, qiang.yu, quic_krichai,
quic_vbadigan
In-Reply-To: <20260313094618.1361418-1-ziyue.zhang@oss.qualcomm.com>
On Fri, Mar 13, 2026 at 05:46:18PM +0800, Ziyue Zhang wrote:
> Commit 960609b22be5 ("arm64: dts: qcom: hamoa: Move PHY, PERST, and Wake
> GPIOs to PCIe port nodes and add port Nodes for all PCIe ports") did not
> convert all Hamoa‑based platforms to the new method of defining PERST and
> Wake GPIOs in the PCIe root port nodes.
>
> Without the change PCIe probe will fail. The probe failure happens because
> the PHY stays in the controller node while the PERST/Wake GPIOs were moved
> to the port nodes.
>
> This fixes probe failures seen on the following platforms:
> - x1-hp-omnibook-x14
> - x1-microsoft-denali
> - x1e80100-lenovo-yoga-slim7x
> - x1e80100-medion-sprchrgd-14-s1
> - x1p42100-lenovo-thinkbook-16
> - x1-asus-zenbook-a14
> - x1-crd
> - x1-dell-thena
>
> Fixes: 960609b22be5 ("arm64: dts: qcom: hamoa: Move PHY, PERST, and Wake GPIOs to PCIe port nodes and add port Nodes for all PCIe ports")
Are you saying that DTs in the field broke because of some kernel
change? That's not supposed to happen. Even though PHY, PERST, and
Wake GPIOs should be described in Root Port nodes instead of the Root
Complex node in *future* DTs, the kernel is still supposed to accept
the old style with them described in the Root Complex node.
If that's the case, the Fixes tag should refer to the driver change
that caused probe to fail with old DTs, and the fix is a driver change
to accept both the old style and the new style.
We can't expect users in the field to update their DTs to match a new
kernel.
Nit: Use PCIe spec nomenclature, e.g., "PERST#" and "WAKE#" in subject
and commit logs.
> Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
> ---
> .../boot/dts/qcom/x1-asus-zenbook-a14.dtsi | 16 ++++++++-----
> arch/arm64/boot/dts/qcom/x1-crd.dtsi | 24 ++++++++++++-------
> arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi | 14 ++++++-----
> .../boot/dts/qcom/x1-hp-omnibook-x14.dtsi | 14 ++++++-----
> .../boot/dts/qcom/x1-microsoft-denali.dtsi | 8 ++++---
> .../dts/qcom/x1e80100-lenovo-yoga-slim7x.dts | 6 ++---
> .../qcom/x1e80100-medion-sprchrgd-14-s1.dts | 15 ++++++------
> .../dts/qcom/x1p42100-lenovo-thinkbook-16.dts | 14 ++++++-----
> 8 files changed, 65 insertions(+), 46 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi b/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi
> index 8e5c5575a532..0a382cc9e643 100644
> --- a/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi
> +++ b/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi
> @@ -1032,9 +1032,6 @@ &mdss_dp3_phy {
> };
>
> &pcie4 {
> - perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
> - wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
> -
> pinctrl-0 = <&pcie4_default>;
> pinctrl-names = "default";
>
> @@ -1048,10 +1045,12 @@ &pcie4_phy {
> status = "okay";
> };
>
> -&pcie6a {
> - perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
> - wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
> +&pcie4_port0 {
> + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
> + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
> +};
>
> +&pcie6a {
> vddpe-3v3-supply = <&vreg_nvme>;
>
> pinctrl-0 = <&pcie6a_default>;
> @@ -1067,6 +1066,11 @@ &pcie6a_phy {
> status = "okay";
> };
>
> +&pcie6a_port0 {
> + reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
> + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
> +};
> +
> &pm8550_gpios {
> rtmr0_default: rtmr0-reset-n-active-state {
> pins = "gpio10";
> diff --git a/arch/arm64/boot/dts/qcom/x1-crd.dtsi b/arch/arm64/boot/dts/qcom/x1-crd.dtsi
> index ded96fb43489..2fbf9ec66fb8 100644
> --- a/arch/arm64/boot/dts/qcom/x1-crd.dtsi
> +++ b/arch/arm64/boot/dts/qcom/x1-crd.dtsi
> @@ -1216,15 +1216,17 @@ &mdss_dp3_phy {
> };
>
> &pcie4 {
> - perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
> - wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
> -
> pinctrl-0 = <&pcie4_default>;
> pinctrl-names = "default";
>
> status = "okay";
> };
>
> +&pcie4_port0 {
> + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
> + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
> +};
> +
> &pcie4_phy {
> vdda-phy-supply = <&vreg_l3i_0p8>;
> vdda-pll-supply = <&vreg_l3e_1p2>;
> @@ -1233,9 +1235,6 @@ &pcie4_phy {
> };
>
> &pcie5 {
> - perst-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
> - wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
> -
> vddpe-3v3-supply = <&vreg_wwan>;
>
> pinctrl-0 = <&pcie5_default>;
> @@ -1251,10 +1250,12 @@ &pcie5_phy {
> status = "okay";
> };
>
> -&pcie6a {
> - perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
> - wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
> +&pcie5_port0 {
> + reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
> + wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
> +};
>
> +&pcie6a {
> vddpe-3v3-supply = <&vreg_nvme>;
>
> pinctrl-names = "default";
> @@ -1270,6 +1271,11 @@ &pcie6a_phy {
> status = "okay";
> };
>
> +&pcie6a_port0 {
> + reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
> + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
> +};
> +
> &pm8550_gpios {
> kypd_vol_up_n: kypd-vol-up-n-state {
> pins = "gpio6";
> diff --git a/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi b/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi
> index bf04a12b16bc..217ca8c7d81d 100644
> --- a/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi
> +++ b/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi
> @@ -1081,9 +1081,6 @@ &mdss_dp3_phy {
> };
>
> &pcie4 {
> - perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
> - wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
> -
> pinctrl-0 = <&pcie4_default>;
> pinctrl-names = "default";
>
> @@ -1098,6 +1095,9 @@ &pcie4_phy {
> };
>
> &pcie4_port0 {
> + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
> + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
> +
> wifi@0 {
> compatible = "pci17cb,1107";
> reg = <0x10000 0x0 0x0 0x0 0x0>;
> @@ -1115,9 +1115,6 @@ wifi@0 {
> };
>
> &pcie6a {
> - perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
> - wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
> -
> vddpe-3v3-supply = <&vreg_nvme>;
>
> pinctrl-0 = <&pcie6a_default>;
> @@ -1126,6 +1123,11 @@ &pcie6a {
> status = "okay";
> };
>
> +&pcie6a_port0 {
> + reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
> + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
> +};
> +
> &pcie6a_phy {
> vdda-phy-supply = <&vreg_l1d_0p8>;
> vdda-pll-supply = <&vreg_l2j_1p2>;
> diff --git a/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi b/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi
> index a4075434162a..41063948c583 100644
> --- a/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi
> +++ b/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi
> @@ -1065,9 +1065,6 @@ &mdss_dp3_phy {
> };
>
> &pcie4 {
> - perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
> - wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
> -
> pinctrl-0 = <&pcie4_default>;
> pinctrl-names = "default";
>
> @@ -1082,6 +1079,9 @@ &pcie4_phy {
> };
>
> &pcie4_port0 {
> + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
> + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
> +
> wifi@0 {
> compatible = "pci17cb,1107";
> reg = <0x10000 0x0 0x0 0x0 0x0>;
> @@ -1099,9 +1099,6 @@ wifi@0 {
> };
>
> &pcie6a {
> - perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
> - wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
> -
> vddpe-3v3-supply = <&vreg_nvme>;
>
> pinctrl-0 = <&pcie6a_default>;
> @@ -1110,6 +1107,11 @@ &pcie6a {
> status = "okay";
> };
>
> +&pcie6a_port0 {
> + reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
> + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
> +};
> +
> &pcie6a_phy {
> vdda-phy-supply = <&vreg_l1d_0p8>;
> vdda-pll-supply = <&vreg_l2j_1p2>;
> diff --git a/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi b/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi
> index d77be02848b5..ba6b7b5a9191 100644
> --- a/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi
> +++ b/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi
> @@ -964,9 +964,6 @@ wifi@0 {
> };
>
> &pcie6a {
> - perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
> - wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
> -
> vddpe-3v3-supply = <&vreg_nvme>;
>
> pinctrl-0 = <&pcie6a_default>;
> @@ -982,6 +979,11 @@ &pcie6a_phy {
> status = "okay";
> };
>
> +&pcie6a_port0 {
> + reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
> + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
> +};
> +
> &pm8550_gpios {
> rtmr0_default: rtmr0-reset-n-active-state {
> pins = "gpio10";
> diff --git a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts
> index d6472e5a3f9f..d7938d349205 100644
> --- a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts
> +++ b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts
> @@ -1126,9 +1126,6 @@ &mdss_dp3_phy {
> };
>
> &pcie4 {
> - perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
> - wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
> -
> pinctrl-0 = <&pcie4_default>;
> pinctrl-names = "default";
>
> @@ -1143,6 +1140,9 @@ &pcie4_phy {
> };
>
> &pcie4_port0 {
> + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
> + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
> +
> wifi@0 {
> compatible = "pci17cb,1107";
> reg = <0x10000 0x0 0x0 0x0 0x0>;
> diff --git a/arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts b/arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts
> index 20a33e6f27ee..3af7f19224ad 100644
> --- a/arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts
> +++ b/arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts
> @@ -1033,9 +1033,6 @@ &mdss_dp3_phy {
> };
>
> &pcie4 {
> - perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
> - wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
> -
> pinctrl-0 = <&pcie4_default>;
> pinctrl-names = "default";
>
> @@ -1050,6 +1047,8 @@ &pcie4_phy {
> };
>
> &pcie4_port0 {
> + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
> + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
> wifi@0 {
> compatible = "pci17cb,1107";
> reg = <0x10000 0x0 0x0 0x0 0x0>;
> @@ -1067,10 +1066,6 @@ wifi@0 {
> };
>
> &pcie6a {
> - perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
> -
> - wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
> -
> vddpe-3v3-supply = <&vreg_nvme>;
>
> pinctrl-0 = <&pcie6a_default>;
> @@ -1086,6 +1081,12 @@ &pcie6a_phy {
> status = "okay";
> };
>
> +&pcie6a_port0 {
> + reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
> + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
> +};
> +
> +
> &pm8550_gpios {
> rtmr0_default: rtmr0-reset-n-active-state {
> pins = "gpio10";
> diff --git a/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts b/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts
> index 1e5eb8c5dc98..06747b54a38e 100644
> --- a/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts
> +++ b/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts
> @@ -1131,9 +1131,6 @@ &mdss_dp3_phy {
> };
>
> &pcie4 {
> - perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
> - wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
> -
> pinctrl-0 = <&pcie4_default>;
> pinctrl-names = "default";
>
> @@ -1148,6 +1145,9 @@ &pcie4_phy {
> };
>
> &pcie4_port0 {
> + reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
> + wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
> +
> wifi@0 {
> compatible = "pci17cb,1107";
> reg = <0x10000 0x0 0x0 0x0 0x0>;
> @@ -1165,9 +1165,6 @@ wifi@0 {
> };
>
> &pcie6a {
> - perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
> - wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
> -
> vddpe-3v3-supply = <&vreg_nvme>;
>
> pinctrl-0 = <&pcie6a_default>;
> @@ -1183,6 +1180,11 @@ &pcie6a_phy {
> status = "okay";
> };
>
> +&pcie6a_port0 {
> + reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
> + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
> +};
> +
> &pm8550_pwm {
> status = "okay";
> };
> --
> 2.43.0
>
--
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linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply
* [PATCH v1 1/1] arm64: dts: qcom: hamoa: Move PCIe PERST and Wake GPIOs to port nodes
From: Ziyue Zhang @ 2026-03-13 9:46 UTC (permalink / raw)
To: andersson, konradybcio, robh, krzk+dt, conor+dt, ziyue.zhang,
jingoohan1, mani, lpieralisi, kwilczynski, bhelgaas, johan+linaro,
vkoul, kishon, neil.armstrong, abel.vesa, kw
Cc: linux-arm-msm, devicetree, linux-kernel, linux-pci, linux-phy,
qiang.yu, quic_krichai, quic_vbadigan
Commit 960609b22be5 ("arm64: dts: qcom: hamoa: Move PHY, PERST, and Wake
GPIOs to PCIe port nodes and add port Nodes for all PCIe ports") did not
convert all Hamoa‑based platforms to the new method of defining PERST and
Wake GPIOs in the PCIe root port nodes.
Without the change PCIe probe will fail. The probe failure happens because
the PHY stays in the controller node while the PERST/Wake GPIOs were moved
to the port nodes.
This fixes probe failures seen on the following platforms:
- x1-hp-omnibook-x14
- x1-microsoft-denali
- x1e80100-lenovo-yoga-slim7x
- x1e80100-medion-sprchrgd-14-s1
- x1p42100-lenovo-thinkbook-16
- x1-asus-zenbook-a14
- x1-crd
- x1-dell-thena
Fixes: 960609b22be5 ("arm64: dts: qcom: hamoa: Move PHY, PERST, and Wake GPIOs to PCIe port nodes and add port Nodes for all PCIe ports")
Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
---
.../boot/dts/qcom/x1-asus-zenbook-a14.dtsi | 16 ++++++++-----
arch/arm64/boot/dts/qcom/x1-crd.dtsi | 24 ++++++++++++-------
arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi | 14 ++++++-----
.../boot/dts/qcom/x1-hp-omnibook-x14.dtsi | 14 ++++++-----
.../boot/dts/qcom/x1-microsoft-denali.dtsi | 8 ++++---
.../dts/qcom/x1e80100-lenovo-yoga-slim7x.dts | 6 ++---
.../qcom/x1e80100-medion-sprchrgd-14-s1.dts | 15 ++++++------
.../dts/qcom/x1p42100-lenovo-thinkbook-16.dts | 14 ++++++-----
8 files changed, 65 insertions(+), 46 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi b/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi
index 8e5c5575a532..0a382cc9e643 100644
--- a/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1-asus-zenbook-a14.dtsi
@@ -1032,9 +1032,6 @@ &mdss_dp3_phy {
};
&pcie4 {
- perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie4_default>;
pinctrl-names = "default";
@@ -1048,10 +1045,12 @@ &pcie4_phy {
status = "okay";
};
-&pcie6a {
- perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+&pcie4_port0 {
+ reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+};
+&pcie6a {
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-0 = <&pcie6a_default>;
@@ -1067,6 +1066,11 @@ &pcie6a_phy {
status = "okay";
};
+&pcie6a_port0 {
+ reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+};
+
&pm8550_gpios {
rtmr0_default: rtmr0-reset-n-active-state {
pins = "gpio10";
diff --git a/arch/arm64/boot/dts/qcom/x1-crd.dtsi b/arch/arm64/boot/dts/qcom/x1-crd.dtsi
index ded96fb43489..2fbf9ec66fb8 100644
--- a/arch/arm64/boot/dts/qcom/x1-crd.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1-crd.dtsi
@@ -1216,15 +1216,17 @@ &mdss_dp3_phy {
};
&pcie4 {
- perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie4_default>;
pinctrl-names = "default";
status = "okay";
};
+&pcie4_port0 {
+ reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+};
+
&pcie4_phy {
vdda-phy-supply = <&vreg_l3i_0p8>;
vdda-pll-supply = <&vreg_l3e_1p2>;
@@ -1233,9 +1235,6 @@ &pcie4_phy {
};
&pcie5 {
- perst-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_wwan>;
pinctrl-0 = <&pcie5_default>;
@@ -1251,10 +1250,12 @@ &pcie5_phy {
status = "okay";
};
-&pcie6a {
- perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+&pcie5_port0 {
+ reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
+};
+&pcie6a {
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-names = "default";
@@ -1270,6 +1271,11 @@ &pcie6a_phy {
status = "okay";
};
+&pcie6a_port0 {
+ reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+};
+
&pm8550_gpios {
kypd_vol_up_n: kypd-vol-up-n-state {
pins = "gpio6";
diff --git a/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi b/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi
index bf04a12b16bc..217ca8c7d81d 100644
--- a/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1-dell-thena.dtsi
@@ -1081,9 +1081,6 @@ &mdss_dp3_phy {
};
&pcie4 {
- perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie4_default>;
pinctrl-names = "default";
@@ -1098,6 +1095,9 @@ &pcie4_phy {
};
&pcie4_port0 {
+ reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;
@@ -1115,9 +1115,6 @@ wifi@0 {
};
&pcie6a {
- perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-0 = <&pcie6a_default>;
@@ -1126,6 +1123,11 @@ &pcie6a {
status = "okay";
};
+&pcie6a_port0 {
+ reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+};
+
&pcie6a_phy {
vdda-phy-supply = <&vreg_l1d_0p8>;
vdda-pll-supply = <&vreg_l2j_1p2>;
diff --git a/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi b/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi
index a4075434162a..41063948c583 100644
--- a/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1-hp-omnibook-x14.dtsi
@@ -1065,9 +1065,6 @@ &mdss_dp3_phy {
};
&pcie4 {
- perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie4_default>;
pinctrl-names = "default";
@@ -1082,6 +1079,9 @@ &pcie4_phy {
};
&pcie4_port0 {
+ reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;
@@ -1099,9 +1099,6 @@ wifi@0 {
};
&pcie6a {
- perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-0 = <&pcie6a_default>;
@@ -1110,6 +1107,11 @@ &pcie6a {
status = "okay";
};
+&pcie6a_port0 {
+ reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+};
+
&pcie6a_phy {
vdda-phy-supply = <&vreg_l1d_0p8>;
vdda-pll-supply = <&vreg_l2j_1p2>;
diff --git a/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi b/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi
index d77be02848b5..ba6b7b5a9191 100644
--- a/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1-microsoft-denali.dtsi
@@ -964,9 +964,6 @@ wifi@0 {
};
&pcie6a {
- perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-0 = <&pcie6a_default>;
@@ -982,6 +979,11 @@ &pcie6a_phy {
status = "okay";
};
+&pcie6a_port0 {
+ reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+};
+
&pm8550_gpios {
rtmr0_default: rtmr0-reset-n-active-state {
pins = "gpio10";
diff --git a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts
index d6472e5a3f9f..d7938d349205 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts
+++ b/arch/arm64/boot/dts/qcom/x1e80100-lenovo-yoga-slim7x.dts
@@ -1126,9 +1126,6 @@ &mdss_dp3_phy {
};
&pcie4 {
- perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie4_default>;
pinctrl-names = "default";
@@ -1143,6 +1140,9 @@ &pcie4_phy {
};
&pcie4_port0 {
+ reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;
diff --git a/arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts b/arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts
index 20a33e6f27ee..3af7f19224ad 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts
+++ b/arch/arm64/boot/dts/qcom/x1e80100-medion-sprchrgd-14-s1.dts
@@ -1033,9 +1033,6 @@ &mdss_dp3_phy {
};
&pcie4 {
- perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie4_default>;
pinctrl-names = "default";
@@ -1050,6 +1047,8 @@ &pcie4_phy {
};
&pcie4_port0 {
+ reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;
@@ -1067,10 +1066,6 @@ wifi@0 {
};
&pcie6a {
- perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
-
- wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-0 = <&pcie6a_default>;
@@ -1086,6 +1081,12 @@ &pcie6a_phy {
status = "okay";
};
+&pcie6a_port0 {
+ reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+};
+
+
&pm8550_gpios {
rtmr0_default: rtmr0-reset-n-active-state {
pins = "gpio10";
diff --git a/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts b/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts
index 1e5eb8c5dc98..06747b54a38e 100644
--- a/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts
+++ b/arch/arm64/boot/dts/qcom/x1p42100-lenovo-thinkbook-16.dts
@@ -1131,9 +1131,6 @@ &mdss_dp3_phy {
};
&pcie4 {
- perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
-
pinctrl-0 = <&pcie4_default>;
pinctrl-names = "default";
@@ -1148,6 +1145,9 @@ &pcie4_phy {
};
&pcie4_port0 {
+ reset-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+
wifi@0 {
compatible = "pci17cb,1107";
reg = <0x10000 0x0 0x0 0x0 0x0>;
@@ -1165,9 +1165,6 @@ wifi@0 {
};
&pcie6a {
- perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
- wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
-
vddpe-3v3-supply = <&vreg_nvme>;
pinctrl-0 = <&pcie6a_default>;
@@ -1183,6 +1180,11 @@ &pcie6a_phy {
status = "okay";
};
+&pcie6a_port0 {
+ reset-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
+};
+
&pm8550_pwm {
status = "okay";
};
--
2.43.0
--
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https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* Re: [PATCH 48/61] mtd: Prefer IS_ERR_OR_NULL over manual NULL check
From: Richard Weinberger @ 2026-03-12 19:33 UTC (permalink / raw)
To: Philipp Hahn
Cc: amd-gfx, apparmor, bpf, ceph-devel, cocci, dm-devel,
DRI mailing list, gfs2, intel-gfx, intel-wired-lan, iommu, kvm,
linux-arm-kernel, linux-block, linux-bluetooth, linux-btrfs,
linux-cifs, linux-clk, linux-erofs, linux-ext4, linux-fsdevel,
linux-gpio, linux-hyperv, linux-input, linux-kernel, linux-leds,
linux-media, linux-mips, linux-mm, linux-modules, linux-mtd,
linux-nfs, linux-omap, linux-phy, linux-pm, linux-rockchip,
linux-s390, linux-scsi, linux-sctp, LSM, linux-sh, linux-sound,
linux-stm32, linux-trace-kernel, linux-usb, linux-wireless,
netdev, ntfs3, samba-technical, sched-ext, target-devel,
tipc-discussion, v9fs, Miquel Raynal, Vignesh Raghavendra
In-Reply-To: <20260310-b4-is_err_or_null-v1-48-bd63b656022d@avm.de>
----- Ursprüngliche Mail -----
> Von: "Philipp Hahn" <phahn-oss@avm.de>
> - if (gpiomtd->nwp && !IS_ERR(gpiomtd->nwp))
> + if (!IS_ERR_OR_NULL(gpiomtd->nwp))
No, please don't.
This makes reading the code not easier.
Thanks,
//richard
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^ permalink raw reply
* Re: [PATCH 00/61] treewide: Use IS_ERR_OR_NULL over manual NULL check - refactor
From: Jason Gunthorpe @ 2026-03-12 16:54 UTC (permalink / raw)
To: James Bottomley
Cc: Kuan-Wei Chiu, Philipp Hahn, amd-gfx, apparmor, bpf, ceph-devel,
cocci, dm-devel, dri-devel, gfs2, intel-gfx, intel-wired-lan,
iommu, kvm, linux-arm-kernel, linux-block, linux-bluetooth,
linux-btrfs, linux-cifs, linux-clk, linux-erofs, linux-ext4,
linux-fsdevel, linux-gpio, linux-hyperv, linux-input,
linux-kernel, linux-leds, linux-media, linux-mips, linux-mm,
linux-modules, linux-mtd, linux-nfs, linux-omap, linux-phy,
linux-pm, linux-rockchip, linux-s390, linux-scsi, linux-sctp,
linux-security-module, linux-sh, linux-sound, linux-stm32,
linux-trace-kernel, linux-usb, linux-wireless, netdev, ntfs3,
samba-technical, sched-ext, target-devel, tipc-discussion, v9fs
In-Reply-To: <f5688b895eaebabae6545a0d9baf8f1404e8454e.camel@HansenPartnership.com>
On Thu, Mar 12, 2026 at 11:32:37AM -0400, James Bottomley wrote:
> On Thu, 2026-03-12 at 09:57 -0300, Jason Gunthorpe wrote:
> > On Wed, Mar 11, 2026 at 02:40:36AM +0800, Kuan-Wei Chiu wrote:
> >
> > > IMHO, the necessity of IS_ERR_OR_NULL() often highlights a
> > > confusing or flawed API design. It usually implies that the caller
> > > is unsure whether a failure results in an error pointer or a NULL
> > > pointer.
> >
> > +1
> >
> > IS_ERR_OR_NULL() should always be looked on with suspicion. Very
> > little should be returning some tri-state 'ERR' 'NULL' 'SUCCESS'
> > pointer. What does the middle condition even mean? IS_ERR_OR_NULL()
> > implies ERR and NULL are semanticly the same, so fix the things to
> > always use ERR.
>
> Not in any way supporting the original patch. However, the pattern
> ERR, NULL, PTR is used extensively in the dentry code of filesystems.
> See the try_lookup..() set of functions in fs/namei.c
>
> The meaning is
>
> PTR - I found it
> NULL - It definitely doesn't exist
> ERR - something went wrong during the lookup.
>
> So I don't think you can blanket say this pattern is wrong.
Lots of places also would return ENOENT, I'd argue that is easier to
use..
But yes, I did use the word "suspicion" not blanket wrong :)
Jason
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^ permalink raw reply
* [PATCH 2/2] phy: econet: Add PCIe PHY driver for EcoNet EN751221 and EN7528 SoCs.
From: Caleb James DeLisle @ 2026-03-12 16:44 UTC (permalink / raw)
To: linux-phy
Cc: naseefkm, vkoul, neil.armstrong, robh, krzk+dt, conor+dt,
linux-mips, devicetree, linux-kernel, Caleb James DeLisle
In-Reply-To: <20260312164432.569566-1-cjd@cjdns.fr>
Introduce support for EcoNet PCIe PHY controllers found in EN751221
and EN7528 SoCs, these SoCs are not identical but are similar, each
having one Gen1 port, and one Gen1/Gen2 port.
Co-developed-by: Ahmed Naseef <naseefkm@gmail.com>
Signed-off-by: Ahmed Naseef <naseefkm@gmail.com>
[cjd@cjdns.fr: add EN751221 support and refactor for clarity]
Co-developed-by: Caleb James DeLisle <cjd@cjdns.fr>
Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
---
MAINTAINERS | 1 +
drivers/phy/Kconfig | 12 +++
drivers/phy/Makefile | 1 +
drivers/phy/phy-econet-pcie.c | 180 ++++++++++++++++++++++++++++++++++
4 files changed, 194 insertions(+)
create mode 100644 drivers/phy/phy-econet-pcie.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 557b6a47ec98..0b2b129e168b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9125,6 +9125,7 @@ M: Caleb James DeLisle <cjd@cjdns.fr>
L: linux-mips@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/phy/econet,en751221-pcie-phy.yaml
+F: drivers/phy/phy-econet-pcie.c
ECRYPT FILE SYSTEM
M: Tyler Hicks <code@tyhicks.com>
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 02467dfd4fb0..60efc37f6eb0 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -123,6 +123,18 @@ config PHY_AIROHA_PCIE
This driver create the basic PHY instance and provides initialize
callback for PCIe GEN3 port.
+config PHY_ECONET_PCIE
+ tristate "EcoNet PCIe-PHY Driver"
+ depends on ECONET || COMPILE_TEST
+ depends on OF
+ select GENERIC_PHY
+ select REGMAP_MMIO
+ help
+ Say Y here to add support for EcoNet PCIe PHY driver.
+ This driver create the basic PHY instance and provides initialize
+ callback for PCIe GEN1 and GEN2 ports. This PHY is found on
+ EcoNet SoCs including EN751221 and EN7528.
+
config PHY_NXP_PTN3222
tristate "NXP PTN3222 1-port eUSB2 to USB2 redriver"
depends on I2C
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index a648c2e02a83..a77f182ee8f3 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
obj-$(CONFIG_PHY_SNPS_EUSB2) += phy-snps-eusb2.o
obj-$(CONFIG_USB_LGM_PHY) += phy-lgm-usb.o
obj-$(CONFIG_PHY_AIROHA_PCIE) += phy-airoha-pcie.o
+obj-$(CONFIG_PHY_ECONET_PCIE) += phy-econet-pcie.o
obj-$(CONFIG_PHY_NXP_PTN3222) += phy-nxp-ptn3222.o
obj-$(CONFIG_PHY_SPACEMIT_K1_PCIE) += phy-spacemit-k1-pcie.o
obj-$(CONFIG_GENERIC_PHY) += allwinner/ \
diff --git a/drivers/phy/phy-econet-pcie.c b/drivers/phy/phy-econet-pcie.c
new file mode 100644
index 000000000000..d2c6e0c1f331
--- /dev/null
+++ b/drivers/phy/phy-econet-pcie.c
@@ -0,0 +1,180 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Author: Caleb James DeLisle <cjd@cjdns.fr>
+ * Ahmed Naseef <naseefkm@gmail.com>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+/* Rx detection timing for EN751221: 16*8 clock cycles */
+#define EN751221_RXDET_VAL 16
+
+/* Rx detection timing when in power mode 3 */
+#define EN75_RXDET_P3_REG 0xa28
+#define EN75_RXDET_P3_MASK GENMASK(17, 9)
+
+/* Rx detection timing when in power mode 2 */
+#define EN75_RXDET_P2_REG 0xa2c
+#define EN75_RXDET_P2_MASK GENMASK(8, 0)
+
+/* Rx impedance */
+#define EN75_RX_IMPEDANCE_REG 0xb2c
+#define EN75_RX_IMPEDANCE_MASK GENMASK(13, 12)
+enum en75_rx_impedance {
+ EN75_RX_IMPEDANCE_100_OHM = 0,
+ EN75_RX_IMPEDANCE_95_OHM = 1,
+ EN75_RX_IMPEDANCE_90_OHM = 2,
+};
+
+/* PLL Invert clock */
+#define EN75_PLL_PH_INV_REG 0x4a0
+#define EN75_PLL_PH_INV_MASK BIT(5)
+
+struct en75_phy_op {
+ u32 reg;
+ u32 mask;
+ u32 val;
+};
+
+struct en7528_pcie_phy {
+ struct regmap *regmap;
+ const struct en75_phy_op *data;
+};
+
+/* Port 0 PHY: set LCDDS_CLK_PH_INV for PLL operation */
+static const struct en75_phy_op en7528_phy_gen1[] = {
+ {
+ .reg = EN75_PLL_PH_INV_REG,
+ .mask = EN75_PLL_PH_INV_MASK,
+ .val = 1,
+ },
+ { /* sentinel */ }
+};
+
+/* EN7528 Port 1 PHY: Rx impedance tuning, target R -5 Ohm */
+static const struct en75_phy_op en7528_phy_gen2[] = {
+ {
+ .reg = EN75_RX_IMPEDANCE_REG,
+ .mask = EN75_RX_IMPEDANCE_MASK,
+ .val = EN75_RX_IMPEDANCE_95_OHM,
+ },
+ { /* sentinel */ }
+};
+
+/* EN751221 Port 1 PHY, set RX detect to 16*8 clock cycles */
+static const struct en75_phy_op en751221_phy_gen2[] = {
+ {
+ .reg = EN75_RXDET_P3_REG,
+ .mask = EN75_RXDET_P3_MASK,
+ .val = EN751221_RXDET_VAL,
+ },
+ {
+ .reg = EN75_RXDET_P2_REG,
+ .mask = EN75_RXDET_P2_MASK,
+ .val = EN751221_RXDET_VAL,
+ },
+ { /* sentinel */ }
+};
+
+static int en75_pcie_phy_init(struct phy *phy)
+{
+ struct en7528_pcie_phy *ephy = phy_get_drvdata(phy);
+ const struct en75_phy_op *data = ephy->data;
+ int i, ret;
+ u32 val;
+
+ for (i = 0; data[i].mask || data[i].val; i++) {
+ if (i)
+ usleep_range(1000, 2000);
+
+ val = field_prep(data[i].mask, data[i].val);
+
+ ret = regmap_update_bits(ephy->regmap, data[i].reg,
+ data[i].mask, val);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct phy_ops en75_pcie_phy_ops = {
+ .init = en75_pcie_phy_init,
+ .owner = THIS_MODULE,
+};
+
+static int en75_pcie_phy_probe(struct platform_device *pdev)
+{
+ struct regmap_config regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ };
+ struct device *dev = &pdev->dev;
+ const struct en75_phy_op *data;
+ struct phy_provider *provider;
+ struct en7528_pcie_phy *ephy;
+ void __iomem *base;
+ struct phy *phy;
+ int i;
+
+ data = of_device_get_match_data(dev);
+ if (!data)
+ return -EINVAL;
+
+ ephy = devm_kzalloc(dev, sizeof(*ephy), GFP_KERNEL);
+ if (!ephy)
+ return -ENOMEM;
+
+ ephy->data = data;
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ /* Set max_register to highest used register */
+ for (i = 0; data[i].mask || data[i].val; i++)
+ if (data[i].reg > regmap_config.max_register)
+ regmap_config.max_register = data[i].reg;
+
+ ephy->regmap = devm_regmap_init_mmio(dev, base, ®map_config);
+ if (IS_ERR(ephy->regmap))
+ return PTR_ERR(ephy->regmap);
+
+ phy = devm_phy_create(dev, dev->of_node, &en75_pcie_phy_ops);
+ if (IS_ERR(phy))
+ return PTR_ERR(phy);
+
+ phy_set_drvdata(phy, ephy);
+
+ provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+ return PTR_ERR_OR_ZERO(provider);
+}
+
+static const struct of_device_id en75_pcie_phy_ids[] = {
+ { .compatible = "econet,en7528-pcie-gen1", .data = en7528_phy_gen1 },
+ { .compatible = "econet,en7528-pcie-gen2", .data = en7528_phy_gen2 },
+ { .compatible = "econet,en751221-pcie-gen1", .data = en7528_phy_gen1 },
+ { .compatible = "econet,en751221-pcie-gen2", .data = en751221_phy_gen2 },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, en75_pcie_phy_ids);
+
+static struct platform_driver en75_pcie_phy_driver = {
+ .probe = en75_pcie_phy_probe,
+ .driver = {
+ .name = "econet-pcie-phy",
+ .of_match_table = en75_pcie_phy_ids,
+ },
+};
+module_platform_driver(en75_pcie_phy_driver);
+
+MODULE_AUTHOR("Caleb James DeLisle <cjd@cjdns.fr>");
+MODULE_DESCRIPTION("EcoNet PCIe PHY driver");
+MODULE_LICENSE("GPL");
--
2.39.5
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^ permalink raw reply related
* [PATCH 1/2] dt-bindings: phy: Document PCIe PHY in EcoNet EN751221 and EN7528
From: Caleb James DeLisle @ 2026-03-12 16:44 UTC (permalink / raw)
To: linux-phy
Cc: naseefkm, vkoul, neil.armstrong, robh, krzk+dt, conor+dt,
linux-mips, devicetree, linux-kernel, Caleb James DeLisle,
Krzysztof Kozlowski
In-Reply-To: <20260312164432.569566-1-cjd@cjdns.fr>
EN751221 and EN7528 SoCs have two PCIe slots, and each one has a PHY
which behaves slightly differently because one slot is Gen1/Gen2 while
the other is Gen1 only.
Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
.../phy/econet,en751221-pcie-phy.yaml | 50 +++++++++++++++++++
MAINTAINERS | 6 +++
2 files changed, 56 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/econet,en751221-pcie-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/econet,en751221-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/econet,en751221-pcie-phy.yaml
new file mode 100644
index 000000000000..987d396c1c64
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/econet,en751221-pcie-phy.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/econet,en751221-pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: EcoNet PCI-Express PHY for EcoNet EN751221 and EN7528
+
+maintainers:
+ - Caleb James DeLisle <cjd@cjdns.fr>
+
+description:
+ The PCIe PHY supports physical layer functionality for PCIe Gen1 and
+ Gen1/Gen2 ports. On these SoCs, port 0 is a Gen1-only port while
+ port 1 is Gen1/Gen2 capable.
+
+properties:
+ compatible:
+ enum:
+ - econet,en751221-pcie-gen1
+ - econet,en751221-pcie-gen2
+ - econet,en7528-pcie-gen1
+ - econet,en7528-pcie-gen2
+
+ reg:
+ maxItems: 1
+
+ "#phy-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ pcie-phy@1faf2000 {
+ compatible = "econet,en7528-pcie-gen1";
+ reg = <0x1faf2000 0x1000>;
+ #phy-cells = <0>;
+ };
+ };
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 14899f1de77e..557b6a47ec98 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9120,6 +9120,12 @@ F: arch/mips/econet/
F: drivers/clocksource/timer-econet-en751221.c
F: drivers/irqchip/irq-econet-en751221.c
+ECONET PCIE PHY DRIVER
+M: Caleb James DeLisle <cjd@cjdns.fr>
+L: linux-mips@vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/phy/econet,en751221-pcie-phy.yaml
+
ECRYPT FILE SYSTEM
M: Tyler Hicks <code@tyhicks.com>
L: ecryptfs@vger.kernel.org
--
2.39.5
--
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^ permalink raw reply related
* [PATCH 0/2] phy: econet: Add PCIe PHY driver for EcoNet SoCs
From: Caleb James DeLisle @ 2026-03-12 16:44 UTC (permalink / raw)
To: linux-phy
Cc: naseefkm, vkoul, neil.armstrong, robh, krzk+dt, conor+dt,
linux-mips, devicetree, linux-kernel, Caleb James DeLisle
Add EcoNet EN751221 and EN7528 PCIe PHY support.
This is split from a larger PCIe patchset which crossed multiple
subsystems. I'm not labeling this a v3 because it's a new patchset, but
I'm keeping the historical record anyway.
Changes from econet-pcie v2: none relevant to this patch set
* econet-pcie v2: https://lore.kernel.org/linux-mips/20260309131818.74467-1-cjd@cjdns.fr
Changes from econet-pcie v1:
* econet,en751221-pcie-phy.yaml Refer to PHYs as "gen1" and "gen2"
* econet-pcie v1: https://lore.kernel.org/linux-mips/20260303190948.694783-1-cjd@cjdns.fr/
Caleb James DeLisle (2):
dt-bindings: phy: Document PCIe PHY in EcoNet EN751221 and EN7528
phy: econet: Add PCIe PHY driver for EcoNet EN751221 and EN7528 SoCs.
.../phy/econet,en751221-pcie-phy.yaml | 50 +++++
MAINTAINERS | 7 +
drivers/phy/Kconfig | 12 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-econet-pcie.c | 180 ++++++++++++++++++
5 files changed, 250 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/econet,en751221-pcie-phy.yaml
create mode 100644 drivers/phy/phy-econet-pcie.c
base-commit: 3fa5e5702a82d259897bd7e209469bc06368bf31
--
2.39.5
--
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^ permalink raw reply
* Re: [PATCH 38/61] net: Prefer IS_ERR_OR_NULL over manual NULL check
From: Przemek Kitszel @ 2026-03-12 16:11 UTC (permalink / raw)
To: Philipp Hahn
Cc: amd-gfx, apparmor, bpf, ceph-devel, cocci, dm-devel, dri-devel,
gfs2, intel-gfx, intel-wired-lan, iommu, kvm, linux-arm-kernel,
linux-block, linux-bluetooth, linux-btrfs, linux-cifs, linux-clk,
linux-erofs, linux-ext4, linux-fsdevel, linux-gpio, linux-hyperv,
linux-input, linux-kernel, linux-leds, linux-media, linux-mips,
linux-mm, linux-modules, linux-mtd, linux-nfs, linux-omap,
linux-phy, linux-pm, linux-rockchip, linux-s390, linux-scsi,
linux-sctp, linux-security-module, linux-sh, linux-sound,
linux-stm32, linux-trace-kernel, linux-usb, linux-wireless,
netdev, ntfs3, samba-technical, sched-ext, target-devel,
tipc-discussion, v9fs, Igor Russkikh, Andrew Lunn,
David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
Pavan Chebbi, Michael Chan, Potnuri Bharat Teja, Tony Nguyen,
Taras Chornyi, Maxime Coquelin, Alexandre Torgue,
Iyappan Subramanian, Keyur Chudgar, Quan Nguyen, Heiner Kallweit,
Russell King
In-Reply-To: <20260310-b4-is_err_or_null-v1-38-bd63b656022d@avm.de>
On 3/10/26 12:49, Philipp Hahn wrote:
> Prefer using IS_ERR_OR_NULL() over using IS_ERR() and a manual NULL
> check.
>
> Change generated with coccinelle.
>
> To: Igor Russkikh <irusskikh@marvell.com>
> To: Andrew Lunn <andrew+netdev@lunn.ch>
> To: "David S. Miller" <davem@davemloft.net>
> To: Eric Dumazet <edumazet@google.com>
> To: Jakub Kicinski <kuba@kernel.org>
> To: Paolo Abeni <pabeni@redhat.com>
> To: Pavan Chebbi <pavan.chebbi@broadcom.com>
> To: Michael Chan <mchan@broadcom.com>
> To: Potnuri Bharat Teja <bharat@chelsio.com>
> To: Tony Nguyen <anthony.l.nguyen@intel.com>
> To: Przemek Kitszel <przemyslaw.kitszel@intel.com>
> To: Taras Chornyi <taras.chornyi@plvision.eu>
> To: Maxime Coquelin <mcoquelin.stm32@gmail.com>
> To: Alexandre Torgue <alexandre.torgue@foss.st.com>
> To: Iyappan Subramanian <iyappan@os.amperecomputing.com>
> To: Keyur Chudgar <keyur@os.amperecomputing.com>
> To: Quan Nguyen <quan@os.amperecomputing.com>
> To: Heiner Kallweit <hkallweit1@gmail.com>
> To: Russell King <linux@armlinux.org.uk>
> Cc: netdev@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> Cc: intel-wired-lan@lists.osuosl.org
> Cc: linux-stm32@st-md-mailman.stormreply.com
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-usb@vger.kernel.org
> Signed-off-by: Philipp Hahn <phahn-oss@avm.de>
this is too trivial change, especially when combined like that
https://docs.kernel.org/process/maintainer-netdev.html#clean-up-patches
> ---
> drivers/net/ethernet/aquantia/atlantic/aq_ring.c | 2 +-
> drivers/net/ethernet/broadcom/tg3.c | 2 +-
> drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c | 3 +--
> drivers/net/ethernet/intel/ice/devlink/devlink.c | 2 +-
> drivers/net/ethernet/marvell/prestera/prestera_router.c | 2 +-
> drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 2 +-
> drivers/net/mdio/mdio-xgene.c | 2 +-
> drivers/net/usb/r8152.c | 2 +-
> 8 files changed, 8 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_ring.c b/drivers/net/ethernet/aquantia/atlantic/aq_ring.c
> index e270327e47fd804cc8ee5cfd53ed1b993c955c41..43edef35c4b1ff606b2f1519a07fad4c9a990ad4 100644
> --- a/drivers/net/ethernet/aquantia/atlantic/aq_ring.c
> +++ b/drivers/net/ethernet/aquantia/atlantic/aq_ring.c
> @@ -810,7 +810,7 @@ static int __aq_ring_xdp_clean(struct aq_ring_s *rx_ring,
> }
>
> skb = aq_xdp_run_prog(aq_nic, &xdp, rx_ring, buff);
> - if (IS_ERR(skb) || !skb)
> + if (IS_ERR_OR_NULL(skb))
> continue;
>
> if (ptp_hwtstamp_len > 0)
> diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c
> index 2328fce336447eb4a796f9300ccc0ab536ff0a35..8ed79f34f03d81184dcc12e6eaff009cb8f7756e 100644
> --- a/drivers/net/ethernet/broadcom/tg3.c
> +++ b/drivers/net/ethernet/broadcom/tg3.c
> @@ -7943,7 +7943,7 @@ static int tg3_tso_bug(struct tg3 *tp, struct tg3_napi *tnapi,
>
> segs = skb_gso_segment(skb, tp->dev->features &
> ~(NETIF_F_TSO | NETIF_F_TSO6));
> - if (IS_ERR(segs) || !segs) {
> + if (IS_ERR_OR_NULL(segs)) {
> tnapi->tx_dropped++;
> goto tg3_tso_bug_end;
> }
> diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c
> index 3307e50426819087ad985178c4a5383f16b8e7b4..1c8a6445d4b2e3535d8f1b7908dd02d8dd2f23fa 100644
> --- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c
> +++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_tc_flower.c
> @@ -1032,8 +1032,7 @@ static void ch_flower_stats_handler(struct work_struct *work)
> do {
> rhashtable_walk_start(&iter);
>
> - while ((flower_entry = rhashtable_walk_next(&iter)) &&
> - !IS_ERR(flower_entry)) {
> + while (!IS_ERR_OR_NULL((flower_entry = rhashtable_walk_next(&iter)))) {
> ret = cxgb4_get_filter_counters(adap->port[0],
> flower_entry->filter_id,
> &packets, &bytes,
> diff --git a/drivers/net/ethernet/intel/ice/devlink/devlink.c b/drivers/net/ethernet/intel/ice/devlink/devlink.c
> index 6c72bd15db6d75a1d4fa04ef8fefbd26fb6e84bd..3d08b9187fd76ca3198af28111b6f1c1765ea01e 100644
> --- a/drivers/net/ethernet/intel/ice/devlink/devlink.c
> +++ b/drivers/net/ethernet/intel/ice/devlink/devlink.c
> @@ -791,7 +791,7 @@ static void ice_traverse_tx_tree(struct devlink *devlink, struct ice_sched_node
> node->parent->rate_node);
> }
>
> - if (rate_node && !IS_ERR(rate_node))
> + if (!IS_ERR_OR_NULL(rate_node))
> node->rate_node = rate_node;
>
> traverse_children:
> diff --git a/drivers/net/ethernet/marvell/prestera/prestera_router.c b/drivers/net/ethernet/marvell/prestera/prestera_router.c
> index b036b173a308b5f994ad8538eb010fa27196988c..4492938e8a3da91d32efe8d45ccbe2eb437c0e49 100644
> --- a/drivers/net/ethernet/marvell/prestera/prestera_router.c
> +++ b/drivers/net/ethernet/marvell/prestera/prestera_router.c
> @@ -1061,7 +1061,7 @@ static void __prestera_k_arb_hw_state_upd(struct prestera_switch *sw,
> n = NULL;
> }
>
> - if (!IS_ERR(n) && n) {
> + if (!IS_ERR_OR_NULL(n)) {
> neigh_event_send(n, NULL);
> neigh_release(n);
> } else {
> diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> index 6827c99bde8c22db42b363d2d36ad6f26075ed50..356a4e9ce04b1fcf8786d7274d31ace404be2cf6 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> @@ -1275,7 +1275,7 @@ static int stmmac_init_phy(struct net_device *dev)
> /* Some DT bindings do not set-up the PHY handle. Let's try to
> * manually parse it
> */
> - if (!phy_fwnode || IS_ERR(phy_fwnode)) {
> + if (IS_ERR_OR_NULL(phy_fwnode)) {
> int addr = priv->plat->phy_addr;
> struct phy_device *phydev;
>
> diff --git a/drivers/net/mdio/mdio-xgene.c b/drivers/net/mdio/mdio-xgene.c
> index a8f91a4b7fed0927ee14e408000cd3a2bfb9b09a..09b30b563295c6085dc1358ac361301e5cf6b2a8 100644
> --- a/drivers/net/mdio/mdio-xgene.c
> +++ b/drivers/net/mdio/mdio-xgene.c
> @@ -265,7 +265,7 @@ struct phy_device *xgene_enet_phy_register(struct mii_bus *bus, int phy_addr)
> struct phy_device *phy_dev;
>
> phy_dev = get_phy_device(bus, phy_addr, false);
> - if (!phy_dev || IS_ERR(phy_dev))
> + if (IS_ERR_OR_NULL(phy_dev))
> return NULL;
>
> if (phy_device_register(phy_dev))
> diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c
> index 0c83bbbea2e7c322ee6339893e281237663bd3ae..73f17ebd7d40007eec5004f887a46249defd28ab 100644
> --- a/drivers/net/usb/r8152.c
> +++ b/drivers/net/usb/r8152.c
> @@ -2218,7 +2218,7 @@ static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
>
> features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
> segs = skb_gso_segment(skb, features);
> - if (IS_ERR(segs) || !segs)
> + if (IS_ERR_OR_NULL(segs))
> goto drop;
>
> __skb_queue_head_init(&seg_list);
>
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^ permalink raw reply
* Re: [PATCH 00/61] treewide: Use IS_ERR_OR_NULL over manual NULL check - refactor
From: James Bottomley @ 2026-03-12 15:32 UTC (permalink / raw)
To: Jason Gunthorpe, Kuan-Wei Chiu
Cc: Philipp Hahn, amd-gfx, apparmor, bpf, ceph-devel, cocci, dm-devel,
dri-devel, gfs2, intel-gfx, intel-wired-lan, iommu, kvm,
linux-arm-kernel, linux-block, linux-bluetooth, linux-btrfs,
linux-cifs, linux-clk, linux-erofs, linux-ext4, linux-fsdevel,
linux-gpio, linux-hyperv, linux-input, linux-kernel, linux-leds,
linux-media, linux-mips, linux-mm, linux-modules, linux-mtd,
linux-nfs, linux-omap, linux-phy, linux-pm, linux-rockchip,
linux-s390, linux-scsi, linux-sctp, linux-security-module,
linux-sh, linux-sound, linux-stm32, linux-trace-kernel, linux-usb,
linux-wireless, netdev, ntfs3, samba-technical, sched-ext,
target-devel, tipc-discussion, v9fs
In-Reply-To: <20260312125730.GI1469476@ziepe.ca>
On Thu, 2026-03-12 at 09:57 -0300, Jason Gunthorpe wrote:
> On Wed, Mar 11, 2026 at 02:40:36AM +0800, Kuan-Wei Chiu wrote:
>
> > IMHO, the necessity of IS_ERR_OR_NULL() often highlights a
> > confusing or flawed API design. It usually implies that the caller
> > is unsure whether a failure results in an error pointer or a NULL
> > pointer.
>
> +1
>
> IS_ERR_OR_NULL() should always be looked on with suspicion. Very
> little should be returning some tri-state 'ERR' 'NULL' 'SUCCESS'
> pointer. What does the middle condition even mean? IS_ERR_OR_NULL()
> implies ERR and NULL are semanticly the same, so fix the things to
> always use ERR.
Not in any way supporting the original patch. However, the pattern
ERR, NULL, PTR is used extensively in the dentry code of filesystems.
See the try_lookup..() set of functions in fs/namei.c
The meaning is
PTR - I found it
NULL - It definitely doesn't exist
ERR - something went wrong during the lookup.
So I don't think you can blanket say this pattern is wrong.
Regards,
James
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^ permalink raw reply
* Re: [PATCH 00/61] treewide: Use IS_ERR_OR_NULL over manual NULL check - refactor
From: Jason Gunthorpe @ 2026-03-12 12:57 UTC (permalink / raw)
To: Kuan-Wei Chiu
Cc: Philipp Hahn, amd-gfx, apparmor, bpf, ceph-devel, cocci, dm-devel,
dri-devel, gfs2, intel-gfx, intel-wired-lan, iommu, kvm,
linux-arm-kernel, linux-block, linux-bluetooth, linux-btrfs,
linux-cifs, linux-clk, linux-erofs, linux-ext4, linux-fsdevel,
linux-gpio, linux-hyperv, linux-input, linux-kernel, linux-leds,
linux-media, linux-mips, linux-mm, linux-modules, linux-mtd,
linux-nfs, linux-omap, linux-phy, linux-pm, linux-rockchip,
linux-s390, linux-scsi, linux-sctp, linux-security-module,
linux-sh, linux-sound, linux-stm32, linux-trace-kernel, linux-usb,
linux-wireless, netdev, ntfs3, samba-technical, sched-ext,
target-devel, tipc-discussion, v9fs
In-Reply-To: <abBlpGKO842B3yl9@google.com>
On Wed, Mar 11, 2026 at 02:40:36AM +0800, Kuan-Wei Chiu wrote:
> IMHO, the necessity of IS_ERR_OR_NULL() often highlights a confusing or
> flawed API design. It usually implies that the caller is unsure whether
> a failure results in an error pointer or a NULL pointer.
+1
IS_ERR_OR_NULL() should always be looked on with suspicion. Very
little should be returning some tri-state 'ERR' 'NULL' 'SUCCESS'
pointer. What does the middle condition even mean? IS_ERR_OR_NULL()
implies ERR and NULL are semanticly the same, so fix the things to
always use ERR.
If you want to improve things work to get rid of the NULL checks this
script identifies. Remove ERR or NULL because only one can ever
happen, or fix the source to consistently return ERR.
Jason
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^ permalink raw reply
* Re: [PATCH v2 net-next 2/5] net: phy: make mdio_device.c part of libphy
From: Paolo Abeni @ 2026-03-12 11:06 UTC (permalink / raw)
To: Heiner Kallweit, Bjorn Andersson, Michael Turquette, Stephen Boyd
Cc: netdev@vger.kernel.org, Philipp Zabel, linux-arm-msm, linux-clk,
linux-phy, Andrew Lunn, Russell King - ARM Linux, Jakub Kicinski,
David Miller, Eric Dumazet, Vinod Koul, Neil Armstrong
In-Reply-To: <c6dbf9b3-3ca0-434b-ad3a-71fe602ab809@gmail.com>
On 3/9/26 6:03 PM, Heiner Kallweit wrote:
> This patch
> - makes mdio_device.c part of libphy
> - makes mdio_device_(un)register_reset() static
> - moves mdiobus_(un)register_device() from mdio_bus.c to mdio_device.c,
> stops exporting both functions and makes them private to phylib
>
> This further decouples the MDIO consumer functionality from libphy.
>
> Note: This makes MDIO driver registration part of phylib, therefore
> adjust Kconfig dependencies where needed.
>
> Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
> ---
> v2:
> - add needed Kconfig dependency changes
> ---
> drivers/clk/qcom/Kconfig | 2 +-
> drivers/net/phy/Makefile | 6 ++---
> drivers/net/phy/mdio-private.h | 11 ---------
> drivers/net/phy/mdio_bus.c | 36 ----------------------------
> drivers/net/phy/mdio_device.c | 39 ++++++++++++++++++++++++++++---
> drivers/net/phy/phylib-internal.h | 4 ++++
> drivers/phy/broadcom/Kconfig | 4 ++--
> include/linux/mdio.h | 2 --
> 8 files changed, 46 insertions(+), 58 deletions(-)
> delete mode 100644 drivers/net/phy/mdio-private.h
>
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index a8a86ea6bb7..a277c434d64 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -392,7 +392,7 @@ config IPQ_NSSCC_9574
>
> config IPQ_NSSCC_QCA8K
> tristate "QCA8K(QCA8386 or QCA8084) NSS Clock Controller"
> - depends on MDIO_BUS
> + depends on PHYLIB
> help
> Support for NSS(Network SubSystem) clock controller on
> qca8386/qca8084 chip.
Bjorn, Micahel, Stephen: are you ok with this change?
Thanks,
Paolo
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^ permalink raw reply
* Re: [PATCH v2 2/8] clk: airoha: Add econet EN751221 clock/reset support to en7523-scu
From: Brian Masney @ 2026-03-11 19:44 UTC (permalink / raw)
To: Caleb James DeLisle
Cc: linux-mips, naseefkm, mturquette, sboyd, robh, krzk+dt, conor+dt,
tsbogend, ryder.lee, jianjun.wang, lpieralisi, kwilczynski, mani,
bhelgaas, vkoul, neil.armstrong, p.zabel, matthias.bgg,
angelogioacchino.delregno, nbd, ansuelsmth, linux-clk, devicetree,
linux-kernel, linux-pci, linux-mediatek, linux-phy,
linux-arm-kernel
In-Reply-To: <de6e8440-99a1-4be7-80aa-3645fdb0bdb9@cjdns.fr>
On Wed, Mar 11, 2026 at 06:12:59PM +0100, Caleb James DeLisle wrote:
> Hello Brian,
>
> Thank you for taking the time!
>
>
> On 11/03/2026 15:39, Brian Masney wrote:
> > Hi Caleb,
> >
> > On Mon, Mar 09, 2026 at 01:18:12PM +0000, Caleb James DeLisle wrote:
> > > EcoNet EN751221 clock/reset driver is significantly similar to the
> > > EN7523 / EN7581, however the EN751221 does not have a neat batch of clock
> > > divider registers so there are fewer known clocks, and the frequency of
> > > each clock is derived differently. This clock driver will probably work
> > > correctly on EN751627, EN7528, and EN7580.
> > >
> > > Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
> > > ---
> > > static u32 en7523_get_base_rate(const struct en_clk_desc *desc, u32 val)
> > > {
> > > @@ -604,7 +703,8 @@ static int en7523_clk_hw_init(struct platform_device *pdev,
> > > en7523_register_clocks(&pdev->dev, clk_data, base, np_base);
> > > return en7581_reset_register(&pdev->dev, np_base, en7523_rst_map,
> > > - ARRAY_SIZE(en7523_rst_map));
> > > + ARRAY_SIZE(en7523_rst_map),
> > > + en7581_rst_ofs);
> > I assume the mix of en7523 and en7581 is ok here?
>
>
> Correct, en7581 came first, then when en7523 was added they reused the
> function. I'm only changing the offsets to be passed in because en751221 has
> more reset registers so different offset table than the others.
Sounds good. I just wanted to confirm.
> > > + else
> > > + clk_data->hws[key] = hw;
> > Should the error code be returned here? I know the function has try in
> > it's name, however if this fails, then it still registers it.
>
>
> This function follows the general pattern of en7581_register_clocks(). If a
> clock can't be registered, leave clk_data->hws[key] as NULL, log, and
> continue. There's only two possible reasons for failing, if
> clk_hw_register_fixed_rate() fails then it's not registered because it
> failed. If key >= EN751221_MAX_CLKS, it does register but I'll fix this so
> it's checking that before clk_hw_register_fixed_rate().
I see that Stephen picked up this driver in 2022 with that behavior. I'm
fine with it if he is.
> > > + /* BUS */
> > > + rate = FIELD_GET(EN751221_REG_BUS_MASK,
> > > + readl(np_base + EN751221_REG_BUS));
> > > + rate *= 1000000;
> > > + en751221_try_register_clk(dev, EN751221_CLK_BUS, clk_data, "bus",
> > > + rate);
> > > +
> > > + /* CPU */
> > > + en751221_try_register_clk(dev, EN751221_CLK_CPU, clk_data, "cpu",
> > > + rate * 4);
> > > +
> > > + /* HPT */
> > > + switch (hid) {
> > > + case HIR_EN751221:
> > > + case HIR_EN751627:
> > > + case HIR_EN7526C:
> > > + case HIR_EN7580:
> > > + case HIR_EN7528:
> > > + rate = 200000000;
> > > + break;
> > > + case HIR_MT7505:
> > > + rate = 100000000;
> > > + break;
> > > + case HIR_MT751020:
> > > + rate = 800000000 / 3;
> > > + break;
> > > + default:
> > > + rate = 250000000;
> > Should a warning be logged here or in get_hw_id() above? hid can be set
> > to HIR_UNKNOWN here.
>
> Now that I'm looking at this again, I'm starting to think it might be better
> to just remove it and use a fixed-clock in the DT. I wrote it aiming for
> completeness, but this particular clock has so much code supporting it, I'm
> feeling like it just doesn't make any sense.
>
> Let me know if you have a feeling on this because I'm swaying in the
> direction of just re-sending with it removed.
That makes sense to me.
Brian
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^ permalink raw reply
* Re: [PATCH v2 2/8] clk: airoha: Add econet EN751221 clock/reset support to en7523-scu
From: Caleb James DeLisle @ 2026-03-11 17:12 UTC (permalink / raw)
To: Brian Masney
Cc: linux-mips, naseefkm, mturquette, sboyd, robh, krzk+dt, conor+dt,
tsbogend, ryder.lee, jianjun.wang, lpieralisi, kwilczynski, mani,
bhelgaas, vkoul, neil.armstrong, p.zabel, matthias.bgg,
angelogioacchino.delregno, nbd, ansuelsmth, linux-clk, devicetree,
linux-kernel, linux-pci, linux-mediatek, linux-phy,
linux-arm-kernel
In-Reply-To: <abF-qFC1Oa4dz-fh@redhat.com>
Hello Brian,
Thank you for taking the time!
On 11/03/2026 15:39, Brian Masney wrote:
> Hi Caleb,
>
> On Mon, Mar 09, 2026 at 01:18:12PM +0000, Caleb James DeLisle wrote:
>> EcoNet EN751221 clock/reset driver is significantly similar to the
>> EN7523 / EN7581, however the EN751221 does not have a neat batch of clock
>> divider registers so there are fewer known clocks, and the frequency of
>> each clock is derived differently. This clock driver will probably work
>> correctly on EN751627, EN7528, and EN7580.
>>
>> Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
>> ---
>> drivers/clk/Kconfig | 6 +-
>> drivers/clk/clk-en7523.c | 238 ++++++++++++++++++++++++++++++++++++++-
>> 2 files changed, 236 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
>> index 3d803b4cf5c1..47df6073a72b 100644
>> --- a/drivers/clk/Kconfig
>> +++ b/drivers/clk/Kconfig
>> @@ -218,13 +218,13 @@ config COMMON_CLK_CS2000_CP
>> If you say yes here you get support for the CS2000 clock multiplier.
>>
>> config COMMON_CLK_EN7523
>> - bool "Clock driver for Airoha EN7523 SoC system clocks"
>> + bool "Clock driver for Airoha/EcoNet SoC system clocks"
>> depends on OF
>> - depends on ARCH_AIROHA || COMPILE_TEST
>> + depends on ARCH_AIROHA || ECONET || COMPILE_TEST
>> default ARCH_AIROHA
>> help
>> This driver provides the fixed clocks and gates present on Airoha
>> - ARM silicon.
>> + and EcoNet silicon.
>>
>> config COMMON_CLK_EP93XX
>> tristate "Clock driver for Cirrus Logic ep93xx SoC"
>> diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c
>> index 08cc8e5acf43..f7bd7034cf7f 100644
>> --- a/drivers/clk/clk-en7523.c
>> +++ b/drivers/clk/clk-en7523.c
>> @@ -1,5 +1,6 @@
>> // SPDX-License-Identifier: GPL-2.0-only
>>
>> +#include <linux/bitfield.h>
>> #include <linux/delay.h>
>> #include <linux/clk-provider.h>
>> #include <linux/io.h>
>> @@ -11,6 +12,8 @@
>> #include <dt-bindings/clock/en7523-clk.h>
>> #include <dt-bindings/reset/airoha,en7523-reset.h>
>> #include <dt-bindings/reset/airoha,en7581-reset.h>
>> +#include <dt-bindings/clock/econet,en751221-scu.h>
>> +#include <dt-bindings/reset/econet,en751221-scu.h>
>>
>> #define RST_NR_PER_BANK 32
>>
>> @@ -33,15 +36,49 @@
>> #define REG_RESET_CONTROL_PCIEHB BIT(29)
>> #define REG_RESET_CONTROL_PCIE1 BIT(27)
>> #define REG_RESET_CONTROL_PCIE2 BIT(26)
>> +#define REG_HIR 0x064
>> +#define REG_HIR_MASK GENMASK(31, 16)
>> /* EN7581 */
>> #define REG_NP_SCU_PCIC 0x88
>> #define REG_NP_SCU_SSTR 0x9c
>> #define REG_PCIE_XSI0_SEL_MASK GENMASK(14, 13)
>> #define REG_PCIE_XSI1_SEL_MASK GENMASK(12, 11)
>> #define REG_CRYPTO_CLKSRC2 0x20c
>> +/* EN751221 */
>> +#define EN751221_REG_SPI_DIV 0x0cc
>> +#define EN751221_REG_SPI_DIV_MASK GENMASK(31, 8)
>> +#define EN751221_SPI_BASE 500000000
>> +#define EN751221_SPI_BASE_EN7526C 400000000
>> +#define EN751221_REG_BUS 0x284
>> +#define EN751221_REG_BUS_MASK GENMASK(21, 12)
>> +#define EN751221_REG_SSR3 0x094
>> +#define EN751221_REG_SSR3_GSW_MASK GENMASK(9, 8)
>>
>> #define REG_RST_CTRL2 0x830
>> #define REG_RST_CTRL1 0x834
>> +#define EN751221_REG_RST_DMT 0x84
>> +#define EN751221_REG_RST_USB 0xec
>> +
>> +#define EN751221_MAX_CLKS 6
>> +
>> +enum en_hir {
>> + HIR_UNKNOWN = -1,
>> + HIR_TC3169 = 0,
>> + HIR_TC3182 = 1,
>> + HIR_RT65168 = 2,
>> + HIR_RT63165 = 3,
>> + HIR_RT63365 = 4,
>> + HIR_MT751020 = 5,
>> + HIR_MT7505 = 6,
>> + HIR_EN751221 = 7,
>> + HIR_EN7526C = 8,
>> + HIR_EN751627 = 9,
>> + HIR_EN7580 = 10,
>> + HIR_EN7528 = 11,
>> + HIR_EN7523 = 12,
>> + HIR_EN7581 = 13,
>> + HIR_MAX = 14,
>> +};
>>
>> struct en_clk_desc {
>> int id;
>> @@ -93,6 +130,8 @@ static const u32 bus7581_base[] = { 600000000, 540000000 };
>> static const u32 npu7581_base[] = { 800000000, 750000000, 720000000, 600000000 };
>> static const u32 crypto_base[] = { 540000000, 480000000 };
>> static const u32 emmc7581_base[] = { 200000000, 150000000 };
>> +/* EN751221 */
>> +static const u32 gsw751221_base[] = { 500000000, 250000000, 400000000, 200000000 };
>>
>> static const struct en_clk_desc en7523_base_clks[] = {
>> {
>> @@ -300,6 +339,13 @@ static const u16 en7581_rst_ofs[] = {
>> REG_RST_CTRL1,
>> };
>>
>> +static const u16 en751221_rst_ofs[] = {
>> + REG_RST_CTRL2,
>> + REG_RST_CTRL1,
>> + EN751221_REG_RST_DMT,
>> + EN751221_REG_RST_USB,
>> +};
>> +
>> static const u16 en7523_rst_map[] = {
>> /* RST_CTRL2 */
>> [EN7523_XPON_PHY_RST] = 0,
>> @@ -405,8 +451,61 @@ static const u16 en7581_rst_map[] = {
>> [EN7581_XPON_MAC_RST] = RST_NR_PER_BANK + 31,
>> };
>>
>> +static const u16 en751221_rst_map[] = {
>> + /* RST_CTRL2 */
>> + [EN751221_XPON_PHY_RST] = 0,
>> + [EN751221_GFAST_RST] = 1,
>> + [EN751221_CPU_TIMER2_RST] = 2,
>> + [EN751221_UART3_RST] = 3,
>> + [EN751221_UART4_RST] = 4,
>> + [EN751221_UART5_RST] = 5,
>> + [EN751221_I2C2_RST] = 6,
>> + [EN751221_XSI_MAC_RST] = 7,
>> + [EN751221_XSI_PHY_RST] = 8,
>> +
>> + /* RST_CTRL1 */
>> + [EN751221_PCM1_ZSI_ISI_RST] = RST_NR_PER_BANK + 0,
>> + [EN751221_FE_QDMA1_RST] = RST_NR_PER_BANK + 1,
>> + [EN751221_FE_QDMA2_RST] = RST_NR_PER_BANK + 2,
>> + [EN751221_FE_UNZIP_RST] = RST_NR_PER_BANK + 3,
>> + [EN751221_PCM2_RST] = RST_NR_PER_BANK + 4,
>> + [EN751221_PTM_MAC_RST] = RST_NR_PER_BANK + 5,
>> + [EN751221_CRYPTO_RST] = RST_NR_PER_BANK + 6,
>> + [EN751221_SAR_RST] = RST_NR_PER_BANK + 7,
>> + [EN751221_TIMER_RST] = RST_NR_PER_BANK + 8,
>> + [EN751221_INTC_RST] = RST_NR_PER_BANK + 9,
>> + [EN751221_BONDING_RST] = RST_NR_PER_BANK + 10,
>> + [EN751221_PCM1_RST] = RST_NR_PER_BANK + 11,
>> + [EN751221_UART_RST] = RST_NR_PER_BANK + 12,
>> + [EN751221_GPIO_RST] = RST_NR_PER_BANK + 13,
>> + [EN751221_GDMA_RST] = RST_NR_PER_BANK + 14,
>> + [EN751221_I2C_MASTER_RST] = RST_NR_PER_BANK + 16,
>> + [EN751221_PCM2_ZSI_ISI_RST] = RST_NR_PER_BANK + 17,
>> + [EN751221_SFC_RST] = RST_NR_PER_BANK + 18,
>> + [EN751221_UART2_RST] = RST_NR_PER_BANK + 19,
>> + [EN751221_GDMP_RST] = RST_NR_PER_BANK + 20,
>> + [EN751221_FE_RST] = RST_NR_PER_BANK + 21,
>> + [EN751221_USB_HOST_P0_RST] = RST_NR_PER_BANK + 22,
>> + [EN751221_GSW_RST] = RST_NR_PER_BANK + 23,
>> + [EN751221_SFC2_PCM_RST] = RST_NR_PER_BANK + 25,
>> + [EN751221_PCIE0_RST] = RST_NR_PER_BANK + 26,
>> + [EN751221_PCIE1_RST] = RST_NR_PER_BANK + 27,
>> + [EN751221_CPU_TIMER_RST] = RST_NR_PER_BANK + 28,
>> + [EN751221_PCIE_HB_RST] = RST_NR_PER_BANK + 29,
>> + [EN751221_SIMIF_RST] = RST_NR_PER_BANK + 30,
>> + [EN751221_XPON_MAC_RST] = RST_NR_PER_BANK + 31,
>> +
>> + /* RST_DMT */
>> + [EN751221_DMT_RST] = 2 * RST_NR_PER_BANK + 0,
>> +
>> + /* RST_USB */
>> + [EN751221_USB_PHY_P0_RST] = 3 * RST_NR_PER_BANK + 6,
>> + [EN751221_USB_PHY_P1_RST] = 3 * RST_NR_PER_BANK + 7,
>> +};
>> +
>> static int en7581_reset_register(struct device *dev, void __iomem *base,
>> - const u16 *rst_map, int nr_resets);
>> + const u16 *rst_map, int nr_resets,
>> + const u16 *rst_reg_ofs);
>>
>> static u32 en7523_get_base_rate(const struct en_clk_desc *desc, u32 val)
>> {
>> @@ -604,7 +703,8 @@ static int en7523_clk_hw_init(struct platform_device *pdev,
>> en7523_register_clocks(&pdev->dev, clk_data, base, np_base);
>>
>> return en7581_reset_register(&pdev->dev, np_base, en7523_rst_map,
>> - ARRAY_SIZE(en7523_rst_map));
>> + ARRAY_SIZE(en7523_rst_map),
>> + en7581_rst_ofs);
> I assume the mix of en7523 and en7581 is ok here?
Correct, en7581 came first, then when en7523 was added they reused the
function. I'm only changing the offsets to be passed in because en751221
has more reset registers so different offset table than the others.
>> }
>>
>> static void en7581_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data,
>> @@ -705,7 +805,8 @@ static const struct reset_control_ops en7581_reset_ops = {
>> };
>>
>> static int en7581_reset_register(struct device *dev, void __iomem *base,
>> - const u16 *rst_map, int nr_resets)
>> + const u16 *rst_map, int nr_resets,
>> + const u16 *rst_reg_ofs)
>> {
>> struct en_rst_data *rst_data;
>>
>> @@ -713,7 +814,7 @@ static int en7581_reset_register(struct device *dev, void __iomem *base,
>> if (!rst_data)
>> return -ENOMEM;
>>
>> - rst_data->bank_ofs = en7581_rst_ofs;
>> + rst_data->bank_ofs = rst_reg_ofs;
>> rst_data->idx_map = rst_map;
>> rst_data->base = base;
>>
>> @@ -752,7 +853,123 @@ static int en7581_clk_hw_init(struct platform_device *pdev,
>> writel(val | 3, base + REG_NP_SCU_PCIC);
>>
>> return en7581_reset_register(&pdev->dev, base, en7581_rst_map,
>> - ARRAY_SIZE(en7581_rst_map));
>> + ARRAY_SIZE(en7581_rst_map),
>> + en7581_rst_ofs);
>> +}
>> +
>> +static enum en_hir get_hw_id(void __iomem *np_base)
>> +{
>> + u32 val = FIELD_GET(REG_HIR_MASK, readl(np_base + REG_HIR));
>> +
>> + if (val < HIR_MAX)
>> + return (enum en_hir) val;
> No space with the cast.
OK
>> +
>> + return HIR_UNKNOWN;
>> +}
>> +
>> +static void en751221_try_register_clk(struct device *dev, int key,
>> + struct clk_hw_onecell_data *clk_data,
>> + const char *name, u32 rate)
>> +{
>> + struct clk_hw *hw;
>> +
>> + hw = clk_hw_register_fixed_rate(dev, name, NULL, 0, rate);
>> + if (IS_ERR(hw) || key >= EN751221_MAX_CLKS)
>> + pr_err("Failed to register clk %s: %pe\n", name, hw);
> Is %pe correct in the case when key >= EN751221_MAX_CLKS?
Hmm, it's gonna give a pointer address, indeed that's not so nice. I'll
re-work this so it makes more sense.
>> + else
>> + clk_data->hws[key] = hw;
> Should the error code be returned here? I know the function has try in
> it's name, however if this fails, then it still registers it.
This function follows the general pattern of en7581_register_clocks().
If a clock can't be registered, leave clk_data->hws[key] as NULL, log,
and continue. There's only two possible reasons for failing, if
clk_hw_register_fixed_rate() fails then it's not registered because it
failed. If key >= EN751221_MAX_CLKS, it does register but I'll fix this
so it's checking that before clk_hw_register_fixed_rate().
>> +}
>> +
>> +static void en751221_register_clocks(struct device *dev,
>> + struct clk_hw_onecell_data *clk_data,
>> + struct regmap *map, void __iomem *np_base)
>> +{
>> + enum en_hir hid = get_hw_id(np_base);
>> + struct clk_hw *hw;
>> + u32 rate;
>> + u32 div;
>> + int err;
>> +
>> + /* PCI */
>> + hw = en7523_register_pcie_clk(dev, np_base);
>> + clk_data->hws[EN751221_CLK_PCIE] = hw;
>> +
>> + /* SPI */
>> + rate = EN751221_SPI_BASE;
>> + if (hid == HIR_EN7526C)
>> + rate = EN751221_SPI_BASE_EN7526C;
>> +
>> + err = regmap_read(map, EN751221_REG_SPI_DIV, &div);
>> + if (err) {
>> + pr_err("Failed reading fixed clk div %s: %d\n",
>> + "spi", err);
>> + } else {
>> + div = FIELD_GET(EN751221_REG_SPI_DIV_MASK, div) * 2;
>> + if (!div)
>> + div = 40;
> Should 40 be documented a little better with a #define?
Ok yes, makes sense.
>> +
>> + en751221_try_register_clk(dev, EN751221_CLK_SPI, clk_data,
>> + "spi", rate / div);
>> + }
>> +
>> + /* BUS */
>> + rate = FIELD_GET(EN751221_REG_BUS_MASK,
>> + readl(np_base + EN751221_REG_BUS));
>> + rate *= 1000000;
>> + en751221_try_register_clk(dev, EN751221_CLK_BUS, clk_data, "bus",
>> + rate);
>> +
>> + /* CPU */
>> + en751221_try_register_clk(dev, EN751221_CLK_CPU, clk_data, "cpu",
>> + rate * 4);
>> +
>> + /* HPT */
>> + switch (hid) {
>> + case HIR_EN751221:
>> + case HIR_EN751627:
>> + case HIR_EN7526C:
>> + case HIR_EN7580:
>> + case HIR_EN7528:
>> + rate = 200000000;
>> + break;
>> + case HIR_MT7505:
>> + rate = 100000000;
>> + break;
>> + case HIR_MT751020:
>> + rate = 800000000 / 3;
>> + break;
>> + default:
>> + rate = 250000000;
> Should a warning be logged here or in get_hw_id() above? hid can be set
> to HIR_UNKNOWN here.
Now that I'm looking at this again, I'm starting to think it might be
better to just remove it and use a fixed-clock in the DT. I wrote it
aiming for completeness, but this particular clock has so much code
supporting it, I'm feeling like it just doesn't make any sense.
Let me know if you have a feeling on this because I'm swaying in the
direction of just re-sending with it removed.
>
>> + }
>> + en751221_try_register_clk(dev, EN751221_CLK_HPT, clk_data, "hpt",
>> + rate);
>> +
>> + /* GSW */
>> + rate = FIELD_GET(EN751221_REG_SSR3_GSW_MASK,
>> + readl(np_base + EN751221_REG_SSR3));
>> + en751221_try_register_clk(dev, EN751221_CLK_GSW, clk_data, "gsw",
>> + gsw751221_base[rate]);
>> +}
>> +
>> +static int en751221_clk_hw_init(struct platform_device *pdev,
>> + struct clk_hw_onecell_data *clk_data)
>> +{
>> + struct regmap *map;
>> + void __iomem *base;
>> +
>> + map = syscon_regmap_lookup_by_compatible("econet,en751221-chip-scu");
>> + if (IS_ERR(map))
>> + return PTR_ERR(map);
>> +
>> + base = devm_platform_ioremap_resource(pdev, 0);
>> + if (IS_ERR(base))
>> + return PTR_ERR(base);
>> +
>> + en751221_register_clocks(&pdev->dev, clk_data, map, base);
> Again, any reason why the error handling is missing here?
I followed the same logic that was used for the en7581 and en7523, but I
think the logic is reasonable. If a clock fails to register, you either
log and continue, or you blow up the whole probe(), which is just going
to make it more frustrating to debug since then no clocks will register
and anything downstream of them will be unhappy.
Thanks,
Caleb
>
> Brian
>
>
>> +
>> + return en7581_reset_register(&pdev->dev, base, en751221_rst_map,
>> + ARRAY_SIZE(en751221_rst_map),
>> + en751221_rst_ofs);
>> }
>>
>> static int en7523_clk_probe(struct platform_device *pdev)
>> @@ -799,9 +1016,20 @@ static const struct en_clk_soc_data en7581_data = {
>> .hw_init = en7581_clk_hw_init,
>> };
>>
>> +static const struct en_clk_soc_data en751221_data = {
>> + .num_clocks = EN751221_MAX_CLKS,
>> + .pcie_ops = {
>> + .is_enabled = en7523_pci_is_enabled,
>> + .prepare = en7523_pci_prepare,
>> + .unprepare = en7523_pci_unprepare,
>> + },
>> + .hw_init = en751221_clk_hw_init,
>> +};
>> +
>> static const struct of_device_id of_match_clk_en7523[] = {
>> { .compatible = "airoha,en7523-scu", .data = &en7523_data },
>> { .compatible = "airoha,en7581-scu", .data = &en7581_data },
>> + { .compatible = "econet,en751221-scu", .data = &en751221_data },
>> { /* sentinel */ }
>> };
>>
>> --
>> 2.39.5
>>
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply
* Re: [PATCH 01/61] Coccinelle: Prefer IS_ERR_OR_NULL over manual NULL check
From: Markus Elfring @ 2026-03-11 15:12 UTC (permalink / raw)
To: Philipp Hahn, cocci, Julia Lawall, Nicolas Palix
Cc: amd-gfx, apparmor, bpf, ceph-devel, dm-devel, dri-devel, gfs2,
intel-gfx, intel-wired-lan, iommu, kvm, linux-arm-kernel,
linux-block, linux-bluetooth, linux-btrfs, linux-cifs, linux-clk,
linux-erofs, linux-ext4, linux-fsdevel, linux-gpio, linux-hyperv,
linux-input, linux-leds, linux-media, linux-mips, linux-mm,
linux-modules, linux-mtd, linux-nfs, linux-omap, linux-phy,
linux-pm, linux-rockchip, linux-s390, linux-scsi, linux-sctp,
linux-security-module, linux-sh, linux-sound, linux-stm32,
linux-trace-kernel, linux-usb, linux-wireless, netdev, ntfs3,
samba-technical, sched-ext, target-devel, tipc-discussion, v9fs,
LKML
In-Reply-To: <20260310-b4-is_err_or_null-v1-1-bd63b656022d@avm.de>
…
> +// Confidence: High
Some contributors presented discerning comments for this change approach.
Thus I became also curious how much they can eventually be taken better into account
by the means of the semantic patch language (Coccinelle software).
…
+@p1 depends on patch@
+expression E;
+@@
+(
> +- E != NULL && !IS_ERR(E)
> ++ !IS_ERR_OR_NULL(E)
> +|
> +- E == NULL || IS_ERR(E)
> ++ IS_ERR_OR_NULL(E)
> +|
> +- !IS_ERR(E) && E != NULL
> ++ !IS_ERR_OR_NULL(E)
> +|
> +- IS_ERR(E) || E == NULL
> ++ IS_ERR_OR_NULL(E)
> +)
Several detected expressions should refer to return values from function calls.
https://en.wikipedia.org/wiki/Return_statement
* Do any development challenges hinder still the determination of corresponding
failure predicates?
* How will interests evolve to improve data processing any further for such
use cases?
Regards,
Markus
--
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https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply
* Re: [PATCH v2 2/8] clk: airoha: Add econet EN751221 clock/reset support to en7523-scu
From: Brian Masney @ 2026-03-11 14:39 UTC (permalink / raw)
To: Caleb James DeLisle
Cc: linux-mips, naseefkm, mturquette, sboyd, robh, krzk+dt, conor+dt,
tsbogend, ryder.lee, jianjun.wang, lpieralisi, kwilczynski, mani,
bhelgaas, vkoul, neil.armstrong, p.zabel, matthias.bgg,
angelogioacchino.delregno, nbd, ansuelsmth, linux-clk, devicetree,
linux-kernel, linux-pci, linux-mediatek, linux-phy,
linux-arm-kernel
In-Reply-To: <20260309131818.74467-3-cjd@cjdns.fr>
Hi Caleb,
On Mon, Mar 09, 2026 at 01:18:12PM +0000, Caleb James DeLisle wrote:
> EcoNet EN751221 clock/reset driver is significantly similar to the
> EN7523 / EN7581, however the EN751221 does not have a neat batch of clock
> divider registers so there are fewer known clocks, and the frequency of
> each clock is derived differently. This clock driver will probably work
> correctly on EN751627, EN7528, and EN7580.
>
> Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
> ---
> drivers/clk/Kconfig | 6 +-
> drivers/clk/clk-en7523.c | 238 ++++++++++++++++++++++++++++++++++++++-
> 2 files changed, 236 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> index 3d803b4cf5c1..47df6073a72b 100644
> --- a/drivers/clk/Kconfig
> +++ b/drivers/clk/Kconfig
> @@ -218,13 +218,13 @@ config COMMON_CLK_CS2000_CP
> If you say yes here you get support for the CS2000 clock multiplier.
>
> config COMMON_CLK_EN7523
> - bool "Clock driver for Airoha EN7523 SoC system clocks"
> + bool "Clock driver for Airoha/EcoNet SoC system clocks"
> depends on OF
> - depends on ARCH_AIROHA || COMPILE_TEST
> + depends on ARCH_AIROHA || ECONET || COMPILE_TEST
> default ARCH_AIROHA
> help
> This driver provides the fixed clocks and gates present on Airoha
> - ARM silicon.
> + and EcoNet silicon.
>
> config COMMON_CLK_EP93XX
> tristate "Clock driver for Cirrus Logic ep93xx SoC"
> diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c
> index 08cc8e5acf43..f7bd7034cf7f 100644
> --- a/drivers/clk/clk-en7523.c
> +++ b/drivers/clk/clk-en7523.c
> @@ -1,5 +1,6 @@
> // SPDX-License-Identifier: GPL-2.0-only
>
> +#include <linux/bitfield.h>
> #include <linux/delay.h>
> #include <linux/clk-provider.h>
> #include <linux/io.h>
> @@ -11,6 +12,8 @@
> #include <dt-bindings/clock/en7523-clk.h>
> #include <dt-bindings/reset/airoha,en7523-reset.h>
> #include <dt-bindings/reset/airoha,en7581-reset.h>
> +#include <dt-bindings/clock/econet,en751221-scu.h>
> +#include <dt-bindings/reset/econet,en751221-scu.h>
>
> #define RST_NR_PER_BANK 32
>
> @@ -33,15 +36,49 @@
> #define REG_RESET_CONTROL_PCIEHB BIT(29)
> #define REG_RESET_CONTROL_PCIE1 BIT(27)
> #define REG_RESET_CONTROL_PCIE2 BIT(26)
> +#define REG_HIR 0x064
> +#define REG_HIR_MASK GENMASK(31, 16)
> /* EN7581 */
> #define REG_NP_SCU_PCIC 0x88
> #define REG_NP_SCU_SSTR 0x9c
> #define REG_PCIE_XSI0_SEL_MASK GENMASK(14, 13)
> #define REG_PCIE_XSI1_SEL_MASK GENMASK(12, 11)
> #define REG_CRYPTO_CLKSRC2 0x20c
> +/* EN751221 */
> +#define EN751221_REG_SPI_DIV 0x0cc
> +#define EN751221_REG_SPI_DIV_MASK GENMASK(31, 8)
> +#define EN751221_SPI_BASE 500000000
> +#define EN751221_SPI_BASE_EN7526C 400000000
> +#define EN751221_REG_BUS 0x284
> +#define EN751221_REG_BUS_MASK GENMASK(21, 12)
> +#define EN751221_REG_SSR3 0x094
> +#define EN751221_REG_SSR3_GSW_MASK GENMASK(9, 8)
>
> #define REG_RST_CTRL2 0x830
> #define REG_RST_CTRL1 0x834
> +#define EN751221_REG_RST_DMT 0x84
> +#define EN751221_REG_RST_USB 0xec
> +
> +#define EN751221_MAX_CLKS 6
> +
> +enum en_hir {
> + HIR_UNKNOWN = -1,
> + HIR_TC3169 = 0,
> + HIR_TC3182 = 1,
> + HIR_RT65168 = 2,
> + HIR_RT63165 = 3,
> + HIR_RT63365 = 4,
> + HIR_MT751020 = 5,
> + HIR_MT7505 = 6,
> + HIR_EN751221 = 7,
> + HIR_EN7526C = 8,
> + HIR_EN751627 = 9,
> + HIR_EN7580 = 10,
> + HIR_EN7528 = 11,
> + HIR_EN7523 = 12,
> + HIR_EN7581 = 13,
> + HIR_MAX = 14,
> +};
>
> struct en_clk_desc {
> int id;
> @@ -93,6 +130,8 @@ static const u32 bus7581_base[] = { 600000000, 540000000 };
> static const u32 npu7581_base[] = { 800000000, 750000000, 720000000, 600000000 };
> static const u32 crypto_base[] = { 540000000, 480000000 };
> static const u32 emmc7581_base[] = { 200000000, 150000000 };
> +/* EN751221 */
> +static const u32 gsw751221_base[] = { 500000000, 250000000, 400000000, 200000000 };
>
> static const struct en_clk_desc en7523_base_clks[] = {
> {
> @@ -300,6 +339,13 @@ static const u16 en7581_rst_ofs[] = {
> REG_RST_CTRL1,
> };
>
> +static const u16 en751221_rst_ofs[] = {
> + REG_RST_CTRL2,
> + REG_RST_CTRL1,
> + EN751221_REG_RST_DMT,
> + EN751221_REG_RST_USB,
> +};
> +
> static const u16 en7523_rst_map[] = {
> /* RST_CTRL2 */
> [EN7523_XPON_PHY_RST] = 0,
> @@ -405,8 +451,61 @@ static const u16 en7581_rst_map[] = {
> [EN7581_XPON_MAC_RST] = RST_NR_PER_BANK + 31,
> };
>
> +static const u16 en751221_rst_map[] = {
> + /* RST_CTRL2 */
> + [EN751221_XPON_PHY_RST] = 0,
> + [EN751221_GFAST_RST] = 1,
> + [EN751221_CPU_TIMER2_RST] = 2,
> + [EN751221_UART3_RST] = 3,
> + [EN751221_UART4_RST] = 4,
> + [EN751221_UART5_RST] = 5,
> + [EN751221_I2C2_RST] = 6,
> + [EN751221_XSI_MAC_RST] = 7,
> + [EN751221_XSI_PHY_RST] = 8,
> +
> + /* RST_CTRL1 */
> + [EN751221_PCM1_ZSI_ISI_RST] = RST_NR_PER_BANK + 0,
> + [EN751221_FE_QDMA1_RST] = RST_NR_PER_BANK + 1,
> + [EN751221_FE_QDMA2_RST] = RST_NR_PER_BANK + 2,
> + [EN751221_FE_UNZIP_RST] = RST_NR_PER_BANK + 3,
> + [EN751221_PCM2_RST] = RST_NR_PER_BANK + 4,
> + [EN751221_PTM_MAC_RST] = RST_NR_PER_BANK + 5,
> + [EN751221_CRYPTO_RST] = RST_NR_PER_BANK + 6,
> + [EN751221_SAR_RST] = RST_NR_PER_BANK + 7,
> + [EN751221_TIMER_RST] = RST_NR_PER_BANK + 8,
> + [EN751221_INTC_RST] = RST_NR_PER_BANK + 9,
> + [EN751221_BONDING_RST] = RST_NR_PER_BANK + 10,
> + [EN751221_PCM1_RST] = RST_NR_PER_BANK + 11,
> + [EN751221_UART_RST] = RST_NR_PER_BANK + 12,
> + [EN751221_GPIO_RST] = RST_NR_PER_BANK + 13,
> + [EN751221_GDMA_RST] = RST_NR_PER_BANK + 14,
> + [EN751221_I2C_MASTER_RST] = RST_NR_PER_BANK + 16,
> + [EN751221_PCM2_ZSI_ISI_RST] = RST_NR_PER_BANK + 17,
> + [EN751221_SFC_RST] = RST_NR_PER_BANK + 18,
> + [EN751221_UART2_RST] = RST_NR_PER_BANK + 19,
> + [EN751221_GDMP_RST] = RST_NR_PER_BANK + 20,
> + [EN751221_FE_RST] = RST_NR_PER_BANK + 21,
> + [EN751221_USB_HOST_P0_RST] = RST_NR_PER_BANK + 22,
> + [EN751221_GSW_RST] = RST_NR_PER_BANK + 23,
> + [EN751221_SFC2_PCM_RST] = RST_NR_PER_BANK + 25,
> + [EN751221_PCIE0_RST] = RST_NR_PER_BANK + 26,
> + [EN751221_PCIE1_RST] = RST_NR_PER_BANK + 27,
> + [EN751221_CPU_TIMER_RST] = RST_NR_PER_BANK + 28,
> + [EN751221_PCIE_HB_RST] = RST_NR_PER_BANK + 29,
> + [EN751221_SIMIF_RST] = RST_NR_PER_BANK + 30,
> + [EN751221_XPON_MAC_RST] = RST_NR_PER_BANK + 31,
> +
> + /* RST_DMT */
> + [EN751221_DMT_RST] = 2 * RST_NR_PER_BANK + 0,
> +
> + /* RST_USB */
> + [EN751221_USB_PHY_P0_RST] = 3 * RST_NR_PER_BANK + 6,
> + [EN751221_USB_PHY_P1_RST] = 3 * RST_NR_PER_BANK + 7,
> +};
> +
> static int en7581_reset_register(struct device *dev, void __iomem *base,
> - const u16 *rst_map, int nr_resets);
> + const u16 *rst_map, int nr_resets,
> + const u16 *rst_reg_ofs);
>
> static u32 en7523_get_base_rate(const struct en_clk_desc *desc, u32 val)
> {
> @@ -604,7 +703,8 @@ static int en7523_clk_hw_init(struct platform_device *pdev,
> en7523_register_clocks(&pdev->dev, clk_data, base, np_base);
>
> return en7581_reset_register(&pdev->dev, np_base, en7523_rst_map,
> - ARRAY_SIZE(en7523_rst_map));
> + ARRAY_SIZE(en7523_rst_map),
> + en7581_rst_ofs);
I assume the mix of en7523 and en7581 is ok here?
> }
>
> static void en7581_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data,
> @@ -705,7 +805,8 @@ static const struct reset_control_ops en7581_reset_ops = {
> };
>
> static int en7581_reset_register(struct device *dev, void __iomem *base,
> - const u16 *rst_map, int nr_resets)
> + const u16 *rst_map, int nr_resets,
> + const u16 *rst_reg_ofs)
> {
> struct en_rst_data *rst_data;
>
> @@ -713,7 +814,7 @@ static int en7581_reset_register(struct device *dev, void __iomem *base,
> if (!rst_data)
> return -ENOMEM;
>
> - rst_data->bank_ofs = en7581_rst_ofs;
> + rst_data->bank_ofs = rst_reg_ofs;
> rst_data->idx_map = rst_map;
> rst_data->base = base;
>
> @@ -752,7 +853,123 @@ static int en7581_clk_hw_init(struct platform_device *pdev,
> writel(val | 3, base + REG_NP_SCU_PCIC);
>
> return en7581_reset_register(&pdev->dev, base, en7581_rst_map,
> - ARRAY_SIZE(en7581_rst_map));
> + ARRAY_SIZE(en7581_rst_map),
> + en7581_rst_ofs);
> +}
> +
> +static enum en_hir get_hw_id(void __iomem *np_base)
> +{
> + u32 val = FIELD_GET(REG_HIR_MASK, readl(np_base + REG_HIR));
> +
> + if (val < HIR_MAX)
> + return (enum en_hir) val;
No space with the cast.
> +
> + return HIR_UNKNOWN;
> +}
> +
> +static void en751221_try_register_clk(struct device *dev, int key,
> + struct clk_hw_onecell_data *clk_data,
> + const char *name, u32 rate)
> +{
> + struct clk_hw *hw;
> +
> + hw = clk_hw_register_fixed_rate(dev, name, NULL, 0, rate);
> + if (IS_ERR(hw) || key >= EN751221_MAX_CLKS)
> + pr_err("Failed to register clk %s: %pe\n", name, hw);
Is %pe correct in the case when key >= EN751221_MAX_CLKS?
> + else
> + clk_data->hws[key] = hw;
Should the error code be returned here? I know the function has try in
it's name, however if this fails, then it still registers it.
> +}
> +
> +static void en751221_register_clocks(struct device *dev,
> + struct clk_hw_onecell_data *clk_data,
> + struct regmap *map, void __iomem *np_base)
> +{
> + enum en_hir hid = get_hw_id(np_base);
> + struct clk_hw *hw;
> + u32 rate;
> + u32 div;
> + int err;
> +
> + /* PCI */
> + hw = en7523_register_pcie_clk(dev, np_base);
> + clk_data->hws[EN751221_CLK_PCIE] = hw;
> +
> + /* SPI */
> + rate = EN751221_SPI_BASE;
> + if (hid == HIR_EN7526C)
> + rate = EN751221_SPI_BASE_EN7526C;
> +
> + err = regmap_read(map, EN751221_REG_SPI_DIV, &div);
> + if (err) {
> + pr_err("Failed reading fixed clk div %s: %d\n",
> + "spi", err);
> + } else {
> + div = FIELD_GET(EN751221_REG_SPI_DIV_MASK, div) * 2;
> + if (!div)
> + div = 40;
Should 40 be documented a little better with a #define?
> +
> + en751221_try_register_clk(dev, EN751221_CLK_SPI, clk_data,
> + "spi", rate / div);
> + }
> +
> + /* BUS */
> + rate = FIELD_GET(EN751221_REG_BUS_MASK,
> + readl(np_base + EN751221_REG_BUS));
> + rate *= 1000000;
> + en751221_try_register_clk(dev, EN751221_CLK_BUS, clk_data, "bus",
> + rate);
> +
> + /* CPU */
> + en751221_try_register_clk(dev, EN751221_CLK_CPU, clk_data, "cpu",
> + rate * 4);
> +
> + /* HPT */
> + switch (hid) {
> + case HIR_EN751221:
> + case HIR_EN751627:
> + case HIR_EN7526C:
> + case HIR_EN7580:
> + case HIR_EN7528:
> + rate = 200000000;
> + break;
> + case HIR_MT7505:
> + rate = 100000000;
> + break;
> + case HIR_MT751020:
> + rate = 800000000 / 3;
> + break;
> + default:
> + rate = 250000000;
Should a warning be logged here or in get_hw_id() above? hid can be set
to HIR_UNKNOWN here.
> + }
> + en751221_try_register_clk(dev, EN751221_CLK_HPT, clk_data, "hpt",
> + rate);
> +
> + /* GSW */
> + rate = FIELD_GET(EN751221_REG_SSR3_GSW_MASK,
> + readl(np_base + EN751221_REG_SSR3));
> + en751221_try_register_clk(dev, EN751221_CLK_GSW, clk_data, "gsw",
> + gsw751221_base[rate]);
> +}
> +
> +static int en751221_clk_hw_init(struct platform_device *pdev,
> + struct clk_hw_onecell_data *clk_data)
> +{
> + struct regmap *map;
> + void __iomem *base;
> +
> + map = syscon_regmap_lookup_by_compatible("econet,en751221-chip-scu");
> + if (IS_ERR(map))
> + return PTR_ERR(map);
> +
> + base = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + en751221_register_clocks(&pdev->dev, clk_data, map, base);
Again, any reason why the error handling is missing here?
Brian
> +
> + return en7581_reset_register(&pdev->dev, base, en751221_rst_map,
> + ARRAY_SIZE(en751221_rst_map),
> + en751221_rst_ofs);
> }
>
> static int en7523_clk_probe(struct platform_device *pdev)
> @@ -799,9 +1016,20 @@ static const struct en_clk_soc_data en7581_data = {
> .hw_init = en7581_clk_hw_init,
> };
>
> +static const struct en_clk_soc_data en751221_data = {
> + .num_clocks = EN751221_MAX_CLKS,
> + .pcie_ops = {
> + .is_enabled = en7523_pci_is_enabled,
> + .prepare = en7523_pci_prepare,
> + .unprepare = en7523_pci_unprepare,
> + },
> + .hw_init = en751221_clk_hw_init,
> +};
> +
> static const struct of_device_id of_match_clk_en7523[] = {
> { .compatible = "airoha,en7523-scu", .data = &en7523_data },
> { .compatible = "airoha,en7581-scu", .data = &en7581_data },
> + { .compatible = "econet,en751221-scu", .data = &en751221_data },
> { /* sentinel */ }
> };
>
> --
> 2.39.5
>
--
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^ permalink raw reply
* Re: [PATCH 15/61] trace: Prefer IS_ERR_OR_NULL over manual NULL check
From: Geert Uytterhoeven @ 2026-03-11 14:06 UTC (permalink / raw)
To: Steven Rostedt
Cc: Masami Hiramatsu (Google), Philipp Hahn, amd-gfx, apparmor, bpf,
ceph-devel, cocci, dm-devel, dri-devel, gfs2, intel-gfx,
intel-wired-lan, iommu, kvm, linux-arm-kernel, linux-block,
linux-bluetooth, linux-btrfs, linux-cifs, linux-clk, linux-erofs,
linux-ext4, linux-fsdevel, linux-gpio, linux-hyperv, linux-input,
linux-kernel, linux-leds, linux-media, linux-mips, linux-mm,
linux-modules, linux-mtd, linux-nfs, linux-omap, linux-phy,
linux-pm, linux-rockchip, linux-s390, linux-scsi, linux-sctp,
linux-security-module, linux-sh, linux-sound, linux-stm32,
linux-trace-kernel, linux-usb, linux-wireless, netdev, ntfs3,
samba-technical, sched-ext, target-devel, tipc-discussion, v9fs,
Mathieu Desnoyers
In-Reply-To: <20260311100332.6a2ce4b1@gandalf.local.home>
Hi Steven,
On Wed, 11 Mar 2026 at 15:03, Steven Rostedt <rostedt@goodmis.org> wrote:
> On Wed, 11 Mar 2026 14:13:32 +0900
> Masami Hiramatsu (Google) <mhiramat@kernel.org> wrote:
>
> > Hmm, now IS_ERR_OR_NULL() is an inline function, so it is safe.
> > But if you want to use IS_ERR_OR_NULL() here, it will be better something like
> >
> > node = rhashtable_walk_next(&iter);
> > while (!IS_ERR_OR_NULL(node)) {
> > fprobe_remove_node_in_module(mod, node, &alist);
> > node = rhashtable_walk_next(&iter);
> > }
>
> But now you need to have a duplicate code in order to acquire "node"
>
> I think the patch just makes the code worse.
Obviously we need a new for_each_*() helper hiding all the gory internals?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
--
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^ permalink raw reply
* Re: [PATCH 15/61] trace: Prefer IS_ERR_OR_NULL over manual NULL check
From: Steven Rostedt @ 2026-03-11 14:03 UTC (permalink / raw)
To: Masami Hiramatsu (Google)
Cc: Philipp Hahn, amd-gfx, apparmor, bpf, ceph-devel, cocci, dm-devel,
dri-devel, gfs2, intel-gfx, intel-wired-lan, iommu, kvm,
linux-arm-kernel, linux-block, linux-bluetooth, linux-btrfs,
linux-cifs, linux-clk, linux-erofs, linux-ext4, linux-fsdevel,
linux-gpio, linux-hyperv, linux-input, linux-kernel, linux-leds,
linux-media, linux-mips, linux-mm, linux-modules, linux-mtd,
linux-nfs, linux-omap, linux-phy, linux-pm, linux-rockchip,
linux-s390, linux-scsi, linux-sctp, linux-security-module,
linux-sh, linux-sound, linux-stm32, linux-trace-kernel, linux-usb,
linux-wireless, netdev, ntfs3, samba-technical, sched-ext,
target-devel, tipc-discussion, v9fs, Mathieu Desnoyers
In-Reply-To: <20260311141332.b611237d36b61b2409e66cb3@kernel.org>
On Wed, 11 Mar 2026 14:13:32 +0900
Masami Hiramatsu (Google) <mhiramat@kernel.org> wrote:
> Hmm, now IS_ERR_OR_NULL() is an inline function, so it is safe.
> But if you want to use IS_ERR_OR_NULL() here, it will be better something like
>
> node = rhashtable_walk_next(&iter);
> while (!IS_ERR_OR_NULL(node)) {
> fprobe_remove_node_in_module(mod, node, &alist);
> node = rhashtable_walk_next(&iter);
> }
But now you need to have a duplicate code in order to acquire "node"
I think the patch just makes the code worse.
-- Steve
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^ permalink raw reply
* Re: [PATCH 36/61] arch/sh: Prefer IS_ERR_OR_NULL over manual NULL check
From: Geert Uytterhoeven @ 2026-03-11 13:15 UTC (permalink / raw)
To: Philipp Hahn
Cc: amd-gfx, apparmor, bpf, ceph-devel, cocci, dm-devel, dri-devel,
gfs2, intel-gfx, intel-wired-lan, iommu, kvm, linux-arm-kernel,
linux-block, linux-bluetooth, linux-btrfs, linux-cifs, linux-clk,
linux-erofs, linux-ext4, linux-fsdevel, linux-gpio, linux-hyperv,
linux-input, linux-kernel, linux-leds, linux-media, linux-mips,
linux-mm, linux-modules, linux-mtd, linux-nfs, linux-omap,
linux-phy, linux-pm, linux-rockchip, linux-s390, linux-scsi,
linux-sctp, linux-security-module, linux-sh, linux-sound,
linux-stm32, linux-trace-kernel, linux-usb, linux-wireless,
netdev, ntfs3, samba-technical, sched-ext, target-devel,
tipc-discussion, v9fs, Yoshinori Sato, Rich Felker,
John Paul Adrian Glaubitz
In-Reply-To: <20260310-b4-is_err_or_null-v1-36-bd63b656022d@avm.de>
On Tue, 10 Mar 2026 at 12:56, Philipp Hahn <phahn-oss@avm.de> wrote:
> Prefer using IS_ERR_OR_NULL() over using IS_ERR() and a manual NULL
> check.
>
> Change generated with coccinelle.
>
> To: Yoshinori Sato <ysato@users.sourceforge.jp>
> To: Rich Felker <dalias@libc.org>
> To: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de>
> Cc: linux-sh@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> Signed-off-by: Philipp Hahn <phahn-oss@avm.de>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
--
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^ permalink raw reply
* Re: [PATCH v4 1/2] dt-bindings: phy: qcom-edp: Add reference clock for sa8775p eDP PHY
From: Ritesh Kumar @ 2026-03-11 13:07 UTC (permalink / raw)
To: Bjorn Andersson
Cc: robin.clark, lumag, abhinav.kumar, sean, marijn.suijten,
maarten.lankhorst, mripard, tzimmermann, airlied, simona, robh,
krzk+dt, conor+dt, quic_mahap, konradybcio, mani, James.Bottomley,
martin.petersen, vkoul, kishon, cros-qcom-dts-watchers, linux-phy,
linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
linux-scsi, quic_vproddut
In-Reply-To: <gurq34svc5p52bqx5qwkgjmschzcbklmssjzmu2tg5wzgppkft@c6nrw2ageyp2>
On 3/5/2026 12:27 AM, Bjorn Andersson wrote:
> On Wed, Jan 28, 2026 at 05:18:49PM +0530, Ritesh Kumar wrote:
> > The initial sa8775p eDP PHY binding contribution missed adding support for
> > voting on the eDP reference clock. This went unnoticed because the UFS PHY
> > driver happened to enable the same clock.
> >
> > After commit 77d2fa54a945 ("scsi: ufs: qcom : Refactor phy_power_on/off
> > calls"), the eDP reference clock is no longer kept enabled, which results
> > in the following PHY power-on failure:
> >
> > phy phy-aec2a00.phy.10: phy poweron failed --> -110
> >
> > To fix this, explicit voting for the eDP reference clock is required.
> > This patch adds the eDP reference clock for sa8775p eDP PHY and updates
> > the corresponding example node.
> >
> > Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
>
> Is there any reason why you didn't follow up on this patch Ritesh?
> Looks like it's ready to be merged.
I was waiting for patch to merge as there is no pending comments.
> Reviewed-by: Bjorn Andersson <andersson@kernel.org>
>
> Regards,
> Bjorn
>
> > ---
> > .../devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml | 6 ++++--
> > Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml | 1 +
> > 2 files changed, 5 insertions(+), 2 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
> > index e2730a2f25cf..6c827cf9692b 100644
> > --- a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
> > +++ b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
> > @@ -200,9 +200,11 @@ examples:
> > <0x0aec2000 0x1c8>;
> >
> > clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
> > - <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>;
> > + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
> > + <&gcc GCC_EDP_REF_CLKREF_EN>;
> > clock-names = "aux",
> > - "cfg_ahb";
> > + "cfg_ahb",
> > + "ref";
> >
> > #clock-cells = <1>;
> > #phy-cells = <0>;
> > diff --git a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
> > index 4a1daae3d8d4..0bf8bf4f66ac 100644
> > --- a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
> > +++ b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml
> > @@ -74,6 +74,7 @@ allOf:
> > compatible:
> > enum:
> > - qcom,glymur-dp-phy
> > + - qcom,sa8775p-edp-phy
> > - qcom,x1e80100-dp-phy
> > then:
> > properties:
> > --
> > 2.34.1
> >
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^ permalink raw reply
* Re: [PATCH 41/61] pinctrl: Prefer IS_ERR_OR_NULL over manual NULL check
From: Linus Walleij @ 2026-03-11 9:32 UTC (permalink / raw)
To: Philipp Hahn
Cc: amd-gfx, apparmor, bpf, ceph-devel, cocci, dm-devel, dri-devel,
gfs2, intel-gfx, intel-wired-lan, iommu, kvm, linux-arm-kernel,
linux-block, linux-bluetooth, linux-btrfs, linux-cifs, linux-clk,
linux-erofs, linux-ext4, linux-fsdevel, linux-gpio, linux-hyperv,
linux-input, linux-kernel, linux-leds, linux-media, linux-mips,
linux-mm, linux-modules, linux-mtd, linux-nfs, linux-omap,
linux-phy, linux-pm, linux-rockchip, linux-s390, linux-scsi,
linux-sctp, linux-security-module, linux-sh, linux-sound,
linux-stm32, linux-trace-kernel, linux-usb, linux-wireless,
netdev, ntfs3, samba-technical, sched-ext, target-devel,
tipc-discussion, v9fs
In-Reply-To: <20260310-b4-is_err_or_null-v1-41-bd63b656022d@avm.de>
On Tue, Mar 10, 2026 at 12:55 PM Philipp Hahn <phahn-oss@avm.de> wrote:
> Prefer using IS_ERR_OR_NULL() over using IS_ERR() and a manual NULL
> check.
>
> Change generated with coccinelle.
>
> To: Linus Walleij <linusw@kernel.org>
> Cc: linux-gpio@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> Signed-off-by: Philipp Hahn <phahn-oss@avm.de>
Patch applied to the pinctrl tree as obviously correct.
Yours,
Linus Walleij
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