* [PATCH v7 phy-next 23/27] power: supply: cpcap-charger: include missing <linux/property.h>
From: Vladimir Oltean @ 2026-04-30 11:06 UTC (permalink / raw)
To: linux-phy
Cc: Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-scsi,
linux-sunxi, linux-tegra, linux-usb, netdev, spacemit,
UNGLinuxDriver, Sebastian Reichel, Sebastian Reichel
In-Reply-To: <20260430110652.558622-1-vladimir.oltean@nxp.com>
This file uses dev_fwnode() without including the proper header for it,
relying on transitive header inclusion from:
drivers/power/supply/cpcap-charger.c
- include/linux/phy/omap_usb.h
- include/linux/usb/phy_companion.h
- include/linux/usb/otg.h
- include/linux/phy/phy.h
- drivers/phy/phy-provider.h
- include/linux/of.h
- include/linux/property.h
With the future removal of drivers/phy/phy-provider.h from
include/linux/phy/phy.h, this transitive inclusion would break.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
Cc: Sebastian Reichel <sre@kernel.org>
v2->v7: none
v1->v2: collect tag
---
drivers/power/supply/cpcap-charger.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/power/supply/cpcap-charger.c b/drivers/power/supply/cpcap-charger.c
index d0c3008db534..24221244b45b 100644
--- a/drivers/power/supply/cpcap-charger.c
+++ b/drivers/power/supply/cpcap-charger.c
@@ -21,6 +21,7 @@
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
#include <linux/power_supply.h>
+#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/gpio/consumer.h>
--
2.34.1
--
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* [PATCH v7 phy-next 17/27] phy: introduce phy_get_max_link_rate() helper for consumers
From: Vladimir Oltean @ 2026-04-30 11:06 UTC (permalink / raw)
To: linux-phy
Cc: Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-scsi,
linux-sunxi, linux-tegra, linux-usb, netdev, spacemit,
UNGLinuxDriver, Markus Schneider-Pargmann, Andrzej Hajda,
Robert Foss, Laurent Pinchart, Jonas Karlman, Jernej Skrabec,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Andy Yan, Marc Kleine-Budde, Vincent Mailhol,
Nicolas Ferre, Alexandre Belloni, Claudiu Beznea,
Geert Uytterhoeven, Magnus Damm
In-Reply-To: <20260430110652.558622-1-vladimir.oltean@nxp.com>
Consumer drivers shouldn't dereference struct phy, not even to get to
its attributes.
We have phy_get_bus_width() as a precedent for getting the bus_width
attribute, so let's add phy_get_max_link_rate() and use it in DRM and
CAN drivers.
In CAN drivers, the transceiver is acquired through devm_phy_optional_get()
and NULL is given by the API as a non-error case, so the PHY API should
also tolerate NULL coming back to it. This means we can further simplify
the call sites that test for the NULL quality of the transceiver.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Markus Schneider-Pargmann <msp@baylibre.com> # m_can
---
Cc: Andrzej Hajda <andrzej.hajda@intel.com>
Cc: Neil Armstrong <neil.armstrong@linaro.org>
Cc: Robert Foss <rfoss@kernel.org>
Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
Cc: Jonas Karlman <jonas@kwiboo.se>
Cc: Jernej Skrabec <jernej.skrabec@gmail.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Maxime Ripard <mripard@kernel.org>
Cc: Thomas Zimmermann <tzimmermann@suse.de>
Cc: David Airlie <airlied@gmail.com>
Cc: Simona Vetter <simona@ffwll.ch>
Cc: Andy Yan <andy.yan@rock-chips.com>
Cc: Marc Kleine-Budde <mkl@pengutronix.de>
Cc: Vincent Mailhol <mailhol@kernel.org>
Cc: Nicolas Ferre <nicolas.ferre@microchip.com>
Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
Cc: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Cc: Markus Schneider-Pargmann <msp@baylibre.com>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Magnus Damm <magnus.damm@gmail.com>
v3->v7: none
v2->v3: collect tag
v1->v2: make phy_get_bus_width() NULL-tolerant to simplify CAN callers
---
drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c | 4 ++--
drivers/gpu/drm/bridge/synopsys/dw-dp.c | 2 +-
drivers/net/can/at91_can.c | 3 +--
drivers/net/can/flexcan/flexcan-core.c | 3 +--
drivers/net/can/m_can/m_can_platform.c | 3 +--
drivers/net/can/rcar/rcar_canfd.c | 3 +--
drivers/phy/phy-core.c | 9 +++++++++
include/linux/phy/phy.h | 6 ++++++
8 files changed, 22 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
index d20c0f8ad04c..87847978c1fb 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
@@ -1296,7 +1296,7 @@ static u32 cdns_mhdp_get_training_interval_us(struct cdns_mhdp_device *mhdp,
static void cdns_mhdp_fill_host_caps(struct cdns_mhdp_device *mhdp)
{
- unsigned int link_rate;
+ u32 link_rate;
/* Get source capabilities based on PHY attributes */
@@ -1304,7 +1304,7 @@ static void cdns_mhdp_fill_host_caps(struct cdns_mhdp_device *mhdp)
if (!mhdp->host.lanes_cnt)
mhdp->host.lanes_cnt = 4;
- link_rate = mhdp->phy->attrs.max_link_rate;
+ link_rate = phy_get_max_link_rate(mhdp->phy);
if (!link_rate)
link_rate = drm_dp_bw_code_to_link_rate(DP_LINK_BW_8_1);
else
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-dp.c b/drivers/gpu/drm/bridge/synopsys/dw-dp.c
index 45b37885d719..137ea6679732 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-dp.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-dp.c
@@ -530,7 +530,7 @@ static int dw_dp_link_parse(struct dw_dp *dp, struct drm_connector *connector)
link->revision = link->dpcd[DP_DPCD_REV];
link->rate = min_t(u32, min(dp->plat_data.max_link_rate,
- dp->phy->attrs.max_link_rate * 100),
+ phy_get_max_link_rate(dp->phy) * 100),
drm_dp_max_link_rate(link->dpcd));
link->lanes = min_t(u8, phy_get_bus_width(dp->phy),
drm_dp_max_lane_count(link->dpcd));
diff --git a/drivers/net/can/at91_can.c b/drivers/net/can/at91_can.c
index 58da323f14d7..7749da0a58f6 100644
--- a/drivers/net/can/at91_can.c
+++ b/drivers/net/can/at91_can.c
@@ -1125,8 +1125,7 @@ static int at91_can_probe(struct platform_device *pdev)
can_rx_offload_add_timestamp(dev, &priv->offload);
- if (transceiver)
- priv->can.bitrate_max = transceiver->attrs.max_link_rate;
+ priv->can.bitrate_max = phy_get_max_link_rate(transceiver);
if (at91_is_sam9263(priv))
dev->sysfs_groups[0] = &at91_sysfs_attr_group;
diff --git a/drivers/net/can/flexcan/flexcan-core.c b/drivers/net/can/flexcan/flexcan-core.c
index f5d22c61503f..093e48b8da58 100644
--- a/drivers/net/can/flexcan/flexcan-core.c
+++ b/drivers/net/can/flexcan/flexcan-core.c
@@ -2210,8 +2210,7 @@ static int flexcan_probe(struct platform_device *pdev)
priv->reg_xceiver = reg_xceiver;
priv->transceiver = transceiver;
- if (transceiver)
- priv->can.bitrate_max = transceiver->attrs.max_link_rate;
+ priv->can.bitrate_max = phy_get_max_link_rate(transceiver);
if (priv->devtype_data.quirks & FLEXCAN_QUIRK_NR_IRQ_3) {
priv->irq_boff = platform_get_irq(pdev, 1);
diff --git a/drivers/net/can/m_can/m_can_platform.c b/drivers/net/can/m_can/m_can_platform.c
index 56da411878af..2a0f163a683a 100644
--- a/drivers/net/can/m_can/m_can_platform.c
+++ b/drivers/net/can/m_can/m_can_platform.c
@@ -131,8 +131,7 @@ static int m_can_plat_probe(struct platform_device *pdev)
goto probe_fail;
}
- if (transceiver)
- mcan_class->can.bitrate_max = transceiver->attrs.max_link_rate;
+ mcan_class->can.bitrate_max = phy_get_max_link_rate(transceiver);
priv->base = addr;
priv->mram_base = mram_addr;
diff --git a/drivers/net/can/rcar/rcar_canfd.c b/drivers/net/can/rcar/rcar_canfd.c
index eaf8cac78038..9062db48d477 100644
--- a/drivers/net/can/rcar/rcar_canfd.c
+++ b/drivers/net/can/rcar/rcar_canfd.c
@@ -1884,8 +1884,7 @@ static int rcar_canfd_channel_probe(struct rcar_canfd_global *gpriv, u32 ch,
priv->transceiver = transceiver;
priv->channel = ch;
priv->gpriv = gpriv;
- if (transceiver)
- priv->can.bitrate_max = transceiver->attrs.max_link_rate;
+ priv->can.bitrate_max = phy_get_max_link_rate(transceiver);
priv->can.clock.freq = fcan_freq;
dev_info(dev, "can_clk rate is %u\n", priv->can.clock.freq);
diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c
index 0d0be494cfd7..737a760d97d1 100644
--- a/drivers/phy/phy-core.c
+++ b/drivers/phy/phy-core.c
@@ -647,6 +647,15 @@ void phy_set_bus_width(struct phy *phy, int bus_width)
}
EXPORT_SYMBOL_GPL(phy_set_bus_width);
+u32 phy_get_max_link_rate(struct phy *phy)
+{
+ if (!phy)
+ return 0;
+
+ return phy->attrs.max_link_rate;
+}
+EXPORT_SYMBOL_GPL(phy_get_max_link_rate);
+
/**
* _of_phy_get() - lookup and obtain a reference to a phy by phandle
* @np: device_node for which to get the phy
diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index a7e2432ca1ae..34b656084caf 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -57,6 +57,7 @@ int phy_notify_disconnect(struct phy *phy, int port);
int phy_notify_state(struct phy *phy, union phy_notify state);
int phy_get_bus_width(struct phy *phy);
void phy_set_bus_width(struct phy *phy, int bus_width);
+u32 phy_get_max_link_rate(struct phy *phy);
#else
static inline struct phy *phy_get(struct device *dev, const char *string)
{
@@ -256,6 +257,11 @@ static inline int phy_get_bus_width(struct phy *phy)
static inline void phy_set_bus_width(struct phy *phy, int bus_width)
{
}
+
+static inline u32 phy_get_max_link_rate(struct phy *phy)
+{
+ return 0;
+}
#endif /* IS_ENABLED(CONFIG_GENERIC_PHY) */
#endif /* __PHY_CONSUMER_H */
--
2.34.1
--
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https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH v7 phy-next 16/27] phy: make phy_get_mode(), phy_(get|set)_bus_width() NULL tolerant
From: Vladimir Oltean @ 2026-04-30 11:06 UTC (permalink / raw)
To: linux-phy
Cc: Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-scsi,
linux-sunxi, linux-tegra, linux-usb, netdev, spacemit,
UNGLinuxDriver
In-Reply-To: <20260430110652.558622-1-vladimir.oltean@nxp.com>
The PHY API has an optional "get" which returns NULL, so it needs to
accept that NULL coming back in.
Most PHY functions do this, only the formerly static inline attribute
dereferences did not.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
v2->v7: none
v1->v2: patch is new
---
drivers/phy/phy-core.c | 9 ++++++++-
include/linux/phy/phy.h | 2 ++
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c
index a1aff00fba7c..0d0be494cfd7 100644
--- a/drivers/phy/phy-core.c
+++ b/drivers/phy/phy-core.c
@@ -624,19 +624,26 @@ EXPORT_SYMBOL_GPL(phy_validate);
enum phy_mode phy_get_mode(struct phy *phy)
{
+ if (!phy)
+ return PHY_MODE_INVALID;
+
return phy->attrs.mode;
}
EXPORT_SYMBOL_GPL(phy_get_mode);
int phy_get_bus_width(struct phy *phy)
{
+ if (!phy)
+ return 0;
+
return phy->attrs.bus_width;
}
EXPORT_SYMBOL_GPL(phy_get_bus_width);
void phy_set_bus_width(struct phy *phy, int bus_width)
{
- phy->attrs.bus_width = bus_width;
+ if (phy)
+ phy->attrs.bus_width = bus_width;
}
EXPORT_SYMBOL_GPL(phy_set_bus_width);
diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index f208edd25afe..a7e2432ca1ae 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -248,6 +248,8 @@ static inline int phy_notify_state(struct phy *phy, union phy_notify state)
static inline int phy_get_bus_width(struct phy *phy)
{
+ if (!phy)
+ return 0;
return -ENOSYS;
}
--
2.34.1
--
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^ permalink raw reply related
* [PATCH v7 phy-next 14/27] usb: gadget: tegra-xudc: avoid direct dereference of phy->dev.of_node
From: Vladimir Oltean @ 2026-04-30 11:06 UTC (permalink / raw)
To: linux-phy
Cc: Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-scsi,
linux-sunxi, linux-tegra, linux-usb, netdev, spacemit,
UNGLinuxDriver, Greg Kroah-Hartman, JC Kuo, Johan Hovold,
Jonathan Hunter, Mathias Nyman, Thierry Reding
In-Reply-To: <20260430110652.558622-1-vladimir.oltean@nxp.com>
In a somewhat similar situation as the Tegra USB host controller driver,
the Tegra XUDC driver for USB gadget mode needs to get to a struct
usb_phy that sits behind the same OF node as the Generic PHY. It does
that directly, which will no longer be possible. The PHY provider is
also the xusb padctl driver.
The rework here is also to implement a parallel OF node lookup path
based on the "phys" phandle and the #phy-cells of the padctl provider.
Some further notes:
- create a local "usbphy" variable to hold the devm_usb_get_phy_by_node()
output. This makes the error checks more obvious (avoids keeping an
error-encoded pointer in xudc->usbphy[i] even temporarily).
- the "if (IS_ERR(utmi_phy)) .. else if (utmi_phy) .. else if (!utmi_phy)"
pattern can be simplified, considering that neither the IS_ERR() nor
the NULL case continue execution in the current block. Therefore, we
can move the case where the "utmi_phy" is a valid pointer outside the
"if" checks, and this reduces the code indentation level.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: JC Kuo <jckuo@nvidia.com>
Cc: Johan Hovold <johan+linaro@kernel.org>
Cc: Jonathan Hunter <jonathanh@nvidia.com>
Cc: Mathias Nyman <mathias.nyman@intel.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
v5->v7: none
v4->v5: patch is new
---
drivers/usb/gadget/udc/tegra-xudc.c | 35 ++++++++++++++++++++---------
1 file changed, 24 insertions(+), 11 deletions(-)
diff --git a/drivers/usb/gadget/udc/tegra-xudc.c b/drivers/usb/gadget/udc/tegra-xudc.c
index e9d33be02866..cf4e6c87e44d 100644
--- a/drivers/usb/gadget/udc/tegra-xudc.c
+++ b/drivers/usb/gadget/udc/tegra-xudc.c
@@ -3494,6 +3494,7 @@ static void tegra_xudc_device_params_init(struct tegra_xudc *xudc)
static int tegra_xudc_phy_get(struct tegra_xudc *xudc)
{
+ struct device_node *np = dev_of_node(xudc->dev);
int err = 0, usb3_companion_port;
unsigned int i, j;
@@ -3515,7 +3516,10 @@ static int tegra_xudc_phy_get(struct tegra_xudc *xudc)
xudc->vbus_nb.notifier_call = tegra_xudc_vbus_notify;
for (i = 0; i < xudc->soc->num_phys; i++) {
+ struct of_phandle_args args;
char phy_name[] = "usb.-.";
+ struct usb_phy *usbphy;
+ int index, err;
/* Get USB2 phy */
snprintf(phy_name, sizeof(phy_name), "usb2-%d", i);
@@ -3525,22 +3529,31 @@ static int tegra_xudc_phy_get(struct tegra_xudc *xudc)
dev_err_probe(xudc->dev, err,
"failed to get PHY for phy-name usb2-%d\n", i);
goto clean_up;
- } else if (xudc->utmi_phy[i]) {
- /* Get usb-phy, if utmi phy is available */
- xudc->usbphy[i] = devm_usb_get_phy_by_node(xudc->dev,
- xudc->utmi_phy[i]->dev.of_node,
- NULL);
- if (IS_ERR(xudc->usbphy[i])) {
- err = PTR_ERR(xudc->usbphy[i]);
- dev_err_probe(xudc->dev, err,
- "failed to get usbphy-%d\n", i);
- goto clean_up;
- }
} else if (!xudc->utmi_phy[i]) {
/* if utmi phy is not available, ignore USB3 phy get */
continue;
}
+ index = of_property_match_string(np, "phy-names", phy_name);
+ if (index < 0)
+ continue;
+
+ err = of_parse_phandle_with_args(np, "phys", "#phy-cells",
+ index, &args);
+ if (err)
+ continue;
+
+ /* Get usb-phy, if utmi phy is available */
+ usbphy = devm_usb_get_phy_by_node(xudc->dev, args.np, NULL);
+ of_node_put(args.np);
+ if (IS_ERR(usbphy)) {
+ err = PTR_ERR(usbphy);
+ dev_err_probe(xudc->dev, err,
+ "failed to get usbphy-%d\n", i);
+ goto clean_up;
+ }
+ xudc->usbphy[i] = usbphy;
+
/* Get USB3 phy */
usb3_companion_port = tegra_xusb_padctl_get_usb3_companion(xudc->padctl, i);
if (usb3_companion_port < 0)
--
2.34.1
--
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* [PATCH v7 phy-next 13/27] usb: host: tegra: avoid direct dereference of phy->dev.of_node
From: Vladimir Oltean @ 2026-04-30 11:06 UTC (permalink / raw)
To: linux-phy
Cc: Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-scsi,
linux-sunxi, linux-tegra, linux-usb, netdev, spacemit,
UNGLinuxDriver, Greg Kroah-Hartman, JC Kuo, Johan Hovold,
Jonathan Hunter, Mathias Nyman, Thierry Reding
In-Reply-To: <20260430110652.558622-1-vladimir.oltean@nxp.com>
A piece of context which seems relevant here is that the USB subsystem
is transitioning from struct usb_phy to struct phy (belonging to the
Generic PHY subsystem). Commit 1a229d8690a0 ("Revert "usb: phy: add usb
phy notify port status API"") seems to confirm that this is the case.
In the transition process, some PHY provider drivers register themselves
as both Generic PHY and USB PHY in an attempt to bridge the API gap.
Such is the case with drivers/phy/tegra/xusb.c, accessed here by the
Tegra USB host driver. This USB host expects the PHY device behind the
Generic PHY to also be a USB PHY, and calls
devm_usb_get_phy_by_node(phy->dev.of_node).
The Generic PHY exposes no API to get the OF node from a PHY device, so
the Tegra USB host driver gets it directly. However, "struct phy" will
be made an opaque pointer, to avoid misuse, so this will no longer be
possible.
Considering the fact that the Generic PHY/USB PHY duality is a
transitional state, I am deliberately not planning to make the life of
this driver any easier by providing a helper to get to the OF node
somehow. Instead, implement a parallel lookup path through which the
Tegra USB host driver can continue to get to the OF node provided by the
padctl component, using the 'phys' phandle.
Secondly (minor issue) the driver uses the phy->dev.of_node again to
print using dev_dbg() that a "remote wake" was detected. Just print the
index at which the PHY appears inside the driver's tegra->phys[] array
instead.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: JC Kuo <jckuo@nvidia.com>
Cc: Johan Hovold <johan+linaro@kernel.org>
Cc: Jonathan Hunter <jonathanh@nvidia.com>
Cc: Mathias Nyman <mathias.nyman@intel.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
v5->v7: none
v4->v5: patch is new
---
drivers/usb/host/xhci-tegra.c | 42 ++++++++++++++++++++++-------------
1 file changed, 26 insertions(+), 16 deletions(-)
diff --git a/drivers/usb/host/xhci-tegra.c b/drivers/usb/host/xhci-tegra.c
index d2214d309e96..99b0ac9763f9 100644
--- a/drivers/usb/host/xhci-tegra.c
+++ b/drivers/usb/host/xhci-tegra.c
@@ -1491,6 +1491,7 @@ static int tegra_xhci_id_notify(struct notifier_block *nb,
static int tegra_xusb_init_usb_phy(struct tegra_xusb *tegra)
{
+ struct device_node *np = dev_of_node(tegra->dev);
unsigned int i;
tegra->usbphy = devm_kcalloc(tegra->dev, tegra->num_usb_phys,
@@ -1504,23 +1505,33 @@ static int tegra_xusb_init_usb_phy(struct tegra_xusb *tegra)
tegra->otg_usb3_port = -EINVAL;
for (i = 0; i < tegra->num_usb_phys; i++) {
- struct phy *phy = tegra_xusb_get_phy(tegra, "usb2", i);
+ struct of_phandle_args args;
+ struct usb_phy *usbphy;
+ int index, err;
+ char prop[8];
- if (!phy)
+ snprintf(prop, sizeof(prop), "usb2-%d", i);
+
+ /*
+ * usb-phy is optional, continue if it's not available.
+ */
+ index = of_property_match_string(np, "phy-names", prop);
+ if (index < 0)
continue;
- tegra->usbphy[i] = devm_usb_get_phy_by_node(tegra->dev,
- phy->dev.of_node,
- &tegra->id_nb);
- if (!IS_ERR(tegra->usbphy[i])) {
- dev_dbg(tegra->dev, "usbphy-%d registered", i);
- otg_set_host(tegra->usbphy[i]->otg, &tegra->hcd->self);
- } else {
- /*
- * usb-phy is optional, continue if its not available.
- */
- tegra->usbphy[i] = NULL;
- }
+ err = of_parse_phandle_with_args(np, "phys", "#phy-cells",
+ index, &args);
+ if (err)
+ continue;
+
+ usbphy = devm_usb_get_phy_by_node(tegra->dev, args.np,
+ &tegra->id_nb);
+ if (IS_ERR(usbphy))
+ continue;
+
+ tegra->usbphy[i] = usbphy;
+ dev_dbg(tegra->dev, "usbphy-%d registered", i);
+ otg_set_host(tegra->usbphy[i]->otg, &tegra->hcd->self);
}
return 0;
@@ -2168,8 +2179,7 @@ static void tegra_xhci_disable_phy_wake(struct tegra_xusb *tegra)
continue;
if (tegra_xusb_padctl_remote_wake_detected(padctl, tegra->phys[i]))
- dev_dbg(tegra->dev, "%pOF remote wake detected\n",
- tegra->phys[i]->dev.of_node);
+ dev_dbg(tegra->dev, "PHY %d remote wake detected\n", i);
tegra_xusb_padctl_disable_phy_wake(padctl, tegra->phys[i]);
}
--
2.34.1
--
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https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH v7 phy-next 11/27] scsi: ufs: qcom: include missing <linux/interrupt.h>
From: Vladimir Oltean @ 2026-04-30 11:06 UTC (permalink / raw)
To: linux-phy
Cc: Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-scsi,
linux-sunxi, linux-tegra, linux-usb, netdev, spacemit,
UNGLinuxDriver, Martin K . Petersen, Manivannan Sadhasivam,
James E.J. Bottomley
In-Reply-To: <20260430110652.558622-1-vladimir.oltean@nxp.com>
This driver uses devm_request_irq() without including <linux/interrupt.h>
by itself, which would lead to build failures if the headers providing
this transitively were to stop providing it.
On aarch64, we can see, using KCFLAGS='-H' make drivers/ufs/host/ufs-qcom.o,
that the inclusion path is:
drivers/ufs/host/ufs-qcom.c
-> include/linux/acpi.h
-> arch/arm64/include/asm/acpi.h
-> include/linux/efi.h
-> include/linux/rtc.h
-> include/linux/interrupt.h
Whereas on armv7, the situation is quite different. This architecture
has no CONFIG_ACPI symbol, and therefore on it, <linux/acpi.h> does not
include <asm/acpi.h>, and <linux/interrupt.h> is not provided that way.
It is provided, however, through this "fallback" path:
drivers/ufs/host/ufs-qcom.c
-> include/linux/phy/phy.h
-> include/linux/regulator/consumer.h
-> include/linux/suspend.h
-> include/linux/swap.h
-> include/linux/memcontrol.h
-> include/linux/writeback.h
-> include/linux/interrupt.h
The point is that <linux/phy/phy.h> will stop providing
<linux/regulator/consumer.h>, and this would break the transitive
include chain on armv7.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Martin K. Petersen <martin.petersen@oracle.com>
---
Cc: Manivannan Sadhasivam <mani@kernel.org>
Cc: "James E.J. Bottomley" <James.Bottomley@HansenPartnership.com>
Cc: "Martin K. Petersen" <martin.petersen@oracle.com>
v6->v7: collect tag from Martin
v5->v6: patch is new
---
drivers/ufs/host/ufs-qcom.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index 872e4effa60f..c7a02f6ef504 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -10,6 +10,7 @@
#include <linux/devfreq.h>
#include <linux/gpio/consumer.h>
#include <linux/interconnect.h>
+#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/phy/phy.h>
--
2.34.1
--
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https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH v7 phy-next 12/27] drm/rockchip: dw_hdmi: avoid direct dereference of phy->dev.of_node
From: Vladimir Oltean @ 2026-04-30 11:06 UTC (permalink / raw)
To: linux-phy
Cc: Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-scsi,
linux-sunxi, linux-tegra, linux-usb, netdev, spacemit,
UNGLinuxDriver, Heiko Stueber, Sandy Huang, Andy Yan,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter
In-Reply-To: <20260430110652.558622-1-vladimir.oltean@nxp.com>
The dw_hdmi-rockchip driver validates pixel clock rates against the
HDMI PHY's internal clock provider on certain SoCs like RK3328.
This is currently achieved by dereferencing hdmi->phy->dev.of_node
to obtain the provider node, which violates the Generic PHY API's
encapsulation (the goal is for struct phy to be an opaque pointer
with a hidden definition, to be interacted with only using API
functions or NULL pointer checks, for the case where optional variants
of phy_get() did not find a PHY).
Refactor dw_hdmi_rockchip_bind() to perform a manual phandle lookup
on the "hdmi" PHY index within the controller's DT node. This provides
a parallel path to the clock provider's OF node without relying on the
internal structure of the struct phy handle.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Heiko Stueber <heiko@sntech.de>
---
Cc: Sandy Huang <hjc@rock-chips.com>
Cc: "Heiko Stübner" <heiko@sntech.de>
Cc: Andy Yan <andy.yan@rock-chips.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Maxime Ripard <mripard@kernel.org>
Cc: Thomas Zimmermann <tzimmermann@suse.de>
Cc: David Airlie <airlied@gmail.com>
Cc: Simona Vetter <simona@ffwll.ch>
v4->v7: none
v3->v4: add commit message clarification of what is understood by
"opaque pointer"
v1->v3: none
---
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 25 ++++++++++++---------
1 file changed, 15 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index 0dc1eb5d2ae3..7abb42e486c0 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -537,21 +537,22 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
void *data)
{
struct platform_device *pdev = to_platform_device(dev);
+ struct device_node *np = dev_of_node(dev);
struct dw_hdmi_plat_data *plat_data;
const struct of_device_id *match;
struct drm_device *drm = data;
struct drm_encoder *encoder;
struct rockchip_hdmi *hdmi;
- int ret;
+ int ret, index;
- if (!pdev->dev.of_node)
+ if (!np)
return -ENODEV;
hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
if (!hdmi)
return -ENOMEM;
- match = of_match_node(dw_hdmi_rockchip_dt_ids, pdev->dev.of_node);
+ match = of_match_node(dw_hdmi_rockchip_dt_ids, np);
plat_data = devm_kmemdup(&pdev->dev, match->data,
sizeof(*plat_data), GFP_KERNEL);
if (!plat_data)
@@ -564,9 +565,9 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
plat_data->priv_data = hdmi;
encoder = &hdmi->encoder.encoder;
- encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
+ encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, np);
rockchip_drm_encoder_set_crtc_endpoint_id(&hdmi->encoder,
- dev->of_node, 0, 0);
+ np, 0, 0);
/*
* If we failed to find the CRTC(s) which this encoder is
@@ -588,13 +589,17 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
return dev_err_probe(hdmi->dev, ret, "failed to get phy\n");
}
- if (hdmi->phy) {
+ index = of_property_match_string(np, "phy-names", "hdmi");
+ if (index >= 0) {
struct of_phandle_args clkspec;
- clkspec.np = hdmi->phy->dev.of_node;
- hdmi->hdmiphy_clk = of_clk_get_from_provider(&clkspec);
- if (IS_ERR(hdmi->hdmiphy_clk))
- hdmi->hdmiphy_clk = NULL;
+ if (!of_parse_phandle_with_args(np, "phys", "#phy-cells", index,
+ &clkspec)) {
+ hdmi->hdmiphy_clk = of_clk_get_from_provider(&clkspec);
+ of_node_put(clkspec.np);
+ if (IS_ERR(hdmi->hdmiphy_clk))
+ hdmi->hdmiphy_clk = NULL;
+ }
}
if (hdmi->chip_data == &rk3568_chip_data) {
--
2.34.1
--
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https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH v7 phy-next 10/27] scsi: ufs: qcom: keep parallel track of PHY power state
From: Vladimir Oltean @ 2026-04-30 11:06 UTC (permalink / raw)
To: linux-phy
Cc: Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-scsi,
linux-sunxi, linux-tegra, linux-usb, netdev, spacemit,
UNGLinuxDriver, James E.J. Bottomley, Manivannan Sadhasivam,
Martin K. Petersen, Nitin Rawat
In-Reply-To: <20260430110652.558622-1-vladimir.oltean@nxp.com>
PHY consumer drivers should not look at the phy->power_count (a PHY
internal field), because in the general case there might also be other
consumers who have called phy_power_on() too, so the fact that the
power_count is non-zero does not mean that we did.
Moreover, struct phy will become opaque soon, so the qcom UFS driver
will not be able to apply this pattern anymore.
By all accounts, the need for ufs_qcom_power_up_sequence() to call
phy_power_off() prior to phy_init() denotes a skewed state of affairs.
(1) The Generic PHY API warns if phy_power_on() is called prior to
phy_init() - which ufs-qcom.c does, from ufs_qcom_setup_clocks().
The UFS controller driver hides its tracks by dropping the power
count prior to phy_init(), and that API violation goes undetected.
(2) phy_calibrate(), as implemented by the phy-qcom-qmp-ufs.c provider,
only works once after power on. Next time it will time out. And
since ufs_qcom_hce_enable_notify() -> ufs_qcom_power_up_sequence()
is called in a retry loop by the UFS core, the PHY power would
normally be on, hence the phy_power_off() call to ensure the
consistent state during phy_calibrate().
The above constitute improper Generic PHY API use, *but* fixing that
requires delicate surgery and I'm only here to stop this PHY consumer
from using fields it's not supposed to.
Once this discussion is settled, I will also address the above issues as
follow-ups:
https://lore.kernel.org/linux-phy/20260327112858.r5lpqygtvsane2vf@skbuf/
Until then, we can reimplement the logic in this driver in a
bug-compatible way, by keeping parallel track of just the UFS
controller's calls to phy_power_on() and phy_power_off().
Note that phy_power_off() shouldn't return an error in general and
doesn't return an error in the particular case of the phy-qcom-qmp-ufs.c
provider. So I've removed the one handling of phy_power_off() errors
from ufs_qcom_setup_clocks().
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
Cc: "James E.J. Bottomley" <James.Bottomley@HansenPartnership.com>
Cc: Manivannan Sadhasivam <mani@kernel.org>
Cc: "Martin K. Petersen" <martin.petersen@oracle.com>
Cc: Nitin Rawat <quic_nitirawa@quicinc.com>
v6->v7: none
v5->v6:
- rewrite commit message
- drop phy_power_off() error handling from ufs_qcom_setup_clocks()
v4->v5: patch is new
---
drivers/ufs/host/ufs-qcom.c | 15 ++++++++-------
drivers/ufs/host/ufs-qcom.h | 1 +
2 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index bc037db46624..872e4effa60f 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -508,9 +508,10 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
if (ret)
return ret;
- if (phy->power_count)
+ if (host->phy_powered_on) {
phy_power_off(phy);
-
+ host->phy_powered_on = false;
+ }
/* phy initialization - calibrate the phy */
ret = phy_init(phy);
@@ -531,6 +532,7 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
__func__, ret);
goto out_disable_phy;
}
+ host->phy_powered_on = true;
ret = phy_calibrate(phy);
if (ret) {
@@ -1447,11 +1449,8 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
ufs_qcom_dev_ref_clk_ctrl(host, false);
}
- err = phy_power_off(phy);
- if (err) {
- dev_err(hba->dev, "phy power off failed, ret=%d\n", err);
- return err;
- }
+ phy_power_off(phy);
+ host->phy_powered_on = false;
}
break;
case POST_CHANGE:
@@ -1461,6 +1460,7 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
dev_err(hba->dev, "phy power on failed, ret = %d\n", err);
return err;
}
+ host->phy_powered_on = true;
/* enable the device ref clock for HS mode*/
if (ufshcd_is_hs_mode(&hba->pwr_info))
@@ -1651,6 +1651,7 @@ static void ufs_qcom_exit(struct ufs_hba *hba)
ufs_qcom_disable_lane_clks(host);
phy_power_off(host->generic_phy);
+ host->phy_powered_on = false;
phy_exit(host->generic_phy);
}
diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h
index 5d083331a7f4..6eafba3c203b 100644
--- a/drivers/ufs/host/ufs-qcom.h
+++ b/drivers/ufs/host/ufs-qcom.h
@@ -322,6 +322,7 @@ struct ufs_qcom_host {
struct clk_bulk_data *clks;
u32 num_clks;
bool is_lane_clks_enabled;
+ bool phy_powered_on;
struct icc_path *icc_ddr;
struct icc_path *icc_cpu;
--
2.34.1
--
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https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH v7 phy-next 09/27] scsi: ufs: exynos: stop poking into struct phy guts
From: Vladimir Oltean @ 2026-04-30 11:06 UTC (permalink / raw)
To: linux-phy
Cc: Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-scsi,
linux-sunxi, linux-tegra, linux-usb, netdev, spacemit,
UNGLinuxDriver, Bart Van Assche, Alim Akhtar, Martin K . Petersen,
Peter Griffin, James E.J. Bottomley, Krzysztof Kozlowski,
Chanho Park
In-Reply-To: <20260430110652.558622-1-vladimir.oltean@nxp.com>
The Exynos host controller driver is clearly a PHY consumer (gets the
ufs->phy using devm_phy_get()), but pokes into the guts of struct phy
to get the generic_phy->power_count.
The UFS core (specifically ufshcd_link_startup()) may call the variant
operation exynos_ufs_pre_link() -> exynos_ufs_phy_init() multiple times
if the link startup fails and needs to be retried.
However ufs-exynos shouldn't be doing what it's doing, i.e. looking at
the generic_phy->power_count, because in the general sense of the API, a
single Generic PHY may have multiple consumers. If ufs-exynos looks at
generic_phy->power_count, there's no guarantee that this ufs-exynos
instance is the one who previously bumped that power count. So it may be
powering down the PHY on behalf of another consumer.
The correct way in which this should be handled is ufs-exynos should
*remember* whether it has initialized and powered up the PHY before, and
power it down during link retries. Not rely on the power_count (which,
btw, on the writer side is modified under &phy->mutex, but on the reader
side is accessed unlocked). This is a discouraged pattern even if here
it doesn't cause functional problems.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Bart Van Assche <bvanassche@acm.org>
Acked-by: Alim Akhtar <alim.akhtar@samsung.com>
Tested-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Martin K. Petersen <martin.petersen@oracle.com>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
---
Cc: Alim Akhtar <alim.akhtar@samsung.com>
Cc: Peter Griffin <peter.griffin@linaro.org>
Cc: "James E.J. Bottomley" <James.Bottomley@HansenPartnership.com>
Cc: "Martin K. Petersen" <martin.petersen@oracle.com>
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Chanho Park <chanho61.park@samsung.com>
v6->v7: collect tags from Martin and Peter
v5->v6: collect tags from Alim Akhtar
v4->v5: collect tag, add "scsi: " prefix to commit title
v3->v4: none
v2->v3:
- add Cc Chanho Park, author of commit 3d73b200f989 ("scsi: ufs:
ufs-exynos: Change ufs phy control sequence")
v1->v2:
- add better ufs->phy_powered_on handling in exynos_ufs_exit(),
exynos_ufs_suspend() and exynos_ufs_resume() which ensures we won't
enter a phy->power_count underrun condition
---
drivers/ufs/host/ufs-exynos.c | 24 ++++++++++++++++++++----
drivers/ufs/host/ufs-exynos.h | 1 +
2 files changed, 21 insertions(+), 4 deletions(-)
diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c
index 77a6c8e44485..be9bfde915ce 100644
--- a/drivers/ufs/host/ufs-exynos.c
+++ b/drivers/ufs/host/ufs-exynos.c
@@ -949,9 +949,10 @@ static int exynos_ufs_phy_init(struct exynos_ufs *ufs)
phy_set_bus_width(generic_phy, ufs->avail_ln_rx);
- if (generic_phy->power_count) {
+ if (ufs->phy_powered_on) {
phy_power_off(generic_phy);
phy_exit(generic_phy);
+ ufs->phy_powered_on = false;
}
ret = phy_init(generic_phy);
@@ -965,6 +966,8 @@ static int exynos_ufs_phy_init(struct exynos_ufs *ufs)
if (ret)
goto out_exit_phy;
+ ufs->phy_powered_on = true;
+
return 0;
out_exit_phy:
@@ -1513,6 +1516,9 @@ static void exynos_ufs_exit(struct ufs_hba *hba)
{
struct exynos_ufs *ufs = ufshcd_get_variant(hba);
+ if (!ufs->phy_powered_on)
+ return;
+
phy_power_off(ufs->phy);
phy_exit(ufs->phy);
}
@@ -1727,8 +1733,10 @@ static int exynos_ufs_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op,
if (ufs->drv_data->suspend)
ufs->drv_data->suspend(ufs);
- if (!ufshcd_is_link_active(hba))
+ if (!ufshcd_is_link_active(hba) && ufs->phy_powered_on) {
phy_power_off(ufs->phy);
+ ufs->phy_powered_on = false;
+ }
return 0;
}
@@ -1736,9 +1744,17 @@ static int exynos_ufs_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op,
static int exynos_ufs_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
{
struct exynos_ufs *ufs = ufshcd_get_variant(hba);
+ int err;
- if (!ufshcd_is_link_active(hba))
- phy_power_on(ufs->phy);
+ if (!ufshcd_is_link_active(hba) && !ufs->phy_powered_on) {
+ err = phy_power_on(ufs->phy);
+ if (err) {
+ dev_err(hba->dev, "Failed to power on PHY: %pe\n",
+ ERR_PTR(err));
+ } else {
+ ufs->phy_powered_on = true;
+ }
+ }
exynos_ufs_config_smu(ufs);
exynos_ufs_fmp_resume(hba);
diff --git a/drivers/ufs/host/ufs-exynos.h b/drivers/ufs/host/ufs-exynos.h
index abe7e472759e..683b9150e2ba 100644
--- a/drivers/ufs/host/ufs-exynos.h
+++ b/drivers/ufs/host/ufs-exynos.h
@@ -227,6 +227,7 @@ struct exynos_ufs {
int avail_ln_rx;
int avail_ln_tx;
int rx_sel_idx;
+ bool phy_powered_on;
struct ufs_pa_layer_attr dev_req_params;
struct ufs_phy_time_cfg t_cfg;
ktime_t entry_hibern8_t;
--
2.34.1
--
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^ permalink raw reply related
* [PATCH v7 phy-next 08/27] PCI: Remove device links to PHY
From: Vladimir Oltean @ 2026-04-30 11:06 UTC (permalink / raw)
To: linux-phy
Cc: Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-scsi,
linux-sunxi, linux-tegra, linux-usb, netdev, spacemit,
UNGLinuxDriver, Bjorn Helgaas, Manivannan Sadhasivam,
Lorenzo Pieralisi, Krzysztof Wilczyński, Rob Herring,
Vignesh Raghavendra, Siddharth Vadapalli
In-Reply-To: <20260430110652.558622-1-vladimir.oltean@nxp.com>
This is practically a full revert of commit
7a4db656a635 ("PCI: dra7xx: Create functional dependency between PCIe and PHY")
and a partial revert of the device link pieces from commits
dfb80534692d ("PCI: cadence: Add generic PHY support to host and EP drivers")
49229238ab47 ("PCI: keystone: Cleanup PHY handling")
The trouble with these commits is that they dereference fields inside
struct phy from a consumer driver, which will become no longer possible.
Since commit 987351e1ea77 ("phy: core: Add consumer device link
support") from 2019, the PHY core also adds a device link to order PHY
provider and consumer suspend/resume operations. All reverted commits
are from 2017-2018, and what they do should actually be redundant now.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
---
Cc: Lorenzo Pieralisi <lpieralisi@kernel.org>
Cc: "Krzysztof Wilczyński" <kwilczynski@kernel.org>
Cc: Manivannan Sadhasivam <mani@kernel.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Vignesh Raghavendra <vigneshr@ti.com>
Cc: Siddharth Vadapalli <s-vadapalli@ti.com>
v6->v7: none
v5->v6: collect tag from Manivannan Sadhasivam
v3->v5: none
v2->v3:
- remove dangling set but unused phy_count local variable in
cdns_plat_pcie_probe()
v1->v2:
- fully remove struct device link **link from struct cdns_pcie and from
cdns_plat_pcie_probe() error path
- collect tag from Bjorn Helgaas
- adjust commit title
---
.../controller/cadence/pcie-cadence-plat.c | 4 ---
drivers/pci/controller/cadence/pcie-cadence.c | 16 +---------
drivers/pci/controller/cadence/pcie-cadence.h | 2 --
drivers/pci/controller/dwc/pci-dra7xx.c | 16 ----------
drivers/pci/controller/dwc/pci-keystone.c | 31 +++----------------
5 files changed, 5 insertions(+), 64 deletions(-)
diff --git a/drivers/pci/controller/cadence/pcie-cadence-plat.c b/drivers/pci/controller/cadence/pcie-cadence-plat.c
index b067a3296dd3..fc39c01b7964 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-plat.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-plat.c
@@ -41,7 +41,6 @@ static int cdns_plat_pcie_probe(struct platform_device *pdev)
struct pci_host_bridge *bridge;
struct cdns_pcie_ep *ep;
struct cdns_pcie_rc *rc;
- int phy_count;
bool is_rc;
int ret;
@@ -122,9 +121,6 @@ static int cdns_plat_pcie_probe(struct platform_device *pdev)
pm_runtime_put_sync(dev);
pm_runtime_disable(dev);
cdns_pcie_disable_phy(cdns_plat_pcie->pcie);
- phy_count = cdns_plat_pcie->pcie->phy_count;
- while (phy_count--)
- device_link_del(cdns_plat_pcie->pcie->link[phy_count]);
return 0;
}
diff --git a/drivers/pci/controller/cadence/pcie-cadence.c b/drivers/pci/controller/cadence/pcie-cadence.c
index a1eada56edba..0ac980249941 100644
--- a/drivers/pci/controller/cadence/pcie-cadence.c
+++ b/drivers/pci/controller/cadence/pcie-cadence.c
@@ -222,7 +222,6 @@ int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie)
struct device_node *np = dev->of_node;
int phy_count;
struct phy **phy;
- struct device_link **link;
int i;
int ret;
const char *name;
@@ -238,10 +237,6 @@ int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie)
if (!phy)
return -ENOMEM;
- link = devm_kcalloc(dev, phy_count, sizeof(*link), GFP_KERNEL);
- if (!link)
- return -ENOMEM;
-
for (i = 0; i < phy_count; i++) {
of_property_read_string_index(np, "phy-names", i, &name);
phy[i] = devm_phy_get(dev, name);
@@ -249,17 +244,10 @@ int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie)
ret = PTR_ERR(phy[i]);
goto err_phy;
}
- link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS);
- if (!link[i]) {
- devm_phy_put(dev, phy[i]);
- ret = -EINVAL;
- goto err_phy;
- }
}
pcie->phy_count = phy_count;
pcie->phy = phy;
- pcie->link = link;
ret = cdns_pcie_enable_phy(pcie);
if (ret)
@@ -268,10 +256,8 @@ int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie)
return 0;
err_phy:
- while (--i >= 0) {
- device_link_del(link[i]);
+ while (--i >= 0)
devm_phy_put(dev, phy[i]);
- }
return ret;
}
diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
index 574e9cf4d003..232b504b5cf9 100644
--- a/drivers/pci/controller/cadence/pcie-cadence.h
+++ b/drivers/pci/controller/cadence/pcie-cadence.h
@@ -82,7 +82,6 @@ struct cdns_plat_pcie_of_data {
* @is_rc: tell whether the PCIe controller mode is Root Complex or Endpoint.
* @phy_count: number of supported PHY devices
* @phy: list of pointers to specific PHY control blocks
- * @link: list of pointers to corresponding device link representations
* @ops: Platform-specific ops to control various inputs from Cadence PCIe
* wrapper
* @cdns_pcie_reg_offsets: Register bank offsets for different SoC
@@ -95,7 +94,6 @@ struct cdns_pcie {
bool is_rc;
int phy_count;
struct phy **phy;
- struct device_link **link;
const struct cdns_pcie_ops *ops;
const struct cdns_plat_pcie_of_data *cdns_pcie_reg_offsets;
};
diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c
index cd904659c321..9c1aef4d0bd1 100644
--- a/drivers/pci/controller/dwc/pci-dra7xx.c
+++ b/drivers/pci/controller/dwc/pci-dra7xx.c
@@ -9,7 +9,6 @@
#include <linux/clk.h>
#include <linux/delay.h>
-#include <linux/device.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
@@ -679,7 +678,6 @@ static int dra7xx_pcie_probe(struct platform_device *pdev)
int i;
int phy_count;
struct phy **phy;
- struct device_link **link;
void __iomem *base;
struct dw_pcie *pci;
struct dra7xx_pcie *dra7xx;
@@ -727,10 +725,6 @@ static int dra7xx_pcie_probe(struct platform_device *pdev)
if (!phy)
return -ENOMEM;
- link = devm_kcalloc(dev, phy_count, sizeof(*link), GFP_KERNEL);
- if (!link)
- return -ENOMEM;
-
dra7xx->clk = devm_clk_get_optional(dev, NULL);
if (IS_ERR(dra7xx->clk))
return dev_err_probe(dev, PTR_ERR(dra7xx->clk),
@@ -745,12 +739,6 @@ static int dra7xx_pcie_probe(struct platform_device *pdev)
phy[i] = devm_phy_get(dev, name);
if (IS_ERR(phy[i]))
return PTR_ERR(phy[i]);
-
- link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS);
- if (!link[i]) {
- ret = -EINVAL;
- goto err_link;
- }
}
dra7xx->base = base;
@@ -852,10 +840,6 @@ static int dra7xx_pcie_probe(struct platform_device *pdev)
pm_runtime_disable(dev);
dra7xx_pcie_disable_phy(dra7xx);
-err_link:
- while (--i >= 0)
- device_link_del(link[i]);
-
return ret;
}
diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c
index fe4836925c4e..cab9fad212ad 100644
--- a/drivers/pci/controller/dwc/pci-keystone.c
+++ b/drivers/pci/controller/dwc/pci-keystone.c
@@ -130,7 +130,6 @@ struct keystone_pcie {
int num_lanes;
u32 num_viewport;
struct phy **phy;
- struct device_link **link;
struct device_node *msi_intc_np;
struct irq_domain *intx_irq_domain;
struct device_node *np;
@@ -1130,7 +1129,6 @@ static int ks_pcie_probe(struct platform_device *pdev)
enum dw_pcie_device_mode mode;
struct dw_pcie *pci;
struct keystone_pcie *ks_pcie;
- struct device_link **link;
struct gpio_desc *gpiod;
struct resource *res;
void __iomem *base;
@@ -1201,31 +1199,17 @@ static int ks_pcie_probe(struct platform_device *pdev)
if (!phy)
return -ENOMEM;
- link = devm_kcalloc(dev, num_lanes, sizeof(*link), GFP_KERNEL);
- if (!link)
- return -ENOMEM;
-
for (i = 0; i < num_lanes; i++) {
snprintf(name, sizeof(name), "pcie-phy%d", i);
phy[i] = devm_phy_optional_get(dev, name);
if (IS_ERR(phy[i])) {
ret = PTR_ERR(phy[i]);
- goto err_link;
- }
-
- if (!phy[i])
- continue;
-
- link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS);
- if (!link[i]) {
- ret = -EINVAL;
- goto err_link;
+ goto err;
}
}
ks_pcie->np = np;
ks_pcie->pci = pci;
- ks_pcie->link = link;
ks_pcie->num_lanes = num_lanes;
ks_pcie->phy = phy;
@@ -1235,7 +1219,7 @@ static int ks_pcie_probe(struct platform_device *pdev)
ret = PTR_ERR(gpiod);
if (ret != -EPROBE_DEFER)
dev_err(dev, "Failed to get reset GPIO\n");
- goto err_link;
+ goto err;
}
/* Obtain references to the PHYs */
@@ -1250,7 +1234,7 @@ static int ks_pcie_probe(struct platform_device *pdev)
if (ret) {
dev_err(dev, "failed to enable phy\n");
- goto err_link;
+ goto err;
}
platform_set_drvdata(pdev, ks_pcie);
@@ -1337,25 +1321,18 @@ static int ks_pcie_probe(struct platform_device *pdev)
pm_runtime_disable(dev);
ks_pcie_disable_phy(ks_pcie);
-err_link:
- while (--i >= 0 && link[i])
- device_link_del(link[i]);
-
+err:
return ret;
}
static void ks_pcie_remove(struct platform_device *pdev)
{
struct keystone_pcie *ks_pcie = platform_get_drvdata(pdev);
- struct device_link **link = ks_pcie->link;
- int num_lanes = ks_pcie->num_lanes;
struct device *dev = &pdev->dev;
pm_runtime_put(dev);
pm_runtime_disable(dev);
ks_pcie_disable_phy(ks_pcie);
- while (num_lanes--)
- device_link_del(link[num_lanes]);
}
static struct platform_driver ks_pcie_driver = {
--
2.34.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH v7 phy-next 06/27] phy: spacemit: include missing <linux/phy/phy.h>
From: Vladimir Oltean @ 2026-04-30 11:06 UTC (permalink / raw)
To: linux-phy
Cc: Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-scsi,
linux-sunxi, linux-tegra, linux-usb, netdev, spacemit,
UNGLinuxDriver, Yixun Lan
In-Reply-To: <20260430110652.558622-1-vladimir.oltean@nxp.com>
This driver relies on a transitive inclusion of the PHY API header
through the USB headers.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Yixun Lan <dlan@kernel.org>
---
Cc: Yixun Lan <dlan@kernel.org>
v5->v7: none
v4->v5: collect tag
v1->v4: none
---
drivers/phy/spacemit/phy-k1-usb2.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/phy/spacemit/phy-k1-usb2.c b/drivers/phy/spacemit/phy-k1-usb2.c
index 9215d0b223b2..01af310d6683 100644
--- a/drivers/phy/spacemit/phy-k1-usb2.c
+++ b/drivers/phy/spacemit/phy-k1-usb2.c
@@ -9,6 +9,7 @@
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/iopoll.h>
+#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/usb/of.h>
--
2.34.1
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply related
* [PATCH v7 phy-next 05/27] phy: add <linux/pm_runtime.h> where missing
From: Vladimir Oltean @ 2026-04-30 11:06 UTC (permalink / raw)
To: linux-phy
Cc: Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-scsi,
linux-sunxi, linux-tegra, linux-usb, netdev, spacemit,
UNGLinuxDriver, Geert Uytterhoeven, André Draszik,
Peter Griffin, Tudor Ambarus, Magnus Damm, Heiko Stuebner
In-Reply-To: <20260430110652.558622-1-vladimir.oltean@nxp.com>
It appears that the phy-mapphone-mdm6600, phy-qcom-snps-femto-v2,
phy-rcar-gen3-pcie, r8a779f0-ether-serdes and phy-rockchip-typec drivers
call runtime PM operations without including the proper header.
This was provided by <linux/phy/phy.h> but no function exported by this
header directly needs it. So we need to drop it from there, and fix up
drivers that used to depend on that.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> # renesas
Reviewed-by: André Draszik <andre.draszik@linaro.org> # google
---
Cc: Peter Griffin <peter.griffin@linaro.org>
Cc: "André Draszik" <andre.draszik@linaro.org>
Cc: Tudor Ambarus <tudor.ambarus@linaro.org>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Heiko Stuebner <heiko@sntech.de>
v2->v7: none
v1->v2: collect tags
---
drivers/phy/motorola/phy-mapphone-mdm6600.c | 1 +
drivers/phy/phy-google-usb.c | 1 +
drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 1 +
drivers/phy/qualcomm/phy-qcom-qmp-usb-legacy.c | 1 +
drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 1 +
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 1 +
drivers/phy/qualcomm/phy-qcom-qusb2.c | 1 +
drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c | 1 +
drivers/phy/renesas/phy-rcar-gen3-pcie.c | 1 +
drivers/phy/renesas/r8a779f0-ether-serdes.c | 1 +
drivers/phy/rockchip/phy-rockchip-typec.c | 1 +
drivers/phy/ti/phy-tusb1210.c | 1 +
12 files changed, 12 insertions(+)
diff --git a/drivers/phy/motorola/phy-mapphone-mdm6600.c b/drivers/phy/motorola/phy-mapphone-mdm6600.c
index fd0e0cd1c1cf..ce1dad8c438d 100644
--- a/drivers/phy/motorola/phy-mapphone-mdm6600.c
+++ b/drivers/phy/motorola/phy-mapphone-mdm6600.c
@@ -17,6 +17,7 @@
#include <linux/of_platform.h>
#include <linux/phy/phy.h>
#include <linux/pinctrl/consumer.h>
+#include <linux/pm_runtime.h>
#define PHY_MDM6600_PHY_DELAY_MS 4000 /* PHY enable 2.2s to 3.5s */
#define PHY_MDM6600_ENABLED_DELAY_MS 8000 /* 8s more total for MDM6600 */
diff --git a/drivers/phy/phy-google-usb.c b/drivers/phy/phy-google-usb.c
index ab20bc20f19e..48cfa2e28347 100644
--- a/drivers/phy/phy-google-usb.c
+++ b/drivers/phy/phy-google-usb.c
@@ -16,6 +16,7 @@
#include <linux/of.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/usb/typec_mux.h>
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
index 93f1aa10d400..b9ea7d058e93 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
@@ -16,6 +16,7 @@
#include <linux/of_graph.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
#include <linux/regulator/consumer.h>
#include <linux/reset.h>
#include <linux/slab.h>
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb-legacy.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb-legacy.c
index 8bf951b0490c..2bd5862c5ba8 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb-legacy.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb-legacy.c
@@ -16,6 +16,7 @@
#include <linux/of_address.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
#include <linux/regulator/consumer.h>
#include <linux/reset.h>
#include <linux/slab.h>
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
index b0ecd5ba2464..d88b8a415e85 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
@@ -15,6 +15,7 @@
#include <linux/of_address.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
#include <linux/regulator/consumer.h>
#include <linux/reset.h>
#include <linux/slab.h>
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
index c342479a3798..f62e1f6ecc07 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
@@ -16,6 +16,7 @@
#include <linux/of_address.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/reset.h>
diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c
index eb93015be841..191040f6d60f 100644
--- a/drivers/phy/qualcomm/phy-qcom-qusb2.c
+++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c
@@ -14,6 +14,7 @@
#include <linux/of.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/reset.h>
diff --git a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c b/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c
index eb0b0f61d98e..8915fa250e81 100644
--- a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c
+++ b/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c
@@ -12,6 +12,7 @@
#include <linux/of.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/reset.h>
diff --git a/drivers/phy/renesas/phy-rcar-gen3-pcie.c b/drivers/phy/renesas/phy-rcar-gen3-pcie.c
index c0e5a4ac82de..3e2cf59ad480 100644
--- a/drivers/phy/renesas/phy-rcar-gen3-pcie.c
+++ b/drivers/phy/renesas/phy-rcar-gen3-pcie.c
@@ -11,6 +11,7 @@
#include <linux/of.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
#include <linux/spinlock.h>
#define PHY_CTRL 0x4000 /* R8A77980 only */
diff --git a/drivers/phy/renesas/r8a779f0-ether-serdes.c b/drivers/phy/renesas/r8a779f0-ether-serdes.c
index 8a6b6f366fe3..c34427ac4fdb 100644
--- a/drivers/phy/renesas/r8a779f0-ether-serdes.c
+++ b/drivers/phy/renesas/r8a779f0-ether-serdes.c
@@ -12,6 +12,7 @@
#include <linux/phy.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
#include <linux/reset.h>
#define R8A779F0_ETH_SERDES_NUM 3
diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c b/drivers/phy/rockchip/phy-rockchip-typec.c
index d9701b6106d5..0a318ccf1bbf 100644
--- a/drivers/phy/rockchip/phy-rockchip-typec.c
+++ b/drivers/phy/rockchip/phy-rockchip-typec.c
@@ -49,6 +49,7 @@
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/reset.h>
diff --git a/drivers/phy/ti/phy-tusb1210.c b/drivers/phy/ti/phy-tusb1210.c
index c3ae9d7948d7..b7080403e649 100644
--- a/drivers/phy/ti/phy-tusb1210.c
+++ b/drivers/phy/ti/phy-tusb1210.c
@@ -13,6 +13,7 @@
#include <linux/ulpi/regs.h>
#include <linux/gpio/consumer.h>
#include <linux/phy/ulpi_phy.h>
+#include <linux/pm_runtime.h>
#include <linux/power_supply.h>
#include <linux/property.h>
#include <linux/workqueue.h>
--
2.34.1
--
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^ permalink raw reply related
* [PATCH v7 phy-next 07/27] net: lan969x: include missing <linux/of.h>
From: Vladimir Oltean @ 2026-04-30 11:06 UTC (permalink / raw)
To: linux-phy
Cc: Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-scsi,
linux-sunxi, linux-tegra, linux-usb, netdev, spacemit,
UNGLinuxDriver, Daniel Machon, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Steen Hegelund
In-Reply-To: <20260430110652.558622-1-vladimir.oltean@nxp.com>
This file is calling of_property_read_u32() without including the proper
header for it. It is provided by <linux/phy/phy.h>, which wants to get
rid of it.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Daniel Machon <daniel.machon@microchip.com>
---
Cc: Daniel Machon <daniel.machon@microchip.com>
Cc: Andrew Lunn <andrew+netdev@lunn.ch>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Eric Dumazet <edumazet@google.com>
Cc: Jakub Kicinski <kuba@kernel.org>
Cc: Paolo Abeni <pabeni@redhat.com>
Cc: Steen Hegelund <Steen.Hegelund@microchip.com>
v2->v7: none
v1->v2: collect tag
---
drivers/net/ethernet/microchip/sparx5/lan969x/lan969x_rgmii.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x_rgmii.c b/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x_rgmii.c
index 4e422ca50828..249114b40c42 100644
--- a/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x_rgmii.c
+++ b/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x_rgmii.c
@@ -4,6 +4,7 @@
* Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries.
*/
+#include <linux/of.h>
#include "lan969x.h"
/* Tx clock selectors */
--
2.34.1
--
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^ permalink raw reply related
* [PATCH v7 phy-next 04/27] drm: add <linux/pm_runtime.h> where missing
From: Vladimir Oltean @ 2026-04-30 11:06 UTC (permalink / raw)
To: linux-phy
Cc: Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-scsi,
linux-sunxi, linux-tegra, linux-usb, netdev, spacemit,
UNGLinuxDriver, Andrzej Hajda, Robert Foss, Laurent Pinchart,
Jonas Karlman, Jernej Skrabec, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Inki Dae,
Jagan Teki, Marek Szyprowski, Rob Clark, Dmitry Baryshkov
In-Reply-To: <20260430110652.558622-1-vladimir.oltean@nxp.com>
Multiple DRM bridge drivers use runtime PM operations without
including the proper header, instead relying on transitive inclusion
by <linux/phy/phy.h>.
The PHY subsystem wants to get rid of headers it provides for no reason,
so modify these drivers to include what they need directly.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
Cc: Andrzej Hajda <andrzej.hajda@intel.com>
Cc: Neil Armstrong <neil.armstrong@linaro.org>
Cc: Robert Foss <rfoss@kernel.org>
Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
Cc: Jonas Karlman <jonas@kwiboo.se>
Cc: Jernej Skrabec <jernej.skrabec@gmail.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Maxime Ripard <mripard@kernel.org>
Cc: Thomas Zimmermann <tzimmermann@suse.de>
Cc: David Airlie <airlied@gmail.com>
Cc: Simona Vetter <simona@ffwll.ch>
Cc: Inki Dae <inki.dae@samsung.com>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Marek Szyprowski <m.szyprowski@samsung.com>
Cc: Rob Clark <robin.clark@oss.qualcomm.com>
Cc: Dmitry Baryshkov <lumag@kernel.org>
v1->v7: none
---
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 1 +
drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c | 1 +
drivers/gpu/drm/bridge/nwl-dsi.c | 1 +
drivers/gpu/drm/bridge/samsung-dsim.c | 1 +
drivers/gpu/drm/msm/dp/dp_aux.c | 1 +
drivers/gpu/drm/rockchip/cdn-dp-core.c | 1 +
6 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 8dee5f2fbde5..4ee08663e626 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -18,6 +18,7 @@
#include <linux/of.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
#include <drm/bridge/analogix_dp.h>
#include <drm/drm_atomic.h>
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
index 064c6915c896..d20c0f8ad04c 100644
--- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8546-core.c
@@ -32,6 +32,7 @@
#include <linux/phy/phy.h>
#include <linux/phy/phy-dp.h>
#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include <linux/wait.h>
diff --git a/drivers/gpu/drm/bridge/nwl-dsi.c b/drivers/gpu/drm/bridge/nwl-dsi.c
index 2f7429b24fc2..9ac8796ae91e 100644
--- a/drivers/gpu/drm/bridge/nwl-dsi.c
+++ b/drivers/gpu/drm/bridge/nwl-dsi.c
@@ -18,6 +18,7 @@
#include <linux/of.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/sys_soc.h>
diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
index c3eb437ef1b0..4244434747af 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -20,6 +20,7 @@
#include <linux/of.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
#include <linux/units.h>
#include <video/mipi_display.h>
diff --git a/drivers/gpu/drm/msm/dp/dp_aux.c b/drivers/gpu/drm/msm/dp/dp_aux.c
index 3825a2fb48e2..5ee22f88bd28 100644
--- a/drivers/gpu/drm/msm/dp/dp_aux.c
+++ b/drivers/gpu/drm/msm/dp/dp_aux.c
@@ -6,6 +6,7 @@
#include <linux/delay.h>
#include <linux/iopoll.h>
#include <linux/phy/phy.h>
+#include <linux/pm_runtime.h>
#include <drm/drm_print.h>
#include "dp_reg.h"
diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.c b/drivers/gpu/drm/rockchip/cdn-dp-core.c
index 177e30445ee8..68556daa54ae 100644
--- a/drivers/gpu/drm/rockchip/cdn-dp-core.c
+++ b/drivers/gpu/drm/rockchip/cdn-dp-core.c
@@ -10,6 +10,7 @@
#include <linux/firmware.h>
#include <linux/mfd/syscon.h>
#include <linux/phy/phy.h>
+#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/reset.h>
--
2.34.1
--
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^ permalink raw reply related
* [PATCH v7 phy-next 03/27] usb: add missing headers transitively included by <linux/phy/phy.h>
From: Vladimir Oltean @ 2026-04-30 11:06 UTC (permalink / raw)
To: linux-phy
Cc: Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-scsi,
linux-sunxi, linux-tegra, linux-usb, netdev, spacemit,
UNGLinuxDriver, Thinh Nguyen, Greg Kroah-Hartman, Peter Chen,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Xu Yang
In-Reply-To: <20260430110652.558622-1-vladimir.oltean@nxp.com>
The chipidea ci_hdrc_imx driver uses regulator consumer API like
regulator_enable() but does not include <linux/regulator/consumer.h>.
The core USB HCD driver calls invalidate_kernel_vmap_range() and
flush_kernel_vmap_range(), but does not include <linux/highmem.h>.
The DWC3 gadget driver calls:
- device_property_present()
- device_property_count_u8()
- device_property_read_u8_array()
but does not include <linux/property.h>
Similarly, dwc3-imx uses device_property_read_bool() without including
<linux/property.h>.
The dwc3-generic-plat driver uses of_device_get_match_data() but does
not include <linux/of.h>.
In all these cases, the necessary includes were still provided somehow,
directly or indirectly, through <linux/phy/phy.h>. I found the following
command to be quite helpful in figuring out the include chain:
$ make KCFLAGS="-H" drivers/usb/dwc3/dwc3-imx.o
Since <linux/phy/phy.h> wants to drop the unnecessary includes, fill in
the required headers to avoid any breakage.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com> # dwc3
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
Cc: Peter Chen <peter.chen@kernel.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Frank Li <Frank.Li@nxp.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
Cc: Xu Yang <xu.yang_2@nxp.com>
v6->v7:
- add drivers/usb/dwc3/dwc3-imx.c to the list of patched files
- collect tag from Greg, keeping it despite the new addition because the
change is minor and in the same spirit as the rest
(https://lore.kernel.org/linux-phy/2026033028-squint-yield-4c23@gregkh/)
v2->v6: none
v1->v2: collect tag
---
drivers/usb/chipidea/ci_hdrc_imx.c | 1 +
drivers/usb/core/hcd.c | 1 +
drivers/usb/dwc3/dwc3-generic-plat.c | 1 +
drivers/usb/dwc3/dwc3-imx.c | 1 +
drivers/usb/dwc3/gadget.c | 1 +
5 files changed, 5 insertions(+)
diff --git a/drivers/usb/chipidea/ci_hdrc_imx.c b/drivers/usb/chipidea/ci_hdrc_imx.c
index 56d2ba824a0b..0a21d7cc5f5a 100644
--- a/drivers/usb/chipidea/ci_hdrc_imx.c
+++ b/drivers/usb/chipidea/ci_hdrc_imx.c
@@ -17,6 +17,7 @@
#include <linux/clk.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pm_qos.h>
+#include <linux/regulator/consumer.h>
#include "ci.h"
#include "ci_hdrc_imx.h"
diff --git a/drivers/usb/core/hcd.c b/drivers/usb/core/hcd.c
index 89221f1ce769..b3826ebcbe98 100644
--- a/drivers/usb/core/hcd.c
+++ b/drivers/usb/core/hcd.c
@@ -10,6 +10,7 @@
*/
#include <linux/bcd.h>
+#include <linux/highmem.h>
#include <linux/module.h>
#include <linux/version.h>
#include <linux/kernel.h>
diff --git a/drivers/usb/dwc3/dwc3-generic-plat.c b/drivers/usb/dwc3/dwc3-generic-plat.c
index ca69ac0eb07c..2f2ae6f4704f 100644
--- a/drivers/usb/dwc3/dwc3-generic-plat.c
+++ b/drivers/usb/dwc3/dwc3-generic-plat.c
@@ -8,6 +8,7 @@
*/
#include <linux/clk.h>
+#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
#include <linux/regmap.h>
diff --git a/drivers/usb/dwc3/dwc3-imx.c b/drivers/usb/dwc3/dwc3-imx.c
index 973a486b544d..6e122674edaf 100644
--- a/drivers/usb/dwc3/dwc3-imx.c
+++ b/drivers/usb/dwc3/dwc3-imx.c
@@ -13,6 +13,7 @@
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
+#include <linux/property.h>
#include "core.h"
#include "glue.h"
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index 3d4ca68e584c..b5a6fd2899f1 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -10,6 +10,7 @@
#include <linux/kernel.h>
#include <linux/delay.h>
+#include <linux/property.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>
--
2.34.1
--
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^ permalink raw reply related
* [PATCH v7 phy-next 02/27] PCI: Add missing headers transitively included by <linux/phy/phy.h>
From: Vladimir Oltean @ 2026-04-30 11:06 UTC (permalink / raw)
To: linux-phy
Cc: Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-scsi,
linux-sunxi, linux-tegra, linux-usb, netdev, spacemit,
UNGLinuxDriver, Bjorn Helgaas, Lorenzo Pieralisi,
Krzysztof Wilczyński, Manivannan Sadhasivam, Rob Herring,
Heiko Stuebner, Shawn Guo, Yixun Lan, Thierry Reding,
Jonathan Hunter, Shawn Lin, Kevin Xie
In-Reply-To: <20260430110652.558622-1-vladimir.oltean@nxp.com>
The tegra as well as a few dwc PCI controller drivers uses PM runtime
operations without including the required <linux/pm_runtime.h> header.
Similarly, pcie-rockchip-host, pcie-starfive as well as a few dwc PCI
controllers use the regulator consumer API without including
<linux/regulator/consumer.h>.
pcie-spacemit-k1.c uses of_get_next_available_child() and of_node_put()
without including <linux/of.h>.
It seems these function prototypes were indirectly provided by
<linux/phy/phy.h>, mostly by mistake (none of the functions it exports
need it).
Before the PHY header can drop the unnecessary includes, make sure the
PCI controller drivers include what they use.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
---
Cc: Lorenzo Pieralisi <lpieralisi@kernel.org>
Cc: "Krzysztof Wilczyński" <kwilczynski@kernel.org>
Cc: Manivannan Sadhasivam <mani@kernel.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Yixun Lan <dlan@kernel.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Jonathan Hunter <jonathanh@nvidia.com>
Cc: Shawn Lin <shawn.lin@rock-chips.com>
Cc: Kevin Xie <kevin.xie@starfivetech.com>
v5->v7: none
v4->v5: fix pcie-spacemit-k1 driver, previously missed due to limited
build coverage
v2->v4: none
v1->v2: collect tag, adjust commit title
---
drivers/pci/controller/dwc/pci-keystone.c | 1 +
drivers/pci/controller/dwc/pcie-dw-rockchip.c | 1 +
drivers/pci/controller/dwc/pcie-histb.c | 1 +
drivers/pci/controller/dwc/pcie-qcom-ep.c | 1 +
drivers/pci/controller/dwc/pcie-spacemit-k1.c | 3 +++
drivers/pci/controller/dwc/pcie-tegra194.c | 1 +
drivers/pci/controller/pci-tegra.c | 1 +
drivers/pci/controller/pcie-rockchip-host.c | 1 +
drivers/pci/controller/plda/pcie-starfive.c | 1 +
9 files changed, 11 insertions(+)
diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c
index 278d2dba1db0..fe4836925c4e 100644
--- a/drivers/pci/controller/dwc/pci-keystone.c
+++ b/drivers/pci/controller/dwc/pci-keystone.c
@@ -24,6 +24,7 @@
#include <linux/of_pci.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/resource.h>
#include <linux/signal.h>
diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
index 731d93663cca..ae27ce05247c 100644
--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
@@ -21,6 +21,7 @@
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
#include <linux/reset.h>
#include <linux/workqueue.h>
#include <trace/events/pci_controller.h>
diff --git a/drivers/pci/controller/dwc/pcie-histb.c b/drivers/pci/controller/dwc/pcie-histb.c
index a52071589377..432a54c5bfce 100644
--- a/drivers/pci/controller/dwc/pcie-histb.c
+++ b/drivers/pci/controller/dwc/pcie-histb.c
@@ -18,6 +18,7 @@
#include <linux/pci.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
#include <linux/resource.h>
#include <linux/reset.h>
diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
index 257c2bcb5f76..35a297923e7f 100644
--- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
+++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
@@ -19,6 +19,7 @@
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
+#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/module.h>
diff --git a/drivers/pci/controller/dwc/pcie-spacemit-k1.c b/drivers/pci/controller/dwc/pcie-spacemit-k1.c
index be20a520255b..41316aa54106 100644
--- a/drivers/pci/controller/dwc/pcie-spacemit-k1.c
+++ b/drivers/pci/controller/dwc/pcie-spacemit-k1.c
@@ -13,9 +13,12 @@
#include <linux/gfp.h>
#include <linux/mfd/syscon.h>
#include <linux/mod_devicetable.h>
+#include <linux/of.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
#include <linux/reset.h>
#include <linux/types.h>
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 9dcfa194050e..f1d08814a73c 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -27,6 +27,7 @@
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/random.h>
+#include <linux/regulator/consumer.h>
#include <linux/reset.h>
#include <linux/resource.h>
#include <linux/types.h>
diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c
index 512309763d1f..a2c1662b6e81 100644
--- a/drivers/pci/controller/pci-tegra.c
+++ b/drivers/pci/controller/pci-tegra.c
@@ -36,6 +36,7 @@
#include <linux/phy/phy.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
#include <linux/reset.h>
#include <linux/sizes.h>
#include <linux/slab.h>
diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/controller/pcie-rockchip-host.c
index ee1822ca01db..46adb4582fcc 100644
--- a/drivers/pci/controller/pcie-rockchip-host.c
+++ b/drivers/pci/controller/pcie-rockchip-host.c
@@ -24,6 +24,7 @@
#include <linux/of_pci.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
#include "../pci.h"
#include "pcie-rockchip.h"
diff --git a/drivers/pci/controller/plda/pcie-starfive.c b/drivers/pci/controller/plda/pcie-starfive.c
index 298036c3e7f9..22344cca167b 100644
--- a/drivers/pci/controller/plda/pcie-starfive.c
+++ b/drivers/pci/controller/plda/pcie-starfive.c
@@ -21,6 +21,7 @@
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
#include <linux/reset.h>
#include "../../pci.h"
--
2.34.1
--
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^ permalink raw reply related
* [PATCH v7 phy-next 01/27] ata: add <linux/pm_runtime.h> where missing
From: Vladimir Oltean @ 2026-04-30 11:06 UTC (permalink / raw)
To: linux-phy
Cc: Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-scsi,
linux-sunxi, linux-tegra, linux-usb, netdev, spacemit,
UNGLinuxDriver, Damien Le Moal, Niklas Cassel
In-Reply-To: <20260430110652.558622-1-vladimir.oltean@nxp.com>
It appears that libahci.c, ahci.c as well as the ahci_brcm, ahci_ceva
and ahci_qoriq drivers are using runtime PM operations without including
<linux/pm_runtime.h>. This header is somehow being indirectly provided
by <linux/phy/phy.h>, which would like to drop it (none of the functions
it exports need it).
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Acked-by: Damien Le Moal <dlemoal@kernel.org>
---
Cc: Damien Le Moal <dlemoal@kernel.org>
Cc: Niklas Cassel <cassel@kernel.org>
v2->v7: none
v1->v2: collect tag
---
drivers/ata/ahci.c | 1 +
drivers/ata/ahci_brcm.c | 1 +
drivers/ata/ahci_ceva.c | 1 +
drivers/ata/ahci_qoriq.c | 1 +
drivers/ata/libahci.c | 1 +
5 files changed, 5 insertions(+)
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 1d73a53370cf..1396a53bd6df 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -26,6 +26,7 @@
#include <linux/device.h>
#include <linux/dmi.h>
#include <linux/gfp.h>
+#include <linux/pm_runtime.h>
#include <scsi/scsi_host.h>
#include <scsi/scsi_cmnd.h>
#include <linux/libata.h>
diff --git a/drivers/ata/ahci_brcm.c b/drivers/ata/ahci_brcm.c
index 29be74fedcf0..48460e515722 100644
--- a/drivers/ata/ahci_brcm.c
+++ b/drivers/ata/ahci_brcm.c
@@ -16,6 +16,7 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
#include <linux/reset.h>
#include <linux/string.h>
diff --git a/drivers/ata/ahci_ceva.c b/drivers/ata/ahci_ceva.c
index 2d6a08c23d6a..3938bf378341 100644
--- a/drivers/ata/ahci_ceva.c
+++ b/drivers/ata/ahci_ceva.c
@@ -12,6 +12,7 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
#include <linux/reset.h>
#include "ahci.h"
diff --git a/drivers/ata/ahci_qoriq.c b/drivers/ata/ahci_qoriq.c
index 0dec1a17e5b1..409152bfefb6 100644
--- a/drivers/ata/ahci_qoriq.c
+++ b/drivers/ata/ahci_qoriq.c
@@ -14,6 +14,7 @@
#include <linux/device.h>
#include <linux/of.h>
#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
#include <linux/libata.h>
#include "ahci.h"
diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c
index c79abdfcd7a9..e0de4703a4f2 100644
--- a/drivers/ata/libahci.c
+++ b/drivers/ata/libahci.c
@@ -30,6 +30,7 @@
#include <scsi/scsi_cmnd.h>
#include <linux/libata.h>
#include <linux/pci.h>
+#include <linux/pm_runtime.h>
#include "ahci.h"
#include "libata.h"
--
2.34.1
--
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^ permalink raw reply related
* [RFC PATCH] phy: ti: tusb1210: Move long delayed work on system_dfl_long_wq
From: Marco Crivellari @ 2026-04-30 10:34 UTC (permalink / raw)
To: linux-kernel, linux-phy
Cc: Tejun Heo, Lai Jiangshan, Frederic Weisbecker,
Sebastian Andrzej Siewior, Marco Crivellari, Michal Hocko,
Vinod Koul, Neil Armstrong
Currently the code enqueue work items using {queue|mod}_delayed_work(),
using system_long_wq. This workqueue should be used when long works are
expected, but it is a per-cpu workqueue.
This is important because queue_delayed_work() queue the work using:
queue_delayed_work_on(WORK_CPU_UNBOUND, ...);
Note that WORK_CPU_UNBOUND = NR_CPUS.
This would end up calling __queue_delayed_work() that does:
if (housekeeping_enabled(HK_TYPE_TIMER)) {
// [....]
} else {
if (likely(cpu == WORK_CPU_UNBOUND))
add_timer_global(timer);
else
add_timer_on(timer, cpu);
}
So when cpu == WORK_CPU_UNBOUND the timer is global and is
not using a specific CPU. Later, when __queue_work() is called:
if (req_cpu == WORK_CPU_UNBOUND) {
if (wq->flags & WQ_UNBOUND)
cpu = wq_select_unbound_cpu(raw_smp_processor_id());
else
cpu = raw_smp_processor_id();
}
Because the wq is not unbound, it takes the CPU where the timer
fired and enqueue the work on that CPU.
The consequence of all of this is that the work can run anywhere,
depending on where the timer fired.
Recently, a new unbound workqueue specific for long running work has
been added:
c116737e972e ("workqueue: Add system_dfl_long_wq for long unbound works")
So change system_long_wq with system_dfl_long_wq so that the work may
benefit from scheduler task placement.
Signed-off-by: Marco Crivellari <marco.crivellari@suse.com>
---
drivers/phy/ti/phy-tusb1210.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/ti/phy-tusb1210.c b/drivers/phy/ti/phy-tusb1210.c
index c3ae9d7948d7..9956921c094b 100644
--- a/drivers/phy/ti/phy-tusb1210.c
+++ b/drivers/phy/ti/phy-tusb1210.c
@@ -197,7 +197,7 @@ static void tusb1210_chg_det_set_state(struct tusb1210 *tusb,
tusb1210_chg_det_states[new_state], delay_ms);
tusb->chg_det_state = new_state;
- mod_delayed_work(system_long_wq, &tusb->chg_det_work,
+ mod_delayed_work(system_dfl_long_wq, &tusb->chg_det_work,
msecs_to_jiffies(delay_ms));
}
@@ -380,7 +380,7 @@ static int tusb1210_psy_notifier(struct notifier_block *nb,
struct power_supply *psy = ptr;
if (psy != tusb->psy && psy->desc->type == POWER_SUPPLY_TYPE_USB)
- queue_delayed_work(system_long_wq, &tusb->chg_det_work, 0);
+ queue_delayed_work(system_dfl_long_wq, &tusb->chg_det_work, 0);
return NOTIFY_OK;
}
@@ -458,7 +458,7 @@ static void tusb1210_probe_charger_detect(struct tusb1210 *tusb)
*/
tusb->chg_det_state = TUSB1210_CHG_DET_DISCONNECTED;
INIT_DELAYED_WORK(&tusb->chg_det_work, tusb1210_chg_det_work);
- queue_delayed_work(system_long_wq, &tusb->chg_det_work, 2 * HZ);
+ queue_delayed_work(system_dfl_long_wq, &tusb->chg_det_work, 2 * HZ);
tusb->psy_nb.notifier_call = tusb1210_psy_notifier;
power_supply_reg_notifier(&tusb->psy_nb);
--
2.53.0
--
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^ permalink raw reply related
* Re: [PATCH 2/2] phy: spacemit: Add USB3/PCIe comb PHY driver for Spacemit K3
From: Ze Huang @ 2026-04-30 7:39 UTC (permalink / raw)
To: Inochi Amaoto, Vinod Koul, Neil Armstrong, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Yixun Lan, Kees Cook,
Gustavo A. R. Silva, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alexandre Ghiti, Ze Huang, Alex Elder
Cc: linux-phy, devicetree, linux-riscv, spacemit, linux-kernel,
linux-hardening, Yixun Lan, Longbin Li
In-Reply-To: <20260430022843.1090138-3-inochiama@gmail.com>
On Thu Apr 30, 2026 at 10:28 AM CST, Inochi Amaoto wrote:
> The comb PHY on K3 requires to configure a syscon device for the
> right mux configuration. And it requires calibration before any
> usage.
>
> Add USB3/PCIe comb PHY driver for Spacemit K3.
>
> Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
> ---
> drivers/phy/spacemit/Kconfig | 16 ++
> drivers/phy/spacemit/Makefile | 2 +
> drivers/phy/spacemit/phy-k3-combphy.c | 250 ++++++++++++++++
> drivers/phy/spacemit/phy-k3-common.c | 398 ++++++++++++++++++++++++++
> drivers/phy/spacemit/phy-k3-common.h | 27 ++
> 5 files changed, 693 insertions(+)
> create mode 100644 drivers/phy/spacemit/phy-k3-combphy.c
> create mode 100644 drivers/phy/spacemit/phy-k3-common.c
> create mode 100644 drivers/phy/spacemit/phy-k3-common.h
>
> diff --git a/drivers/phy/spacemit/Kconfig b/drivers/phy/spacemit/Kconfig
> index 50b0005acf66..5fdf18fce499 100644
> --- a/drivers/phy/spacemit/Kconfig
> +++ b/drivers/phy/spacemit/Kconfig
> @@ -23,3 +23,19 @@ config PHY_SPACEMIT_K1_USB2
> help
> Enable this to support K1 USB 2.0 PHY driver. This driver takes care of
> enabling and clock setup and will be used by K1 udc/ehci/otg/xhci driver.
> +
> +config PHY_SPACEMIT_K3_COMMON_OPS
> + tristate
> + select MFD_SYSCON
> + select GENERIC_PHY
> +
> +config PHY_SPACEMIT_K3_COMBO_PHY
> + tristate "SpacemiT K3 USB3/PCIe PHY support"
> + depends on (ARCH_SPACEMIT || COMPILE_TEST) && OF
> + depends on COMMON_CLK
> + select PHY_SPACEMIT_K3_COMMON_OPS
> + help
> + Enable this to support K3 USB3/PCIe combo PHY driver. This
> + driver takes care of enabling and clock setup and will be used
> + by K3 dwc3 driver.
> + If unsure, say N.
> diff --git a/drivers/phy/spacemit/Makefile b/drivers/phy/spacemit/Makefile
> index a821a21d6142..41be7b0388da 100644
> --- a/drivers/phy/spacemit/Makefile
> +++ b/drivers/phy/spacemit/Makefile
> @@ -1,3 +1,5 @@
> # SPDX-License-Identifier: GPL-2.0-only
> obj-$(CONFIG_PHY_SPACEMIT_K1_PCIE) += phy-k1-pcie.o
> obj-$(CONFIG_PHY_SPACEMIT_K1_USB2) += phy-k1-usb2.o
> +obj-$(CONFIG_PHY_SPACEMIT_K3_COMBO_PHY) += phy-k3-combphy.o
> +obj-$(CONFIG_PHY_SPACEMIT_K3_COMMON_OPS) += phy-k3-common.o
> diff --git a/drivers/phy/spacemit/phy-k3-combphy.c b/drivers/phy/spacemit/phy-k3-combphy.c
> new file mode 100644
> index 000000000000..66fa6330ad6e
> --- /dev/null
> +++ b/drivers/phy/spacemit/phy-k3-combphy.c
> @@ -0,0 +1,250 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * phy-k3-usb3.c - SpacemiT K3 Type-C Orientation Switch Driver
> + *
> + * Copyright (c) 2025 SpacemiT Technology Co. Ltd
> + */
> +
> +#include <linux/bitfield.h>
> +#include <linux/io.h>
...
> +
> + phy->apb_spare = syscon_regmap_lookup_by_phandle(node, "spacemit,apb-spare");
> + if (IS_ERR(phy->apb_spare))
> + return dev_err_probe(dev, PTR_ERR(phy->apb_spare),
> + "Failed to fine APB SPARE syscon");
typo, s/fine/find
> +
> + apmu = syscon_regmap_lookup_by_phandle_args(node, "spacemit,apmu", 1, &config);
> + if (IS_ERR(apmu))
> + return dev_err_probe(dev, PTR_ERR(phy->apb_spare),
> + "Failed to fine APMU syscon");
1. typo, s/fine/find
2. PTR_ERR(phy->apb_spare) should be PTR_ERR(apmu)
> +
> + ret = k3_comb_phy_update_config(apmu, config);
> + if (ret < 0)
> + return dev_err_probe(dev, ret, "Failed to set lane configuration");
> +
> + phy->dev = dev;
> + platform_set_drvdata(pdev, phy);
> +
> + ret = k3_phy_calibrate(phy->apb_spare);
> + if (ret < 0)
> + return dev_err_probe(dev, ret, "Failed to calibrate phy");
> +
> + ret = k3_comb_phy_init_lanes(phy, config);
> + if (ret < 0)
> + return dev_err_probe(dev, ret, "Failed to init lanes");
> +
> + provider = devm_of_phy_provider_register(dev, k3_comb_phy_xlate);
> + if (IS_ERR(provider))
> + return dev_err_probe(dev, PTR_ERR(provider),
> + "Failed to register provider\n");
> +
> + return 0;
> +}
> +
> +static const struct of_device_id k3_comb_phy_of_match[] = {
> + { .compatible = "spacemit,k3-comb-phy" },
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, k3_comb_phy_of_match);
> +
> +static struct platform_driver k3_comb_phy_driver = {
> + .probe = k3_comb_phy_probe,
> + .driver = {
> + .name = "spacemit,k3-comb-phy",
> + .of_match_table = k3_comb_phy_of_match,
> + },
> +};
> +module_platform_driver(k3_comb_phy_driver);
> +
> +MODULE_DESCRIPTION("SpacemiT K3 USB3/PCIe comb PHY driver");
> +MODULE_LICENSE("GPL");
> diff --git a/drivers/phy/spacemit/phy-k3-common.c b/drivers/phy/spacemit/phy-k3-common.c
> new file mode 100644
> index 000000000000..77c4b4073b96
> --- /dev/null
> +++ b/drivers/phy/spacemit/phy-k3-common.c
> @@ -0,0 +1,398 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +
> +#include <linux/bitfield.h>
> +#include <linux/cleanup.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <linux/module.h>
> +#include <linux/regmap.h>
> +#include <linux/usb.h>
> +
> +#include <dt-bindings/phy/phy.h>
> +
> +#include "phy-k3-common.h"
> +
> +/* PHY Registers */
> +#define PHY_VERSION 0x0
> +
> +#define PHY_RESET_CFG 0x04
> +
> +#define PHY_RESET_RXBUF_RST BIT(0)
> +#define PHY_RESET_SOFT_RST_PCS BIT(1)
> +#define PHY_RESET_SOFT_RST_AHB BIT(2)
> +#define PHY_RESET_EN_SD_AFTER_LOCK BIT(6)
> +
> +#define PHY_CLK_CFG 0x08
> +
> +#define PHY_CLK_PLL_READY BIT(0)
> +#define PHY_CLK_TXCLK_INV BIT(2)
> +#define PHY_CLK_RXCLK_EN BIT(3)
> +#define PHY_CLK_TXCLK_EN BIT(4)
> +#define PHY_CLK_PCLK_EN BIT(5)
> +#define PHY_CLK_PIPE_PCLK_EN BIT(6)
> +#define PHY_CLK_REFCLK_FREQ GENMASK(10, 7)
> +#define PHY_CLK_REFCLK_24M 2
> +#define PHY_CLK_SW_INIT_DONE BIT(11)
> +#define PHY_CLK_PU_SSC_OUT BIT(23)
> +
> +#define PHY_MODE_CFG 0x0C
> +
> +#define PHY_MODE_PCIE_INT_EN BIT(0)
> +#define PHY_MODE_LFPS_TPERIOD GENMASK(9, 8)
> +#define PHY_MODE_LFPS_TPERIOD_USB 3
> +
> +#define PHY_PU_SEL 0x40
> +
> +#define PHY_PU_CFG_STATUS BIT(9)
> +#define PHY_PU_OVRD_STATUS BIT(10)
> +
> +#define PHY_PU_CK_REG 0x54
> +
> +#define PHY_PU_REFCLK_100 BIT(25)
> +
> +#define PHY_PLL_REG1 0x58
> +
> +#define PHY_PLL_FREF_SEL GENMASK(15, 13)
> +#define PHY_PLL_FREF_24M 0x1
> +#define PHY_PLL_SSC_DEP_SEL GENMASK(27, 24)
> +#define PHY_PLL_SSC_5000PPM 0xa
> +#define PHY_PLL_SSC_MODE GENMASK(29, 28)
> +#define PHY_PLL_SSC_MODE_CENTER_SPREAD 0
> +#define PHY_PLL_SSC_MODE_UP_SPREAD 1
> +#define PHY_PLL_SSC_MODE_DOWN_SPREAD 2
> +#define PHY_PLL_SSC_MODE_DOWN_SPREAD1 3
> +
> +#define PHY_PLL_REG2 0x5c
> +
> +#define PHY_PLL_SEL_REF100 BIT(21)
> +
> +/* PHY RX Register Definitions */
> +#define PHY_RX_REG_A 0x60
> +
> +#define PHY_RX_REG0_RLOAD BIT(4)
> +#define PHY_RX_REG1_RTERM GENMASK(11, 8)
> +#define PHY_RX_REG1_RC_CALI GENMASK(15, 12)
> +#define PHY_RX_REG2_CSEL GENMASK(19, 16)
> +#define PHY_RX_REG2_FORCE_CSEL BIT(20)
> +#define PHY_RX_REG2_PSEL GENMASK(23, 21)
> +#define PHY_RX_REG3_I_LOAD GENMASK(26, 24)
> +#define PHY_RX_REG3_SEL_CBOOST_CODE BIT(27)
> +#define PHY_RX_REG3_ADJ_BIAS GENMASK(29, 28)
> +#define PHY_RX_REG3_RDEG1 GENMASK(31, 30)
> +
> +#define PHY_RX_REG_B 0x64
> +
> +#define PHY_RX_REGB_MASK GENMASK(23, 0)
> +
> +#define PHY_RX_REG4_RDEG2 GENMASK(2, 1)
> +#define PHY_RX_REG4_ENVOS BIT(4)
> +#define PHY_RX_REG4_RTERM_SEL BIT(5)
> +#define PHY_RX_REG4_MANUAL_CFG BIT(7)
> +#define PHY_RX_REG5_RCELL_VCM GENMASK(11, 8)
> +#define PHY_RX_REG5_RCELL_BIAS GENMASK(15, 12)
> +#define PHY_RX_REG6_H1_REG GENMASK(19, 16)
> +#define PHY_RX_REG6_ADAPT_GAIN GENMASK(21, 20)
> +#define PHY_RX_REG6_BYPASS_ADPT BIT(22)
> +
> +#define PHY_ADPT_CFG0 0x140
> +#define PHY_ADPT_AFE_RST_OVRD_EN BIT(1)
> +#define PHY_ADPT_AFE_RST_OVRD_VAL BIT(4)
> +
> +#define PHY_RXEQ_TIME 0xb4
> +#define PHY_RXEQ_TIME_OVRD_POST_C_SOC BIT(21)
> +#define PHY_RXEQ_TIME_CFG_AMP_SOC GENMASK(23, 22)
> +#define PHY_RXEQ_TIME_AMP_SOC_650M 0
> +#define PHY_RXEQ_TIME_AMP_SOC_800M 1
> +#define PHY_RXEQ_TIME_AMP_SOC_870M 2
> +#define PHY_RXEQ_TIME_AMP_SOC_900M 3
> +#define PHY_RXEQ_TIME_OVRD_AMP_SOC BIT(24)
> +
> +#define PCIE_PU_ADDR_CLK_CFG 0x0008
> +#define PHY_CLK_PLL_READY BIT(0)
> +#define PCIE_INITAL_TIMER GENMASK(6, 3)
> +#define CFG_INTERNAL_TIMER_ADJ GENMASK(10, 7)
> +#define CFG_SW_PHY_INIT_DONE BIT(11)
> +
> +/* Lane RX/TX configuration (per‑lane, at lane_base) */
> +#define PCIE_RX_REG1 0x050
> +#define PCIE_TX_REG1 0x064
> +
> +#define PCIE_PLL_TIMEOUT 500000
> +#define PCIE_POLL_DELAY 500
> +
> +
...
> +static int k3_pcie_phy_init(struct phy *phy)
> +{
> + struct k3_lane_group *lg = phy_get_drvdata(phy);
> + void __iomem *phy_base = lg->base + lg->data->offsets[0];
> + u32 val;
> + int ret;
> + int i;
> +
> + val = readl(phy_base + PHY_PLL_REG1);
> + val = u32_replace_bits(val, 0x2, GENMASK(15, 12));
> + writel(val, phy_base + PHY_PLL_REG1);
> +
> + val = readl(phy_base + PHY_PLL_REG2);
> + val = u32_replace_bits(val, 0, BIT(21));
> + writel(val, phy_base + PHY_PLL_REG2);
> +
> + for (i = 0; i < lg->data->lanes; i++) {
> + void __iomem *lane_base = lg->base + lg->data->offsets[i];
> +
> + val = readl(lane_base + PCIE_RX_REG1);
> + val = u32_replace_bits(val, 0, 0x3);
> + writel(val, phy_base + PCIE_RX_REG1);
This looks like a copy-paste bug.
Read from lane_base but write the modified value to phy_base.
> + }
> +
> + val = readl(phy_base + PHY_PLL_REG2);
> + val |= BIT(20);
> + writel(val, phy_base + PHY_PLL_REG2);
> +
> + writel(0x00006505, phy_base + PCIE_RX_REG1);
Is it intentional? The loop above configured PCIE_RX_REG1, while the
hard-coded 0x00006505 overwrites what's done for lane0.
> +
> + /* pll_reg1 of lane0, disable SSC: pll_reg4[3:0] = 0 */
> + val = readl(phy_base + PHY_PLL_REG1);
> + val = u32_replace_bits(val, 0, GENMASK(27, 24));
> + writel(val, phy_base + PHY_PLL_REG1);
A little confusing here, comment says "pll_reg4[3:0] = 0" but the code is
modifying PHY_PLL_REG1[27:24]
> +
> + for (i = 0; i < lg->data->lanes; i++) {
> + void __iomem *lane_base = lg->base + lg->data->offsets[i];
> +
> + /* set cfg_tx_send_dummy_data to be 1'b1 for disable dash data */
> + val = readl(lane_base + PHY_PU_SEL);
> + val = u32_replace_bits(val, 1, BIT(13));
> + writel(val, lane_base + PHY_PU_SEL);
> +
> + /* disable en_sample_data_after_cdr_locked */
> + val = readl(lane_base + PHY_RESET_CFG);
> + val = u32_replace_bits(val, 0, BIT(6));
> + writel(val, lane_base + PHY_RESET_CFG);
> +
> + /* Dynamic Lock */
> + val = readl(lane_base + PHY_MODE_CFG);
> + val = u32_replace_bits(val, 1, BIT(2));
> + writel(val, lane_base + PHY_MODE_CFG);
> +
> + val = FIELD_PREP(GENMASK(7, 0), 0x10) |
> + FIELD_PREP(GENMASK(15, 8), 0x78) |
> + FIELD_PREP(GENMASK(23, 16), 0x98) |
> + FIELD_PREP(GENMASK(31, 24), 0xdf);
> + writel(val, lane_base + PHY_RX_REG_A);
> +
> + val = readl(lane_base + PHY_RX_REG_B);
> + val &= ~PHY_RX_REGB_MASK;
> + val |= FIELD_PREP(GENMASK(7, 0), 0xb4) |
> + FIELD_PREP(GENMASK(15, 8), 0x88) |
> + FIELD_PREP(GENMASK(23, 16), 0x28);
> + writel(val, lane_base + PHY_RX_REG_B);
Can we define macros for these values? Just like you did for
PHY_CLK_CFG.
> +
> + /* Set init done */
> + val = readl(lane_base + PCIE_PU_ADDR_CLK_CFG);
> + val = u32_replace_bits(val, 1, CFG_SW_PHY_INIT_DONE);
> + writel(val, lane_base + PCIE_PU_ADDR_CLK_CFG);
> + }
> +
> + ret = readl_poll_timeout(phy_base + PCIE_PU_ADDR_CLK_CFG, val,
> + (val & PHY_CLK_PLL_READY), PCIE_POLL_DELAY,
> + PCIE_PLL_TIMEOUT);
> + if (ret) {
> + dev_err(&lg->phy->dev, "PHY PLL lock timeout\n");
> + return ret;
> + }
> +
> + return 0;
> +}
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
^ permalink raw reply
* [PATCH 2/2] phy: spacemit: Add USB3/PCIe comb PHY driver for Spacemit K3
From: Inochi Amaoto @ 2026-04-30 2:28 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Yixun Lan, Kees Cook, Gustavo A. R. Silva,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
Inochi Amaoto, Ze Huang, Alex Elder
Cc: linux-phy, devicetree, linux-riscv, spacemit, linux-kernel,
linux-hardening, Yixun Lan, Longbin Li
In-Reply-To: <20260430022843.1090138-1-inochiama@gmail.com>
The comb PHY on K3 requires to configure a syscon device for the
right mux configuration. And it requires calibration before any
usage.
Add USB3/PCIe comb PHY driver for Spacemit K3.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
drivers/phy/spacemit/Kconfig | 16 ++
drivers/phy/spacemit/Makefile | 2 +
drivers/phy/spacemit/phy-k3-combphy.c | 250 ++++++++++++++++
drivers/phy/spacemit/phy-k3-common.c | 398 ++++++++++++++++++++++++++
drivers/phy/spacemit/phy-k3-common.h | 27 ++
5 files changed, 693 insertions(+)
create mode 100644 drivers/phy/spacemit/phy-k3-combphy.c
create mode 100644 drivers/phy/spacemit/phy-k3-common.c
create mode 100644 drivers/phy/spacemit/phy-k3-common.h
diff --git a/drivers/phy/spacemit/Kconfig b/drivers/phy/spacemit/Kconfig
index 50b0005acf66..5fdf18fce499 100644
--- a/drivers/phy/spacemit/Kconfig
+++ b/drivers/phy/spacemit/Kconfig
@@ -23,3 +23,19 @@ config PHY_SPACEMIT_K1_USB2
help
Enable this to support K1 USB 2.0 PHY driver. This driver takes care of
enabling and clock setup and will be used by K1 udc/ehci/otg/xhci driver.
+
+config PHY_SPACEMIT_K3_COMMON_OPS
+ tristate
+ select MFD_SYSCON
+ select GENERIC_PHY
+
+config PHY_SPACEMIT_K3_COMBO_PHY
+ tristate "SpacemiT K3 USB3/PCIe PHY support"
+ depends on (ARCH_SPACEMIT || COMPILE_TEST) && OF
+ depends on COMMON_CLK
+ select PHY_SPACEMIT_K3_COMMON_OPS
+ help
+ Enable this to support K3 USB3/PCIe combo PHY driver. This
+ driver takes care of enabling and clock setup and will be used
+ by K3 dwc3 driver.
+ If unsure, say N.
diff --git a/drivers/phy/spacemit/Makefile b/drivers/phy/spacemit/Makefile
index a821a21d6142..41be7b0388da 100644
--- a/drivers/phy/spacemit/Makefile
+++ b/drivers/phy/spacemit/Makefile
@@ -1,3 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_PHY_SPACEMIT_K1_PCIE) += phy-k1-pcie.o
obj-$(CONFIG_PHY_SPACEMIT_K1_USB2) += phy-k1-usb2.o
+obj-$(CONFIG_PHY_SPACEMIT_K3_COMBO_PHY) += phy-k3-combphy.o
+obj-$(CONFIG_PHY_SPACEMIT_K3_COMMON_OPS) += phy-k3-common.o
diff --git a/drivers/phy/spacemit/phy-k3-combphy.c b/drivers/phy/spacemit/phy-k3-combphy.c
new file mode 100644
index 000000000000..66fa6330ad6e
--- /dev/null
+++ b/drivers/phy/spacemit/phy-k3-combphy.c
@@ -0,0 +1,250 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * phy-k3-usb3.c - SpacemiT K3 Type-C Orientation Switch Driver
+ *
+ * Copyright (c) 2025 SpacemiT Technology Co. Ltd
+ */
+
+#include <linux/bitfield.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/mfd/syscon.h>
+#include <linux/iopoll.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/phy/phy.h>
+
+#include <dt-bindings/phy/phy.h>
+
+#include "phy-k3-common.h"
+
+/*
+ * The PCIE/USB Subsystem on SpacemiT K3 have 3 single lane PIPE3 PHYs
+ * (PHY2/3/4) shared by PCIE PortC/D and USB3 PortB/C/D.
+ *
+ * PMUA_PCIE_SUBSYS_MGMT[4:0]
+ *
+ * bit4 = 0 : PCIe A X8 mode, all 8 lanes dedicated to PCIe Port A
+ * 1 : PHY lanes shared between PCIe or USB according to [3:0]
+ *
+ * All PHY matrix combinations according to [4:0]:
+ *
+ * 0x0X : PCIe-A X8
+ * 0x10 : PCIe-C x2 (PHY2+PHY3) + PCIe-D x1 (PHY4)
+ * 0x11 : PCIe-C x2 (PHY2+PHY3) + USB-D (PHY4)
+ * 0x12 : PCIe-C x1 (PHY2) + USB-C (PHY3)
+ * 0x13 : PCIe-C x1 (PHY2) + USB-C (PHY3) + USB-D (PHY4)
+ * 0x14 : PCIe-C x1 (PHY3) + USB-B (PHY2)
+ * 0x15 : PCIe-C x1 (PHY3) + USB-B (PHY2) + USB-D (PHY4)
+ * 0x16 : USB-B (PHY2) + USB-C (PHY3) + PCIe D x1 (PHY4)
+ * 0x17 : USB-B (PHY2) + USB-C (PHY3) + USB-D (PHY4)
+ *
+ * So any USB Port B/C/D operation requires PCIe A X8 mode to be disabled.
+ */
+#define PMUA_PCIE_SUBSYS_MGMT 0x1d8
+#define PU_MATRIX_CONF_MASK GENMASK(4, 0)
+
+#define COMBPHY_MAX_SUBPHYS 6
+
+struct k3_comb_phy {
+ struct device *dev;
+ struct k3_lane_group groups[COMBPHY_MAX_SUBPHYS];
+ void __iomem *base;
+ struct regmap *apb_spare;
+};
+
+static const struct k3_phy_lane_group_data k3_combphy_lane_group0 = {
+ .lanes = 2,
+ .config = 0x00,
+ .mask = 0xff,
+ .offsets = {
+ 0x0, 0x400
+ },
+};
+
+static const struct k3_phy_lane_group_data k3_combphy_lane_group1 = {
+ .lanes = 2,
+ .config = 0x00,
+ .mask = 0xff,
+ .offsets = {
+ 0x100000, 0x100400
+ },
+};
+
+static const struct k3_phy_lane_group_data k3_combphy_lane_group2 = {
+ .lanes = 1,
+ .config = 0x14,
+ .mask = 0x14,
+ .offsets = {
+ 0x200000
+ },
+};
+
+static const struct k3_phy_lane_group_data k3_combphy_lane_group3 = {
+ .lanes = 1,
+ .config = 0x12,
+ .mask = 0x12,
+ .offsets = {
+ 0x300000
+ },
+};
+
+static const struct k3_phy_lane_group_data k3_combphy_lane_group4 = {
+ .lanes = 1,
+ .config = 0x11,
+ .mask = 0x11,
+ .offsets = {
+ 0x400000
+ },
+};
+
+static const struct k3_phy_lane_group_data k3_combphy_lane_group5 = {
+ .lanes = 1,
+ .config = 0x00,
+ .mask = 0xff,
+ .offsets = {
+ 0x500000
+ },
+};
+
+static const struct k3_phy_lane_group_data *k3_combphy_lane_datas[] = {
+ &k3_combphy_lane_group0,
+ &k3_combphy_lane_group1,
+ &k3_combphy_lane_group2,
+ &k3_combphy_lane_group3,
+ &k3_combphy_lane_group4,
+ &k3_combphy_lane_group5,
+};
+
+static int k3_comb_phy_init_lanes(struct k3_comb_phy *phy, unsigned int config)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(k3_combphy_lane_datas); i++) {
+ const struct k3_phy_lane_group_data *data = k3_combphy_lane_datas[i];
+ struct k3_lane_group *lg = &phy->groups[i];
+ const struct phy_ops *ops;
+ bool is_usb;
+
+ is_usb = (data->mask & config) == data->config;
+ if (is_usb)
+ ops = &k3_usb3_phy_ops;
+ else
+ ops = &k3_pcie_phy_ops;
+
+ lg->phy = devm_phy_create(phy->dev, NULL, ops);
+ if (IS_ERR(lg->phy))
+ return PTR_ERR(lg->phy);
+
+ lg->is_pcie = !is_usb;
+ lg->data = data;
+ lg->base = phy->base;
+ phy_set_drvdata(lg->phy, lg);
+ }
+
+ return 0;
+}
+
+static int k3_comb_phy_update_config(struct regmap *apmu, unsigned int config)
+{
+ if (config & ~PU_MATRIX_CONF_MASK)
+ return -EINVAL;
+
+ return regmap_update_bits(apmu, PMUA_PCIE_SUBSYS_MGMT, PU_MATRIX_CONF_MASK, config);
+}
+
+static struct phy *k3_comb_phy_xlate(struct device *dev, const struct of_phandle_args *args)
+{
+ struct k3_comb_phy *phy = dev_get_drvdata(dev);
+ struct k3_lane_group *lg;
+
+ if (args->args_count != 2) {
+ dev_err(dev, "Invalid number of arguments\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ if (args->args[0] >= ARRAY_SIZE(k3_combphy_lane_datas)) {
+ dev_err(dev, "Invalid PHY id\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ lg = &phy->groups[args->args[0]];
+
+ if ((lg->is_pcie && args->args[1] != PHY_TYPE_PCIE) ||
+ (!lg->is_pcie && args->args[1] != PHY_TYPE_USB3)) {
+ dev_err(dev, "Invalid PHY mode\n");
+ return ERR_PTR(-EINVAL);
+ }
+
+ return lg->phy;
+}
+
+static int k3_comb_phy_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *node = dev->of_node;
+ struct phy_provider *provider;
+ struct k3_comb_phy *phy;
+ struct regmap *apmu;
+ u32 config = 0;
+ int ret;
+
+ phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
+ if (!phy)
+ return -ENOMEM;
+
+ phy->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(phy->base))
+ return PTR_ERR(phy->base);
+
+ phy->apb_spare = syscon_regmap_lookup_by_phandle(node, "spacemit,apb-spare");
+ if (IS_ERR(phy->apb_spare))
+ return dev_err_probe(dev, PTR_ERR(phy->apb_spare),
+ "Failed to fine APB SPARE syscon");
+
+ apmu = syscon_regmap_lookup_by_phandle_args(node, "spacemit,apmu", 1, &config);
+ if (IS_ERR(apmu))
+ return dev_err_probe(dev, PTR_ERR(phy->apb_spare),
+ "Failed to fine APMU syscon");
+
+ ret = k3_comb_phy_update_config(apmu, config);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "Failed to set lane configuration");
+
+ phy->dev = dev;
+ platform_set_drvdata(pdev, phy);
+
+ ret = k3_phy_calibrate(phy->apb_spare);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "Failed to calibrate phy");
+
+ ret = k3_comb_phy_init_lanes(phy, config);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "Failed to init lanes");
+
+ provider = devm_of_phy_provider_register(dev, k3_comb_phy_xlate);
+ if (IS_ERR(provider))
+ return dev_err_probe(dev, PTR_ERR(provider),
+ "Failed to register provider\n");
+
+ return 0;
+}
+
+static const struct of_device_id k3_comb_phy_of_match[] = {
+ { .compatible = "spacemit,k3-comb-phy" },
+ { },
+};
+MODULE_DEVICE_TABLE(of, k3_comb_phy_of_match);
+
+static struct platform_driver k3_comb_phy_driver = {
+ .probe = k3_comb_phy_probe,
+ .driver = {
+ .name = "spacemit,k3-comb-phy",
+ .of_match_table = k3_comb_phy_of_match,
+ },
+};
+module_platform_driver(k3_comb_phy_driver);
+
+MODULE_DESCRIPTION("SpacemiT K3 USB3/PCIe comb PHY driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/phy/spacemit/phy-k3-common.c b/drivers/phy/spacemit/phy-k3-common.c
new file mode 100644
index 000000000000..77c4b4073b96
--- /dev/null
+++ b/drivers/phy/spacemit/phy-k3-common.c
@@ -0,0 +1,398 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <linux/bitfield.h>
+#include <linux/cleanup.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
+#include <linux/regmap.h>
+#include <linux/usb.h>
+
+#include <dt-bindings/phy/phy.h>
+
+#include "phy-k3-common.h"
+
+/* PHY Registers */
+#define PHY_VERSION 0x0
+
+#define PHY_RESET_CFG 0x04
+
+#define PHY_RESET_RXBUF_RST BIT(0)
+#define PHY_RESET_SOFT_RST_PCS BIT(1)
+#define PHY_RESET_SOFT_RST_AHB BIT(2)
+#define PHY_RESET_EN_SD_AFTER_LOCK BIT(6)
+
+#define PHY_CLK_CFG 0x08
+
+#define PHY_CLK_PLL_READY BIT(0)
+#define PHY_CLK_TXCLK_INV BIT(2)
+#define PHY_CLK_RXCLK_EN BIT(3)
+#define PHY_CLK_TXCLK_EN BIT(4)
+#define PHY_CLK_PCLK_EN BIT(5)
+#define PHY_CLK_PIPE_PCLK_EN BIT(6)
+#define PHY_CLK_REFCLK_FREQ GENMASK(10, 7)
+#define PHY_CLK_REFCLK_24M 2
+#define PHY_CLK_SW_INIT_DONE BIT(11)
+#define PHY_CLK_PU_SSC_OUT BIT(23)
+
+#define PHY_MODE_CFG 0x0C
+
+#define PHY_MODE_PCIE_INT_EN BIT(0)
+#define PHY_MODE_LFPS_TPERIOD GENMASK(9, 8)
+#define PHY_MODE_LFPS_TPERIOD_USB 3
+
+#define PHY_PU_SEL 0x40
+
+#define PHY_PU_CFG_STATUS BIT(9)
+#define PHY_PU_OVRD_STATUS BIT(10)
+
+#define PHY_PU_CK_REG 0x54
+
+#define PHY_PU_REFCLK_100 BIT(25)
+
+#define PHY_PLL_REG1 0x58
+
+#define PHY_PLL_FREF_SEL GENMASK(15, 13)
+#define PHY_PLL_FREF_24M 0x1
+#define PHY_PLL_SSC_DEP_SEL GENMASK(27, 24)
+#define PHY_PLL_SSC_5000PPM 0xa
+#define PHY_PLL_SSC_MODE GENMASK(29, 28)
+#define PHY_PLL_SSC_MODE_CENTER_SPREAD 0
+#define PHY_PLL_SSC_MODE_UP_SPREAD 1
+#define PHY_PLL_SSC_MODE_DOWN_SPREAD 2
+#define PHY_PLL_SSC_MODE_DOWN_SPREAD1 3
+
+#define PHY_PLL_REG2 0x5c
+
+#define PHY_PLL_SEL_REF100 BIT(21)
+
+/* PHY RX Register Definitions */
+#define PHY_RX_REG_A 0x60
+
+#define PHY_RX_REG0_RLOAD BIT(4)
+#define PHY_RX_REG1_RTERM GENMASK(11, 8)
+#define PHY_RX_REG1_RC_CALI GENMASK(15, 12)
+#define PHY_RX_REG2_CSEL GENMASK(19, 16)
+#define PHY_RX_REG2_FORCE_CSEL BIT(20)
+#define PHY_RX_REG2_PSEL GENMASK(23, 21)
+#define PHY_RX_REG3_I_LOAD GENMASK(26, 24)
+#define PHY_RX_REG3_SEL_CBOOST_CODE BIT(27)
+#define PHY_RX_REG3_ADJ_BIAS GENMASK(29, 28)
+#define PHY_RX_REG3_RDEG1 GENMASK(31, 30)
+
+#define PHY_RX_REG_B 0x64
+
+#define PHY_RX_REGB_MASK GENMASK(23, 0)
+
+#define PHY_RX_REG4_RDEG2 GENMASK(2, 1)
+#define PHY_RX_REG4_ENVOS BIT(4)
+#define PHY_RX_REG4_RTERM_SEL BIT(5)
+#define PHY_RX_REG4_MANUAL_CFG BIT(7)
+#define PHY_RX_REG5_RCELL_VCM GENMASK(11, 8)
+#define PHY_RX_REG5_RCELL_BIAS GENMASK(15, 12)
+#define PHY_RX_REG6_H1_REG GENMASK(19, 16)
+#define PHY_RX_REG6_ADAPT_GAIN GENMASK(21, 20)
+#define PHY_RX_REG6_BYPASS_ADPT BIT(22)
+
+#define PHY_ADPT_CFG0 0x140
+#define PHY_ADPT_AFE_RST_OVRD_EN BIT(1)
+#define PHY_ADPT_AFE_RST_OVRD_VAL BIT(4)
+
+#define PHY_RXEQ_TIME 0xb4
+#define PHY_RXEQ_TIME_OVRD_POST_C_SOC BIT(21)
+#define PHY_RXEQ_TIME_CFG_AMP_SOC GENMASK(23, 22)
+#define PHY_RXEQ_TIME_AMP_SOC_650M 0
+#define PHY_RXEQ_TIME_AMP_SOC_800M 1
+#define PHY_RXEQ_TIME_AMP_SOC_870M 2
+#define PHY_RXEQ_TIME_AMP_SOC_900M 3
+#define PHY_RXEQ_TIME_OVRD_AMP_SOC BIT(24)
+
+#define PCIE_PU_ADDR_CLK_CFG 0x0008
+#define PHY_CLK_PLL_READY BIT(0)
+#define PCIE_INITAL_TIMER GENMASK(6, 3)
+#define CFG_INTERNAL_TIMER_ADJ GENMASK(10, 7)
+#define CFG_SW_PHY_INIT_DONE BIT(11)
+
+/* Lane RX/TX configuration (per‑lane, at lane_base) */
+#define PCIE_RX_REG1 0x050
+#define PCIE_TX_REG1 0x064
+
+#define PCIE_PLL_TIMEOUT 500000
+#define PCIE_POLL_DELAY 500
+
+static int k3_usb3phy_init_single(struct k3_lane_group *lg, void __iomem *base)
+{
+ struct phy *phy = lg->phy;
+ u32 val, tmp;
+ int ret;
+
+ val = readl(base + PHY_PU_SEL);
+ val = u32_replace_bits(val, 0, PHY_PU_CFG_STATUS);
+ val |= PHY_PU_OVRD_STATUS;
+ writel(val, base + PHY_PU_SEL);
+
+ udelay(200);
+
+ /* Do not wait CDR lock before sampling data */
+ val = readl(base + PHY_RESET_CFG);
+ val = u32_replace_bits(val, 0, PHY_RESET_EN_SD_AFTER_LOCK);
+ writel(val, base + PHY_RESET_CFG);
+
+ /* Power down 100MHz refclk buffer */
+ val = readl(base + PHY_PU_CK_REG);
+ val = u32_replace_bits(val, 0, PHY_PU_REFCLK_100);
+ writel(val, base + PHY_PU_CK_REG);
+
+ /* Program PLL REG1 configure the SSC */
+ val = FIELD_PREP(PHY_PLL_SSC_MODE, PHY_PLL_SSC_MODE_DOWN_SPREAD1) |
+ FIELD_PREP(PHY_PLL_SSC_DEP_SEL, PHY_PLL_SSC_5000PPM) |
+ FIELD_PREP(PHY_PLL_FREF_SEL, PHY_PLL_FREF_24M);
+ writel(val, base + PHY_PLL_REG1);
+
+ /* Un-select 100MHz PLL reference */
+ val = readl(base + PHY_PLL_REG2);
+ val = u32_replace_bits(val, 0, PHY_PLL_SEL_REF100);
+ writel(val, base + PHY_PLL_REG2);
+
+ /* USB LFPS period configuration */
+ val = readl(base + PHY_MODE_CFG);
+ val = u32_replace_bits(val, PHY_MODE_LFPS_TPERIOD_USB, PHY_MODE_LFPS_TPERIOD);
+ writel(val, base + PHY_MODE_CFG);
+
+ /* Force AFE adaptation reset */
+ val = readl(base + PHY_ADPT_CFG0);
+ val |= PHY_ADPT_AFE_RST_OVRD_EN | PHY_ADPT_AFE_RST_OVRD_VAL;
+ writel(val, base + PHY_ADPT_CFG0);
+
+ /* Override driver amplitude value to 900m */
+ val = readl(base + PHY_RXEQ_TIME);
+ val |= PHY_RXEQ_TIME_OVRD_AMP_SOC;
+ val = u32_replace_bits(val, PHY_RXEQ_TIME_AMP_SOC_900M, PHY_RXEQ_TIME_CFG_AMP_SOC);
+ writel(val, base + PHY_RXEQ_TIME);
+
+ /* Configure RX parameters */
+ val = PHY_RX_REG0_RLOAD |
+ FIELD_PREP(PHY_RX_REG1_RTERM, 0x8) |
+ FIELD_PREP(PHY_RX_REG1_RC_CALI, 0x7) |
+ FIELD_PREP(PHY_RX_REG2_CSEL, 0x8) |
+ PHY_RX_REG2_FORCE_CSEL |
+ FIELD_PREP(PHY_RX_REG2_PSEL, 0x4) |
+ FIELD_PREP(PHY_RX_REG3_I_LOAD, 0x7) |
+ PHY_RX_REG3_SEL_CBOOST_CODE |
+ FIELD_PREP(PHY_RX_REG3_ADJ_BIAS, 0x1) |
+ FIELD_PREP(PHY_RX_REG3_RDEG1, 0x3);
+ writel(val, base + PHY_RX_REG_A);
+
+ val = readl(base + PHY_RX_REG_B);
+ tmp = FIELD_PREP(PHY_RX_REG4_RDEG2, 0x2) |
+ PHY_RX_REG4_ENVOS | PHY_RX_REG4_RTERM_SEL | PHY_RX_REG4_MANUAL_CFG |
+ FIELD_PREP(PHY_RX_REG5_RCELL_VCM, 0x8) |
+ FIELD_PREP(PHY_RX_REG5_RCELL_BIAS, 0x8) |
+ FIELD_PREP(PHY_RX_REG6_H1_REG, 0x8) |
+ FIELD_PREP(PHY_RX_REG6_ADAPT_GAIN, 0x2);
+ val = u32_replace_bits(val, tmp, PHY_RX_REGB_MASK);
+ writel(val, base + PHY_RX_REG_B);
+
+ /*
+ * Inform PHY that all PLL-related configuration is done.
+ * PLL will not start locking until PHY_CLK_SW_INIT_DONE is set.
+ */
+ val = PHY_CLK_SW_INIT_DONE | PHY_CLK_PU_SSC_OUT |
+ FIELD_PREP(PHY_CLK_REFCLK_FREQ, PHY_CLK_REFCLK_24M) |
+ PHY_CLK_RXCLK_EN | PHY_CLK_TXCLK_EN |
+ PHY_CLK_PCLK_EN | PHY_CLK_PIPE_PCLK_EN;
+ writel(val, base + PHY_CLK_CFG);
+
+ ret = readl_poll_timeout(base + PHY_CLK_CFG, val,
+ (val & PHY_CLK_PLL_READY),
+ PCIE_POLL_DELAY, PCIE_PLL_TIMEOUT);
+ if (ret) {
+ dev_err(&phy->dev, "PHY PLL polling timeout\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int k3_usb3phy_init(struct phy *phy)
+{
+ struct k3_lane_group *lg = phy_get_drvdata(phy);
+ int ret, i;
+
+ for (i = 0; i < lg->data->lanes; i++) {
+ ret = k3_usb3phy_init_single(lg, lg->base + lg->data->offsets[i]);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int k3_usb3phy_set_speed(struct phy *phy, int speed)
+{
+ struct k3_lane_group *lg = phy_get_drvdata(phy);
+ void __iomem *base = lg->base + lg->data->offsets[0];
+ u32 val;
+
+ if (speed == USB_SPEED_HIGH) {
+ val = readl(base + PHY_PU_SEL);
+ val = u32_replace_bits(val, 0, PHY_PU_CFG_STATUS);
+ val |= PHY_PU_OVRD_STATUS;
+ writel(val, base + PHY_PU_SEL);
+
+ udelay(200);
+ }
+
+ return 0;
+}
+
+const struct phy_ops k3_usb3_phy_ops = {
+ .init = k3_usb3phy_init,
+ .set_speed = k3_usb3phy_set_speed,
+ .owner = THIS_MODULE,
+};
+EXPORT_SYMBOL_GPL(k3_usb3_phy_ops);
+
+static int k3_pcie_phy_init(struct phy *phy)
+{
+ struct k3_lane_group *lg = phy_get_drvdata(phy);
+ void __iomem *phy_base = lg->base + lg->data->offsets[0];
+ u32 val;
+ int ret;
+ int i;
+
+ val = readl(phy_base + PHY_PLL_REG1);
+ val = u32_replace_bits(val, 0x2, GENMASK(15, 12));
+ writel(val, phy_base + PHY_PLL_REG1);
+
+ val = readl(phy_base + PHY_PLL_REG2);
+ val = u32_replace_bits(val, 0, BIT(21));
+ writel(val, phy_base + PHY_PLL_REG2);
+
+ for (i = 0; i < lg->data->lanes; i++) {
+ void __iomem *lane_base = lg->base + lg->data->offsets[i];
+
+ val = readl(lane_base + PCIE_RX_REG1);
+ val = u32_replace_bits(val, 0, 0x3);
+ writel(val, phy_base + PCIE_RX_REG1);
+ }
+
+ val = readl(phy_base + PHY_PLL_REG2);
+ val |= BIT(20);
+ writel(val, phy_base + PHY_PLL_REG2);
+
+ writel(0x00006505, phy_base + PCIE_RX_REG1);
+
+ /* pll_reg1 of lane0, disable SSC: pll_reg4[3:0] = 0 */
+ val = readl(phy_base + PHY_PLL_REG1);
+ val = u32_replace_bits(val, 0, GENMASK(27, 24));
+ writel(val, phy_base + PHY_PLL_REG1);
+
+ for (i = 0; i < lg->data->lanes; i++) {
+ void __iomem *lane_base = lg->base + lg->data->offsets[i];
+
+ /* set cfg_tx_send_dummy_data to be 1'b1 for disable dash data */
+ val = readl(lane_base + PHY_PU_SEL);
+ val = u32_replace_bits(val, 1, BIT(13));
+ writel(val, lane_base + PHY_PU_SEL);
+
+ /* disable en_sample_data_after_cdr_locked */
+ val = readl(lane_base + PHY_RESET_CFG);
+ val = u32_replace_bits(val, 0, BIT(6));
+ writel(val, lane_base + PHY_RESET_CFG);
+
+ /* Dynamic Lock */
+ val = readl(lane_base + PHY_MODE_CFG);
+ val = u32_replace_bits(val, 1, BIT(2));
+ writel(val, lane_base + PHY_MODE_CFG);
+
+ val = FIELD_PREP(GENMASK(7, 0), 0x10) |
+ FIELD_PREP(GENMASK(15, 8), 0x78) |
+ FIELD_PREP(GENMASK(23, 16), 0x98) |
+ FIELD_PREP(GENMASK(31, 24), 0xdf);
+ writel(val, lane_base + PHY_RX_REG_A);
+
+ val = readl(lane_base + PHY_RX_REG_B);
+ val &= ~PHY_RX_REGB_MASK;
+ val |= FIELD_PREP(GENMASK(7, 0), 0xb4) |
+ FIELD_PREP(GENMASK(15, 8), 0x88) |
+ FIELD_PREP(GENMASK(23, 16), 0x28);
+ writel(val, lane_base + PHY_RX_REG_B);
+
+ /* Set init done */
+ val = readl(lane_base + PCIE_PU_ADDR_CLK_CFG);
+ val = u32_replace_bits(val, 1, CFG_SW_PHY_INIT_DONE);
+ writel(val, lane_base + PCIE_PU_ADDR_CLK_CFG);
+ }
+
+ ret = readl_poll_timeout(phy_base + PCIE_PU_ADDR_CLK_CFG, val,
+ (val & PHY_CLK_PLL_READY), PCIE_POLL_DELAY,
+ PCIE_PLL_TIMEOUT);
+ if (ret) {
+ dev_err(&lg->phy->dev, "PHY PLL lock timeout\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+const struct phy_ops k3_pcie_phy_ops = {
+ .init = k3_pcie_phy_init,
+ .owner = THIS_MODULE,
+};
+EXPORT_SYMBOL_GPL(k3_pcie_phy_ops);
+
+/* PHY rcal init requires APB_SPARE regmap access */
+
+#define APB_SPARE_PU_CAL 0x178
+#define PU_CAL BIT(17)
+
+#define APB_SPARE_RCAL_HSIO 0x17c
+#define APB_SPARE_PU_CAL_DONE BIT(8)
+#define RCAL_OVRD_PTRIM GENMASK(23, 20)
+#define RCAL_OVRD_NTRIM GENMASK(27, 24)
+#define RCAL_OVRD_PTRIM_EN BIT(28)
+#define RCAL_OVRD_NTRIM_EN BIT(29)
+#define RCAL_OVRD_STABLE_VAL BIT(30)
+#define RCAL_OVRD_STABLE_EN BIT(31)
+
+#define RCAL_OVRD_TRIM_EN (RCAL_OVRD_NTRIM_EN | RCAL_OVRD_PTRIM_EN)
+#define RCAL_OVRD_TRIM_MASK (RCAL_OVRD_NTRIM | RCAL_OVRD_PTRIM)
+
+#define PU_CAL_TIMEOUT 2000000
+
+static DEFINE_MUTEX(calibrate_lock);
+
+int k3_phy_calibrate(struct regmap *apb_spare)
+{
+ unsigned int val;
+ int ret;
+
+ guard(mutex)(&calibrate_lock);
+
+ regmap_read(apb_spare, APB_SPARE_RCAL_HSIO, &val);
+ if (val & APB_SPARE_PU_CAL_DONE)
+ return 0;
+
+ regmap_update_bits(apb_spare, APB_SPARE_PU_CAL, PU_CAL,
+ PU_CAL);
+
+ ret = regmap_read_poll_timeout(apb_spare, APB_SPARE_RCAL_HSIO,
+ val, (val & APB_SPARE_PU_CAL_DONE), PCIE_POLL_DELAY,
+ PU_CAL_TIMEOUT);
+
+ if (ret)
+ regmap_update_bits(apb_spare, APB_SPARE_RCAL_HSIO,
+ RCAL_OVRD_TRIM_EN | RCAL_OVRD_STABLE_VAL |
+ RCAL_OVRD_TRIM_MASK | RCAL_OVRD_STABLE_EN,
+ RCAL_OVRD_TRIM_EN | RCAL_OVRD_STABLE_VAL |
+ FIELD_PREP(RCAL_OVRD_NTRIM, 0x6) |
+ FIELD_PREP(RCAL_OVRD_PTRIM, 0xa) |
+ RCAL_OVRD_STABLE_EN);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(k3_phy_calibrate);
+
+MODULE_DESCRIPTION("SpacemiT K3 PHY common ops");
+MODULE_LICENSE("GPL");
diff --git a/drivers/phy/spacemit/phy-k3-common.h b/drivers/phy/spacemit/phy-k3-common.h
new file mode 100644
index 000000000000..49009c3c313a
--- /dev/null
+++ b/drivers/phy/spacemit/phy-k3-common.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _PHY_K3_COMMON_H
+#define _PHY_K3_COMMON_H
+
+#include <linux/phy/phy.h>
+
+struct k3_phy_lane_group_data {
+ u32 lanes;
+ u8 config;
+ u8 mask;
+ u32 offsets[] __counted_by(lanes);
+};
+
+struct k3_lane_group {
+ const struct k3_phy_lane_group_data *data;
+ void __iomem *base;
+ struct phy *phy;
+ bool is_pcie;
+};
+
+extern const struct phy_ops k3_pcie_phy_ops;
+extern const struct phy_ops k3_usb3_phy_ops;
+
+int k3_phy_calibrate(struct regmap *apb_spare);
+
+#endif
--
2.54.0
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^ permalink raw reply related
* [PATCH 1/2] dt-bindings: phy: Add Spacemit K3 USB3/PCIe comb phy support
From: Inochi Amaoto @ 2026-04-30 2:28 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Yixun Lan, Kees Cook, Gustavo A. R. Silva,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
Inochi Amaoto, Ze Huang, Alex Elder
Cc: linux-phy, devicetree, linux-riscv, spacemit, linux-kernel,
linux-hardening, Yixun Lan, Longbin Li
In-Reply-To: <20260430022843.1090138-1-inochiama@gmail.com>
The USB3/PCIe comb PHY on the K3 is a complex PHY group that
can provide multiple phy for both PCIe and USB controller.
Its mux configuration is controlled by the APMU syscon device.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
---
.../bindings/phy/spacemit,k3-comb-phy.yaml | 63 +++++++++++++++++++
1 file changed, 63 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/spacemit,k3-comb-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/spacemit,k3-comb-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,k3-comb-phy.yaml
new file mode 100644
index 000000000000..7aa2cf9301b7
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/spacemit,k3-comb-phy.yaml
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/spacemit,k3-comb-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Spacemit K3 PCIE/USB3 Comb PHY
+
+maintainers:
+ - Inochi Amaoto <inochiama@gmail.com>
+
+properties:
+ compatible:
+ const: spacemit,k3-comb-phy
+
+ reg:
+ maxItems: 1
+
+ "#phy-cells":
+ const: 2
+ description:
+ The first one is phy id, the second one is phy type.
+
+ spacemit,apb-spare:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to APB SPARE system controller interface, used for
+ PHY calibration.
+
+ spacemit,apmu:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle of APMU syscon
+ - description: configuration of the PHY lanes
+ description: |
+ Phandle to control PHY mux configuration. The configuration
+ is described as follows:
+ bit 4: 0 - PCIe A x8 mode, 1 - PCIe lane share mode
+ bit 3: 0 - PCIe A x4 mode, 1 - PCIe A x2 and PCIe B x2 mode
+ bit 2: 0 - PCIe C lane 0 is PCIe mode , 1 - USB mode
+ bit 1: 0 - PCIe C lane 1 is PCIe mode , 1 - USB mode
+ bit 0: 0 - PCIe D lane is PCIe mode , 1 - USB mode
+
+ The bit[3:0] is only valid when bit 4 is 1.
+
+required:
+ - compatible
+ - "#phy-cells"
+ - spacemit,apb-spare
+ - spacemit,apmu
+
+additionalProperties: false
+
+examples:
+ - |
+ phy@81d00000 {
+ compatible = "spacemit,k3-comb-phy";
+ reg = <0x81d00000 0x600000>;
+ #phy-cells = <2>;
+ spacemit,apb-spare = <&apb_spare>;
+ spacemit,apmu = <&apmu 0x00>;
+ };
--
2.54.0
--
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^ permalink raw reply related
* [PATCH 0/2] riscv: spacemit: Add K3 PCIe/USB comb phy support
From: Inochi Amaoto @ 2026-04-30 2:28 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Yixun Lan, Kees Cook, Gustavo A. R. Silva,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti,
Inochi Amaoto, Ze Huang, Alex Elder
Cc: linux-phy, devicetree, linux-riscv, spacemit, linux-kernel,
linux-hardening, Yixun Lan, Longbin Li
The PCIe/USB comb phy on K3 is a big phy that contains multiple
standalone phys for each PCIe and USB controllers. This phy is
required to configure a syscon device for mux configuration and
calibration.
Inochi Amaoto (2):
dt-bindings: phy: Add Spacemit K3 USB3/PCIe comb phy support
phy: spacemit: Add USB3/PCIe comb PHY driver for Spacemit K3
.../bindings/phy/spacemit,k3-comb-phy.yaml | 63 +++
drivers/phy/spacemit/Kconfig | 16 +
drivers/phy/spacemit/Makefile | 2 +
drivers/phy/spacemit/phy-k3-combphy.c | 250 +++++++++++
drivers/phy/spacemit/phy-k3-common.c | 398 ++++++++++++++++++
drivers/phy/spacemit/phy-k3-common.h | 27 ++
6 files changed, 756 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/spacemit,k3-comb-phy.yaml
create mode 100644 drivers/phy/spacemit/phy-k3-combphy.c
create mode 100644 drivers/phy/spacemit/phy-k3-common.c
create mode 100644 drivers/phy/spacemit/phy-k3-common.h
--
2.54.0
--
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^ permalink raw reply
* Re: [PATCH v4 0/2] phy: spacemit: Add USB2 PHY support for K3 SoC
From: Yixun Lan @ 2026-04-30 2:04 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Ze Huang
Cc: Junzhong Pan, linux-phy, devicetree, linux-riscv, spacemit,
linux-kernel, Krzysztof Kozlowski, Yao Zi
In-Reply-To: <20260401130713-GKD976850@kernel.org>
Hi Vinod Koul,
On 21:07 Wed 01 Apr , Yixun Lan wrote:
> Hi Vinod Koul,
>
> On 08:14 Thu 26 Mar , Yixun Lan wrote:
> > Hi Vinod Koul,
> >
> > On 01:00 Thu 05 Mar , Yixun Lan wrote:
> > > The series trys to add USB2 PHY support for SpacemiT K3 SoC, while
> > > patch [1/2] implement a disconnect function which is needed during
> > > next connection.
> > >
> > > No DTS part has been inclueded in this series, instead I plan to
> > > submit them later while adding USB host support.
> > >
> > > I've collected all patches and pushed a complete review branch here[1],
> > > for people who interested to test easily, which include DTS and necessary
> > > changes, other patches may still need to improve, but sufficient for
> > > verifying the functionality.
> > >
> > > Link: https://github.com/spacemit-com/linux/tree/WIP/k3/usb2 [1]
> > >
> >
> > Just want to ping this, Can you queue it for v7.1? Thanks
> >
> Ping again, I'd like to see USB2.0 support in v7.1 for SpacemiT K3
> SoC.. and I think this phy patch is the only dependency that waiting
> for, the USB DWC[1], and hub[2] patch already merged
>
> Link: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git/commit/?h=usb-next&id=c05cf9d274daf72dc7e433480cf2e0e888f6bd89 [1]
> Link: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git/commit/?h=usb-next&id=00b4fe5be06aecd6426930de86b7cffc2330f4b8 [2]
>
I'd like to ping inclusion for v7.2 cycle, checked locally, it's still able
to apply to v7.1-rc1 cleanly, so I see no need to send new version.
Many thanks
--
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* Re: [PATCH] phy: tegra: xusb: Fix per-pad high-speed termination calibration
From: Jon Hunter @ 2026-04-29 9:10 UTC (permalink / raw)
To: Wei-Cheng Chen, jckuo, vkoul, neil.armstrong, thierry.reding
Cc: linux-phy, linux-tegra, linux-kernel, waynec, wtsai
In-Reply-To: <fde997f6-c0a8-430b-8e45-38a490e683ad@nvidia.com>
Hi Vinod,
On 17/04/2026 09:23, Jon Hunter wrote:
> Hi Vinod,
>
> On 24/03/2026 09:11, Jon Hunter wrote:
>>
>> On 04/03/2026 10:26, Wei-Cheng Chen wrote:
>>> From: Wayne Chang <waynec@nvidia.com>
>>>
>>> The existing code reads a single hs_term_range_adj value from bit field
>>> [10:7] of FUSE_SKU_CALIB_0 and applies it to all USB2 pads uniformly.
>>> However, on SoCs that support per-pad termination, each pad has its own
>>> hs_term_range_adj field: pad 0 in FUSE_SKU_CALIB_0[10:7], and pads 1-3
>>> in FUSE_USB_CALIB_EXT_0 at bit offsets [8:5], [12:9], and [16:13]
>>> respectively.
>>>
>>> Fix the calibration by reading per-pad values from the appropriate fuse
>>> registers. For SoCs that do not support per-pad termination, replicate
>>> pad 0's value to all pads to maintain existing behavior.
>>>
>>> Add a has_per_pad_term flag to the SoC data to indicate whether per-pad
>>> termination values are available in FUSE_USB_CALIB_EXT_0.
>>>
>>> Fixes: 1ef535c6ba8e ("phy: tegra: xusb: Add Tegra194 support")
>>> Cc: stable@vger.kernel.org
>>> Signed-off-by: Wayne Chang <waynec@nvidia.com>
>>> Signed-off-by: Wei-Cheng Chen <weichengc@nvidia.com>
>>> ---
>>> drivers/phy/tegra/xusb-tegra186.c | 33 ++++++++++++++++++++++++-------
>>> drivers/phy/tegra/xusb.h | 1 +
>>> 2 files changed, 27 insertions(+), 7 deletions(-)
>>>
>>> diff --git a/drivers/phy/tegra/xusb-tegra186.c b/drivers/phy/tegra/
>>> xusb-tegra186.c
>>> index bec9616c4a2..4452e73fb82 100644
>>> --- a/drivers/phy/tegra/xusb-tegra186.c
>>> +++ b/drivers/phy/tegra/xusb-tegra186.c
>>> @@ -20,8 +20,8 @@
>>> /* FUSE USB_CALIB registers */
>>> #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
>>> #define HS_CURR_LEVEL_PAD_MASK 0x3f
>>> -#define HS_TERM_RANGE_ADJ_SHIFT 7
>>> -#define HS_TERM_RANGE_ADJ_MASK 0xf
>>> +#define HS_TERM_RANGE_ADJ_PADX_SHIFT(x) ((x) ? (5 + (x - 1) *
>>> 4) : 7)
>>> +#define HS_TERM_RANGE_ADJ_PAD_MASK 0xf
>>> #define HS_SQUELCH_SHIFT 29
>>> #define HS_SQUELCH_MASK 0x7
>>> @@ -253,7 +253,7 @@
>>> struct tegra_xusb_fuse_calibration {
>>> u32 *hs_curr_level;
>>> u32 hs_squelch;
>>> - u32 hs_term_range_adj;
>>> + u32 *hs_term_range_adj;
>>> u32 rpd_ctrl;
>>> };
>>> @@ -930,7 +930,7 @@ static int tegra186_utmi_phy_power_on(struct phy
>>> *phy)
>>> value = padctl_readl(padctl,
>>> XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
>>> value &= ~TERM_RANGE_ADJ(~0);
>>> - value |= TERM_RANGE_ADJ(priv->calib.hs_term_range_adj);
>>> + value |= TERM_RANGE_ADJ(priv->calib.hs_term_range_adj[index]);
>>> value &= ~RPD_CTRL(~0);
>>> value |= RPD_CTRL(priv->calib.rpd_ctrl);
>>> padctl_writel(padctl, value,
>>> XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
>>> @@ -1464,17 +1464,23 @@ static const char * const
>>> tegra186_usb3_functions[] = {
>>> static int
>>> tegra186_xusb_read_fuse_calibration(struct tegra186_xusb_padctl
>>> *padctl)
>>> {
>>> + const struct tegra_xusb_padctl_soc *soc = padctl->base.soc;
>>> struct device *dev = padctl->base.dev;
>>> unsigned int i, count;
>>> u32 value, *level;
>>> + u32 *hs_term_range_adj;
>>> int err;
>>> - count = padctl->base.soc->ports.usb2.count;
>>> + count = soc->ports.usb2.count;
>>> level = devm_kcalloc(dev, count, sizeof(u32), GFP_KERNEL);
>>> if (!level)
>>> return -ENOMEM;
>>> + hs_term_range_adj = devm_kcalloc(dev, count, sizeof(u32),
>>> GFP_KERNEL);
>>> + if (!hs_term_range_adj)
>>> + return -ENOMEM;
>>> +
>>> err = tegra_fuse_readl(TEGRA_FUSE_SKU_CALIB_0, &value);
>>> if (err)
>>> return dev_err_probe(dev, err,
>>> @@ -1490,8 +1496,8 @@ tegra186_xusb_read_fuse_calibration(struct
>>> tegra186_xusb_padctl *padctl)
>>> padctl->calib.hs_squelch = (value >> HS_SQUELCH_SHIFT) &
>>> HS_SQUELCH_MASK;
>>> - padctl->calib.hs_term_range_adj = (value >>
>>> HS_TERM_RANGE_ADJ_SHIFT) &
>>> - HS_TERM_RANGE_ADJ_MASK;
>>> + hs_term_range_adj[0] = (value >> HS_TERM_RANGE_ADJ_PADX_SHIFT(0)) &
>>> + HS_TERM_RANGE_ADJ_PAD_MASK;
>>> err = tegra_fuse_readl(TEGRA_FUSE_USB_CALIB_EXT_0, &value);
>>> if (err) {
>>> @@ -1503,6 +1509,17 @@ tegra186_xusb_read_fuse_calibration(struct
>>> tegra186_xusb_padctl *padctl)
>>> padctl->calib.rpd_ctrl = (value >> RPD_CTRL_SHIFT) &
>>> RPD_CTRL_MASK;
>>> + for (i = 1; i < count; i++) {
>>> + if (soc->has_per_pad_term)
>>> + hs_term_range_adj[i] =
>>> + (value >> HS_TERM_RANGE_ADJ_PADX_SHIFT(i)) &
>>> + HS_TERM_RANGE_ADJ_PAD_MASK;
>>> + else
>>> + hs_term_range_adj[i] = hs_term_range_adj[0];
>>> + }
>>> +
>>> + padctl->calib.hs_term_range_adj = hs_term_range_adj;
>>> +
>>> return 0;
>>> }
>>> @@ -1708,6 +1725,7 @@ const struct tegra_xusb_padctl_soc
>>> tegra194_xusb_padctl_soc = {
>>> .num_supplies = ARRAY_SIZE(tegra194_xusb_padctl_supply_names),
>>> .supports_gen2 = true,
>>> .poll_trk_completed = true,
>>> + .has_per_pad_term = true,
>>> };
>>> EXPORT_SYMBOL_GPL(tegra194_xusb_padctl_soc);
>>> @@ -1732,6 +1750,7 @@ const struct tegra_xusb_padctl_soc
>>> tegra234_xusb_padctl_soc = {
>>> .trk_hw_mode = false,
>>> .trk_update_on_idle = true,
>>> .supports_lp_cfg_en = true,
>>> + .has_per_pad_term = true,
>>> };
>>> EXPORT_SYMBOL_GPL(tegra234_xusb_padctl_soc);
>>> #endif
>>> diff --git a/drivers/phy/tegra/xusb.h b/drivers/phy/tegra/xusb.h
>>> index d2b5f956513..810b410672f 100644
>>> --- a/drivers/phy/tegra/xusb.h
>>> +++ b/drivers/phy/tegra/xusb.h
>>> @@ -436,6 +436,7 @@ struct tegra_xusb_padctl_soc {
>>> bool trk_hw_mode;
>>> bool trk_update_on_idle;
>>> bool supports_lp_cfg_en;
>>> + bool has_per_pad_term;
>>> };
>>> struct tegra_xusb_padctl {
>>
>> Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
>> Tested-by: Jon Hunter <jonathanh@nvidia.com>
>
> I guess this was missed for Linux v7.1. If you don't have any concerns
> can you pick this up for v7.2 once v7.1-rc1 is out?
OK to pick this up now? It would be great to get this into -next.
Thanks!
Jon
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^ permalink raw reply
* Re: [PATCH 4/4] phy: qualcomm: qmp-combo: Add support for Hawi SoC
From: Ronak Raheja @ 2026-04-29 7:28 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: vkoul, krzk+dt, conor+dt, robh, neil.armstrong, gregkh,
konrad.dybcio, abel.vesa, wesley.cheng, krzysztof.kozlowski,
linux-arm-msm, linux-phy, devicetree, linux-usb, linux-kernel
In-Reply-To: <s6ortwyjjoq6lsxjjykbbshg2rczchtol4ntmxipcrsqufvsby@whwxtlnn74id>
On 4/28/2026 4:40 AM, Dmitry Baryshkov wrote:
> On Mon, Apr 27, 2026 at 02:42:17PM -0700, Ronak Raheja wrote:
>> Add support for the USB3-DP combo PHY found on Hawi platform.
>>
>> The QMP PHY for Hawi uses QSERDES V10 register layouts. Add the required
>> PHY sequences from the hardware programming guide and new V10 register
>> header files. Also add a new v10 offset structure to incorporate the new
>> COM AON register module.
>
> Was this tested with the DP too or did you test only the USB part?
>
Only USB was tested. DP support will be added in a follow-up patch
once the MDSS nodes are ready for Hawi.
>>
>> Signed-off-by: Ronak Raheja <ronak.raheja@oss.qualcomm.com>
>> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
>> ---
>> .../phy/qualcomm/phy-qcom-qmp-com-aon-v10.h | 15 ++
>> drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 231 +++++++++++++++++-
>> .../phy/qualcomm/phy-qcom-qmp-dp-phy-v10.h | 15 ++
>> .../phy/qualcomm/phy-qcom-qmp-pcs-aon-v10.h | 13 +
>> .../phy/qualcomm/phy-qcom-qmp-pcs-usb-v10.h | 19 ++
>> drivers/phy/qualcomm/phy-qcom-qmp-pcs-v10.h | 34 +++
>> .../qualcomm/phy-qcom-qmp-qserdes-com-v10.h | 89 +++++++
>> .../qualcomm/phy-qcom-qmp-qserdes-txrx-v10.h | 89 +++++++
>> drivers/phy/qualcomm/phy-qcom-qmp.h | 5 +
>> 9 files changed, 506 insertions(+), 4 deletions(-)
>> create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-com-aon-v10.h
>> create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-dp-phy-v10.h
>> create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-aon-v10.h
>> create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v10.h
>> create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v10.h
>> create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v10.h
>> create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v10.h
>>
>> @@ -2198,6 +2368,7 @@ struct qmp_combo_offsets {
>> u16 dp_txa;
>> u16 dp_txb;
>> u16 dp_dp_phy;
>> + u16 aon_toggle;
>
> Are there (or will there) be any other regs? Is it just one-register
> space?
>
The COM AON block has 3 registers: USB3_AON_TOGGLE_ENABLE (0x00),
DP_AON_TOGGLE_ENABLE (0x04), and DUMMY_STATUS (0x08). Only the first
two are currently used.
>> };
>>
>> struct qmp_phy_cfg {
>> @@ -2705,6 +2895,27 @@ static const struct qmp_phy_cfg x1e80100_usb3dpphy_cfg = {
>> .regs = qmp_v6_n4_usb3phy_regs_layout,
>> };
>>
>> +static const struct qmp_phy_cfg hawi_usb3dpphy_cfg = {
>> + .offsets = &qmp_combo_offsets_v10,
>> +
>> + .serdes_tbl = hawi_usb3_serdes_tbl,
>> + .serdes_tbl_num = ARRAY_SIZE(hawi_usb3_serdes_tbl),
>> + .tx_tbl = hawi_usb3_tx_tbl,
>> + .tx_tbl_num = ARRAY_SIZE(hawi_usb3_tx_tbl),
>> + .rx_tbl = hawi_usb3_rx_tbl,
>> + .rx_tbl_num = ARRAY_SIZE(hawi_usb3_rx_tbl),
>> + .pcs_tbl = hawi_usb3_pcs_tbl,
>> + .pcs_tbl_num = ARRAY_SIZE(hawi_usb3_pcs_tbl),
>> + .pcs_usb_tbl = hawi_usb3_pcs_usb_tbl,
>> + .pcs_usb_tbl_num = ARRAY_SIZE(hawi_usb3_pcs_usb_tbl),
>> +
>> + .regs = qmp_v10_usb3phy_regs_layout,
>> + .reset_list = msm8996_usb3phy_reset_l,
>> + .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
>> + .vreg_list = qmp_phy_vreg_l,
>> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
>
> No DP counterpart and no mention of it in the commit message.
>
The DP configuration will be added in a follow-up patch once the MDSS
nodes are ready for Hawi.
Thanks,
Ronak
>> +};
>> +
>> static const struct qmp_phy_cfg sm6350_usb3dpphy_cfg = {
>> .offsets = &qmp_combo_offsets_v3,
>>
>
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