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* Re: [PATCH v1 6/6] phy: tegra: Add support for Nvidia Tegra XMM6260 PHY
From: sashiko-bot @ 2026-05-12 23:29 UTC (permalink / raw)
  To: Svyatoslav Ryhel
  Cc: conor+dt, krzk+dt, robh, devicetree, neil.armstrong, vkoul,
	linux-phy, olteanv
In-Reply-To: <20260511135703.62470-7-clamor95@gmail.com>

Thank you for your contribution! Sashiko AI review found 5 potential issue(s) to consider:
- [Critical] Incorrect error checking of `of_parse_phandle()` leads to arbitrary device matching and memory corruption.
- [Critical] Type confusion and NULL pointer dereference due to illegal access of an external device's driver data.
- [High] Permanent memory and reference count leak of the USB platform device.
- [Medium] Improper usage of `dev_err_probe()` inside runtime execution paths.
- [Medium] Missing Kconfig dependency on `CONFIG_USB_PHY`.
--

commit c599fd7b5a962e5696a6eb64dff41cd0427d8dde
Author: Svyatoslav Ryhel <clamor95@gmail.com>

phy: tegra: Add support for Nvidia Tegra XMM6260 PHY

Nvidia Tegra XMM6260 PHY is a hardware configuration used in Tegra SoCs
to provide proper interaction between the application processor and the
modem, as well as control over one of the SoC's USB lines for the modem.

> diff --git a/drivers/phy/tegra/Kconfig b/drivers/phy/tegra/Kconfig
> index 342fb736da4b1..41b5ce460f37c 100644
> --- a/drivers/phy/tegra/Kconfig
> +++ b/drivers/phy/tegra/Kconfig
> @@ -18,3 +18,15 @@ config PHY_TEGRA194_P2U
>  	help
>  	  Enable this to support the P2U (PIPE to UPHY) that is part of Tegra 19x
>  	  and 234 SOCs.
> +
> +config PHY_TEGRA_XMM6260
> +	tristate "NVIDIA Tegra XMM6260 PHY driver"
> +	depends on ARCH_TEGRA && USB_NET_XMM6260 && USB_SUPPORT
> +	select GENERIC_PHY

This driver relies on USB PHY APIs like devm_usb_get_phy_by_phandle(), but
doesn't seem to depend on USB_PHY. Could this cause silent probe failures if
CONFIG_USB_PHY is disabled and the stub functions are used?

[ ... ]

> diff --git a/drivers/phy/tegra/phy-tegra-xmm6260.c b/drivers/phy/tegra/phy-tegra-xmm6260.c
> new file mode 100644
> index 0000000000000..7511de1333aaf
> --- /dev/null
> +++ b/drivers/phy/tegra/phy-tegra-xmm6260.c
[ ... ]
> +struct tegra_usb_device {
> +	struct ci_hdrc_platform_data data;
> +	struct platform_device *dev;
> +};
[ ... ]
> +static int tegra_xmm6260_phy_power_on(struct phy *phy)
> +{
> +	struct tegra_xmm6260_phy *mphy = phy_get_drvdata(phy);
> +	struct tegra_usb_device *usb = platform_get_drvdata(mphy->usb_dev);

Does this rely on the exact memory layout of an external driver's private
structure? The tegra_usb_device struct is defined locally here.

Also, if the external driver hasn't probed yet, platform_get_drvdata()
returns NULL, which could lead to a NULL pointer dereference later when
accessing usb->dev.

> +	int ret;
> +
> +	gpiod_set_value_cansleep(mphy->enable_gpio, 1);
> +
> +	ret = usb_phy_init(mphy->usb_phy);
> +	if (ret) {
> +		gpiod_set_value_cansleep(mphy->enable_gpio, 0);
> +		return dev_err_probe(mphy->dev, ret,
> +				     "failed to init USB PHY\n");
> +	}

Is it safe to call dev_err_probe() outside of a probe function? This is a
runtime PHY operation callback, and using dev_err_probe() here might pollute
the deferred probe lists if the error code happens to match -EPROBE_DEFER.

[ ... ]
> +static int tegra_xmm6260_phy_probe(struct platform_device *pdev)
> +{
[ ... ]
> +	usb_node = of_parse_phandle(dev->of_node, "nvidia,usb-bus", 0);
> +	if (IS_ERR(usb_node))
> +		return dev_err_probe(dev, PTR_ERR(usb_node),
> +				     "failed to parse modem USB bus\n");

Should this check be if (!usb_node) instead? of_parse_phandle() returns NULL
when a property is missing, not an ERR_PTR.

If usb_node is NULL, this check is bypassed and of_find_device_by_node(NULL)
will be called below, which matches the very first platform device in the
system lacking a device tree node.

> +
> +	mphy->usb_dev = of_find_device_by_node(usb_node);
> +	of_node_put(usb_node);
> +	if (!mphy->usb_dev)
> +		return dev_err_probe(dev, -ENODEV,
> +				     "failed to get modem USB bus\n");

Does this leak the reference to the platform_device returned by
of_find_device_by_node()? It increments the reference count via
get_device(), but there doesn't seem to be a corresponding put_device() in
the error paths below or in a remove callback.

> +
> +	mphy->usb_phy = devm_usb_get_phy_by_phandle(dev, "nvidia,usb-bus", 1);

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260511135703.62470-1-clamor95@gmail.com?part=6

-- 
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^ permalink raw reply

* Re: [PATCH v1 5/6] dt-bindings: phy: tegra: Document Nvidia Tegra XMM6260 PHY
From: sashiko-bot @ 2026-05-12 23:29 UTC (permalink / raw)
  To: Svyatoslav Ryhel
  Cc: krzk+dt, linux-phy, vkoul, robh, olteanv, devicetree,
	neil.armstrong, conor+dt
In-Reply-To: <20260511135703.62470-6-clamor95@gmail.com>

Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider:
- [High] The binding models an external USB/HSIC modem as a standalone, virtual 'PHY' node instead of representing it accurately in the hardware hierarchy.
- [Medium] The `nvidia,usb-bus` property groups two unrelated phandles (USB controller and USB PHY) and introduces a reverse-dependency.
- [Low] The compatible string `nvidia,tegra-xmm6260` uses the incorrect vendor prefix for the hardware it represents.
- [Low] The `nvidia,usb-bus` property is defined as a `phandle-array` but lacks the necessary `items` description to define the cell count, leading to a `dt_binding_check` validation failure.
--

commit 9a3c0eae039eb5a94c2d0ec7ecce7c586c326f99
Author: Svyatoslav Ryhel <clamor95@gmail.com>

dt-bindings: phy: tegra: Document Nvidia Tegra XMM6260 PHY

This commit documents the XMM6260 PHY binding, a hardware configuration
used in Tegra SoCs to control power sequencing and manage the USB lines
for the modem.

> diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra-xmm6260.yaml b/Documentation/devicetree/bindings/phy/nvidia,tegra-xmm6260.yaml
> new file mode 100644
> index 0000000000000..0346433c97725
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/nvidia,tegra-xmm6260.yaml
> @@ -0,0 +1,58 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/nvidia,tegra-xmm6260.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Nvidia Tegra PHY for XMM6260 modem
> +
> +description:
> +  A hardware configuration used in Tegra SoCs to provide proper interaction
> +  between the application processor and the modem, as well as control over
> +  one of the SoC's USB lines for the modem.

Is modeling this external modem as a standalone virtual PHY node the best
approach for representing the hardware topology?

The device tree should describe physical hardware hierarchy. Since the
XMM6260 is an external modem connected to the host via a USB or HSIC bus,
it would traditionally be modeled as a child node of the USB controller.

Handling power sequencing by creating a virtual PHY node is a known
anti-pattern. Power requirements are typically managed by the USB subsystem's
device tree bindings or a generic power sequencing framework.

> +
> +maintainers:
> +  - Svyatoslav Ryhel <clamor95@gmail.com>
> +
> +properties:
> +  compatible:
> +    const: nvidia,tegra-xmm6260

This isn't a bug, but the XMM6260 is a modem manufactured by Infineon/Intel.
Should the compatible string use a vendor prefix corresponding to the actual
manufacturer (e.g., "infineon" or "intel") instead of "nvidia", since this
represents an external component rather than a Tegra-specific SoC block?

> +
> +  enable-gpios:
> +    description: GPIO connected to the EINT1 pin
> +    maxItems: 1
> +
> +  nvidia,usb-bus:
> +    description:
> +      Contains two phandles; the first is pointing to the Host's USB controller
> +      and the second linking to the controller's PHY.
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    minItems: 2
> +    maxItems: 2

Does this custom property introduce an unnecessary reverse-dependency in the
device tree?

Standard bus hierarchy dictates that relationships are established naturally
via parent-child nodes. Pointing an external device back to its host
controller via a custom phandle is a non-standard way to represent a bus
connection. Additionally, grouping two distinct hardware components (a host
controller and its PHY) into a single phandle array mixes unrelated
references.

Can this property definition cause a validation failure during
dt_binding_check?

Because this is typed as a phandle-array, the dtschema validation framework
will attempt to parse the array elements by looking for a
"#nvidia,usb-bus-cells" property on the referenced target nodes (the USB
controller and PHY). Since those target nodes won't define that custom cells
property, the example schema validation is likely to fail.

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260511135703.62470-1-clamor95@gmail.com?part=5

-- 
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^ permalink raw reply

* Re: [PATCH v2 2/6] phy: rockchip: samsung-hdptx: Handle uncommitted PHY config changes
From: sashiko-bot @ 2026-05-12 23:57 UTC (permalink / raw)
  To: Cristian Ciocaltea; +Cc: vkoul, olteanv, linux-phy, neil.armstrong
In-Reply-To: <20260511-hdptx-clk-fixes-v2-2-664e41379cab@collabora.com>

Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider:
- [High] Abuse of CCF determine_rate corrupts the clock tree rate cache.
- [High] Ignored return value in clk_ops.prepare masks hardware initialization failures.
- [High] Missing mutual exclusion between CCF and PHY frameworks causes concurrent hardware corruption.
- [High] Unbalanced PHY usage count on lane mode configuration failure in rk_hdptx_phy_power_on.
--

commit 53b6461d3d35f9f83438d0a57cf5379f7c1fcba8
Author: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>

phy: rockchip: samsung-hdptx: Handle uncommitted PHY config changes

Any changes to the PHY link rate and/or color depth done via the HDMI
PHY configuration API are not immediately programmed into the hardware,
but are delayed until the PHY usage count gets incremented from 0 to 1,
that is when it is powered on or when the PLL clock exposed through
the CCF API is prepared, whichever comes first.

[ ... ]

> diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
> index 7fb1c22318bbf..12c259d9544cf 100644
> --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
> +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
> @@ -1347,25 +1354,22 @@ static int rk_hdptx_phy_consumer_get(struct rk_hdptx_phy *hdptx)
>  		return 0;
>  
>  	ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &status);
> -	if (ret)
> -		goto dec_usage;
> -
> -	if (status & HDPTX_O_PLL_LOCK_DONE)
> -		dev_warn(hdptx->dev, "PLL locked by unknown consumer!\n");
> +	if (ret) {
> +		atomic_dec(&hdptx->usage_count);
> +		return ret;
> +	}
>  
>  	if (mode == PHY_MODE_DP) {
>  		rk_hdptx_dp_reset(hdptx);
>  	} else {
> -		ret = rk_hdptx_pll_cmn_config(hdptx);
> -		if (ret)
> -			goto dec_usage;
> +		/*
> +		 * Ignore PLL config errors at this point as pll_config_dirty
> +		 * was not reset and, therefore, operation will be retried.
> +		 */
> +		rk_hdptx_pll_cmn_config(hdptx);
>  	}
>  
>  	return 0;

Does dropping the return value of rk_hdptx_pll_cmn_config() mask hardware
initialization failures?

If pll_config_dirty is false (for example, the clock was previously prepared
and unprepared), a subsequent failure won't be retried later.

Also, if a caller invokes clk_prepare_enable() but not clk_set_rate() or
phy_power_on(), will the hardware remain unconfigured while CCF incorrectly
assumes the clock is running?

> @@ -1700,16 +1704,20 @@ static int rk_hdptx_phy_power_on(struct phy *phy)
>  		if (ret)
>  			rk_hdptx_phy_consumer_put(hdptx, true);
>  	} else {
> -		regmap_write(hdptx->grf, GRF_HDPTX_CON0,
> -			     HDPTX_MODE_SEL << 16 | FIELD_PREP(HDPTX_MODE_SEL, 0x0));
> +		if (hdptx->pll_config_dirty)
> +			ret = rk_hdptx_pll_cmn_config(hdptx);
>  
> -		if (hdptx->hdmi_cfg.mode == PHY_HDMI_MODE_FRL)
> -			ret = rk_hdptx_frl_lcpll_mode_config(hdptx);
> -		else
> -			ret = rk_hdptx_tmds_ropll_mode_config(hdptx);
> +		if (!ret) {
> +			regmap_write(hdptx->grf, GRF_HDPTX_CON0,
> +				     HDPTX_MODE_SEL << 16 | FIELD_PREP(HDPTX_MODE_SEL, 0x0));
>  
> -		if (ret)
> +			if (hdptx->hdmi_cfg.mode == PHY_HDMI_MODE_FRL)
> +				ret = rk_hdptx_frl_lcpll_mode_config(hdptx);
> +			else
> +				ret = rk_hdptx_tmds_ropll_mode_config(hdptx);
> +		} else {
>  			rk_hdptx_phy_consumer_put(hdptx, true);
> +		}
>  	}

If rk_hdptx_tmds_ropll_mode_config() or rk_hdptx_frl_lcpll_mode_config()
fails, ret is set but the else block is never executed. Does this leave
usage_count unbalanced and prevent the PHY from being powered down? I noted
this was addressed later in the series by commit "phy: rockchip:
samsung-hdptx: Drop TMDS rate setup workaround", but wanted to point it out.

Also, does this logic introduce a race condition between CCF (clk_prepare)
and the PHY framework (phy_power_on)? The usage_count is atomic, but there
appears to be no mutual exclusion for the hardware configuration itself.

If Thread A calls clk_prepare() and increments the count to 1, it starts the
lengthy rk_hdptx_pll_cmn_config() hardware sequence.

If Thread B calls phy_power_on() concurrently and increments the count to 2,
it returns immediately from rk_hdptx_phy_consumer_get(). Thread B will then
evaluate hdptx->pll_config_dirty, see it is still true, and concurrently
execute rk_hdptx_pll_cmn_config() while Thread A is already modifying the
same registers.

> @@ -2303,8 +2314,19 @@ static int rk_hdptx_phy_clk_determine_rate(struct clk_hw *hw,
>  {
>  	struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
>  
> -	if (hdptx->hdmi_cfg.mode == PHY_HDMI_MODE_FRL)
> -		return hdptx->hdmi_cfg.rate;
> +	/*
> +	 * Invalidate current clock rate to ensure rk_hdptx_phy_clk_set_rate()
> +	 * will be invoked to commit PLL configuration.
> +	 */
> +	if (hdptx->pll_config_dirty) {
> +		req->rate = 0;
> +		return 0;
> +	}

Does returning req->rate = 0 here corrupt the clock tree rate cache?

By returning 0 to bypass CCF's optimization and force set_rate(), the Common
Clock Framework will cache 0 Hz as the actual hardware rate and propagate it
downstream. 

Could this cause downstream consumers (like the VOP2 display clock dclk)
or rate change notifiers to receive 0 Hz, potentially leading to
division-by-zero errors or broken pixel clock math?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260511-hdptx-clk-fixes-v2-0-664e41379cab@collabora.com?part=2

-- 
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^ permalink raw reply

* Re: [PATCH 2/4] arm64: dts: qcom: Introduce Shikra SoC base dtsi
From: sashiko-bot @ 2026-05-13  4:06 UTC (permalink / raw)
  To: Komal Bajaj
  Cc: linux-phy, krzk+dt, devicetree, neil.armstrong, olteanv, conor+dt,
	robh, vkoul
In-Reply-To: <20260512-shikra-dt-v1-2-716438330dd0@oss.qualcomm.com>

Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider:
- [High] Invalid PPI interrupt numbers (1, 2, 3, 0) are specified for the ARMv8 generic timer instead of the architecturally required numbers (13, 14, 11, 10).
- [Medium] The `sdhc_1` node incorrectly uses RPMh interconnect tags (`QCOM_ICC_TAG_ALWAYS`, `QCOM_ICC_TAG_ACTIVE_ONLY`) on an RPM-based interconnect topology.
- [Medium] The USB SuperSpeed wakeup interrupt (`ss_phy_irq`) directly references the GIC instead of routing through the MPM, breaking system wake-up from deep sleep.
- [Low] The `sdhc_1` node uses the undeclared macro `RPMHPD_CX` for its `power-domains` property, which will cause a Device Tree compiler syntax error.
--

commit e2ee94ef3a5741f2cb9aae14dbef52c5f4a760f1
Author: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Subject: arm64: dts: qcom: Introduce Shikra SoC base dtsi

This commit adds initial device tree support for the Qualcomm Shikra SoC, an
IoT-focused platform featuring a Cortex-A55 and Cortex-A78C cluster. It
configures RPM-based power and clock management alongside various peripherals
like USB, eMMC, and the generic timer.

> diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
> new file mode 100644
> index 0000000000000..262c488add1ec
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi

[ ... ]

> +		sdhc_1: mmc@4744000 {
> +			compatible = "qcom,shikra-sdhci", "qcom,sdhci-msm-v5";
> +
> +			reg = <0x0 0x04744000 0x0 0x1000>,
> +			      <0x0 0x04745000 0x0 0x1000>;

[ ... ]

> +			interconnects = <&system_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS
> +					&mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>,
> +					<&mem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
> +					&config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ACTIVE_ONLY>;

Since the Shikra SoC utilizes an RPM-based architecture, should this node use
interconnect tags from qcom,rpm-icc.h (such as RPM_ALWAYS_TAG) instead? 
Passing RPMh interconnect tags from qcom,icc.h to an RPM interconnect provider
might result in unhandled parameters or silent bandwidth request failures.

> +			interconnect-names = "sdhc-ddr",
> +					     "cpu-sdhc";
> +
> +			power-domains = <&rpmpd RPMHPD_CX>;

Does this power-domains assignment use an undeclared macro? RPMHPD_CX belongs
to RPMh-based power domains, while this platform relies on RPMPD. This looks
like it will cause a dtc syntax error during the build.

[ ... ]

> +		usb_1: usb@4e00000 {
> +			compatible = "qcom,shikra-dwc3", "qcom,snps-dwc3";
> +			reg = <0x0 0x04e00000 0x0 0xfc100>;

[ ... ]

> +			interrupts-extended = <&intc GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
> +					      <&intc GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
> +					      <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
> +					      <&intc GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
> +					      <&intc GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "dwc_usb3",
> +					  "pwr_event",
> +					  "qusb2_phy",
> +					  "hs_phy_irq",
> +					  "ss_phy_irq";

The mpm node correctly maps pin 12 to GIC SPI 422 for the DWC3 ss_phy_irq.
Could routing this directly to the GIC here instead of hierarchically through
the mpm (e.g., <&mpm 12 IRQ_TYPE_LEVEL_HIGH>) prevent the hardware from
waking up from low-power states upon USB activity?

[ ... ]

> +	timer {
> +		compatible = "arm,armv8-timer";
> +
> +		interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
> +			     <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
> +			     <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
> +			     <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
> +	};

Are these PPI interrupt numbers correct for the ARMv8 generic timer? The
architecturally defined numbers are typically 13 for Secure, 14 for Non-secure,
11 for Virtual, and 10 for Hypervisor. Using invalid hardware IRQ lines here
could prevent the kernel from receiving scheduler ticks and stall the boot.

> +};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260512-shikra-dt-v1-0-716438330dd0@oss.qualcomm.com?part=2

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^ permalink raw reply

* Re: [PATCH 3/4] arm64: dts: qcom: Add Shikra CQM SoM platform
From: sashiko-bot @ 2026-05-13  4:28 UTC (permalink / raw)
  To: Komal Bajaj
  Cc: robh, linux-phy, neil.armstrong, vkoul, olteanv, krzk+dt,
	conor+dt, devicetree
In-Reply-To: <20260512-shikra-dt-v1-3-716438330dd0@oss.qualcomm.com>

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] The PMIC regulator definitions omit their required input supply dependencies (e.g., `vdd_s2-supply`, `vdd_l3-supply`), breaking the power hierarchy.
- [Medium] The device tree inaccurately hardcodes the `compatible` string to a different PMIC model (`qcom,rpm-pm2250-regulators`) instead of explicitly identifying the actual hardware (PM4125).
--

commit 457abf6e7ac410430c866842e08e602ec3daaa51
Author: Komal Bajaj <komal.bajaj@oss.qualcomm.com>

arm64: dts: qcom: Add Shikra CQM SoM platform

Add device tree include for the CQM variant of the Shikra System-on-Module.
This variant integrates the Shikra SoC and PM4125 PMIC. The DTSI includes
the common shikra.dtsi and adds PM4125 PMIC regulator definitions.

> diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi
> new file mode 100644
> index 0000000000000..401e71720519d
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi
[ ... ]
> +&rpm_requests {
> +	regulators {
> +		compatible = "qcom,rpm-pm2250-regulators";

Since the commit message indicates this is a PM4125 PMIC, should the
compatible string include a specific identifier for the actual hardware?

Using a specific identifier like "qcom,rpm-pm4125-regulators" alongside
the fallback allows the kernel to apply specific quirks if PM4125 errata
are discovered later.

> +
> +		pm4125_s2: s2 {
> +			regulator-min-microvolt = <1000000>;
> +			regulator-max-microvolt = <1200000>;
> +		};

Do these regulators need to explicitly define their input supply dependencies
such as vdd_s2-supply?

Without these properties, the regulator framework might be unaware that the
PMIC regulators draw power from upstream supplies.

If the kernel dynamically manages the upstream supply and its reference count
drops to zero, could it be disabled, causing an unexpected power loss for
downstream components?

[ ... ]

-- 
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* [PATCH] phy: ti: pipe3: Fix clock resource leak on probe errors
From: Hongling Zeng @ 2026-05-13  6:39 UTC (permalink / raw)
  To: vkoul, neil.armstrong, johan, kishon
  Cc: linux-phy, linux-kernel, zhongling0719, Hongling Zeng

When devm_phy_create() or devm_of_phy_provider_register() fails,
the refclk that was enabled earlier is not disabled, causing a
resource leak.

Fix this by adding an error handling path to disable the clock
when these functions fail.

Fixes: 234738ea3390 ("phy: ti-pipe3: Add PHY driver for TI PIPE3 PHY")
Signed-off-by: Hongling Zeng <zenghongling@kylinos.cn>
---
 drivers/phy/ti/phy-ti-pipe3.c | 18 +++++++++++++++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/drivers/phy/ti/phy-ti-pipe3.c b/drivers/phy/ti/phy-ti-pipe3.c
index b5543b5c674c..29a4cbe73781 100644
--- a/drivers/phy/ti/phy-ti-pipe3.c
+++ b/drivers/phy/ti/phy-ti-pipe3.c
@@ -837,15 +837,27 @@ static int ti_pipe3_probe(struct platform_device *pdev)
 	}
 
 	generic_phy = devm_phy_create(dev, NULL, &ops);
-	if (IS_ERR(generic_phy))
-		return PTR_ERR(generic_phy);
+	if (IS_ERR(generic_phy)) {
+		ret = PTR_ERR(generic_phy);
+		goto err_clk_disable;
+	}
 
 	phy_set_drvdata(generic_phy, phy);
 
 	ti_pipe3_power_off(generic_phy);
 
 	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
-	return PTR_ERR_OR_ZERO(phy_provider);
+	if (IS_ERR(phy_provider)) {
+		ret = PTR_ERR(phy_provider);
+		goto err_clk_disable;
+	}
+
+	return 0;
+
+err_clk_disable:
+	if (phy->sata_refclk_enabled)
+		clk_disable_unprepare(phy->refclk);
+	return ret;
 }
 
 static void ti_pipe3_remove(struct platform_device *pdev)
-- 
2.25.1


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* Re: [PATCH v2 3/5] dt-bindings: phy: rockchip,inno-usb2phy: Add compatible for RK3528
From: Diederik de Haas @ 2026-05-13  9:09 UTC (permalink / raw)
  To: Heiko Stuebner, vkoul
  Cc: neil.armstrong, robh, krzk+dt, conor+dt, linux-phy, devicetree,
	linux-arm-kernel, linux-rockchip, linux-kernel, jonas
In-Reply-To: <20260505170410.3265305-4-heiko@sntech.de>

Hi Heiko,

On Tue May 5, 2026 at 7:04 PM CEST, Heiko Stuebner wrote:
> From: Jonas Karlman <jonas@kwiboo.se>
>
> The embedded USB2 PHY on RK3528 is very similar to the one in RK3568,
> the main difference being that it only uses two clocks instead of three.
>
> Add compatible to support the USB2 PHY in RK3528.
>
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
> Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
>  .../bindings/phy/rockchip,inno-usb2phy.yaml   | 30 ++++++++++++++++---
>  1 file changed, 26 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml
> index b95c9e3e44fe..f50fc69fbbe4 100644
> --- a/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml
> @@ -20,6 +20,7 @@ properties:
>        - rockchip,rk3328-usb2phy
>        - rockchip,rk3366-usb2phy
>        - rockchip,rk3399-usb2phy
> +      - rockchip,rk3528-usb2phy
>        - rockchip,rk3562-usb2phy
>        - rockchip,rk3568-usb2phy
>        - rockchip,rk3576-usb2phy
> @@ -41,11 +42,15 @@ properties:
>      maxItems: 3
>  
>    clock-names:
> -    minItems: 1
> -    items:
> +    oneOf:
>        - const: phyclk
> -      - const: aclk
> -      - const: aclk_slv
> +      - items:
> +          - const: phyclk
> +          - const: pclk
> +      - items:
> +          - const: phyclk
> +          - const: aclk
> +          - const: aclk_slv
>  
>    assigned-clocks:
>      description:
> @@ -65,6 +70,9 @@ properties:
>      description: Muxed interrupt for both ports
>      maxItems: 1
>  
> +  power-domains:
> +    maxItems: 1
> +

The commit message talks about (the differences in) clocks, but says
nothing about power-domains. Shouldn't that be mentioned and/or split
off into its own patch? (FWIW: I like the change itself)

Cheers,
  Diederik

>    resets:
>      maxItems: 2
>  
> @@ -150,6 +158,7 @@ allOf:
>          compatible:
>            contains:
>              enum:
> +              - rockchip,rk3528-usb2phy
>                - rockchip,rk3568-usb2phy
>                - rockchip,rv1108-usb2phy
>      then:
> @@ -218,6 +227,19 @@ allOf:
>          clock-names:
>            maxItems: 1
>  
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - rockchip,rk3528-usb2phy
> +    then:
> +      properties:
> +        clocks:
> +          minItems: 2
> +        clock-names:
> +          minItems: 2
> +
>    - if:
>        properties:
>          compatible:


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* Re: [PATCH] phy: ti: pipe3: Fix clock resource leak on probe errors
From: Vladimir Oltean @ 2026-05-13  9:21 UTC (permalink / raw)
  To: Hongling Zeng
  Cc: vkoul, neil.armstrong, johan, kishon, linux-phy, linux-kernel,
	zhongling0719
In-Reply-To: <20260513063902.113956-1-zenghongling@kylinos.cn>

On Wed, May 13, 2026 at 02:39:02PM +0800, Hongling Zeng wrote:
> When devm_phy_create() or devm_of_phy_provider_register() fails,
> the refclk that was enabled earlier is not disabled, causing a
> resource leak.
> 
> Fix this by adding an error handling path to disable the clock
> when these functions fail.
> 
> Fixes: 234738ea3390 ("phy: ti-pipe3: Add PHY driver for TI PIPE3 PHY")
> Signed-off-by: Hongling Zeng <zenghongling@kylinos.cn>
> ---

Fixes tag: Fixes: 234738ea3390 ("phy: ti-pipe3: Add PHY driver for TI PIPE3 PHY")
Has these problem(s):
	- Subject does not match target commit subject
	  Just use
		git log -1 --format='Fixes: %h ("%s")'

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* [PATCH v1] phy: ti: pipe3: Fix clock resource leak on probe errors
From: Hongling Zeng @ 2026-05-13  9:43 UTC (permalink / raw)
  To: vkoul, neil.armstrong, johan, kishon
  Cc: linux-phy, linux-kernel, zhongling0719, Hongling Zeng

When devm_phy_create() or devm_of_phy_provider_register() fails,
the refclk that was enabled earlier is not disabled, causing a
resource leak.

Fix this by adding an error handling path to disable the clock
when these functions fail.

Fixes: 234738ea3390 ("phy: ti-pipe3: move clk initialization to a separate function")
Signed-off-by: Hongling Zeng <zenghongling@kylinos.cn>

---
 Change in v1:
  -correct the fix tag.
---
---
 drivers/phy/ti/phy-ti-pipe3.c | 18 +++++++++++++++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/drivers/phy/ti/phy-ti-pipe3.c b/drivers/phy/ti/phy-ti-pipe3.c
index b5543b5c674c..29a4cbe73781 100644
--- a/drivers/phy/ti/phy-ti-pipe3.c
+++ b/drivers/phy/ti/phy-ti-pipe3.c
@@ -837,15 +837,27 @@ static int ti_pipe3_probe(struct platform_device *pdev)
 	}
 
 	generic_phy = devm_phy_create(dev, NULL, &ops);
-	if (IS_ERR(generic_phy))
-		return PTR_ERR(generic_phy);
+	if (IS_ERR(generic_phy)) {
+		ret = PTR_ERR(generic_phy);
+		goto err_clk_disable;
+	}
 
 	phy_set_drvdata(generic_phy, phy);
 
 	ti_pipe3_power_off(generic_phy);
 
 	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
-	return PTR_ERR_OR_ZERO(phy_provider);
+	if (IS_ERR(phy_provider)) {
+		ret = PTR_ERR(phy_provider);
+		goto err_clk_disable;
+	}
+
+	return 0;
+
+err_clk_disable:
+	if (phy->sata_refclk_enabled)
+		clk_disable_unprepare(phy->refclk);
+	return ret;
 }
 
 static void ti_pipe3_remove(struct platform_device *pdev)
-- 
2.25.1


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* Re: [PATCH phy-next 5/5] phy: lynx-28g: add support for 25GBASER
From: Josua Mayer @ 2026-05-13 11:00 UTC (permalink / raw)
  To: Vladimir Oltean, linux-phy@lists.infradead.org
  Cc: netdev@vger.kernel.org, Ioana Ciornei, Vinod Koul, Neil Armstrong,
	linux-kernel@vger.kernel.org
In-Reply-To: <20260511150023.1903577-6-vladimir.oltean@nxp.com>


Am 11.05.26 um 17:00 schrieb Vladimir Oltean:
> From: Ioana Ciornei <ioana.ciornei@nxp.com>
>
> Add support for 25GBASE-R in the Lynx 28G SerDes PHY driver. This will
> be used by the dpaa2-mac consumer on LX2160A with:
> - phy_validate(phy, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_25GBASER) to
>   detect support.
> - phy_set_mode_ext(phy, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_25GBASER)
>   to reconfigure the lane for this protocol.
>
> The intended use case for dynamic protocol switching to 25GBase-R is
> with SFP28 modules, and protocol switching is triggered by the SFP
> module insertion. There also exists a 25GBase-KR use case, where the
> protocol switching is covered by IEEE 802.3 clause 73 auto-negotiation.
> However, that is not handled here; it merely needs the support added
> here as basic ground work.
>
> The lane frequency for 25GbE is sourced from a clock net frequency of
> 12.890625 GHz, as produced by PLLF or PLLS, further multiplied by the
> lane by 2. The clock net frequencies produced by the PLLs are treated as
> read-only by the driver, so the absence of a PLL provisioned for the
> right clock net frequency implies absence of 25GbE support, even though
> a lane might have the appropriate protocol converter for it.
>
> In terms of implementation, the change consists of:
> - determining at probe time if any PLL was preconfigured for the
>   required clock net frequency for 25GbE
> - adding the default lane parameters for reconfiguring a lane to 25GbE
>   irrespective of the original protocol
> - allowing this operating mode only on supported lanes, i.e. all lanes
>   of LX2162A SerDes #1, and LX2160A SerDes lanes 0-1, 4-7.
>
> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> ---
> Change previously submitted at:
> https://lore.kernel.org/linux-phy/20260114152111.625350-6-vladimir.oltean@nxp.com/
>
> Changes:
> - reword commit message
> ---
>  drivers/phy/freescale/phy-fsl-lynx-28g.c | 90 +++++++++++++++++++++++-
>  1 file changed, 88 insertions(+), 2 deletions(-)
> +static int lynx_28g_e25g_pcvt(int lane)
> +{
> +	return 7 - lane;
> +}
> +
>  static int lynx_28g_get_pccr(enum lynx_lane_mode lane_mode, int lane,
>  			     struct lynx_pccr *pccr)
>  {
> @@ -776,6 +840,11 @@ static int lynx_28g_get_pccr(enum lynx_lane_mode lane_mode, int lane,
>  		pccr->width = 4;
>  		pccr->shift = SXGMII_CFG(lane);
>  		break;
> +	case LANE_MODE_25GBASER:
> +		pccr->offset = PCCD;
> +		pccr->width = 4;
> +		pccr->shift = E25G_CFG(lynx_28g_e25g_pcvt(lane));
> +		break;
>  	default:
>  		return -EOPNOTSUPP;
>  	}
Wouldn't it be more clear instead of indirect lane offset shift with
lynx_28g_e25g_pcvt, to instead fix the E25G_CFG definition?:

-#define E25G_CFG(id) (28 - (id) * 4) /* Offset into PCCD */
+#define E25G_CFG(id) ((id) * 4)      /* Offset into PCCD */

This is equivalent when inserting (7 - lane) into E25G_CFG id:

(28 - (id) * 4) = (28 - (7 - lane) * 4) = (28 - 7*4 + lane*4)
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* Re: [PATCH phy-next 5/5] phy: lynx-28g: add support for 25GBASER
From: Vladimir Oltean @ 2026-05-13 11:22 UTC (permalink / raw)
  To: Josua Mayer
  Cc: linux-phy@lists.infradead.org, netdev@vger.kernel.org,
	Ioana Ciornei, Vinod Koul, Neil Armstrong,
	linux-kernel@vger.kernel.org
In-Reply-To: <375dddbc-385c-4dcb-a280-33292215ae67@solid-run.com>

On Wed, May 13, 2026 at 11:00:32AM +0000, Josua Mayer wrote:
> Wouldn't it be more clear instead of indirect lane offset shift with
> lynx_28g_e25g_pcvt, to instead fix the E25G_CFG definition?:
> 
> -#define E25G_CFG(id) (28 - (id) * 4) /* Offset into PCCD */
> +#define E25G_CFG(id) ((id) * 4)      /* Offset into PCCD */
> 
> This is equivalent when inserting (7 - lane) into E25G_CFG id:
> 
> (28 - (id) * 4) = (28 - (7 - lane) * 4) = (28 - 7*4 + lane*4)

The 'indirect' lane offset shift is actually a two-step lookup:
lane -> protocol converter index
protocol converted index -> offset into PCCD

LX2160ARM documents PCCD fields as:
E25GA_CFG, aka E25G_CFG(0) in code: 30:28
E25GB_CFG, aka E25G_CFG(1) in code: 26:24
...
E25GH_CFG, aka E25G_CFG(7) in code: 2:0

The odd bit is that lane 0 uses E25G protocol converter 7, unlike, say,
1G and 10G where we have a lane:pcvt identity mapping.
lynx_28g_e25g_pcvt() performs that translation.

Additionally, for locating E40GA_CFG, E40GB_CFG in PCCE, I've adopted
the same scheme downstream, where E40G_CFG() returns bits 30:28 for
argument 0 (pcvt A) and bits 26:24 for argument 1 (pcvt B), and it is
called with this lane->pcvt translation function:

static int lynx_28g_e40g_pcvt(int lane)
{
	return lane < 4 ? 1 : 0;
}

Are you saying that merging the two lookups would be more clear because
as a reader you'd get to ask yourself less questions (the code would
flow more naturally) despite the non-trivial lane<->pcvt mapping, or why
exactly? For me it is the exact opposite. I can follow the RM
definitions and then I have a separate function that tells me how lanes
are mapped to the protocol converters.

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* Re: [PATCH phy-next 5/5] phy: lynx-28g: add support for 25GBASER
From: Josua Mayer @ 2026-05-13 11:37 UTC (permalink / raw)
  To: Vladimir Oltean, linux-phy@lists.infradead.org
  Cc: netdev@vger.kernel.org, Ioana Ciornei, Vinod Koul, Neil Armstrong,
	linux-kernel@vger.kernel.org, Rabeeh Khoury, Yazan Shhady
In-Reply-To: <20260511150023.1903577-6-vladimir.oltean@nxp.com>

Am 11.05.26 um 17:00 schrieb Vladimir Oltean:
> From: Ioana Ciornei <ioana.ciornei@nxp.com>
>
> Add support for 25GBASE-R in the Lynx 28G SerDes PHY driver. This will
> be used by the dpaa2-mac consumer on LX2160A with:
> - phy_validate(phy, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_25GBASER) to
>   detect support.
> - phy_set_mode_ext(phy, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_25GBASER)
>   to reconfigure the lane for this protocol.
>
> The intended use case for dynamic protocol switching to 25GBase-R is
> with SFP28 modules, and protocol switching is triggered by the SFP
> module insertion. There also exists a 25GBase-KR use case, where the
> protocol switching is covered by IEEE 802.3 clause 73 auto-negotiation.
> However, that is not handled here; it merely needs the support added
> here as basic ground work.
>
> The lane frequency for 25GbE is sourced from a clock net frequency of
> 12.890625 GHz, as produced by PLLF or PLLS, further multiplied by the
> lane by 2. The clock net frequencies produced by the PLLs are treated as
> read-only by the driver, so the absence of a PLL provisioned for the
> right clock net frequency implies absence of 25GbE support, even though
> a lane might have the appropriate protocol converter for it.
>
> In terms of implementation, the change consists of:
> - determining at probe time if any PLL was preconfigured for the
>   required clock net frequency for 25GbE
> - adding the default lane parameters for reconfiguring a lane to 25GbE
>   irrespective of the original protocol
> - allowing this operating mode only on supported lanes, i.e. all lanes
>   of LX2162A SerDes #1, and LX2160A SerDes lanes 0-1, 4-7.
>
> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> ---
> Change previously submitted at:
> https://lore.kernel.org/linux-phy/20260114152111.625350-6-vladimir.oltean@nxp.com/
>
> Changes:
> - reword commit message
> ---
>  drivers/phy/freescale/phy-fsl-lynx-28g.c | 90 +++++++++++++++++++++++-
>  1 file changed, 88 insertions(+), 2 deletions(-)

In order to test this patch with 25Gbps link, additional changes on other drivers are needed.
This is not a short-coming of this patch.

1. I tested this patch-set alone on LX2162 Clearfog with SD1 Protocl 18 (i.e. 2x 10G SFP, 2x 25G SFP):

10Gbps ports are working fine!

25Gbps fail to probe (but this is partly expected):

[    8.373048] fsl_dpaa2_eth dpni.9 (unnamed net_device) (uninitialized): MAC returned PCS which does not support 25gbase-r
[    8.373065] fsl_dpaa2_eth dpni.9 (unnamed net_device) (uninitialized): MAC returned PCS which does not support 25gbase-r
[    8.373074] fsl_dpaa2_eth dpni.9 (unnamed net_device) (uninitialized): failed to validate link configuration for in-band status
[    8.373078] fsl_dpaa2_eth dpni.9 (unnamed net_device) (uninitialized): Error connecting to the MAC endpoint: -EINVAL
[    8.725004] fsl_dpaa2_eth dpni.9: probe with driver fsl_dpaa2_eth failed with error -22
[    8.920766] fsl_dpaa2_eth dpni.8 (unnamed net_device) (uninitialized): MAC returned PCS which does not support 25gbase-r
[    8.920783] fsl_dpaa2_eth dpni.8 (unnamed net_device) (uninitialized): MAC returned PCS which does not support 25gbase-r
[    8.920791] fsl_dpaa2_eth dpni.8 (unnamed net_device) (uninitialized): failed to validate link configuration for in-band status
[    8.920795] fsl_dpaa2_eth dpni.8 (unnamed net_device) (uninitialized): Error connecting to the MAC endpoint: -EINVAL
[    9.290005] fsl_dpaa2_eth dpni.8: probe with driver fsl_dpaa2_eth failed with error -22

Perhaps driver could switch to 10G instead? However not important in my opinion.

2. Tested with additional out of tree patches:

net: phylink: extend phylink_mii_c45_pcs_get_state also for PHY_INTERFACE_MODE_25GBASER
net: pcs: lynx: extend support to also handle PHY_INTERFACE_MODE_25GBASER

Then insert 10Gbps SFP module and link-up + TX/RX working fine!
I.e. driver switched successfully from 25Gbps configuration to 10Gbps.

Then insert 25Gbps SFP module. Errors start occuring:

[  357.043894] fsl_dpaa2_eth dpni.9 eth2: Link is Down
[  357.941036] sfp sfp-bt: module removed
[  364.269580] sfp sfp-bt: module FS               SFP-25GSL-85     rev 1A   sn C2501330127      dc 250203  
[  364.269625] fsl_dpaa2_eth dpni.9 eth2: switched to inband/25gbase-r link mode
[  364.271674] fsl_dpaa2_eth dpni.9 eth2: phy_set_mode_ext() = -95
[  364.293232] hwmon hwmon8: temp1_input not attached to any thermal zone

The link starts flapping, which is likely due to a combination of:

1. the lane has been halted but not stopped
2. the lane is still configured for 10G speed
3. the retimer (not supported by kernel) is still configured for 10G speed

[  364.333777] fsl_dpaa2_eth dpni.9 eth2: Link is Up - 25Gbps/Full - flow control off
[  365.280234] fsl_dpaa2_eth dpni.9 eth2: Link is Down
[  365.287750] fsl_dpaa2_eth dpni.9 eth2: Link is Up - 25Gbps/Full - flow control off
[  366.304434] fsl_dpaa2_eth dpni.9 eth2: Link is Down
[  366.311868] fsl_dpaa2_eth dpni.9 eth2: Link is Up - 25Gbps/Full - flow control off
[  367.328306] fsl_dpaa2_eth dpni.9 eth2: Link is Down
...

So I reconfigure the retimer by i2cset for 25Gbps speed, and link goes down permanently.

root@localhost:~# ethtool eth2
Settings for eth2:
        Supported ports: [ FIBRE ]
        Supported link modes:   25000baseSR/Full
        Supported pause frame use: Symmetric Receive-only
        Supports auto-negotiation: No
        Supported FEC modes: Not reported
        Advertised link modes:  Not reported
        Advertised pause frame use: No
        Advertised auto-negotiation: No
        Advertised FEC modes: Not reported
        Speed: Unknown!
        Duplex: Half
        Auto-negotiation: off
        Port: FIBRE
        PHYAD: 0
        Transceiver: internal
        Link detected: no

I would give this a partial tested-by, considering it switched successfully to 10G,
but failed switching to 25G, which is new with this patch. and needs extra patches.
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* Re: [PATCH phy-next 5/5] phy: lynx-28g: add support for 25GBASER
From: Josua Mayer @ 2026-05-13 11:41 UTC (permalink / raw)
  To: Vladimir Oltean
  Cc: linux-phy@lists.infradead.org, netdev@vger.kernel.org,
	Ioana Ciornei, Vinod Koul, Neil Armstrong,
	linux-kernel@vger.kernel.org
In-Reply-To: <20260513112222.2szwvxptk2udv7ga@skbuf>

Am 13.05.26 um 13:22 schrieb Vladimir Oltean:

> On Wed, May 13, 2026 at 11:00:32AM +0000, Josua Mayer wrote:
>> Wouldn't it be more clear instead of indirect lane offset shift with
>> lynx_28g_e25g_pcvt, to instead fix the E25G_CFG definition?:
>>
>> -#define E25G_CFG(id) (28 - (id) * 4) /* Offset into PCCD */
>> +#define E25G_CFG(id) ((id) * 4)      /* Offset into PCCD */
>>
>> This is equivalent when inserting (7 - lane) into E25G_CFG id:
>>
>> (28 - (id) * 4) = (28 - (7 - lane) * 4) = (28 - 7*4 + lane*4)
> The 'indirect' lane offset shift is actually a two-step lookup:
> lane -> protocol converter index
> protocol converted index -> offset into PCCD
>
> LX2160ARM documents PCCD fields as:
> E25GA_CFG, aka E25G_CFG(0) in code: 30:28
> E25GB_CFG, aka E25G_CFG(1) in code: 26:24
> ...
> E25GH_CFG, aka E25G_CFG(7) in code: 2:0
>
> The odd bit is that lane 0 uses E25G protocol converter 7, unlike, say,
> 1G and 10G where we have a lane:pcvt identity mapping.
> lynx_28g_e25g_pcvt() performs that translation.
>
> Additionally, for locating E40GA_CFG, E40GB_CFG in PCCE, I've adopted
> the same scheme downstream, where E40G_CFG() returns bits 30:28 for
> argument 0 (pcvt A) and bits 26:24 for argument 1 (pcvt B), and it is
> called with this lane->pcvt translation function:
>
> static int lynx_28g_e40g_pcvt(int lane)
> {
> 	return lane < 4 ? 1 : 0;
> }
>
> Are you saying that merging the two lookups would be more clear because
> as a reader you'd get to ask yourself less questions (the code would
> flow more naturally) despite the non-trivial lane<->pcvt mapping,
Exactly for this reason. Fewer look-up steps.
RM dos not document this mapping, but now you do in source-code.

Perhaps a short comment on the function will help, e.g.
/* get protocol converter id for lane */

> or why
> exactly? For me it is the exact opposite. I can follow the RM
> definitions and then I have a separate function that tells me how lanes
> are mapped to the protocol converters.
I think you give a good reason here!
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^ permalink raw reply

* Re: [PATCH phy-next 5/5] phy: lynx-28g: add support for 25GBASER
From: Josua Mayer @ 2026-05-13 11:44 UTC (permalink / raw)
  To: Vladimir Oltean, linux-phy@lists.infradead.org
  Cc: netdev@vger.kernel.org, Ioana Ciornei, Vinod Koul, Neil Armstrong,
	linux-kernel@vger.kernel.org, Rabeeh Khoury, Yazan Shhady
In-Reply-To: <1ba1f688-9f68-4749-a18f-20ae91738ae0@solid-run.com>


Am 13.05.26 um 13:37 schrieb Josua Mayer:
> Am 11.05.26 um 17:00 schrieb Vladimir Oltean:
>> From: Ioana Ciornei <ioana.ciornei@nxp.com>
>>
>> Add support for 25GBASE-R in the Lynx 28G SerDes PHY driver. This will
>> be used by the dpaa2-mac consumer on LX2160A with:
>> - phy_validate(phy, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_25GBASER) to
>>   detect support.
>> - phy_set_mode_ext(phy, PHY_MODE_ETHERNET, PHY_INTERFACE_MODE_25GBASER)
>>   to reconfigure the lane for this protocol.
>>
>> The intended use case for dynamic protocol switching to 25GBase-R is
>> with SFP28 modules, and protocol switching is triggered by the SFP
>> module insertion. There also exists a 25GBase-KR use case, where the
>> protocol switching is covered by IEEE 802.3 clause 73 auto-negotiation.
>> However, that is not handled here; it merely needs the support added
>> here as basic ground work.
>>
>> The lane frequency for 25GbE is sourced from a clock net frequency of
>> 12.890625 GHz, as produced by PLLF or PLLS, further multiplied by the
>> lane by 2. The clock net frequencies produced by the PLLs are treated as
>> read-only by the driver, so the absence of a PLL provisioned for the
>> right clock net frequency implies absence of 25GbE support, even though
>> a lane might have the appropriate protocol converter for it.
>>
>> In terms of implementation, the change consists of:
>> - determining at probe time if any PLL was preconfigured for the
>>   required clock net frequency for 25GbE
>> - adding the default lane parameters for reconfiguring a lane to 25GbE
>>   irrespective of the original protocol
>> - allowing this operating mode only on supported lanes, i.e. all lanes
>>   of LX2162A SerDes #1, and LX2160A SerDes lanes 0-1, 4-7.
>>
>> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
>> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
>> ---
>> Change previously submitted at:
>> https://lore.kernel.org/linux-phy/20260114152111.625350-6-vladimir.oltean@nxp.com/
>>
>> Changes:
>> - reword commit message
>> ---
>>  drivers/phy/freescale/phy-fsl-lynx-28g.c | 90 +++++++++++++++++++++++-
>>  1 file changed, 88 insertions(+), 2 deletions(-)
> In order to test this patch with 25Gbps link, additional changes on other drivers are needed.
> This is not a short-coming of this patch.
>
> 1. I tested this patch-set alone on LX2162 Clearfog with SD1 Protocl 18 (i.e. 2x 10G SFP, 2x 25G SFP):
>
> 10Gbps ports are working fine!
>
> 25Gbps fail to probe (but this is partly expected):
>
> [    8.373048] fsl_dpaa2_eth dpni.9 (unnamed net_device) (uninitialized): MAC returned PCS which does not support 25gbase-r
> [    8.373065] fsl_dpaa2_eth dpni.9 (unnamed net_device) (uninitialized): MAC returned PCS which does not support 25gbase-r
> [    8.373074] fsl_dpaa2_eth dpni.9 (unnamed net_device) (uninitialized): failed to validate link configuration for in-band status
> [    8.373078] fsl_dpaa2_eth dpni.9 (unnamed net_device) (uninitialized): Error connecting to the MAC endpoint: -EINVAL
> [    8.725004] fsl_dpaa2_eth dpni.9: probe with driver fsl_dpaa2_eth failed with error -22
> [    8.920766] fsl_dpaa2_eth dpni.8 (unnamed net_device) (uninitialized): MAC returned PCS which does not support 25gbase-r
> [    8.920783] fsl_dpaa2_eth dpni.8 (unnamed net_device) (uninitialized): MAC returned PCS which does not support 25gbase-r
> [    8.920791] fsl_dpaa2_eth dpni.8 (unnamed net_device) (uninitialized): failed to validate link configuration for in-band status
> [    8.920795] fsl_dpaa2_eth dpni.8 (unnamed net_device) (uninitialized): Error connecting to the MAC endpoint: -EINVAL
> [    9.290005] fsl_dpaa2_eth dpni.8: probe with driver fsl_dpaa2_eth failed with error -22
>
> Perhaps driver could switch to 10G instead? However not important in my opinion.
>
> 2. Tested with additional out of tree patches:
>
> net: phylink: extend phylink_mii_c45_pcs_get_state also for PHY_INTERFACE_MODE_25GBASER
> net: pcs: lynx: extend support to also handle PHY_INTERFACE_MODE_25GBASER
>
> Then insert 10Gbps SFP module and link-up + TX/RX working fine!
> I.e. driver switched successfully from 25Gbps configuration to 10Gbps.
>
> Then insert 25Gbps SFP module. Errors start occuring:
>
> [  357.043894] fsl_dpaa2_eth dpni.9 eth2: Link is Down
> [  357.941036] sfp sfp-bt: module removed
> [  364.269580] sfp sfp-bt: module FS               SFP-25GSL-85     rev 1A   sn C2501330127      dc 250203  
> [  364.269625] fsl_dpaa2_eth dpni.9 eth2: switched to inband/25gbase-r link mode
> [  364.271674] fsl_dpaa2_eth dpni.9 eth2: phy_set_mode_ext() = -95
> [  364.293232] hwmon hwmon8: temp1_input not attached to any thermal zone
>
> The link starts flapping, which is likely due to a combination of:
>
> 1. the lane has been halted but not stopped
> 2. the lane is still configured for 10G speed
> 3. the retimer (not supported by kernel) is still configured for 10G speed
>
> [  364.333777] fsl_dpaa2_eth dpni.9 eth2: Link is Up - 25Gbps/Full - flow control off
> [  365.280234] fsl_dpaa2_eth dpni.9 eth2: Link is Down
> [  365.287750] fsl_dpaa2_eth dpni.9 eth2: Link is Up - 25Gbps/Full - flow control off
> [  366.304434] fsl_dpaa2_eth dpni.9 eth2: Link is Down
> [  366.311868] fsl_dpaa2_eth dpni.9 eth2: Link is Up - 25Gbps/Full - flow control off
> [  367.328306] fsl_dpaa2_eth dpni.9 eth2: Link is Down
> ...
>
> So I reconfigure the retimer by i2cset for 25Gbps speed, and link goes down permanently.
>
> root@localhost:~# ethtool eth2
> Settings for eth2:
>         Supported ports: [ FIBRE ]
>         Supported link modes:   25000baseSR/Full
>         Supported pause frame use: Symmetric Receive-only
>         Supports auto-negotiation: No
>         Supported FEC modes: Not reported
>         Advertised link modes:  Not reported
>         Advertised pause frame use: No
>         Advertised auto-negotiation: No
>         Advertised FEC modes: Not reported
>         Speed: Unknown!
>         Duplex: Half
>         Auto-negotiation: off
>         Port: FIBRE
>         PHYAD: 0
>         Transceiver: internal
>         Link detected: no
>
> I would give this a partial tested-by, considering it switched successfully to 10G,
> but failed switching to 25G, which is new with this patch. and needs extra patches.

I should clarify testing was done on v7.1-rc2, plus:

https://lore.kernel.org/r/0-v1-44b2fef88b25+d3-iommupt_map_rc_jgg@nvidia.com
https://lore.kernel.org/r/20260226182853.1103616-1-vladimir.oltean@nxp.com
https://lore.kernel.org/r/20260321011451.1557091-1-vladimir.oltean@nxp.com
https://lore.kernel.org/r/20260511150023.1903577-1-vladimir.oltean@nxp.com

I may have missed something important.
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^ permalink raw reply

* Re: [PATCH 3/4] arm64: dts: qcom: Add Shikra CQM SoM platform
From: Dmitry Baryshkov @ 2026-05-13 12:01 UTC (permalink / raw)
  To: sashiko-reviews
  Cc: Komal Bajaj, robh, linux-phy, neil.armstrong, vkoul, olteanv,
	krzk+dt, conor+dt, devicetree
In-Reply-To: <20260513042836.073F9C2BCB7@smtp.kernel.org>

On Wed, May 13, 2026 at 04:28:35AM +0000, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
> - [High] The PMIC regulator definitions omit their required input supply dependencies (e.g., `vdd_s2-supply`, `vdd_l3-supply`), breaking the power hierarchy.
> - [Medium] The device tree inaccurately hardcodes the `compatible` string to a different PMIC model (`qcom,rpm-pm2250-regulators`) instead of explicitly identifying the actual hardware (PM4125).
> --
> 
> commit 457abf6e7ac410430c866842e08e602ec3daaa51
> Author: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
> 
> arm64: dts: qcom: Add Shikra CQM SoM platform
> 
> Add device tree include for the CQM variant of the Shikra System-on-Module.
> This variant integrates the Shikra SoC and PM4125 PMIC. The DTSI includes
> the common shikra.dtsi and adds PM4125 PMIC regulator definitions.
> 
> > diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi
> > new file mode 100644
> > index 0000000000000..401e71720519d
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi
> [ ... ]
> > +&rpm_requests {
> > +	regulators {
> > +		compatible = "qcom,rpm-pm2250-regulators";
> 
> Since the commit message indicates this is a PM4125 PMIC, should the
> compatible string include a specific identifier for the actual hardware?
> 
> Using a specific identifier like "qcom,rpm-pm4125-regulators" alongside
> the fallback allows the kernel to apply specific quirks if PM4125 errata
> are discovered later.

This can be ignored. The compat is a leftover from the historically
incorrect naming.

> 
> > +
> > +		pm4125_s2: s2 {
> > +			regulator-min-microvolt = <1000000>;
> > +			regulator-max-microvolt = <1200000>;
> > +		};
> 
> Do these regulators need to explicitly define their input supply dependencies
> such as vdd_s2-supply?
> 
> Without these properties, the regulator framework might be unaware that the
> PMIC regulators draw power from upstream supplies.
> 
> If the kernel dynamically manages the upstream supply and its reference count
> drops to zero, could it be disabled, causing an unexpected power loss for
> downstream components?

And this is a correct comment. Please provide missing supplies.

> 
> [ ... ]
> 
> -- 
> Sashiko AI review · https://sashiko.dev/#/patchset/20260512-shikra-dt-v1-0-716438330dd0@oss.qualcomm.com?part=3

-- 
With best wishes
Dmitry

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^ permalink raw reply

* Re: [PATCH 4/4] arm64: dts: qcom: Add Shikra CQM and CQS EVK boards
From: Dmitry Baryshkov @ 2026-05-13 12:04 UTC (permalink / raw)
  To: Komal Bajaj
  Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
	Conor Dooley, Vinod Koul, Neil Armstrong, Wesley Cheng,
	Ulf Hansson, linux-arm-msm, devicetree, linux-kernel, linux-phy,
	linux-mmc, Imran Shaik, Krishna Kurapati, Monish Chunara,
	Rakesh Kota, Raviteja Laggyshetty, Sneh Mankad, Vishnu Santhosh,
	Xueyao An
In-Reply-To: <20260512-shikra-dt-v1-4-716438330dd0@oss.qualcomm.com>

On Tue, May 12, 2026 at 09:38:07AM +0530, Komal Bajaj wrote:
> Add device trees for the Shikra EVK platform, which combines the CQM
> SoM variant with a common carrier board.
> 
> Two EVK boards are introduced:
>   - shikra-cqm-evk.dts: pairs with CQM SoM (retail, with modem)
>   - shikra-cqs-evk.dts: pairs with CQM SoM (retail, board has no modem

CQS

>     support)
> 
> Also add shikra-evk.dtsi common across both EVK boards.

What is the split between shikra-cq[ms]-evk.dts and shikra-evk.dtsi?

> 
> Each board DTS enables USB (peripheral mode) with the appropriate PMIC
> regulator supplies for the QUSB2 and QMP PHYs, and eMMC with the
> correct vmmc/vqmmc supplies for the CQM SoM's PMIC.
> 
> Co-developed-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
> Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
> Co-developed-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
> Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
> Co-developed-by: Monish Chunara <quic_mchunara@quicinc.com>
> Signed-off-by: Monish Chunara <quic_mchunara@quicinc.com>
> Co-developed-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com>
> Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com>
> Co-developed-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
> Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
> Co-developed-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com>
> Signed-off-by: Sneh Mankad <sneh.mankad@oss.qualcomm.com>
> Co-developed-by: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com>
> Signed-off-by: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com>
> Co-developed-by: Xueyao An <xueyao.an@oss.qualcomm.com>
> Signed-off-by: Xueyao An <xueyao.an@oss.qualcomm.com>
> Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
> ---
>  arch/arm64/boot/dts/qcom/Makefile           |  2 +
>  arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 61 +++++++++++++++++++++++++++++
>  arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 61 +++++++++++++++++++++++++++++
>  arch/arm64/boot/dts/qcom/shikra-evk.dtsi    | 13 ++++++
>  4 files changed, 137 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index cc42829f92eb..6de783bcd133 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -328,6 +328,8 @@ dtb-$(CONFIG_ARCH_QCOM)	+= sdm850-huawei-matebook-e-2019.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= sdm850-lenovo-yoga-c630.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= sdm850-samsung-w737.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= sdx75-idp.dtb
> +dtb-$(CONFIG_ARCH_QCOM)	+= shikra-cqm-evk.dtb
> +dtb-$(CONFIG_ARCH_QCOM)	+= shikra-cqs-evk.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= sm4250-oneplus-billie2.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= sm4450-qrd.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= sm6115-fxtec-pro1x.dtb
> diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
> new file mode 100644
> index 000000000000..12eeca84832c
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
> @@ -0,0 +1,61 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +
> +/dts-v1/;
> +
> +#include "shikra-cqm-som.dtsi"
> +#include "shikra-evk.dtsi"
> +
> +/ {
> +	model = "Qualcomm Technologies, Inc. Shikra CQM EVK";
> +	compatible = "qcom,shikra-cqm-evk", "qcom,shikra-cqm-som", "qcom,shikra";
> +	chassis-type = "embedded";
> +
> +	aliases {
> +		mmc0 = &sdhc_1;
> +		serial0 = &uart0;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +};
> +
> +&sdhc_1 {
> +	vmmc-supply = <&pm4125_l20>;
> +	vqmmc-supply = <&pm4125_l14>;
> +
> +	pinctrl-0 = <&sdc1_state_on>;
> +	pinctrl-1 = <&sdc1_state_off>;
> +	pinctrl-names = "default", "sleep";
> +
> +	non-removable;
> +	supports-cqe;
> +	no-sdio;
> +	no-sd;
> +
> +	status = "okay";
> +};
> +
> +&usb_1 {
> +	dr_mode = "peripheral";
> +
> +	status = "okay";
> +};
> +
> +&usb_1_hsphy {
> +	vdd-supply = <&pm4125_l12>;
> +	vdda-pll-supply = <&pm4125_l13>;
> +	vdda-phy-dpdm-supply = <&pm4125_l21>;
> +
> +	status = "okay";
> +};
> +
> +&usb_qmpphy {
> +	vdda-phy-supply = <&pm4125_l8>;
> +	vdda-pll-supply = <&pm4125_l13>;
> +
> +	status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
> new file mode 100644
> index 000000000000..bc93282f64cf
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
> @@ -0,0 +1,61 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +
> +/dts-v1/;
> +
> +#include "shikra-cqm-som.dtsi"
> +#include "shikra-evk.dtsi"
> +
> +/ {
> +	model = "Qualcomm Technologies, Inc. Shikra CQS EVK";
> +	compatible = "qcom,shikra-cqs-evk", "qcom,shikra-cqm-som", "qcom,shikra";
> +	chassis-type = "embedded";
> +
> +	aliases {
> +		mmc0 = &sdhc_1;
> +		serial0 = &uart0;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +};
> +
> +&sdhc_1 {
> +	vmmc-supply = <&pm4125_l20>;
> +	vqmmc-supply = <&pm4125_l14>;
> +
> +	pinctrl-0 = <&sdc1_state_on>;
> +	pinctrl-1 = <&sdc1_state_off>;
> +	pinctrl-names = "default", "sleep";
> +
> +	non-removable;
> +	supports-cqe;
> +	no-sdio;
> +	no-sd;
> +
> +	status = "okay";
> +};
> +
> +&usb_1 {
> +	dr_mode = "peripheral";
> +
> +	status = "okay";
> +};
> +
> +&usb_1_hsphy {
> +	vdd-supply = <&pm4125_l12>;
> +	vdda-pll-supply = <&pm4125_l13>;
> +	vdda-phy-dpdm-supply = <&pm4125_l21>;
> +
> +	status = "okay";
> +};
> +
> +&usb_qmpphy {
> +	vdda-phy-supply = <&pm4125_l8>;
> +	vdda-pll-supply = <&pm4125_l13>;
> +
> +	status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/qcom/shikra-evk.dtsi b/arch/arm64/boot/dts/qcom/shikra-evk.dtsi
> new file mode 100644
> index 000000000000..fae8c75b68b3
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/shikra-evk.dtsi
> @@ -0,0 +1,13 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +
> +&qupv3_0 {
> +	firmware-name = "qcom/shikra/qupv3fw.elf";
> +	status = "okay";
> +};
> +
> +&uart0 {
> +	status = "okay";
> +};
> 
> -- 
> 2.34.1
> 

-- 
With best wishes
Dmitry

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* [PATCH v5 0/2] phy: add basic support for NXPs TJA1145 CAN transceiver
From: Dimitri Fedrau via B4 Relay @ 2026-05-13 13:12 UTC (permalink / raw)
  To: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
	Krzysztof Kozlowski, Conor Dooley, Neil Armstrong
  Cc: linux-phy, devicetree, linux-kernel, Dimitri Fedrau,
	Dimitri Fedrau, Conor Dooley, lee.lockhey, Marc Kleine-Budde

Add basic driver support for NXPs TJA1145 CAN transceiver which brings the
PHY up/down by switching to normal/standby mode using SPI commands.

Signed-off-by: Dimitri Fedrau <dimitri.fedrau@liebherr.com>
---
Changes in v5:
- No functional change, basically a resend with added tags
- fixed typo in define TJA1145_MODE_CRTL_STBY to TJA1145_MODE_CTRL_STBY
  and TJA1145_MODE_CRTL_NORMAL to TJA1145_MODE_CTRL_NORMAL
- remove unneeded include -#include <linux/bitfield.h>
- added owner to tja1145_phy_ops
- Link to v4: https://lore.kernel.org/r/20251015-tja1145-support-v4-0-4d3ca13c8881@liebherr.com

Changes in v4:
- Change compatible to: nxp,tja1145 (Connor)
- Mark spi-cpha as required (Connor)
- Switch from unevaluatedProperties: false to
  additionalProperties: false (Connor)
- Remove double newline after tja1145_rd_table (Marc)
- Link to v3: https://lore.kernel.org/r/20251013-tja1145-support-v3-0-4a9d245fe067@liebherr.com

Changes in v3:
- bindings: fix SPI bus unit address format error
- bindings: added resolution of discussion into commit msg
- Checked binding with:
  make dt_binding_check DT_SCHEMA_FILES=nxp,tja1145-can.yaml
  Missed it for V2, didn't do it intentionally. Sorry.
- Link to v2: https://lore.kernel.org/r/20250829-tja1145-support-v2-0-60997f328979@liebherr.com

Changes in v2:
- bindings: Change node name in example to can-phy
- bindings: Fix order of properties, reg property is second
- bindings: Change compatible to match filename
- change compatible to nxp,tja1145-can
- Link to v1: https://lore.kernel.org/r/20250728-tja1145-support-v1-0-ebd8494d545c@liebherr.com

---
Dimitri Fedrau (2):
      dt-bindings: phy: add support for NXPs TJA1145 CAN transceiver
      phy: add basic support for NXPs TJA1145 CAN transceiver

 .../devicetree/bindings/phy/nxp,tja1145.yaml       |  80 +++++++++
 drivers/phy/Kconfig                                |  10 ++
 drivers/phy/Makefile                               |   1 +
 drivers/phy/phy-nxp-tja1145.c                      | 184 +++++++++++++++++++++
 4 files changed, 275 insertions(+)
---
base-commit: 29b4d8a7637f027b538787896bee520f2dacc904
change-id: 20250726-tja1145-support-d6ccdc4d2da3

Best regards,
-- 
Dimitri Fedrau <dimitri.fedrau@liebherr.com>



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* [PATCH v5 2/2] phy: add basic support for NXPs TJA1145 CAN transceiver
From: Dimitri Fedrau via B4 Relay @ 2026-05-13 13:12 UTC (permalink / raw)
  To: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
	Krzysztof Kozlowski, Conor Dooley, Neil Armstrong
  Cc: linux-phy, devicetree, linux-kernel, Dimitri Fedrau,
	Dimitri Fedrau, lee.lockhey, Marc Kleine-Budde
In-Reply-To: <20260513-tja1145-support-v5-0-38720a7ee63e@liebherr.com>

From: Dimitri Fedrau <dimitri.fedrau@liebherr.com>

Add basic driver support for NXPs TJA1145 CAN transceiver which brings the
PHY up/down by switching to normal/standby mode using SPI commands.

Tested-by: <lee.lockhey@gmail.com>
Reviewed-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Dimitri Fedrau <dimitri.fedrau@liebherr.com>
---
 drivers/phy/Kconfig           |  10 +++
 drivers/phy/Makefile          |   1 +
 drivers/phy/phy-nxp-tja1145.c | 184 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 195 insertions(+)

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index ab96ee5858c1a9dee2aea3a896c09b397cc30c7f..a3f9a05e222002e23d5080aa22b56f2a822a4b97 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -124,6 +124,16 @@ config PHY_NXP_PTN3222
 	  schemes. It supports all three USB 2.0 data rates: Low Speed, Full
 	  Speed and High Speed.
 
+config PHY_NXP_TJA1145
+	tristate "NXP TJA1145 CAN transceiver PHY"
+	select GENERIC_PHY
+	select REGMAP_SPI
+	depends on SPI
+	help
+	  This option enables support for NXPs TJA1145 CAN transceiver as a PHY.
+	  This driver provides function for putting the transceiver in various
+	  functional modes using SPI commands.
+
 config PHY_PISTACHIO_USB
 	tristate "IMG Pistachio USB2.0 PHY driver"
 	depends on MIPS || COMPILE_TEST
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index f31767745123773757e84b0b5fb85ec286c1d977..65ea9f0bc7f151378caa6e161f8b8a5c6884d7e5 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_PHY_GOOGLE_USB)		+= phy-google-usb.o
 obj-$(CONFIG_USB_LGM_PHY)		+= phy-lgm-usb.o
 obj-$(CONFIG_PHY_LPC18XX_USB_OTG)	+= phy-lpc18xx-usb-otg.o
 obj-$(CONFIG_PHY_NXP_PTN3222)		+= phy-nxp-ptn3222.o
+obj-$(CONFIG_PHY_NXP_TJA1145)		+= phy-nxp-tja1145.o
 obj-$(CONFIG_PHY_PISTACHIO_USB)		+= phy-pistachio-usb.o
 obj-$(CONFIG_PHY_SNPS_EUSB2)		+= phy-snps-eusb2.o
 obj-$(CONFIG_PHY_XGENE)			+= phy-xgene.o
diff --git a/drivers/phy/phy-nxp-tja1145.c b/drivers/phy/phy-nxp-tja1145.c
new file mode 100644
index 0000000000000000000000000000000000000000..1e8bd169743abfaeee6948d200e6ac320cd616ff
--- /dev/null
+++ b/drivers/phy/phy-nxp-tja1145.c
@@ -0,0 +1,184 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025 Liebherr-Electronics and Drives GmbH
+ */
+#include <linux/module.h>
+#include <linux/regmap.h>
+
+#include <linux/phy/phy.h>
+#include <linux/spi/spi.h>
+
+#define TJA1145_MODE_CTRL		0x01
+#define TJA1145_MODE_CTRL_MC		GENMASK(2, 0)
+#define TJA1145_MODE_CTRL_STBY		BIT(2)
+#define TJA1145_MODE_CTRL_NORMAL	TJA1145_MODE_CTRL_MC
+
+#define TJA1145_CAN_CTRL		0x20
+#define TJA1145_CAN_CTRL_CMC		GENMASK(1, 0)
+#define TJA1145_CAN_CTRL_ACTIVE		BIT(1)
+
+#define TJA1145_IDENT			0x7e
+#define TJA1145_IDENT_TJA1145T		0x70
+
+#define TJA1145_SPI_READ_BIT		BIT(0)
+#define TJA1145T_MAX_BITRATE		1000000
+
+static int tja1145_phy_power_on(struct phy *phy)
+{
+	struct regmap *map = phy_get_drvdata(phy);
+	int ret;
+
+	/*
+	 * Switch operating mode to normal which is the active operating mode.
+	 * In this mode, the device is fully operational.
+	 */
+	ret = regmap_update_bits(map, TJA1145_MODE_CTRL, TJA1145_MODE_CTRL_MC,
+				 TJA1145_MODE_CTRL_NORMAL);
+	if (ret)
+		return ret;
+
+	/*
+	 * Switch to CAN operating mode active where the PHY can transmit and
+	 * receive data.
+	 */
+	return regmap_update_bits(map, TJA1145_CAN_CTRL, TJA1145_CAN_CTRL_CMC,
+				  TJA1145_CAN_CTRL_ACTIVE);
+}
+
+static int tja1145_phy_power_off(struct phy *phy)
+{
+	struct regmap *map = phy_get_drvdata(phy);
+
+	/*
+	 * Switch to operating mode standby, the PHY is unable to transmit or
+	 * receive data in standby mode.
+	 */
+	return regmap_update_bits(map, TJA1145_MODE_CTRL, TJA1145_MODE_CTRL_MC,
+				  TJA1145_MODE_CTRL_STBY);
+}
+
+static const struct phy_ops tja1145_phy_ops = {
+	.power_on = tja1145_phy_power_on,
+	.power_off = tja1145_phy_power_off,
+	.owner = THIS_MODULE,
+};
+
+static const struct regmap_range tja1145_wr_holes_ranges[] = {
+	regmap_reg_range(0x00, 0x00),
+	regmap_reg_range(0x02, 0x03),
+	regmap_reg_range(0x05, 0x05),
+	regmap_reg_range(0x0b, 0x1f),
+	regmap_reg_range(0x21, 0x22),
+	regmap_reg_range(0x24, 0x25),
+	regmap_reg_range(0x30, 0x4b),
+	regmap_reg_range(0x4d, 0x60),
+	regmap_reg_range(0x62, 0x62),
+	regmap_reg_range(0x65, 0x67),
+	regmap_reg_range(0x70, 0xff),
+};
+
+static const struct regmap_access_table tja1145_wr_table = {
+	.no_ranges = tja1145_wr_holes_ranges,
+	.n_no_ranges = ARRAY_SIZE(tja1145_wr_holes_ranges),
+};
+
+static const struct regmap_range tja1145_rd_holes_ranges[] = {
+	regmap_reg_range(0x00, 0x00),
+	regmap_reg_range(0x02, 0x02),
+	regmap_reg_range(0x05, 0x05),
+	regmap_reg_range(0x0b, 0x1f),
+	regmap_reg_range(0x21, 0x21),
+	regmap_reg_range(0x24, 0x25),
+	regmap_reg_range(0x30, 0x4a),
+	regmap_reg_range(0x4d, 0x5f),
+	regmap_reg_range(0x62, 0x62),
+	regmap_reg_range(0x65, 0x67),
+	regmap_reg_range(0x70, 0x7d),
+	regmap_reg_range(0x7f, 0xff),
+};
+
+static const struct regmap_access_table tja1145_rd_table = {
+	.no_ranges = tja1145_rd_holes_ranges,
+	.n_no_ranges = ARRAY_SIZE(tja1145_rd_holes_ranges),
+};
+
+static const struct regmap_config tja1145_regmap_config = {
+	.reg_bits = 8,
+	.reg_shift = -1,
+	.val_bits = 8,
+	.wr_table = &tja1145_wr_table,
+	.rd_table = &tja1145_rd_table,
+	.read_flag_mask = TJA1145_SPI_READ_BIT,
+	.max_register = TJA1145_IDENT,
+};
+
+static int tja1145_check_ident(struct device *dev, struct regmap *map)
+{
+	unsigned int val;
+	int ret;
+
+	ret = regmap_read(map, TJA1145_IDENT, &val);
+	if (ret)
+		return ret;
+
+	if (val != TJA1145_IDENT_TJA1145T) {
+		dev_err(dev, "Expected device id: 0x%02x, got: 0x%02x\n",
+			TJA1145_IDENT_TJA1145T, val);
+		return -ENODEV;
+	}
+
+	return 0;
+}
+
+static int tja1145_probe(struct spi_device *spi)
+{
+	struct phy_provider *phy_provider;
+	struct device *dev = &spi->dev;
+	struct regmap *map;
+	struct phy *phy;
+	int ret;
+
+	map = devm_regmap_init_spi(spi, &tja1145_regmap_config);
+	if (IS_ERR(map))
+		return dev_err_probe(dev, PTR_ERR(map), "failed to init regmap\n");
+
+	ret = tja1145_check_ident(dev, map);
+	if (ret)
+		return dev_err_probe(dev, ret, "failed to identify device\n");
+
+	phy = devm_phy_create(dev, dev->of_node, &tja1145_phy_ops);
+	if (IS_ERR(phy))
+		return dev_err_probe(dev, PTR_ERR(phy), "failed to create PHY\n");
+
+	phy->attrs.max_link_rate = TJA1145T_MAX_BITRATE;
+	phy_set_drvdata(phy, map);
+	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+	return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static const struct spi_device_id tja1145_spi_id[] = {
+	{ "tja1145" },
+	{ }
+};
+MODULE_DEVICE_TABLE(spi, tja1145_spi_id);
+
+static const struct of_device_id tja1145_of_match[] = {
+	{ .compatible = "nxp,tja1145" },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, tja1145_of_match);
+
+static struct spi_driver tja1145_driver = {
+	.driver = {
+		.name = "tja1145",
+		.of_match_table = tja1145_of_match,
+	},
+	.probe = tja1145_probe,
+	.id_table = tja1145_spi_id,
+};
+module_spi_driver(tja1145_driver);
+
+MODULE_DESCRIPTION("NXP TJA1145 CAN transceiver PHY driver");
+MODULE_AUTHOR("Dimitri Fedrau <dimitri.fedrau@liebherr.com>");
+MODULE_LICENSE("GPL");

-- 
2.39.5



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* [PATCH v5 1/2] dt-bindings: phy: add support for NXPs TJA1145 CAN transceiver
From: Dimitri Fedrau via B4 Relay @ 2026-05-13 13:12 UTC (permalink / raw)
  To: Vinod Koul, Kishon Vijay Abraham I, Rob Herring,
	Krzysztof Kozlowski, Conor Dooley, Neil Armstrong
  Cc: linux-phy, devicetree, linux-kernel, Dimitri Fedrau,
	Dimitri Fedrau, Conor Dooley
In-Reply-To: <20260513-tja1145-support-v5-0-38720a7ee63e@liebherr.com>

From: Dimitri Fedrau <dimitri.fedrau@liebherr.com>

Adding documentation for NXPs TJA1145 CAN transceiver, which resides like
the ti,tcan104x-can.yaml in the same directory as other generic PHY
subsystem bindings. At the moment there is only support for simple PHYs
by using regulator bindings in combination with can-transceiver.yaml or
PHYs that implement the generic PHY subsystem like the NXP TJA1145.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Dimitri Fedrau <dimitri.fedrau@liebherr.com>
---
 .../devicetree/bindings/phy/nxp,tja1145.yaml       | 80 ++++++++++++++++++++++
 1 file changed, 80 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/nxp,tja1145.yaml b/Documentation/devicetree/bindings/phy/nxp,tja1145.yaml
new file mode 100644
index 0000000000000000000000000000000000000000..46de6d0f2dd9b9fd41c97eb4c9340e3ac36090a3
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/nxp,tja1145.yaml
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/nxp,tja1145.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TJA1145 CAN transceiver
+
+maintainers:
+  - Dimitri Fedrau <dimitri.fedrau@liebherr.com>
+
+allOf:
+  - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+properties:
+  compatible:
+    const: nxp,tja1145
+
+  reg:
+    maxItems: 1
+
+  "#phy-cells":
+    const: 0
+
+  spi-cpha: true
+
+  spi-max-frequency:
+    maximum: 4000000
+
+  spi-cs-setup-delay-ns:
+    minimum: 50
+    default: 50
+
+  spi-cs-hold-delay-ns:
+    minimum: 50
+    default: 50
+
+  spi-cs-inactive-delay-ns:
+    minimum: 250
+    default: 250
+
+  vcc-supply:
+    description:
+      CAN transceiver supply voltage
+
+  vio-supply:
+    description:
+      Supply voltage for I/O level adaptor
+
+  vbat-supply:
+    description:
+      Battery supply voltage
+
+required:
+  - compatible
+  - reg
+  - "#phy-cells"
+  - spi-cpha
+
+additionalProperties: false
+
+examples:
+  - |
+    spi {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        can-phy@0 {
+            compatible = "nxp,tja1145";
+            reg = <0>;
+            #phy-cells = <0>;
+            spi-cpha;
+            spi-max-frequency = <4000000>;
+            spi-cs-setup-delay-ns = <50>;
+            spi-cs-hold-delay-ns = <50>;
+            spi-cs-inactive-delay-ns = <250>;
+            vcc-supply = <&reg_5v0>;
+            vio-supply = <&reg_3v3>;
+            vbat-supply = <&reg_24v0>;
+        };
+    };

-- 
2.39.5



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* Re: [PATCH 3/4] arm64: dts: qcom: Add Shikra CQM SoM platform
From: Rakesh Kota @ 2026-05-13 13:31 UTC (permalink / raw)
  To: sashiko-reviews
  Cc: Komal Bajaj, robh, linux-phy, neil.armstrong, vkoul, olteanv,
	krzk+dt, conor+dt, devicetree
In-Reply-To: <20260513042836.073F9C2BCB7@smtp.kernel.org>

On Wed, May 13, 2026 at 04:28:35AM +0000, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
> - [High] The PMIC regulator definitions omit their required input supply dependencies (e.g., `vdd_s2-supply`, `vdd_l3-supply`), breaking the power hierarchy.
> - [Medium] The device tree inaccurately hardcodes the `compatible` string to a different PMIC model (`qcom,rpm-pm2250-regulators`) instead of explicitly identifying the actual hardware (PM4125).
> --
> 
> commit 457abf6e7ac410430c866842e08e602ec3daaa51
> Author: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
> 
> arm64: dts: qcom: Add Shikra CQM SoM platform
> 
> Add device tree include for the CQM variant of the Shikra System-on-Module.
> This variant integrates the Shikra SoC and PM4125 PMIC. The DTSI includes
> the common shikra.dtsi and adds PM4125 PMIC regulator definitions.
> 
> > diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi
> > new file mode 100644
> > index 0000000000000..401e71720519d
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi
> [ ... ]
> > +&rpm_requests {
> > +	regulators {
> > +		compatible = "qcom,rpm-pm2250-regulators";
> 
> Since the commit message indicates this is a PM4125 PMIC, should the
> compatible string include a specific identifier for the actual hardware?
> 
> Using a specific identifier like "qcom,rpm-pm4125-regulators" alongside
> the fallback allows the kernel to apply specific quirks if PM4125 errata
> are discovered later.
>
PM2250 and PM4125 share identical regulator hardware with no functional
differences. Therefore, using qcom,rpm-pm2250-regulators as the
compatible string is sufficient i think.

> > +
> > +		pm4125_s2: s2 {
> > +			regulator-min-microvolt = <1000000>;
> > +			regulator-max-microvolt = <1200000>;
> > +		};
> 
> Do these regulators need to explicitly define their input supply dependencies
> such as vdd_s2-supply?
> 
> Without these properties, the regulator framework might be unaware that the
> PMIC regulators draw power from upstream supplies.
> 
> If the kernel dynamically manages the upstream supply and its reference count
> drops to zero, could it be disabled, causing an unexpected power loss for
> downstream components?
> 
As per the Qualcomm system design, the parent-child supply relationships
for these regulators are managed by the AOP (Always-On Processor) FW.

regards
Rakesh Kota
> [ ... ]
> 
> -- 
> Sashiko AI review · https://sashiko.dev/#/patchset/20260512-shikra-dt-v1-0-716438330dd0@oss.qualcomm.com?part=3
> 
> -- 
> linux-phy mailing list
> linux-phy@lists.infradead.org
> https://lists.infradead.org/mailman/listinfo/linux-phy
On Wed, May 13, 2026 at 04:28:35AM +0000, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
> - [High] The PMIC regulator definitions omit their required input supply dependencies (e.g., `vdd_s2-supply`, `vdd_l3-supply`), breaking the power hierarchy.
> - [Medium] The device tree inaccurately hardcodes the `compatible` string to a different PMIC model (`qcom,rpm-pm2250-regulators`) instead of explicitly identifying the actual hardware (PM4125).
> --
> 
> commit 457abf6e7ac410430c866842e08e602ec3daaa51
> Author: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
> 
> arm64: dts: qcom: Add Shikra CQM SoM platform
> 
> Add device tree include for the CQM variant of the Shikra System-on-Module.
> This variant integrates the Shikra SoC and PM4125 PMIC. The DTSI includes
> the common shikra.dtsi and adds PM4125 PMIC regulator definitions.
> 
> > diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi
> > new file mode 100644
> > index 0000000000000..401e71720519d
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi
> [ ... ]
> > +&rpm_requests {
> > +	regulators {
> > +		compatible = "qcom,rpm-pm2250-regulators";
> 
> Since the commit message indicates this is a PM4125 PMIC, should the
> compatible string include a specific identifier for the actual hardware?
> 
> Using a specific identifier like "qcom,rpm-pm4125-regulators" alongside
> the fallback allows the kernel to apply specific quirks if PM4125 errata
> are discovered later.
>
PM2250 and PM4125 share identical regulator hardware with no functional
differences. Therefore, using qcom,rpm-pm2250-regulators as the
compatible string is sufficient i think.

> > +
> > +		pm4125_s2: s2 {
> > +			regulator-min-microvolt = <1000000>;
> > +			regulator-max-microvolt = <1200000>;
> > +		};
> 
> Do these regulators need to explicitly define their input supply dependencies
> such as vdd_s2-supply?
> 
> Without these properties, the regulator framework might be unaware that the
> PMIC regulators draw power from upstream supplies.
> 
> If the kernel dynamically manages the upstream supply and its reference count
> drops to zero, could it be disabled, causing an unexpected power loss for
> downstream components?
> 
As per the Qualcomm system design, the parent-child supply relationships
for these regulators are managed by the AOP (Always-On Processor) FW.

regards
Rakesh Kota
> [ ... ]
> 
> -- 
> Sashiko AI review · https://sashiko.dev/#/patchset/20260512-shikra-dt-v1-0-716438330dd0@oss.qualcomm.com?part=3
> 
> -- 
> linux-phy mailing list
> linux-phy@lists.infradead.org
> https://lists.infradead.org/mailman/listinfo/linux-phy

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* Re: [PATCH phy-next 5/5] phy: lynx-28g: add support for 25GBASER
From: Vladimir Oltean @ 2026-05-13 13:37 UTC (permalink / raw)
  To: Josua Mayer
  Cc: linux-phy@lists.infradead.org, netdev@vger.kernel.org,
	Ioana Ciornei, Vinod Koul, Neil Armstrong,
	linux-kernel@vger.kernel.org, Rabeeh Khoury, Yazan Shhady
In-Reply-To: <1ba1f688-9f68-4749-a18f-20ae91738ae0@solid-run.com>

On Wed, May 13, 2026 at 11:37:14AM +0000, Josua Mayer wrote:
> In order to test this patch with 25Gbps link, additional changes on other drivers are needed.
> This is not a short-coming of this patch.
> 
> 1. I tested this patch-set alone on LX2162 Clearfog with SD1 Protocl 18 (i.e. 2x 10G SFP, 2x 25G SFP):
> 
> 10Gbps ports are working fine!
> 
> 25Gbps fail to probe (but this is partly expected):
> 
> [    8.373048] fsl_dpaa2_eth dpni.9 (unnamed net_device) (uninitialized): MAC returned PCS which does not support 25gbase-r
> [    8.373065] fsl_dpaa2_eth dpni.9 (unnamed net_device) (uninitialized): MAC returned PCS which does not support 25gbase-r
> [    8.373074] fsl_dpaa2_eth dpni.9 (unnamed net_device) (uninitialized): failed to validate link configuration for in-band status
> [    8.373078] fsl_dpaa2_eth dpni.9 (unnamed net_device) (uninitialized): Error connecting to the MAC endpoint: -EINVAL
> [    8.725004] fsl_dpaa2_eth dpni.9: probe with driver fsl_dpaa2_eth failed with error -22
> [    8.920766] fsl_dpaa2_eth dpni.8 (unnamed net_device) (uninitialized): MAC returned PCS which does not support 25gbase-r
> [    8.920783] fsl_dpaa2_eth dpni.8 (unnamed net_device) (uninitialized): MAC returned PCS which does not support 25gbase-r
> [    8.920791] fsl_dpaa2_eth dpni.8 (unnamed net_device) (uninitialized): failed to validate link configuration for in-band status
> [    8.920795] fsl_dpaa2_eth dpni.8 (unnamed net_device) (uninitialized): Error connecting to the MAC endpoint: -EINVAL
> [    9.290005] fsl_dpaa2_eth dpni.8: probe with driver fsl_dpaa2_eth failed with error -22
> 
> Perhaps driver could switch to 10G instead? However not important in my opinion.
> 
> 2. Tested with additional out of tree patches:
> 
> net: phylink: extend phylink_mii_c45_pcs_get_state also for PHY_INTERFACE_MODE_25GBASER
> net: pcs: lynx: extend support to also handle PHY_INTERFACE_MODE_25GBASER
> 
> Then insert 10Gbps SFP module and link-up + TX/RX working fine!
> I.e. driver switched successfully from 25Gbps configuration to 10Gbps.
> 
> Then insert 25Gbps SFP module. Errors start occuring:
> 
> [  357.043894] fsl_dpaa2_eth dpni.9 eth2: Link is Down
> [  357.941036] sfp sfp-bt: module removed
> [  364.269580] sfp sfp-bt: module FS               SFP-25GSL-85     rev 1A   sn C2501330127      dc 250203  
> [  364.269625] fsl_dpaa2_eth dpni.9 eth2: switched to inband/25gbase-r link mode
> [  364.271674] fsl_dpaa2_eth dpni.9 eth2: phy_set_mode_ext() = -95

-95 is -EOPNOTSUPP. Is it coming from lynx_28g_set_mode()? If it is,
I suppose it is from lynx_28g_supports_lane_mode() returning false.

Assuming your list of additional patches is exhaustive, I think you
missed from patch 4/5:

 For old device trees with just "fsl,lynx-28g", the only things that
 change are:
 (...)

 - the feature set is frozen in time (e.g. no 25GbE). Since we cannot
   guarantee that this protocol will work on a lane, just err on the safe
   side and don't offer it (and require a device tree update to get it).

You can look at my branch
https://github.com/vladimiroltean/linux/commits/net-phy-upstreaming,
specifically commit "arm64: dts: lx2160a: transition to device-specific
SerDes compatible strings".

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* Re: [PATCH 3/4] arm64: dts: qcom: Add Shikra CQM SoM platform
From: Rakesh Kota @ 2026-05-13 14:29 UTC (permalink / raw)
  To: Dmitry Baryshkov
  Cc: sashiko-reviews, Komal Bajaj, robh, linux-phy, neil.armstrong,
	vkoul, olteanv, krzk+dt, conor+dt, devicetree
In-Reply-To: <t2sw6owdxy5iyodjqsldbw6bfaqnezhgvc4hhylxuyrrbjkjto@iwf4dr5nmot3>

On Wed, May 13, 2026 at 03:01:47PM +0300, Dmitry Baryshkov wrote:
> On Wed, May 13, 2026 at 04:28:35AM +0000, sashiko-bot@kernel.org wrote:
> > Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
> > - [High] The PMIC regulator definitions omit their required input supply dependencies (e.g., `vdd_s2-supply`, `vdd_l3-supply`), breaking the power hierarchy.
> > - [Medium] The device tree inaccurately hardcodes the `compatible` string to a different PMIC model (`qcom,rpm-pm2250-regulators`) instead of explicitly identifying the actual hardware (PM4125).
> > --
> > 
> > commit 457abf6e7ac410430c866842e08e602ec3daaa51
> > Author: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
> > 
> > arm64: dts: qcom: Add Shikra CQM SoM platform
> > 
> > Add device tree include for the CQM variant of the Shikra System-on-Module.
> > This variant integrates the Shikra SoC and PM4125 PMIC. The DTSI includes
> > the common shikra.dtsi and adds PM4125 PMIC regulator definitions.
> > 
> > > diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi
> > > new file mode 100644
> > > index 0000000000000..401e71720519d
> > > --- /dev/null
> > > +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-som.dtsi
> > [ ... ]
> > > +&rpm_requests {
> > > +	regulators {
> > > +		compatible = "qcom,rpm-pm2250-regulators";
> > 
> > Since the commit message indicates this is a PM4125 PMIC, should the
> > compatible string include a specific identifier for the actual hardware?
> > 
> > Using a specific identifier like "qcom,rpm-pm4125-regulators" alongside
> > the fallback allows the kernel to apply specific quirks if PM4125 errata
> > are discovered later.
> 
> This can be ignored. The compat is a leftover from the historically
> incorrect naming.
> 
> > 
> > > +
> > > +		pm4125_s2: s2 {
> > > +			regulator-min-microvolt = <1000000>;
> > > +			regulator-max-microvolt = <1200000>;
> > > +		};
> > 
> > Do these regulators need to explicitly define their input supply dependencies
> > such as vdd_s2-supply?
> > 
> > Without these properties, the regulator framework might be unaware that the
> > PMIC regulators draw power from upstream supplies.
> > 
> > If the kernel dynamically manages the upstream supply and its reference count
> > drops to zero, could it be disabled, causing an unexpected power loss for
> > downstream components?
> 
> And this is a correct comment. Please provide missing supplies.
>
As per the Qualcomm system design, the parent-child supply relationship
is managed by the RPM firmware, not the Linux regulator framework. The
RPM ensures the parent supply is never disabled until all subsystem
votes are cleared. 

regards
Rakesh kota
> > 
> > [ ... ]
> > 
> > -- 
> > Sashiko AI review · https://sashiko.dev/#/patchset/20260512-shikra-dt-v1-0-716438330dd0@oss.qualcomm.com?part=3
> 
> -- 
> With best wishes
> Dmitry
> 
> -- 
> linux-phy mailing list
> linux-phy@lists.infradead.org
> https://lists.infradead.org/mailman/listinfo/linux-phy

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* Re: [PATCH phy-next 5/5] phy: lynx-28g: add support for 25GBASER
From: Josua Mayer @ 2026-05-13 14:50 UTC (permalink / raw)
  To: Vladimir Oltean
  Cc: linux-phy@lists.infradead.org, netdev@vger.kernel.org,
	Ioana Ciornei, Vinod Koul, Neil Armstrong,
	linux-kernel@vger.kernel.org, Rabeeh Khoury, Yazan Shhady
In-Reply-To: <20260513133721.huu4j3wksxykizz4@skbuf>

Am 13.05.26 um 15:37 schrieb Vladimir Oltean:

> On Wed, May 13, 2026 at 11:37:14AM +0000, Josua Mayer wrote:
>> In order to test this patch with 25Gbps link, additional changes on other drivers are needed.
>> This is not a short-coming of this patch.
>>
>> 1. I tested this patch-set alone on LX2162 Clearfog with SD1 Protocl 18 (i.e. 2x 10G SFP, 2x 25G SFP):
>>
>> 10Gbps ports are working fine!
>>
>> 25Gbps fail to probe (but this is partly expected):
>>
>> [    8.373048] fsl_dpaa2_eth dpni.9 (unnamed net_device) (uninitialized): MAC returned PCS which does not support 25gbase-r
>> [    8.373065] fsl_dpaa2_eth dpni.9 (unnamed net_device) (uninitialized): MAC returned PCS which does not support 25gbase-r
>> [    8.373074] fsl_dpaa2_eth dpni.9 (unnamed net_device) (uninitialized): failed to validate link configuration for in-band status
>> [    8.373078] fsl_dpaa2_eth dpni.9 (unnamed net_device) (uninitialized): Error connecting to the MAC endpoint: -EINVAL
>> [    8.725004] fsl_dpaa2_eth dpni.9: probe with driver fsl_dpaa2_eth failed with error -22
>> [    8.920766] fsl_dpaa2_eth dpni.8 (unnamed net_device) (uninitialized): MAC returned PCS which does not support 25gbase-r
>> [    8.920783] fsl_dpaa2_eth dpni.8 (unnamed net_device) (uninitialized): MAC returned PCS which does not support 25gbase-r
>> [    8.920791] fsl_dpaa2_eth dpni.8 (unnamed net_device) (uninitialized): failed to validate link configuration for in-band status
>> [    8.920795] fsl_dpaa2_eth dpni.8 (unnamed net_device) (uninitialized): Error connecting to the MAC endpoint: -EINVAL
>> [    9.290005] fsl_dpaa2_eth dpni.8: probe with driver fsl_dpaa2_eth failed with error -22
>>
>> Perhaps driver could switch to 10G instead? However not important in my opinion.
>>
>> 2. Tested with additional out of tree patches:
>>
>> net: phylink: extend phylink_mii_c45_pcs_get_state also for PHY_INTERFACE_MODE_25GBASER
>> net: pcs: lynx: extend support to also handle PHY_INTERFACE_MODE_25GBASER
>>
>> Then insert 10Gbps SFP module and link-up + TX/RX working fine!
>> I.e. driver switched successfully from 25Gbps configuration to 10Gbps.
>>
>> Then insert 25Gbps SFP module. Errors start occuring:
>>
>> [  357.043894] fsl_dpaa2_eth dpni.9 eth2: Link is Down
>> [  357.941036] sfp sfp-bt: module removed
>> [  364.269580] sfp sfp-bt: module FS               SFP-25GSL-85     rev 1A   sn C2501330127      dc 250203  
>> [  364.269625] fsl_dpaa2_eth dpni.9 eth2: switched to inband/25gbase-r link mode
>> [  364.271674] fsl_dpaa2_eth dpni.9 eth2: phy_set_mode_ext() = -95
> -95 is -EOPNOTSUPP. Is it coming from lynx_28g_set_mode()? If it is,
> I suppose it is from lynx_28g_supports_lane_mode() returning false.
>
> Assuming your list of additional patches is exhaustive, I think you
> missed from patch 4/5:
>
>  For old device trees with just "fsl,lynx-28g", the only things that
>  change are:
>  (...)
>
>  - the feature set is frozen in time (e.g. no 25GbE). Since we cannot
>    guarantee that this protocol will work on a lane, just err on the safe
>    side and don't offer it (and require a device tree update to get it).

Yes I missed that.

With updated compatible string it is working perfectly!

I'll send my tested-by on the series, thanks!

>
> You can look at my branch
> https://github.com/vladimiroltean/linux/commits/net-phy-upstreaming,
> specifically commit "arm64: dts: lx2160a: transition to device-specific
> SerDes compatible strings".

Thanks!

I will probably have retimer comments i.e. one phy object ehach for rx, and tx,
instead of combined - as we can not rely on hardware designers making clean choices.
E.g. imagine two retimer chips, one handling rx direction of 2 ports and one tx of 2 ports.

phys = <&serdes_1 0, &retimer_rx 0>, <&retimer_tx 0>;

Not relevant to this patch.
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* Re: [PATCH phy-next 0/5] Lynx 28G SerDes: 25GbE support
From: Josua Mayer @ 2026-05-13 14:51 UTC (permalink / raw)
  To: Vladimir Oltean, linux-phy@lists.infradead.org
  Cc: netdev@vger.kernel.org, Ioana Ciornei, Vinod Koul, Neil Armstrong,
	linux-kernel@vger.kernel.org
In-Reply-To: <20260511150023.1903577-1-vladimir.oltean@nxp.com>

Am 11.05.26 um 17:00 schrieb Vladimir Oltean:
> This is the remainder of "Lynx 28G improvements part 2", previously
> submitted here:
> https://lore.kernel.org/linux-phy/176850672122.1082429.444623229961712368.robh@kernel.org/
>
> but split up into smaller portions (merged separately):
> - https://lore.kernel.org/linux-phy/20260226182853.1103616-1-vladimir.oltean@nxp.com/
> - https://lore.kernel.org/linux-phy/20260321011451.1557091-1-vladimir.oltean@nxp.com/
>
> What remains is the highlight feature (patch 5/5): support for dynamic
> protocol changes to/from 25GBase-R, required by SFP28 modules. These are
> used with the NXP LX2160A and the (Ethernet) dpaa2-mac consumer.
>
> Patches 1-4 handle the following situation: with current device trees,
> the driver will think 25GBase-R will work on a lane, but it may work or
> may not. This is because not all lanes support this protocol. So we
> modify the SerDes compatible strings to identify them, and we use a
> driver-internal database to figure out on which lanes does each SerDes
> instance support this protocol.
>
> On current device trees, 25GbE is not supported.
>
> Detailed change log in patches. Summary:
> - reworded commit messages
> - change match condition from dt-bindings change 2/5
> - patch 3/5 is new (reject probing on devices with no OF node)
>
> Ioana Ciornei (1):
>   phy: lynx-28g: add support for 25GBASER
>
> Vladimir Oltean (4):
>   dt-bindings: phy: lynx-28g: add compatible strings per SerDes and
>     instantiation
>   dt-bindings: phy: lynx-28g: add constraint on LX2162A lane indices
>   phy: lynx-28g: require an OF node to probe
>   phy: lynx-28g: probe on per-SoC and per-instance compatible strings
>
>  .../devicetree/bindings/phy/fsl,lynx-28g.yaml |  48 +++-
>  drivers/phy/freescale/phy-fsl-lynx-28g.c      | 221 +++++++++++++++++-
>  2 files changed, 254 insertions(+), 15 deletions(-)
>
Tested-by: Josua Mayer <josua@solid-run.com>
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* Re: [PATCH phy-next 5/5] phy: lynx-28g: add support for 25GBASER
From: Vladimir Oltean @ 2026-05-13 15:10 UTC (permalink / raw)
  To: Josua Mayer
  Cc: linux-phy@lists.infradead.org, netdev@vger.kernel.org,
	Ioana Ciornei, Vinod Koul, Neil Armstrong,
	linux-kernel@vger.kernel.org, Rabeeh Khoury, Yazan Shhady
In-Reply-To: <5cc008f1-d2c4-4a56-a1b4-6fd9bd470049@solid-run.com>

On Wed, May 13, 2026 at 02:50:38PM +0000, Josua Mayer wrote:
> With updated compatible string it is working perfectly!
> 
> I'll send my tested-by on the series, thanks!

Thanks.

> >
> > You can look at my branch
> > https://github.com/vladimiroltean/linux/commits/net-phy-upstreaming
> > specifically commit "arm64: dts: lx2160a: transition to device-specific
> > SerDes compatible strings".
> 
> Thanks!
> 
> I will probably have retimer comments i.e. one phy object ehach for rx, and tx,
> instead of combined - as we can not rely on hardware designers making clean choices.
> E.g. imagine two retimer chips, one handling rx direction of 2 ports and one tx of 2 ports.
> 
> phys = <&serdes_1 0, &retimer_rx 0>, <&retimer_tx 0>;
> 
> Not relevant to this patch.

Correct. For the retimers we will upstream (Ioana is working on the TI
DS125DF111), their channels will be split to separate Generic PHY
objects, to cater specifically to that use case. Hoping that all other
multi-channel retimer submissions where there is no meaningful
distinction between RX and TX will do the same.

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