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Howlett" , Uladzislau Rezki , Miguel Ojeda , Alex Gaynor , Gary Guo , Bj??rn Roy Baron , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , "Rafael J. Wysocki" , Viresh Kumar , Sebastian Andrzej Siewior , Ingo Molnar , Ryo Takakura , K Prateek Nayak , "open list:CPU FREQUENCY SCALING FRAMEWORK" References: <20251013155205.2004838-1-lyude@redhat.com> <20251013155205.2004838-2-lyude@redhat.com> <20251014104839.GN4067720@noisy.programming.kicks-ass.net> <4a237ec0-05ae-439b-a1cb-6b7f451c0d7e@nvidia.com> <20251014194349.GC1206438@noisy.programming.kicks-ass.net> <20251020204421.GA197647@joelbox2> Content-Language: en-US In-Reply-To: <20251020204421.GA197647@joelbox2> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-ClientProxiedBy: BLAPR03CA0093.namprd03.prod.outlook.com (2603:10b6:208:32a::8) To SN7PR12MB8059.namprd12.prod.outlook.com (2603:10b6:806:32b::7) Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN7PR12MB8059:EE_|DS7PR12MB6024:EE_ X-MS-Office365-Filtering-Correlation-Id: 5c77f9a1-9383-4fe0-4f91-08de1807a213 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|1800799024|366016; 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\ >>>>> arch_nmi_enter(); \ >>>>> - BUG_ON(in_nmi() == NMI_MASK); \ >>>>> - __preempt_count_add(NMI_OFFSET + HARDIRQ_OFFSET); \ >>>>> + BUG_ON(__this_cpu_read(nmi_nesting) == UINT_MAX); \ >>>>> + __this_cpu_inc(nmi_nesting); \ >>>> >>>> An NMI that nests from here.. >>>> >>>>> + __preempt_count_add(HARDIRQ_OFFSET); \ >>>>> + if (__this_cpu_read(nmi_nesting) == 1) \ >>>> >>>> .. until here, will see nmi_nesting > 1 and not set NMI_OFFSET. >>> >>> This is true, I can cure it by setting NMI_OFFSET unconditionally when >>> nmi_nesting >= 1. Then the outer most NMI will then reset it. I think that will >>> work. Do you see any other issue with doing so? >> >> unconditionally set NMI_FFSET, regardless of nmi_nesting >> and only clear on exit when nmi_nesting == 0. >> >> Notably, when you use u64 __preempt_count, you can limit this to 32bit >> only. The NMI nesting can happen in the single instruction window >> between ADD and ADC. But on 64bit you don't have that gap and so don't >> need to fix it. > > Wouldn't this break __preempt_count_dec_and_test though? If we make it > 64-bit, then there is no longer a way on x86 32-bit to decrement the preempt > count and zero-test the entire word in the same instruction (decl). And I > feel there might be other races as well. Also this means that every > preempt_disable/enable will be heavier on 32-bit. > > If we take the approach of this patch, but move the per-cpu counter to cache > hot area, what are the other drawbacks other than few more instructions on > NMI entry/exit? It feels simpler and less risky. But let me know if I missed > something. > If its Ok, for the next revision, I will just do the following to cure the issue Peter found, and respin the patch. Let me know any objections. Thanks. diff --git a/include/linux/hardirq.h b/include/linux/hardirq.h index 177eed1de35c..cc06bda52c3e 100644 --- a/include/linux/hardirq.h +++ b/include/linux/hardirq.h @@ -113,8 +113,7 @@ void irq_exit_rcu(void); BUG_ON(__this_cpu_read(nmi_nesting) == UINT_MAX); \ __this_cpu_inc(nmi_nesting); \ __preempt_count_add(HARDIRQ_OFFSET); \ - if (__this_cpu_read(nmi_nesting) == 1) \ - __preempt_count_add(NMI_OFFSET); \ + preempt_count_set(preempt_count() | NMI_MASK); \ } while (0) #define nmi_enter()