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From: Mario Limonciello <mario.limonciello@amd.com>
To: Fourhundred Thecat <400thecat@ik.me>,
	platform-driver-x86@vger.kernel.org
Cc: linux-pm@vger.kernel.org, Shyam-sundar.S-k@amd.com,
	hansg@kernel.org, ilpo.jarvinen@linux.intel.com,
	rafael@kernel.org
Subject: Re: [BUG] s2idle: unrecoverable sleep on ThinkPad P16s Gen 4 AMD, (Strix Point) when more than 16 logical CPUs are online
Date: Wed, 23 Sep 2026 11:20:59 -0500	[thread overview]
Message-ID: <0bb77796-790f-44db-b4cc-e4742ed1b2d0@amd.com> (raw)
In-Reply-To: <66dee9c5-ad66-4bd7-982c-c5694d806cf2@amd.com>



On 9/23/26 11:15, Mario Limonciello wrote:
> 
> 
> On 9/23/26 11:12, Fourhundred Thecat wrote:
>> On 2026-09-23 16:36, Mario Limonciello wrote:
>>>
>>>
>>> Some other thoughts that might be the root cause based on other 
>>> historical issues.
>>>
>>> 1) Have you changed TPM policy or Pluton policy in BIOS setup?  What 
>>> did you change it from and to.
>>> 2) Have you enabled a storage security password?  If you disable it 
>>> does it help this issue?
>>> 3) Do you have WWAN in your device?  If you disable it does it help?
>>> 4) Does booting with `amd_iommu=off` help?
>>
>> 4) amd_iommu=off
>>
>> Yes, that fixes it. With amd_iommu=off and all 24 CPUs online, 
>> suspend/ resume works reliably.
>>
>> So this is not really a CPU count problem. nr_cpus=16 was only masking 
>> an IOMMU interaction. But narrowing it further was surprising: neither 
>> of the IOMMU's two functions is responsible on its own. All of the 
>> following were run with all 24 CPUs online, and I verified in each 
>> case that the parameter actually took effect:
>>
>>    amd_iommu=off            IOMMU off entirely                     WAKES
>>    intremap=off             IR off, DMA remapping on               no 
>> wake
>>    iommu=pt                 DMA passthrough, IR on                 no 
>> wake
>>    amd_iommu_intr=legacy    legacy GA mode, IR on, DMA on          no 
>> wake
>>
>> Verification for each:
>>
>>    intremap=off           /proc/interrupts went from 58 IR- lines to 0,
>>                           and irq 1 (i8042) is no longer IR-IO-APIC.
>>                           iommu still enabled, domain type Translated.
>>    iommu=pt               "iommu: Default domain type: Passthrough 
>> (set via
>>                           kernel command line)", all 40 PCI devices in
>>                           identity domains, IR still on (58 IR- lines).
>>    amd_iommu_intr=legacy  "AMD-Vi: Virtual APIC enabled" no longer 
>> printed,
>>                           only "AMD-Vi: Interrupt remapping enabled".
>>
>> So only disabling the IOMMU outright helps. Turning off interrupt 
>> remapping alone, bypassing DMA translation alone, or dropping out of 
>> vAPIC/GA mode all still hang.
>>
>> The CPU dependency is still there on top of that. With the IOMMU 
>> enabled, nr_cpus=16 works and 24 CPUs hangs. Offlining cpu16-23 by 
>> hotplug after booting with all 24 does not help; the CPUs have to 
>> never be brought up. cpu16-23 here are the second SMT thread of the 
>> eight Zen5c cores (APIC ids 17,19..31).
>>
>> Both conditions appear to be required: the IOMMU enabled, and more 
>> than 16 CPUs brought up at boot. Either one alone is fine.
>>
>>
>> 1) TPM / Pluton policy
>>
>> Current values:
>>
>>    TpmSelection            = DiscreteTPM2.0   (possible: 
>> DiscreteTPM2.0;PlutonTPM2.0)
>>    PlutonSecurityProcessor = Disable
>>    SecurityChip            = Enable
>>
>> The TPM that binds is a discrete STMicro part, tpm0 -> STM0925:00.
>>
>> I did change this. As I recall I disabled Microsoft Pluton, which 
>> moves the TPM selection off the PlutonTPM2.0 default onto the discrete 
>> part, so Enable -> Disable for Pluton and PlutonTPM2.0 -> 
>> DiscreteTPM2.0 for the selection. I will confirm the exact original 
>> values in setup. I have not yet tested whether restoring the Pluton 
>> default changes the behaviour, since the IOMMU result looked more 
>> promising.
>>
>>
>> 2) Storage security password
>>
>> None enrolled. HardDiskPasswordControl=Disable, and the HDD, NVMe, 
>> Admin, System and Power-on authentication slots all report 
>> is_enabled=0. BlockSIDAuthentication=Enable is the only non-default 
>> setting in that area. Nothing to disable, so nothing to test.
>>
>>
>> 3) WWAN
>>
>> Yes: Quectel [1eac:1007] at 0000:c4:00.0, attached over MHI, exposing 
>> wwan0. Its power/wakeup is enabled. Not yet tested with 
>> WirelessWANAccess disabled in BIOS.
>>
>>
>> so please suggest which test I should do next, now that we have more info
> 
> Of your above the most likely cause is PlutonSecurityProcessor = 
> Disable.  Please try to re-enable that and then try with IOMMU enabled.

BTW - what version of amd-s2idle didn't flag this?  I am surprised, we 
had a check for this that /should/ have failed prerequisites.


  reply	other threads:[~2026-09-23 16:21 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-22 13:43 [BUG] s2idle: unrecoverable sleep on ThinkPad P16s Gen 4 AMD, (Strix Point) when more than 16 logical CPUs are online Fourhundred Thecat
2026-09-22 14:47 ` Mario Limonciello
2026-09-23  5:58   ` Fourhundred Thecat
2026-09-23 12:41     ` Mario Limonciello
2026-09-23 13:51       ` Fourhundred Thecat
2026-09-23 14:36         ` Mario Limonciello
2026-09-23 16:12           ` Fourhundred Thecat
2026-09-23 16:15             ` Mario Limonciello
2026-09-23 16:20               ` Mario Limonciello [this message]
2026-09-23 16:37                 ` Fourhundred Thecat
2026-09-23 16:41                   ` Mario Limonciello
2026-09-23 16:54                     ` Fourhundred Thecat
2026-09-23 16:59                       ` Mario Limonciello
2026-09-23 18:02                         ` Fourhundred Thecat
2026-09-23 18:11                           ` Mario Limonciello
2026-09-23 18:14                             ` Fourhundred Thecat
2026-09-23 18:25                               ` Mario Limonciello
2026-09-23 18:39                                 ` Fourhundred Thecat
2026-09-23 18:57                                   ` Mario Limonciello
2026-09-23 19:13                                     ` Fourhundred Thecat
2026-09-23 19:20                                       ` Mario Limonciello
2026-09-23 20:26                                         ` Fourhundred Thecat
2026-09-23 20:48                                           ` Fourhundred Thecat
2026-09-23 21:10                                             ` Mario Limonciello
2026-09-24  5:36                                               ` Fourhundred Thecat
2026-09-25  7:05                                               ` Fourhundred Thecat
2026-09-25 13:30                                                 ` Mario Limonciello
2026-09-26  4:13                                                   ` Fourhundred Thecat
2026-09-26 18:29                                                     ` Mario Limonciello
2026-09-29  5:43                                                       ` Fourhundred Thecat
2026-09-29  5:57                                                         ` Fourhundred Thecat
2026-09-29 13:37                                                           ` Mario Limonciello

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