From: Gregory CLEMENT <gregory.clement@free-electrons.com>
To: Daniel Lezcano <daniel.lezcano@linaro.org>,
"Rafael J. Wysocki" <rjw@rjwysocki.net>,
linux-pm@vger.kernel.org, Jason Cooper <jason@lakedaemon.net>,
Andrew Lunn <andrew@lunn.ch>,
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>,
Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>,
Lior Amsalem <alior@marvell.com>,
Tawfik Bayouk <tawfik@marvell.com>,
linux-kernel@vger.kernel.org, Nadav Haklai <nadavh@marvell.com>,
Ezequiel Garcia <ezequiel.garcia@free-electrons.com>,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v5 04/14] ARM: mvebu: Remove the unused argument of set_cpu_coherent()
Date: Tue, 25 Mar 2014 23:48:15 +0100 [thread overview]
Message-ID: <1395787705-31061-5-git-send-email-gregory.clement@free-electrons.com> (raw)
In-Reply-To: <1395787705-31061-1-git-send-email-gregory.clement@free-electrons.com>
set_cpu_coherent() took the SMP group ID as parameter. But this
parameter was never used, and the CPU always uses the SMP group 0. So
we can remove this parameter.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
arch/arm/mach-mvebu/coherency.c | 4 ++--
arch/arm/mach-mvebu/coherency.h | 2 +-
arch/arm/mach-mvebu/platsmp.c | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c
index 51010dbbf7e4..ad61251f7faf 100644
--- a/arch/arm/mach-mvebu/coherency.c
+++ b/arch/arm/mach-mvebu/coherency.c
@@ -46,7 +46,7 @@ static struct of_device_id of_coherency_table[] = {
/* Function defined in coherency_ll.S */
int ll_set_cpu_coherent(void);
-int set_cpu_coherent(int smp_group_id)
+int set_cpu_coherent(void)
{
if (!coherency_base) {
pr_warn("Can't make current CPU cache coherent.\n");
@@ -140,7 +140,7 @@ int __init coherency_init(void)
sync_cache_w(&coherency_phys_base);
coherency_base = of_iomap(np, 0);
coherency_cpu_base = of_iomap(np, 1);
- set_cpu_coherent(0);
+ set_cpu_coherent();
of_node_put(np);
}
diff --git a/arch/arm/mach-mvebu/coherency.h b/arch/arm/mach-mvebu/coherency.h
index c7e5df368d98..dff16612dd93 100644
--- a/arch/arm/mach-mvebu/coherency.h
+++ b/arch/arm/mach-mvebu/coherency.h
@@ -15,8 +15,8 @@
#define __MACH_370_XP_COHERENCY_H
extern unsigned long coherency_phys_base;
+int set_cpu_coherent(void);
-int set_cpu_coherent(int smp_group_id);
int coherency_init(void);
#endif /* __MACH_370_XP_COHERENCY_H */
diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c
index a99d71a747f0..f2f1830063c8 100644
--- a/arch/arm/mach-mvebu/platsmp.c
+++ b/arch/arm/mach-mvebu/platsmp.c
@@ -102,7 +102,7 @@ static void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus)
set_secondary_cpus_clock();
flush_cache_all();
- set_cpu_coherent(0);
+ set_cpu_coherent();
/*
* In order to boot the secondary CPUs we need to ensure
--
1.8.1.2
next prev parent reply other threads:[~2014-03-25 22:48 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-03-25 22:48 [PATCH v5 00/14] CPU idle for Armada XP Gregory CLEMENT
2014-03-25 22:48 ` [PATCH v5 01/14] ARM: PJ4B: Add cpu_suspend/cpu_resume hooks for PJ4B Gregory CLEMENT
2014-03-25 22:48 ` [PATCH v5 02/14] ARM: mvebu: remove the address parameter for ll_set_cpu_coherent Gregory CLEMENT
2014-03-25 22:48 ` [PATCH v5 03/14] ARM: mvebu: ll_set_cpu_coherent always uses the current CPU Gregory CLEMENT
2014-03-26 11:52 ` Sebastian Hesselbarth
2014-03-26 11:51 ` Gregory CLEMENT
2014-03-25 22:48 ` Gregory CLEMENT [this message]
2014-03-25 22:48 ` [PATCH v5 05/14] ARM: mvebu: Split low level functions to manipulate HW coherency Gregory CLEMENT
2014-03-25 22:48 ` [PATCH v5 06/14] ARM: mvebu: Low level function to disable HW coherency support Gregory CLEMENT
2014-03-25 22:48 ` [PATCH v5 07/14] ARM: mvebu: Extend the pmsu registers Gregory CLEMENT
2014-03-26 0:30 ` Jason Cooper
2014-03-26 9:33 ` Gregory CLEMENT
2014-03-26 9:55 ` Sebastian Hesselbarth
2014-03-26 12:04 ` Sebastian Hesselbarth
2014-03-26 12:01 ` Gregory CLEMENT
2014-03-26 12:59 ` Thomas Petazzoni
2014-03-25 22:48 ` [PATCH v5 08/14] ARM: dts: mvebu: Introduce a new compatible for the PMSU node Gregory CLEMENT
[not found] ` <1395787705-31061-9-git-send-email-gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2014-03-26 0:32 ` Jason Cooper
2014-03-25 22:48 ` [PATCH v5 09/14] ARM: mvebu: Allow to power down L2 cache controller in idle mode Gregory CLEMENT
2014-03-25 22:48 ` [PATCH v5 10/14] ARM: mvebu: Add the PMSU related part of the cpu idle functions Gregory CLEMENT
2014-03-25 22:48 ` [PATCH v5 11/14] ARM: mvebu: Set the start address of a CPU in a separate function Gregory CLEMENT
2014-03-25 22:48 ` [PATCH v5 12/14] ARM: mvebu: Register notifier callback for the cpuidle transition Gregory CLEMENT
2014-03-25 22:48 ` [PATCH v5 13/14] cpuidle: mvebu: Add initial CPU idle support for Armada 370/XP SoC Gregory CLEMENT
2014-03-25 22:48 ` [PATCH v5 14/14] ARM: mvebu: register the cpuidle driver for the Armada XP SoCs Gregory CLEMENT
2014-03-26 10:30 ` Ezequiel Garcia
2014-03-26 10:31 ` Thomas Petazzoni
2014-03-26 10:38 ` Gregory CLEMENT
2014-03-26 0:42 ` [PATCH v5 00/14] CPU idle for Armada XP Jason Cooper
2014-03-26 9:53 ` Gregory CLEMENT
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