[RFC PATCH v2 0/3] CPPC as PID backend

[Ashwin Chaugule <ashwin.chaugule@linaro.org>]

This patchset introduces CPPC(Collaborative Processor Performance Control) as a backend
to the PID governor. The PID governor from intel_pstate.c maps cleanly onto some CPPC
interfaces.
e.g. The CPU performance requests are made on a continuous scale as against discrete pstate
levels. The CPU performance feedback over an interval is gauged using platform specific
counters which are also described by CPPC.

Although CPPC describes several other registers to provide more hints to the platform,
Linux as of today does not have the infrastructure to make use of those registers.
Some of the CPPC specific information could be made available from the scheduler as
part of the CPUfreq and Scheduler intergration work. Until then PID can be used as the
front end for CPPC.

This implementation was tested using a Thinkpad X240 Laptop which seemed to have
CPPC and PCC tables in its ACPI firmware. However, it seems as though some addresses
pointed to by the tables do not exist. This patchset also shows the hacks that
were made in order to work around those limitations and test the control flow.

This patchset builds on top of the PCC driver which is being reviewed separately[3].

Changes since V1:
-	Create a new driver based on Dirks suggestion.
-	Fold in CPPC backend hooks into main driver.

Changes since V0: [1]
-	Split intel_pstate.c into a generic PID governor and platform specific backend.
-	Add CPPC accessors as PID backend.


CPPC:
====

CPPC (Collaborative Processor Performance Control) is a new way to control CPU
performance using an abstract continous scale as against a discretized P-state scale
which is tied to CPU frequency only. It is defined in the ACPI 5.0+ spec. In brief,
the basic operation involves:
- OS makes a CPU performance request. (Can provide min and max tolerable bounds)

- Platform (such as BMC) is free to optimize request within requested bounds depending
on power/thermal budgets etc.

- Platform conveys its decision back to OS

The communication between OS and platform occurs through another medium called (PCC)
Platform communication Channel. This is a generic mailbox like mechanism which includes
doorbell semantics to indicate register updates. The PCC driver is being discussed in a
separate patchset [3] and is not included here, since CPPC is only one client of PCC.

Finer details about the PCC and CPPC spec are available in the latest ACPI 5.1
specification.[2]

[1] - http://lwn.net/Articles/608715/
[2] - http://www.uefi.org/sites/default/files/resources/ACPI_5_1release.pdf
[3] - http://comments.gmane.org/gmane.linux.acpi.devel/71171


Ashwin Chaugule (3):
  PCC HACKS: Update PCC comm region with MSR data
  CPPC as a PID controller backend
  CPPC HACKS

 drivers/cpufreq/Kconfig    |   12 +
 drivers/cpufreq/Makefile   |    1 +
 drivers/cpufreq/acpi_pid.c | 1085 ++++++++++++++++++++++++++++++++++++++++++++
 drivers/mailbox/pcc.c      |  125 ++++-
 4 files changed, 1207 insertions(+), 16 deletions(-)
 create mode 100644 drivers/cpufreq/acpi_pid.c

-- 
1.9.1