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From: Marek Szyprowski <m.szyprowski@samsung.com>
To: linux-samsung-soc@vger.kernel.org, linux-pm@vger.kernel.org
Cc: Marek Szyprowski <m.szyprowski@samsung.com>,
	Sylwester Nawrocki <s.nawrocki@samsung.com>,
	Krzysztof Kozlowski <krzk@kernel.org>,
	Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>,
	Chanwoo Choi <cw00.choi@samsung.com>,
	Inki Dae <inki.dae@samsung.com>
Subject: [PATCH 6/8] arm64: dts: exynos: Add AUD power domain to Exynos5433 SoC
Date: Wed, 25 Jan 2017 12:55:40 +0100	[thread overview]
Message-ID: <1485345342-3273-7-git-send-email-m.szyprowski@samsung.com> (raw)
In-Reply-To: <1485345342-3273-1-git-send-email-m.szyprowski@samsung.com>

This patch adds support for AUD power domain to Exynos5433 SoCs, which
contains following devices: a clock controller, a pin controller, LPASS
module, I2S controller, ADMA PL330 engine and UART #3 device.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 arch/arm64/boot/dts/exynos/exynos5433.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 3487981726d9..24fc3b46cc40 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -377,6 +377,7 @@
 			#clock-cells = <1>;
 			clock-names = "oscclk", "fout_aud_pll";
 			clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>;
+			power-domains = <&pd_aud>;
 		};
 
 		cmu_bus0: clock-controller@13600000 {
@@ -553,6 +554,12 @@
 			#power-domain-cells = <0>;
 		};
 
+		pd_aud: aud-power-domain@105c40c0 {
+			compatible = "samsung,exynos5433-pd";
+			reg = <0x105c40c0 0x20>;
+			#power-domain-cells = <0>;
+		};
+
 		tmu_atlas0: tmu@10060000 {
 			compatible = "samsung,exynos5433-tmu";
 			reg = <0x10060000 0x200>;
@@ -665,6 +672,7 @@
 			compatible = "samsung,exynos5433-pinctrl";
 			reg = <0x114b0000 0x1000>;
 			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+			power-domains = <&pd_aud>;
 		};
 
 		pinctrl_cpif: pinctrl@10fe0000 {
@@ -1544,6 +1552,7 @@
 			clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>;
 			clock-names = "sfr0_ctrl";
 			samsung,pmu-syscon = <&pmu_system_controller>;
+			power-domains = <&pd_aud>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges;
@@ -1557,6 +1566,7 @@
 				#dma-cells = <1>;
 				#dma-channels = <8>;
 				#dma-requests = <32>;
+				power-domains = <&pd_aud>;
 			};
 
 			i2s0: i2s0@11440000 {
@@ -1573,6 +1583,7 @@
 				clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
 				pinctrl-names = "default";
 				pinctrl-0 = <&i2s0_bus>;
+				power-domains = <&pd_aud>;
 				status = "disabled";
 			};
 
@@ -1585,6 +1596,7 @@
 				clock-names = "uart", "clk_uart_baud0";
 				pinctrl-names = "default";
 				pinctrl-0 = <&uart_aud_bus>;
+				power-domains = <&pd_aud>;
 				status = "disabled";
 			};
 		};
-- 
1.9.1


  parent reply	other threads:[~2017-01-25 11:56 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <CGME20170125115558eucas1p18dcb5c4cbab28dcb10bd412b825256b7@eucas1p1.samsung.com>
2017-01-25 11:55 ` [PATCH 0/8] Power domains support for Exynos5433 SoCs Marek Szyprowski
2017-01-25 11:55   ` [PATCH 1/8] soc: samsung: pm_domains: Add new exynos5433 compatible Marek Szyprowski
2017-01-27  7:42     ` Krzysztof Kozlowski
2017-01-25 11:55   ` [PATCH 2/8] arm64: dts: exynos: Add GSCL power domain to Exynos 5433 SoC Marek Szyprowski
2017-01-27  7:46     ` Krzysztof Kozlowski
2017-01-27 10:33       ` Marek Szyprowski
2017-01-27 11:28         ` Krzysztof Kozlowski
2017-01-25 11:55   ` [PATCH 3/8] arm64: dts: exynos: Add DISP " Marek Szyprowski
2017-01-25 11:55   ` [PATCH 4/8] arm64: dts: exynos: Add MSCL " Marek Szyprowski
2017-01-25 11:55   ` [PATCH 5/8] arm64: dts: exynos: Add MFC " Marek Szyprowski
2017-01-25 11:55   ` Marek Szyprowski [this message]
2017-01-25 11:55   ` [PATCH 7/8] arm64: dts: exynos: Add FSYS power domain to Exynos5433 SoC Marek Szyprowski
2017-01-25 11:55   ` [PATCH 8/8] arm64: dts: exynos: Add remaining power domains " Marek Szyprowski
2017-01-27  7:43   ` [PATCH 0/8] Power domains support for Exynos5433 SoCs Krzysztof Kozlowski
2017-01-27  7:47     ` Marek Szyprowski
2017-01-27  7:52       ` Krzysztof Kozlowski
2017-01-27  7:59         ` Marek Szyprowski

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