From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: Hans de Goede <hdegoede@redhat.com>, Johannes Stezenbach <js@sig21.net>
Cc: Michael Turquette <mturquette@baylibre.com>,
"Rafael J. Wysocki" <rjw@rjwysocki.net>,
Mika Westerberg <mika.westerberg@linux.intel.com>,
Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>,
linux-clk <linux-clk@vger.kernel.org>,
Linux PM list <linux-pm@vger.kernel.org>,
Carlo Caione <carlo@endlessm.com>,
Darren Hart <dvhart@infradead.org>,
Enric Balletbo i Serra <enric.balletbo@collabora.com>,
Takashi Iwai <tiwai@suse.de>,
ACPI Devel Maling List <linux-acpi@vger.kernel.org>
Subject: Re: [RFC PATCH 1/2] platform/x86: add Atom PMC quirk to disable SATA
Date: Wed, 13 Dec 2017 21:33:33 +0200 [thread overview]
Message-ID: <1513193613.7000.58.camel@linux.intel.com> (raw)
In-Reply-To: <e6aa5c55-8174-7ad9-009f-c254d3aeaf72@redhat.com>
On Wed, 2017-12-13 at 17:37 +0100, Hans de Goede wrote:
> Hi,
>
> On 13-12-17 17:22, Johannes Stezenbach wrote:
> >
> > Please don't get confused with the other thread about clocks.
> > This issue sets the "disable IP" bit, found by doing stupid
> > experiments to enable S0ix on E200HA.
>
> Ah my bad.
Oh, perhaps I also need to refresh my memory from that buglink.
> > 1. no idea if Cherry Trail even has SATA IP, maybe this is a
> > meaningless bit but PMC firmware carried over from
> > Bay Trail looks at it
>
>
> There are no CHT SoCs with SATA AFAIK, but Braswell SoCs,
> which I believe is the same die do have SATA.
>
> I think the best fix here is to look at the model-string part
> of the CPU-id and do a quirk based on that, setting the "disable IP"
> bit for the SATA on all SoC models known to not have SATA
> (Z8300, Z8350, Z8500, Z8550, Z8700, Z8750).
>
> Rafael, Andy how does that sound as a solution?
Yeah, that bit is a property of PMC microcontroller and thus belongs to
its driver in Linux kernel.
To make it strict we need a matching property. AFAIR CPU model ID is all
the same for all CHT and BSW SoCs, so, can't be used to distinguish
them. So, you are thinking about comparing CPU model name then?
It might work. However, SATA itself is a part of PCH, and thus can not
exactly be matched by CPU ID.
Btw, Pentium Celeron N-series according to spec has SATA host.
--
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy
next prev parent reply other threads:[~2017-12-13 19:33 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-06 20:42 S0ix failure due to "clk: x86: Do not gate clocks enabled by the firmware" Johannes Stezenbach
2017-09-06 21:02 ` Pierre-Louis Bossart
2017-09-08 13:49 ` Johannes Stezenbach
2017-09-21 9:40 ` Johannes Stezenbach
2017-09-21 14:21 ` Rafael J. Wysocki
2017-09-21 16:23 ` Johannes Stezenbach
2017-09-21 22:20 ` Rafael J. Wysocki
2017-09-21 22:24 ` Rafael J. Wysocki
2017-09-21 22:35 ` Rafael J. Wysocki
2017-09-22 8:04 ` Johannes Stezenbach
2017-09-22 12:27 ` Takashi Iwai
2017-09-22 21:04 ` Johannes Stezenbach
2017-09-22 22:12 ` Rafael J. Wysocki
2017-09-22 22:09 ` Rafael J. Wysocki
2017-09-25 19:17 ` Johannes Stezenbach
2017-09-25 19:21 ` [RFC PATCH 1/2] platform/x86: add Atom PMC quirk to disable SATA Johannes Stezenbach
2017-12-13 0:00 ` Rafael J. Wysocki
2017-12-13 8:53 ` Hans de Goede
2017-12-13 11:13 ` Johannes Stezenbach
2017-12-13 15:25 ` Michael Turquette
2017-12-13 16:04 ` Hans de Goede
2017-12-13 16:22 ` Johannes Stezenbach
2017-12-13 16:37 ` Hans de Goede
2017-12-13 19:33 ` Andy Shevchenko [this message]
2017-12-14 10:53 ` Hans de Goede
2017-09-25 19:23 ` [RFC PATCH 2/2] clk: x86: Disable unused clocks to fix S0ix Johannes Stezenbach
2017-12-13 0:01 ` Rafael J. Wysocki
2017-12-13 8:56 ` Hans de Goede
2017-12-13 10:20 ` Carlo Caione
2017-12-13 11:22 ` Johannes Stezenbach
2017-12-13 14:25 ` Pierre-Louis Bossart
2017-12-13 14:29 ` Andy Shevchenko
2017-09-06 21:14 ` S0ix failure due to "clk: x86: Do not gate clocks enabled by the firmware" Carlo Caione
2017-09-18 8:00 ` Andy Shevchenko
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