From: Zhang Rui <rui.zhang@intel.com>
To: rjw@rjwysocki.net
Cc: linux-pm@vger.kernel.org, srinivas.pandruvada@intel.com,
rui.zhang@intel.com
Subject: [PATCH 08/13] intel_rapl: cleanup hardcoded MSR access
Date: Fri, 28 Jun 2019 13:50:24 +0800 [thread overview]
Message-ID: <1561701029-3415-9-git-send-email-rui.zhang@intel.com> (raw)
In-Reply-To: <1561701029-3415-1-git-send-email-rui.zhang@intel.com>
There are still some places in the common code that have hardcoded
MSR access, convert them to follow the abstracted register access.
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
---
drivers/powercap/intel_rapl.c | 38 ++++++++++++++++++++++----------------
1 file changed, 22 insertions(+), 16 deletions(-)
diff --git a/drivers/powercap/intel_rapl.c b/drivers/powercap/intel_rapl.c
index fbf91dd5..e476bd1 100644
--- a/drivers/powercap/intel_rapl.c
+++ b/drivers/powercap/intel_rapl.c
@@ -766,22 +766,24 @@ static int rapl_write_data_raw(struct rapl_domain *rd,
*/
static int rapl_check_unit_core(struct rapl_package *rp, int cpu)
{
- u64 msr_val;
+ struct reg_action ra;
u32 value;
- if (rdmsrl_safe_on_cpu(cpu, rp->priv->reg_unit, &msr_val)) {
- pr_err("Failed to read power unit MSR 0x%x on CPU %d, exit.\n",
+ ra.reg = rp->priv->reg_unit;
+ ra.mask = ~0;
+ if (rp->priv->read_raw(cpu, &ra)) {
+ pr_err("Failed to read power unit REG 0x%x on CPU %d, exit.\n",
rp->priv->reg_unit, cpu);
return -ENODEV;
}
- value = (msr_val & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET;
+ value = (ra.value & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET;
rp->energy_unit = ENERGY_UNIT_SCALE * 1000000 / (1 << value);
- value = (msr_val & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET;
+ value = (ra.value & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET;
rp->power_unit = 1000000 / (1 << value);
- value = (msr_val & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET;
+ value = (ra.value & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET;
rp->time_unit = 1000000 / (1 << value);
pr_debug("Core CPU %s energy=%dpJ, time=%dus, power=%duW\n",
@@ -792,21 +794,24 @@ static int rapl_check_unit_core(struct rapl_package *rp, int cpu)
static int rapl_check_unit_atom(struct rapl_package *rp, int cpu)
{
- u64 msr_val;
+ struct reg_action ra;
u32 value;
- if (rdmsrl_safe_on_cpu(cpu, rp->priv->reg_unit, &msr_val)) {
- pr_err("Failed to read power unit MSR 0x%x on CPU %d, exit.\n",
+ ra.reg = rp->priv->reg_unit;
+ ra.mask = ~0;
+ if (rp->priv->read_raw(cpu, &ra)) {
+ pr_err("Failed to read power unit REG 0x%x on CPU %d, exit.\n",
rp->priv->reg_unit, cpu);
return -ENODEV;
}
- value = (msr_val & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET;
+
+ value = (ra.value & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET;
rp->energy_unit = ENERGY_UNIT_SCALE * 1 << value;
- value = (msr_val & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET;
+ value = (ra.value & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET;
rp->power_unit = (1 << value) * 1000;
- value = (msr_val & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET;
+ value = (ra.value & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET;
rp->time_unit = 1000000 / (1 << value);
pr_debug("Atom %s energy=%dpJ, time=%dus, power=%duW\n",
@@ -1179,15 +1184,14 @@ static void rapl_remove_platform_domain(struct rapl_priv *priv)
static int rapl_check_domain(int cpu, int domain, struct rapl_package *rp)
{
- u32 reg;
- u64 val = 0;
+ struct reg_action ra;
switch (domain) {
case RAPL_DOMAIN_PACKAGE:
case RAPL_DOMAIN_PP0:
case RAPL_DOMAIN_PP1:
case RAPL_DOMAIN_DRAM:
- reg = rp->priv->regs[domain][RAPL_DOMAIN_REG_STATUS];
+ ra.reg = rp->priv->regs[domain][RAPL_DOMAIN_REG_STATUS];
break;
case RAPL_DOMAIN_PLATFORM:
/* PSYS(PLATFORM) is not a CPU domain, so avoid printng error */
@@ -1199,7 +1203,9 @@ static int rapl_check_domain(int cpu, int domain, struct rapl_package *rp)
/* make sure domain counters are available and contains non-zero
* values, otherwise skip it.
*/
- if (rdmsrl_safe_on_cpu(cpu, reg, &val) || !val)
+
+ ra.mask = ~0;
+ if (rp->priv->read_raw(cpu, &ra) || !ra.value)
return -ENODEV;
return 0;
--
2.7.4
next prev parent reply other threads:[~2019-06-28 5:50 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-28 5:50 [PATCH 00/13] intel_rapl: RAPL abstraction and MMIO RAPL support Zhang Rui
2019-06-28 5:50 ` [PATCH 01/13] intel_rapl: use reg instead of msr Zhang Rui
2019-06-28 5:50 ` [PATCH 02/13] intel_rapl: remove hardcoded register index Zhang Rui
2019-06-28 5:50 ` [PATCH 03/13] intel_rapl: introduce intel_rapl.h Zhang Rui
2019-07-02 22:01 ` Rafael J. Wysocki
2019-07-02 22:13 ` Pandruvada, Srinivas
2019-07-02 23:26 ` Rafael J. Wysocki
2019-06-28 5:50 ` [PATCH 04/13] intel_rapl: introduce struct rapl_private Zhang Rui
2019-07-02 21:44 ` Rafael J. Wysocki
2019-07-03 8:14 ` Zhang Rui
2019-06-28 5:50 ` [PATCH 05/13] intel_rapl: abstract register address Zhang Rui
2019-06-28 5:50 ` [PATCH 06/13] intel_rapl: abstract register access operations Zhang Rui
2019-07-02 21:56 ` Rafael J. Wysocki
2019-07-03 8:14 ` Zhang Rui
2019-06-28 5:50 ` [PATCH 07/13] intel_rapl: cleanup some functions Zhang Rui
2019-06-28 5:50 ` Zhang Rui [this message]
2019-06-28 5:50 ` [PATCH 09/13] intel_rapl: abstract RAPL common code Zhang Rui
2019-07-02 21:59 ` Rafael J. Wysocki
2019-07-03 8:23 ` Zhang Rui
2019-07-03 9:02 ` Rafael J. Wysocki
2019-07-02 22:45 ` Pandruvada, Srinivas
2019-06-28 5:50 ` [PATCH 10/13] intel_rapl: support 64 bit register Zhang Rui
2019-06-28 5:50 ` [PATCH 11/13] intel_rapl: support two power limits for every RAPL domain Zhang Rui
2019-06-28 5:50 ` [PATCH 12/13] int340X/processor_thermal_device: add support for MMIO RAPL Zhang Rui
2019-06-28 5:50 ` [PATCH 13/13] intel_rapl: Fix module autoloading issue Zhang Rui
-- strict thread matches above, loose matches on Subject: below --
2019-06-25 15:16 [PATCH 00/13] intel_rapl: RAPL abstraction and MMIO RAPL support Zhang Rui
2019-06-25 15:16 ` [PATCH 08/13] intel_rapl: cleanup hardcoded MSR access Zhang Rui
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