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From: "thermal-bot for Biju Das" <tip-bot2@linutronix.de>
To: linux-pm@vger.kernel.org
Cc: Biju Das <biju.das.jz@bp.renesas.com>,
	Geert Uytterhoeven <geert+renesas@glider.be>,
	Daniel Lezcano <daniel.lezcano@linaro.org>,
	rui.zhang@intel.com, amitk@kernel.org
Subject: [thermal: thermal/next] thermal/drivers/rz2gl: Fix OTP Calibration Register values
Date: Thu, 19 May 2022 12:44:09 -0000	[thread overview]
Message-ID: <165296424932.4207.992501972227598497.tip-bot2@tip-bot2> (raw)
In-Reply-To: <20220428093346.7552-1-biju.das.jz@bp.renesas.com>

The following commit has been merged into the thermal/next branch of thermal:

Commit-ID:     2d37f5c90bdc659b329dac7cf6d165a4bbf34cb6
Gitweb:        https://git.kernel.org/pub/scm/linux/kernel/git/thermal/linux.git//2d37f5c90bdc659b329dac7cf6d165a4bbf34cb6
Author:        Biju Das <biju.das.jz@bp.renesas.com>
AuthorDate:    Thu, 28 Apr 2022 10:33:46 +01:00
Committer:     Daniel Lezcano <daniel.lezcano@linaro.org>
CommitterDate: Thu, 19 May 2022 12:11:52 +02:00

thermal/drivers/rz2gl: Fix OTP Calibration Register values

As per the latest RZ/G2L Hardware User's Manual (Rev.1.10 Apr, 2022),
the bit 31 of TSU OTP Calibration Register(OTPTSUTRIM) indicates
whether bit [11:0] of OTPTSUTRIM is valid or invalid.

This patch updates the code to reflect this change.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20220428093346.7552-1-biju.das.jz@bp.renesas.com
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
 drivers/thermal/rzg2l_thermal.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/thermal/rzg2l_thermal.c b/drivers/thermal/rzg2l_thermal.c
index 7a9cdc1..be07e04 100644
--- a/drivers/thermal/rzg2l_thermal.c
+++ b/drivers/thermal/rzg2l_thermal.c
@@ -32,6 +32,8 @@
 #define TSU_SS		0x10
 
 #define OTPTSUTRIM_REG(n)	(0x18 + ((n) * 0x4))
+#define OTPTSUTRIM_EN_MASK	BIT(31)
+#define OTPTSUTRIM_MASK		GENMASK(11, 0)
 
 /* Sensor Mode Register(TSU_SM) */
 #define TSU_SM_EN_TS		BIT(0)
@@ -183,11 +185,15 @@ static int rzg2l_thermal_probe(struct platform_device *pdev)
 	pm_runtime_get_sync(dev);
 
 	priv->calib0 = rzg2l_thermal_read(priv, OTPTSUTRIM_REG(0));
-	if (!priv->calib0)
+	if (priv->calib0 & OTPTSUTRIM_EN_MASK)
+		priv->calib0 &= OTPTSUTRIM_MASK;
+	else
 		priv->calib0 = SW_CALIB0_VAL;
 
 	priv->calib1 = rzg2l_thermal_read(priv, OTPTSUTRIM_REG(1));
-	if (!priv->calib1)
+	if (priv->calib1 & OTPTSUTRIM_EN_MASK)
+		priv->calib1 &= OTPTSUTRIM_MASK;
+	else
 		priv->calib1 = SW_CALIB1_VAL;
 
 	platform_set_drvdata(pdev, priv);

      parent reply	other threads:[~2022-05-19 12:44 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-28  9:33 [PATCH] thermal/drivers/rz2gl: Fix OTP Calibration Register values Biju Das
2022-05-02 15:43 ` Geert Uytterhoeven
2022-05-09 10:01 ` Daniel Lezcano
2022-05-19 12:44 ` thermal-bot for Biju Das [this message]

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