Re: [PATCH V2] dt-bindings: thermal: mediatek,thermal: document AUXADC 32k clock

[AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>]

Il 09/02/24 06:52, Rafał Miłecki ha scritto:
> From: Rafał Miłecki <rafal@milecki.pl>
> 
> SoCs MT7981 and MT7986 include a newer thermal block (V3) that requires
> enabling one more clock called AUXADC 32k. Require it in binding.
> 
> Cc: Daniel Golle <daniel@makrotopia.org>
> Cc: Sam Shih <sam.shih@mediatek.com>
> Signed-off-by: Rafał Miłecki <rafal@milecki.pl>

So, I've made some research on this matter.. and this is a NACK.

I'll keep it short: you don't really have any 32KHz clock input for the ADC in
the infracfg clock controller (nor others).

What you're trying to say here is that you have a FastRC Oscillator input clock
(in your case, this is CLK_INFRA_ADC_FRC_CK): this clock is responsible for
providing an input clock of either 26MHz or something that is MPLL/16 (I do not
know what MPLL outputs on your platform, but those PLLs are usually giving out
"big numbers").

The FRC osc in the AUXADC will perhaps output a 32KHz clock for internal reference
and/or whatever else, but I'm not even sure that it's really going to be 32k then
internally to the IP block.

(I said "I'll keep it short" btw :-P)

Anyway.

The FRC clock is also required for the INFRA_ADC_26M clock to work correctly and,
in the clock controller driver(s) of both 7981 and 7986, that is parented to....
... surprise surprise ... INFRA_ADC_FRC_CK :-)


Finally, you do *not* need this commit, INFRA does *not* provide an adc_32k clock
to the thermal block, and you do *not* need to add the FRC clock in the devicetree
of 7981, nor 7986.

Mind you - at least in mt7986a.dtsi, there is an adc_32k clock in the thermal node,
so the right way to get your thermal node validated is not to modify the binding,
but to adhere to it by removing the extra, unneeded, clock.

Cheers!
Angelo