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[82.149.12.148]) by smtp.gmail.com with ESMTPSA id bh15-20020a05600c3d0f00b0040b4ccdcffbsm26013151wmb.2.2023.12.14.09.15.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Dec 2023 09:15:02 -0800 (PST) From: Jernej =?utf-8?B?xaBrcmFiZWM=?= To: Andre Przywara Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Samuel Holland , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Viresh Kumar , Yangtao Li , Brandon Cheo Fusi , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: Re: [PATCH 2/5] cpufreq: sun50i: Add D1 support Date: Thu, 14 Dec 2023 18:15:01 +0100 Message-ID: <1921146.taCxCBeP46@archlinux> In-Reply-To: <20231214164010.0be50a89@donnerap.manchester.arm.com> References: <20231214103342.30775-1-fusibrandon13@gmail.com> <8351928.NyiUUSuA9g@archlinux> <20231214164010.0be50a89@donnerap.manchester.arm.com> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="UTF-8" On Thursday, December 14, 2023 5:40:10 PM CET Andre Przywara wrote: > On Thu, 14 Dec 2023 17:29:30 +0100 > Jernej =C5=A0krabec wrote: >=20 > Hi, >=20 > > On Thursday, December 14, 2023 11:33:39 AM CET Brandon Cheo Fusi wrote: > > > Add support for D1 based devices to the Allwinner H6 cpufreq > > > driver > > >=20 > > > Signed-off-by: Brandon Cheo Fusi > > > --- > > > drivers/cpufreq/sun50i-cpufreq-nvmem.c | 1 + > > > 1 file changed, 1 insertion(+) > > >=20 > > > diff --git a/drivers/cpufreq/sun50i-cpufreq-nvmem.c b/drivers/cpufreq= /sun50i-cpufreq-nvmem.c > > > index 32a9c88f8..ccf83780f 100644 > > > --- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c > > > +++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c > > > @@ -160,6 +160,7 @@ static struct platform_driver sun50i_cpufreq_driv= er =3D { > > > =20 > > > static const struct of_device_id sun50i_cpufreq_match_list[] =3D { > > > { .compatible =3D "allwinner,sun50i-h6" }, > > > + { .compatible =3D "allwinner,sun20i-d1" }, =20 > >=20 > > This is not needed, as there is no functionality change. >=20 > That was my first reflex, too, but this is the *board* (fallback) > compatible, listed in the root node, so you have to list it here for each > SoC, together with the respective blocklist in the next patch. > We are doing the same for the H616, and actually also need that for the > H618. Weird, I know, but last time I check not easy to fix. Oh, that's bad. What's the rationale to have so complicated probe method? Why not using standard, compatible based one? Best regards, Jernej