From: "Rafael J. Wysocki" <rjw@sisk.pl>
To: Shaohua Li <shaohua.li@intel.com>
Cc: Matthew Garrett <mjg59@srcf.ucam.org>,
linux acpi <linux-acpi@vger.kernel.org>,
linux-pm <linux-pm@lists.osdl.org>,
Alan Stern <stern@rowland.harvard.edu>
Subject: Re: [PATCH 4/5]PCIe native PME support
Date: Thu, 20 Aug 2009 22:07:20 +0200 [thread overview]
Message-ID: <200908202207.20923.rjw@sisk.pl> (raw)
In-Reply-To: <20090820031056.GB26357@sli10-desk.sh.intel.com>
On Thursday 20 August 2009, Shaohua Li wrote:
> On Wed, Aug 19, 2009 at 07:58:11PM +0800, Matthew Garrett wrote:
> > On Wed, Aug 19, 2009 at 03:24:19PM +0800, Shaohua Li wrote:
> >
> > > +static inline void npme_enable_pme(struct pci_dev *pdev, bool enable)
> > > +{
> > > + int pos;
> > > + u16 rtctl;
> > > +
> > > + pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
> > > +
> > > + pci_read_config_word(pdev, pos + PCI_EXP_RTCTL, &rtctl);
> > > + if (!enable)
> > > + rtctl &= ~PCI_EXP_RTCTL_PMEIE;
> > > + else
> > > + rtctl |= PCI_EXP_RTCTL_PMEIE;
> > > + pci_write_config_word(pdev, pos + PCI_EXP_RTCTL, rtctl);
> > > +}
> >
> > This seems to duplicate the existing pci_pme_active() function?
> No, these registers are completely different. pci_pme_active is to handle
> the PM capability regiser. This routine is to handle the PCI express capability.
>
> > > +static inline void npme_clear_pme(struct pci_dev *pdev)
> > > +{
> > > + int pos;
> > > + u32 rtsta;
> > > +
> > > + pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
> > > +
> > > + pci_read_config_dword(pdev, pos + PCI_EXP_RTSTA, &rtsta);
> > > + rtsta |= PCI_EXP_RTSTA_PME;
> > > + pci_write_config_dword(pdev, pos + PCI_EXP_RTSTA, rtsta);
> > > +}
> >
> > Ditto.
> Ditto.
>
> > > +static bool npme_pme_target(struct pci_dev *target)
> > > +{
> > > + bool ret = false;
> > > + if (target->dev.bus->pm && target->dev.bus->pm->wakeup_event)
> > > + ret = target->dev.bus->pm->wakeup_event(&target->dev);
> > > + return ret;
> > > +}
> >
> > Is there any situation in which we wouldn't want to just perform a
> > runtime resume of the device here?
> The devices pcie-to-pci bridge can send wakeup event, but the event might use
> root port or the bridge pci id, so can't directly send the event to the device.
>
> Surely we can move the logic in my patch 3 here if we don't want to duplicate
> code, and then we can directly perform a runtime resume for target devices.
Do that, please.
Rafael
next prev parent reply other threads:[~2009-08-20 20:07 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-08-19 7:24 [PATCH 4/5]PCIe native PME support Shaohua Li
2009-08-19 11:58 ` Matthew Garrett
2009-08-20 3:10 ` Shaohua Li
2009-08-20 20:07 ` Rafael J. Wysocki [this message]
2009-08-20 21:22 ` Rafael J. Wysocki
[not found] ` <200908202322.02588.rjw@sisk.pl>
2009-08-21 7:01 ` Shaohua Li
[not found] ` <20090821070112.GC16694@sli10-desk.sh.intel.com>
2009-08-21 16:47 ` Rafael J. Wysocki
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=200908202207.20923.rjw@sisk.pl \
--to=rjw@sisk.pl \
--cc=linux-acpi@vger.kernel.org \
--cc=linux-pm@lists.osdl.org \
--cc=mjg59@srcf.ucam.org \
--cc=shaohua.li@intel.com \
--cc=stern@rowland.harvard.edu \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox