From mboxrd@z Thu Jan  1 00:00:00 1970
From: Jacob Pan <jacob.jun.pan@linux.intel.com>
Subject: Re: [PATCH v2 6/6] Introduce Intel RAPL power capping driver
Date: Fri, 4 Oct 2013 13:12:28 -0700
Message-ID: <20131004131228.54eb7098@ultegra>
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To: Joe Perches <joe@perches.com>
Cc: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, gregkh@linuxfoundation.org, len.brown@intel.com, rjw@sisk.pl, arjan@linux.intel.com

On Fri, 04 Oct 2013 11:07:45 -0700
Joe Perches <joe@perches.com> wrote:

> On Fri, 2013-10-04 at 09:36 -0700, Srinivas Pandruvada wrote:
> > The Intel Running Average Power Limit(RAPL) technology provides
> > platform software with the ability to monitor, control, and get
> > notifications on power usage.
> []
> > diff --git a/drivers/powercap/Makefile b/drivers/powercap/Makefile
> []
> > +/* bitmasks for RAPL MSRs, used by primitive access functions */
> > +#define ENERGY_STATUS_MASK      0xffffffff
> > +
> > +#define POWER_LIMIT1_MASK       0x7FFF
> > +#define POWER_LIMIT1_ENABLE     BIT(15)
> > +#define POWER_LIMIT1_CLAMP      BIT(16)
> > +
> > +#define POWER_LIMIT2_MASK       (0x7FFFULL<<32)
> > +#define POWER_LIMIT2_ENABLE     BIT_ULL(47)
> > +#define POWER_LIMIT2_CLAMP      BIT_ULL(48)
> > +#define POWER_PACKAGE_LOCK      BIT_ULL(63)
> > +#define POWER_PP_LOCK           BIT(31)
> > +
> > +#define TIME_WINDOW1_MASK       (0x7F<<17)
> > +#define TIME_WINDOW2_MASK       (0x7FULL<<49)
> 
> 
> Is there a reason why these masks aren't all ULL?
> 
> 

are you referring to this line below not being ULL?
> > +#define TIME_WINDOW1_MASK       (0x7F<<17)
if this is the case, I did that because it is not more than 32 bit.

Thanks,

Jacob