From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mark Rutland Subject: Re: [PATCH v4 4/4] mvebu: Dove: Add clocks and DFS interrupt to cpu node in DT. Date: Wed, 4 Dec 2013 14:39:21 +0000 Message-ID: <20131204143921.GC29200@e106331-lin.cambridge.arm.com> References: <1386166641-7567-1-git-send-email-andrew@lunn.ch> <1386166641-7567-5-git-send-email-andrew@lunn.ch> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Received: from cam-admin0.cambridge.arm.com ([217.140.96.50]:47421 "EHLO cam-admin0.cambridge.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932165Ab3LDOjt (ORCPT ); Wed, 4 Dec 2013 09:39:49 -0500 Content-Disposition: inline In-Reply-To: <1386166641-7567-5-git-send-email-andrew@lunn.ch> Sender: linux-pm-owner@vger.kernel.org List-Id: linux-pm@vger.kernel.org To: Andrew Lunn Cc: "rjw@rjwysocki.net" , "viresh.kumar@linaro.org" , Jason Cooper , Sebastian Hesselbarth , linux ARM , "linux-pm@vger.kernel.org" On Wed, Dec 04, 2013 at 02:17:21PM +0000, Andrew Lunn wrote: > The dove-cpufreq driver needs access to the DDR and CPU clock. There > is also an interrupt generated when the DFS hardware completes a > change of frequencey. Add these to the cpu node in DT. > > Signed-off-by: Andrew Lunn > Tested-by: Sebastian Hesselbarth > --- > arch/arm/boot/dts/dove.dtsi | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi > index 4c8028513133..3842ba02dddf 100644 > --- a/arch/arm/boot/dts/dove.dtsi > +++ b/arch/arm/boot/dts/dove.dtsi > @@ -22,6 +22,10 @@ > device_type = "cpu"; > next-level-cache = <&l2>; > reg = <0>; > + clocks = <&core_clk 1>, <&core_clk 3>; > + clock-names = "cpu_clk", "ddrclk"; > + interrupt-parent = <&pmu_intc>; > + interrupts = <0>; Is this interrupt actually generated by the CPU, or by the power management unit? Is ddrclk actually fed into the CPU? Given that you seem to have an external L2 I don't see why the CPU would need the DDR clock. Thanks, Mark.