[PATCH v3 0/3] firmware: qcom: scm: Add cpu power on/off support

[PATCH v3 0/3] firmware: qcom: scm: Add cpu power on/off support

[Lina Iyer]

Hi,

This series of patches adds SCM cold boot clean up and support for warm boot
for QCOM quad core (and dual core) cpus.

v3 Changed:
- Addressed review comments from Kumar.
	+ Cleaned up the cold boot api and the warm boot api to match
	+ Uniform qcom_scm_ prefix
- Add support for cpu power down using scm_call_atomic1() from [1].
	+ No longer dependent on the series from sboyd.

v2 Changes:
- Merge the warm boot patches into a single patch.

[1]. https://lkml.org/lkml/2014/8/4/765

Thanks,
Lina

Lina Iyer (3):
  firmware: qcom: scm: Clean cold boot entry to export only the API
  firmware: qcom: scm: Add qcom_scm_set_warm_boot_addr function
  firmware: qcom: scm: Support cpu power down through SCM

 arch/arm/mach-qcom/platsmp.c |  21 +-----
 drivers/firmware/qcom_scm.c  | 154 ++++++++++++++++++++++++++++++++++++++++++-
 include/linux/qcom_scm.h     |  16 ++---
 3 files changed, 162 insertions(+), 29 deletions(-)

-- 
2.1.0

[PATCH v3 1/3] firmware: qcom: scm: Clean cold boot entry to export only the API

[Lina Iyer]

We dont need to export the SCM specific cold boot flags to the platform
code. Export only a function to set the cold boot address.

Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
---
 arch/arm/mach-qcom/platsmp.c | 21 +++------------------
 drivers/firmware/qcom_scm.c  | 41 +++++++++++++++++++++++++++++++++++++++--
 include/linux/qcom_scm.h     |  5 +----
 3 files changed, 43 insertions(+), 24 deletions(-)

diff --git a/arch/arm/mach-qcom/platsmp.c b/arch/arm/mach-qcom/platsmp.c
index 4b67e56..5cde63a 100644
--- a/arch/arm/mach-qcom/platsmp.c
+++ b/arch/arm/mach-qcom/platsmp.c
@@ -319,25 +319,10 @@ static int kpssv2_boot_secondary(unsigned int cpu, struct task_struct *idle)
 
 static void __init qcom_smp_prepare_cpus(unsigned int max_cpus)
 {
-	int cpu, map;
-	unsigned int flags = 0;
-	static const int cold_boot_flags[] = {
-		0,
-		QCOM_SCM_FLAG_COLDBOOT_CPU1,
-		QCOM_SCM_FLAG_COLDBOOT_CPU2,
-		QCOM_SCM_FLAG_COLDBOOT_CPU3,
-	};
-
-	for_each_present_cpu(cpu) {
-		map = cpu_logical_map(cpu);
-		if (WARN_ON(map >= ARRAY_SIZE(cold_boot_flags))) {
-			set_cpu_present(cpu, false);
-			continue;
-		}
-		flags |= cold_boot_flags[map];
-	}
+	int cpu;
 
-	if (qcom_scm_set_boot_addr(virt_to_phys(secondary_startup_arm), flags)) {
+	if (qcom_scm_set_cold_boot_addr(secondary_startup_arm,
+					cpu_present_mask)) {
 		for_each_present_cpu(cpu) {
 			if (cpu == smp_processor_id())
 				continue;
diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
index 6e7a72b..c953cc3 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
@@ -34,6 +34,11 @@
 #define QCOM_SCM_ERROR		-1
 #define QCOM_SCM_INTERRUPTED	1
 
+#define QCOM_SCM_FLAG_COLDBOOT_CPU0	0x00
+#define QCOM_SCM_FLAG_COLDBOOT_CPU1	0x01
+#define QCOM_SCM_FLAG_COLDBOOT_CPU2	0x08
+#define QCOM_SCM_FLAG_COLDBOOT_CPU3	0x20
+
 static DEFINE_MUTEX(qcom_scm_lock);
 
 /**
@@ -329,7 +334,7 @@ EXPORT_SYMBOL(qcom_scm_get_version);
 /*
  * Set the cold/warm boot address for one of the CPU cores.
  */
-int qcom_scm_set_boot_addr(u32 addr, int flags)
+static int qcom_scm_set_boot_addr(u32 addr, int flags)
 {
 	struct {
 		__le32 flags;
@@ -341,4 +346,36 @@ int qcom_scm_set_boot_addr(u32 addr, int flags)
 	return qcom_scm_call(QCOM_SCM_SVC_BOOT, QCOM_SCM_BOOT_ADDR,
 			&cmd, sizeof(cmd), NULL, 0);
 }
-EXPORT_SYMBOL(qcom_scm_set_boot_addr);
+
+/**
+ * qcom_scm_set_cold_boot_addr() - Set the cold boot address for cpus
+ * @entry: Entry point function for the cpus
+ * @cpus: The cpumask of cpus that will use the entry point
+ *
+ * Set the cold boot address of the cpus. Any cpu outside the supported
+ * range would be removed from the cpu present mask.
+ */
+int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
+{
+	int flags = 0;
+	int cpu;
+	int scm_cb_flags[] = {
+		QCOM_SCM_FLAG_COLDBOOT_CPU0,
+		QCOM_SCM_FLAG_COLDBOOT_CPU1,
+		QCOM_SCM_FLAG_COLDBOOT_CPU2,
+		QCOM_SCM_FLAG_COLDBOOT_CPU3,
+	};
+
+	if (!cpus || (cpus && cpumask_empty(cpus)))
+		return -EINVAL;
+
+	for_each_cpu(cpu, cpus) {
+		if (cpu < ARRAY_SIZE(scm_cb_flags))
+			flags |= scm_cb_flags[cpu];
+		else
+			set_cpu_present(cpu, false);
+	}
+
+	return qcom_scm_set_boot_addr(virt_to_phys(entry), flags);
+}
+EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);
diff --git a/include/linux/qcom_scm.h b/include/linux/qcom_scm.h
index 6bb84cf..68a1d88 100644
--- a/include/linux/qcom_scm.h
+++ b/include/linux/qcom_scm.h
@@ -12,15 +12,12 @@
 #ifndef __QCOM_SCM_H
 #define __QCOM_SCM_H
 
-#define QCOM_SCM_FLAG_COLDBOOT_CPU1		0x01
-#define QCOM_SCM_FLAG_COLDBOOT_CPU2		0x08
-#define QCOM_SCM_FLAG_COLDBOOT_CPU3		0x20
 #define QCOM_SCM_FLAG_WARMBOOT_CPU0		0x04
 #define QCOM_SCM_FLAG_WARMBOOT_CPU1		0x02
 #define QCOM_SCM_FLAG_WARMBOOT_CPU2		0x10
 #define QCOM_SCM_FLAG_WARMBOOT_CPU3		0x40
 
-extern int qcom_scm_set_boot_addr(u32 addr, int flags);
+extern int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
 
 #define QCOM_SCM_VERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
 
-- 
2.1.0

[PATCH v3 2/3] firmware: qcom: scm: Add qcom_scm_set_warm_boot_addr function

[Lina Iyer]

A core can be powered down for cpuidle or when it is hotplugged off. In
either case, the warmboot return address would be different. Allow
setting the warmboot address for a specific cpu, optimize and write to
the firmware, if the address is different than the previously set
address.

Export qcom_scm_set_warm_boot_addr function move the warm boot flags to
implementation.

Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
---
 drivers/firmware/qcom_scm.c | 56 +++++++++++++++++++++++++++++++++++++++++++++
 include/linux/qcom_scm.h    |  7 ++----
 2 files changed, 58 insertions(+), 5 deletions(-)

diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
index c953cc3..4d8ede4 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
@@ -1,4 +1,5 @@
 /* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ * Copyright (C) 2015 Linaro Ltd.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -39,6 +40,23 @@
 #define QCOM_SCM_FLAG_COLDBOOT_CPU2	0x08
 #define QCOM_SCM_FLAG_COLDBOOT_CPU3	0x20
 
+#define QCOM_SCM_FLAG_WARMBOOT_CPU0	0x04
+#define QCOM_SCM_FLAG_WARMBOOT_CPU1	0x02
+#define QCOM_SCM_FLAG_WARMBOOT_CPU2	0x10
+#define QCOM_SCM_FLAG_WARMBOOT_CPU3	0x40
+
+struct qcom_scm_entry {
+	int flag;
+	void *entry;
+};
+
+static struct qcom_scm_entry qcom_scm_wb[] = {
+	{ .flag = QCOM_SCM_FLAG_WARMBOOT_CPU0 },
+	{ .flag = QCOM_SCM_FLAG_WARMBOOT_CPU1 },
+	{ .flag = QCOM_SCM_FLAG_WARMBOOT_CPU2 },
+	{ .flag = QCOM_SCM_FLAG_WARMBOOT_CPU3 },
+};
+
 static DEFINE_MUTEX(qcom_scm_lock);
 
 /**
@@ -379,3 +397,41 @@ int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
 	return qcom_scm_set_boot_addr(virt_to_phys(entry), flags);
 }
 EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);
+
+/**
+ * qcom_scm_set_warm_boot_addr() - Set the warm boot address for cpus
+ * @entry: Entry point function for the cpus
+ * @cpus: The cpumask of cpus that will use the entry point
+ *
+ * Set the Linux entry point for the SCM to transfer control to when coming
+ * out of a power down. CPU power down may be executed on cpuidle or hotplug.
+ */
+int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
+{
+	int ret;
+	int flags = 0;
+	int cpu;
+
+	/*
+	 * Reassign only if we are switching from hotplug entry point
+	 * to cpuidle entry point or vice versa.
+	 */
+	for_each_cpu(cpu, cpus) {
+		if (entry == qcom_scm_wb[cpu].entry)
+			continue;
+		flags |= qcom_scm_wb[cpu].flag;
+	}
+
+	/* No change in entry function */
+	if (!flags)
+		return 0;
+
+	ret = qcom_scm_set_boot_addr(virt_to_phys(entry), flags);
+	if (!ret) {
+		for_each_cpu(cpu, cpus)
+			qcom_scm_wb[cpu].entry = entry;
+	}
+
+	return ret;
+}
+EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);
diff --git a/include/linux/qcom_scm.h b/include/linux/qcom_scm.h
index 68a1d88..95ef72a 100644
--- a/include/linux/qcom_scm.h
+++ b/include/linux/qcom_scm.h
@@ -1,4 +1,5 @@
 /* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ * Copyright (C) 2015 Linaro Ltd.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -12,12 +13,8 @@
 #ifndef __QCOM_SCM_H
 #define __QCOM_SCM_H
 
-#define QCOM_SCM_FLAG_WARMBOOT_CPU0		0x04
-#define QCOM_SCM_FLAG_WARMBOOT_CPU1		0x02
-#define QCOM_SCM_FLAG_WARMBOOT_CPU2		0x10
-#define QCOM_SCM_FLAG_WARMBOOT_CPU3		0x40
-
 extern int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
+extern int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus);
 
 #define QCOM_SCM_VERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
 
-- 
2.1.0

[PATCH v3 3/3] firmware: qcom: scm: Support cpu power down through SCM

[Lina Iyer]

Support powering down the calling cpu, by trapping into SCM. This
termination function triggers the ARM cpu to execute WFI instruction,
causing the power controller to safely power the cpu down.

Caches may be flushed before powering down the cpu. If cache controller
is set to turn off when the cpu is powered down, then the flags argument
indicates to the secure mode to flush its cache lines before executing
WFI.The warm boot reset address for the cpu should be set before the
calling into this function for the cpu to resume.

The original code for the qcom_scm_call_atomic1() comes from a patch by
Stephen Boyd [1]. The function scm_call_atomic1() has been cherry picked
and renamed to match the convention used in this file. Since there are
no users of scm_call_atomic2(), the function is not included.

[1]. https://lkml.org/lkml/2014/8/4/765

Signed-off-by: Stephen Boyd <sboyd@codeauraro.org>
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
---
 drivers/firmware/qcom_scm.c | 57 +++++++++++++++++++++++++++++++++++++++++++++
 include/linux/qcom_scm.h    |  6 ++++-
 2 files changed, 62 insertions(+), 1 deletion(-)

diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
index 4d8ede4..994b50f 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
@@ -311,6 +311,45 @@ out:
 	return ret;
 }
 
+#define SCM_CLASS_REGISTER	(0x2 << 8)
+#define SCM_MASK_IRQS		BIT(5)
+#define SCM_ATOMIC(svc, cmd, n) (((((svc) << 10)|((cmd) & 0x3ff)) << 12) | \
+				SCM_CLASS_REGISTER | \
+				SCM_MASK_IRQS | \
+				(n & 0xf))
+
+/**
+ * qcom_scm_call_atomic1() - Send an atomic SCM command with one argument
+ * @svc_id: service identifier
+ * @cmd_id: command identifier
+ * @arg1: first argument
+ *
+ * This shall only be used with commands that are guaranteed to be
+ * uninterruptable, atomic and SMP safe.
+ */
+static s32 qcom_scm_call_atomic1(u32 svc, u32 cmd, u32 arg1)
+{
+	int context_id;
+
+	register u32 r0 asm("r0") = SCM_ATOMIC(svc, cmd, 1);
+	register u32 r1 asm("r1") = (u32)&context_id;
+	register u32 r2 asm("r2") = arg1;
+
+	asm volatile(
+			__asmeq("%0", "r0")
+			__asmeq("%1", "r0")
+			__asmeq("%2", "r1")
+			__asmeq("%3", "r2")
+#ifdef REQUIRES_SEC
+			".arch_extension sec\n"
+#endif
+			"smc    #0      @ switch to secure world\n"
+			: "=r" (r0)
+			: "r" (r0), "r" (r1), "r" (r2)
+			: "r3");
+	return r0;
+}
+
 u32 qcom_scm_get_version(void)
 {
 	int context_id;
@@ -435,3 +474,21 @@ int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
 	return ret;
 }
 EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);
+
+#define QCOM_SCM_CMD_TERMINATE_PC	0x2
+#define QCOM_SCM_FLUSH_FLAG_MASK	0x3
+
+/**
+ * qcom_scm_cpu_power_down() - Power down the cpu
+ * @flags - Flags to flush cache
+ *
+ * This is an end point to power down cpu. If there was a pending interrupt,
+ * the control would return from this function, otherwise, the cpu jumps to the
+ * warm boot entry point set for this cpu upon reset.
+ */
+void qcom_scm_cpu_power_down(u32 flags)
+{
+	qcom_scm_call_atomic1(QCOM_SCM_SVC_BOOT, QCOM_SCM_CMD_TERMINATE_PC,
+			flags & QCOM_SCM_FLUSH_FLAG_MASK);
+}
+EXPORT_SYMBOL(qcom_scm_cpu_power_down);
diff --git a/include/linux/qcom_scm.h b/include/linux/qcom_scm.h
index 95ef72a..0f26f44 100644
--- a/include/linux/qcom_scm.h
+++ b/include/linux/qcom_scm.h
@@ -1,4 +1,4 @@
-/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2010-2014, The Linux Foundation. All rights reserved.
  * Copyright (C) 2015 Linaro Ltd.
  *
  * This program is free software; you can redistribute it and/or modify
@@ -13,8 +13,12 @@
 #ifndef __QCOM_SCM_H
 #define __QCOM_SCM_H
 
+#define QCOM_SCM_L2_ON		0x0
+#define QCOM_SCM_L2_OFF		0x1
+
 extern int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
 extern int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus);
+extern void qcom_scm_cpu_power_down(u32 flags);
 
 #define QCOM_SCM_VERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
 
-- 
2.1.0

Re: [PATCH v3 3/3] firmware: qcom: scm: Support cpu power down through SCM

[Kumar Gala]

On Mar 2, 2015, at 2:30 PM, Lina Iyer <lina.iyer@linaro.org> wrote:

> Support powering down the calling cpu, by trapping into SCM. This
> termination function triggers the ARM cpu to execute WFI instruction,
> causing the power controller to safely power the cpu down.
> 
> Caches may be flushed before powering down the cpu. If cache controller
> is set to turn off when the cpu is powered down, then the flags argument
> indicates to the secure mode to flush its cache lines before executing
> WFI.The warm boot reset address for the cpu should be set before the
> calling into this function for the cpu to resume.
> 
> The original code for the qcom_scm_call_atomic1() comes from a patch by
> Stephen Boyd [1]. The function scm_call_atomic1() has been cherry picked
> and renamed to match the convention used in this file. Since there are
> no users of scm_call_atomic2(), the function is not included.
> 
> [1]. https://lkml.org/lkml/2014/8/4/765
> 
> Signed-off-by: Stephen Boyd <sboyd@codeauraro.org>
> Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
> ---
> drivers/firmware/qcom_scm.c | 57 +++++++++++++++++++++++++++++++++++++++++++++
> include/linux/qcom_scm.h    |  6 ++++-
> 2 files changed, 62 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
> index 4d8ede4..994b50f 100644
> --- a/drivers/firmware/qcom_scm.c
> +++ b/drivers/firmware/qcom_scm.c
> @@ -311,6 +311,45 @@ out:
> 	return ret;
> }
> 
> +#define SCM_CLASS_REGISTER	(0x2 << 8)
> +#define SCM_MASK_IRQS		BIT(5)
> +#define SCM_ATOMIC(svc, cmd, n) (((((svc) << 10)|((cmd) & 0x3ff)) << 12) | \
> +				SCM_CLASS_REGISTER | \
> +				SCM_MASK_IRQS | \
> +				(n & 0xf))
> +
> +/**
> + * qcom_scm_call_atomic1() - Send an atomic SCM command with one argument
> + * @svc_id: service identifier
> + * @cmd_id: command identifier
> + * @arg1: first argument
> + *
> + * This shall only be used with commands that are guaranteed to be
> + * uninterruptable, atomic and SMP safe.
> + */
> +static s32 qcom_scm_call_atomic1(u32 svc, u32 cmd, u32 arg1)
> +{
> +	int context_id;
> +
> +	register u32 r0 asm("r0") = SCM_ATOMIC(svc, cmd, 1);
> +	register u32 r1 asm("r1") = (u32)&context_id;
> +	register u32 r2 asm("r2") = arg1;
> +
> +	asm volatile(
> +			__asmeq("%0", "r0")
> +			__asmeq("%1", "r0")
> +			__asmeq("%2", "r1")
> +			__asmeq("%3", "r2")
> +#ifdef REQUIRES_SEC
> +			".arch_extension sec\n"
> +#endif
> +			"smc    #0      @ switch to secure world\n"
> +			: "=r" (r0)
> +			: "r" (r0), "r" (r1), "r" (r2)
> +			: "r3");
> +	return r0;
> +}
> +
> u32 qcom_scm_get_version(void)
> {
> 	int context_id;
> @@ -435,3 +474,21 @@ int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
> 	return ret;
> }
> EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);
> +
> +#define QCOM_SCM_CMD_TERMINATE_PC	0x2
> +#define QCOM_SCM_FLUSH_FLAG_MASK	0x3

why is the mask 0x3 and not 0x1?

> +
> +/**
> + * qcom_scm_cpu_power_down() - Power down the cpu
> + * @flags - Flags to flush cache
> + *
> + * This is an end point to power down cpu. If there was a pending interrupt,
> + * the control would return from this function, otherwise, the cpu jumps to the
> + * warm boot entry point set for this cpu upon reset.
> + */
> +void qcom_scm_cpu_power_down(u32 flags)
> +{
> +	qcom_scm_call_atomic1(QCOM_SCM_SVC_BOOT, QCOM_SCM_CMD_TERMINATE_PC,
> +			flags & QCOM_SCM_FLUSH_FLAG_MASK);
> +}
> +EXPORT_SYMBOL(qcom_scm_cpu_power_down);
> diff --git a/include/linux/qcom_scm.h b/include/linux/qcom_scm.h
> index 95ef72a..0f26f44 100644
> --- a/include/linux/qcom_scm.h
> +++ b/include/linux/qcom_scm.h
> @@ -1,4 +1,4 @@
> -/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
> +/* Copyright (c) 2010-2014, The Linux Foundation. All rights reserved.
>  * Copyright (C) 2015 Linaro Ltd.
>  *
>  * This program is free software; you can redistribute it and/or modify
> @@ -13,8 +13,12 @@
> #ifndef __QCOM_SCM_H
> #define __QCOM_SCM_H
> 
> +#define QCOM_SCM_L2_ON		0x0
> +#define QCOM_SCM_L2_OFF		0x1

One, can you move this below qcom_scm_set_warm_boot_addr so they are closer to qcom_scm_cpu_power_down.  Also, we probably need to prefix the names to be clear the flags are associated with qcom_scm_cpu_power_down.  QCOM_SCM_CPU_PWR_DOWN_{L2_ON,L2_OFF}?

> +
> extern int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
> extern int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus);
> +extern void qcom_scm_cpu_power_down(u32 flags);
> 
> #define QCOM_SCM_VERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
> 
> -- 
> 2.1.0
> 

- k

-- 
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH v3 3/3] firmware: qcom: scm: Support cpu power down through SCM

[Lina Iyer]

On Mon, Mar 02 2015 at 13:52 -0700, Kumar Gala wrote:
>
>On Mar 2, 2015, at 2:30 PM, Lina Iyer <lina.iyer@linaro.org> wrote:
>
>> Support powering down the calling cpu, by trapping into SCM. This
>> termination function triggers the ARM cpu to execute WFI instruction,
>> causing the power controller to safely power the cpu down.
>>
>> Caches may be flushed before powering down the cpu. If cache controller
>> is set to turn off when the cpu is powered down, then the flags argument
>> indicates to the secure mode to flush its cache lines before executing
>> WFI.The warm boot reset address for the cpu should be set before the
>> calling into this function for the cpu to resume.
>>
>> The original code for the qcom_scm_call_atomic1() comes from a patch by
>> Stephen Boyd [1]. The function scm_call_atomic1() has been cherry picked
>> and renamed to match the convention used in this file. Since there are
>> no users of scm_call_atomic2(), the function is not included.
>>
>> [1]. https://lkml.org/lkml/2014/8/4/765
>>
>> Signed-off-by: Stephen Boyd <sboyd@codeauraro.org>
>> Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
>> ---
>> drivers/firmware/qcom_scm.c | 57 +++++++++++++++++++++++++++++++++++++++++++++
>> include/linux/qcom_scm.h    |  6 ++++-
>> 2 files changed, 62 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
>> index 4d8ede4..994b50f 100644
>> --- a/drivers/firmware/qcom_scm.c
>> +++ b/drivers/firmware/qcom_scm.c
>> @@ -311,6 +311,45 @@ out:
>> 	return ret;
>> }
>>
>> +#define SCM_CLASS_REGISTER	(0x2 << 8)
>> +#define SCM_MASK_IRQS		BIT(5)
>> +#define SCM_ATOMIC(svc, cmd, n) (((((svc) << 10)|((cmd) & 0x3ff)) << 12) | \
>> +				SCM_CLASS_REGISTER | \
>> +				SCM_MASK_IRQS | \
>> +				(n & 0xf))
>> +
>> +/**
>> + * qcom_scm_call_atomic1() - Send an atomic SCM command with one argument
>> + * @svc_id: service identifier
>> + * @cmd_id: command identifier
>> + * @arg1: first argument
>> + *
>> + * This shall only be used with commands that are guaranteed to be
>> + * uninterruptable, atomic and SMP safe.
>> + */
>> +static s32 qcom_scm_call_atomic1(u32 svc, u32 cmd, u32 arg1)
>> +{
>> +	int context_id;
>> +
>> +	register u32 r0 asm("r0") = SCM_ATOMIC(svc, cmd, 1);
>> +	register u32 r1 asm("r1") = (u32)&context_id;
>> +	register u32 r2 asm("r2") = arg1;
>> +
>> +	asm volatile(
>> +			__asmeq("%0", "r0")
>> +			__asmeq("%1", "r0")
>> +			__asmeq("%2", "r1")
>> +			__asmeq("%3", "r2")
>> +#ifdef REQUIRES_SEC
>> +			".arch_extension sec\n"
>> +#endif
>> +			"smc    #0      @ switch to secure world\n"
>> +			: "=r" (r0)
>> +			: "r" (r0), "r" (r1), "r" (r2)
>> +			: "r3");
>> +	return r0;
>> +}
>> +
>> u32 qcom_scm_get_version(void)
>> {
>> 	int context_id;
>> @@ -435,3 +474,21 @@ int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
>> 	return ret;
>> }
>> EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);
>> +
>> +#define QCOM_SCM_CMD_TERMINATE_PC	0x2
>> +#define QCOM_SCM_FLUSH_FLAG_MASK	0x3
>
>why is the mask 0x3 and not 0x1?
>
Per the secure code, this is a 2 bit entity, hence a 0x3 for the mask.

>> +
>> +/**
>> + * qcom_scm_cpu_power_down() - Power down the cpu
>> + * @flags - Flags to flush cache
>> + *
>> + * This is an end point to power down cpu. If there was a pending interrupt,
>> + * the control would return from this function, otherwise, the cpu jumps to the
>> + * warm boot entry point set for this cpu upon reset.
>> + */
>> +void qcom_scm_cpu_power_down(u32 flags)
>> +{
>> +	qcom_scm_call_atomic1(QCOM_SCM_SVC_BOOT, QCOM_SCM_CMD_TERMINATE_PC,
>> +			flags & QCOM_SCM_FLUSH_FLAG_MASK);
>> +}
>> +EXPORT_SYMBOL(qcom_scm_cpu_power_down);
>> diff --git a/include/linux/qcom_scm.h b/include/linux/qcom_scm.h
>> index 95ef72a..0f26f44 100644
>> --- a/include/linux/qcom_scm.h
>> +++ b/include/linux/qcom_scm.h
>> @@ -1,4 +1,4 @@
>> -/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
>> +/* Copyright (c) 2010-2014, The Linux Foundation. All rights reserved.
>>  * Copyright (C) 2015 Linaro Ltd.
>>  *
>>  * This program is free software; you can redistribute it and/or modify
>> @@ -13,8 +13,12 @@
>> #ifndef __QCOM_SCM_H
>> #define __QCOM_SCM_H
>>
>> +#define QCOM_SCM_L2_ON		0x0
>> +#define QCOM_SCM_L2_OFF		0x1
>
>One, can you move this below qcom_scm_set_warm_boot_addr so they are closer to qcom_scm_cpu_power_down.  Also, we probably need to prefix the names to be clear the flags are associated with qcom_scm_cpu_power_down.  QCOM_SCM_CPU_PWR_DOWN_{L2_ON,L2_OFF}?
>

Okay.

>> +
>> extern int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
>> extern int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus);
>> +extern void qcom_scm_cpu_power_down(u32 flags);
>>
>> #define QCOM_SCM_VERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
>>
>> --
>> 2.1.0
>>
>
>- k
>
>-- 
>Qualcomm Innovation Center, Inc.
>The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
>a Linux Foundation Collaborative Project
>