[PATCH v6 0/8] mfd: introduce a driver for LPSS devices on SPT

[PATCH v6 0/8] mfd: introduce a driver for LPSS devices on SPT

[Andy Shevchenko]

The new coming Intel platforms such as Skylake will contain Sunrisepoint PCH.

The driver is based on MFD framework since the main device, i.e. serial bus
controller, contains register space for itself, DMA part, and an additional
address space (convergence layer). 

The public specification of the register map is avaiable in [1].

This is sixth generation of the patch series to bring support LPSS devices
found on Intel Sunrisepoint (Intel Skylake PCH). Previous one can be found here
[2].

The series has few logical parts:
- patches 1-3 prepares PM core, ACPI, and driver core (PM) to handle our case
- patches 4-6 introduce unregistering platform devices in MFD in reversed
  order
- patch 7 implements iDMA 64-bit driver
- patch 8 introduces an MFD driver for LPSS devices

The driver has been tested with SPI and UART on Intel Skylake PCH.

Stephen, can you, please, have a look into patch 8 regarding to clock name
matching and other stuff Lee asked?

[1] https://download.01.org/future-platform-configuration-hub/skylake/register-definitions/332219-002.pdf
[2] http://www.spinics.net/lists/linux-acpi/msg59267.html

Changelog v6:
  - rebase on top of v4.2-rc4
  - address Vinod's comments regarding to idma64 driver
  - fix a bug in idma64 driver found by our Q/A team (use after free)

Changelog v5:
  - rebase on top of v4.2-rc1
  - patch 3 is modified accordingly to new changes in drivers/base/dd.c
  - correct Rafael's email in patch 3

Changelog v4:
  - replace patch 3 by Rafael's suggession
  - append ACKs from Rafael
  - rebase on top of v4.1-rc8

Changelog v3:
  - rework patch 3 to be used for all kind of devices (address Alan comment)
  - iDMA 64-bit driver improvements:
    - fix burst-to-register conversion
    - remove excessive locking
  - do not expose core part to the user (Kconfig)
  - address most of Lee's comments
  - append ACKs
  - rebase on top of v4.1-rc6

Changelog v2:
  - new DMA driver to fully support iDMA 64-bit IP
  - patch 3 is added to wake up parent devices when ->probe(), ->remove(), or
    ->shutdown()
  - MFD core is unregistering devices in reversed order
  - address few Lee's comments on v1
  - address Russel's comment, therefore use clkdev_create() helper
  - intel-lpss{,-acpi,-pci} are modified regarding to above changes

Andy Shevchenko (5):
  klist: implement klist_prev()
  driver core: implement device_for_each_child_reverse()
  mfd: make mfd_remove_devices() iterate in reverse order
  dmaengine: add a driver for Intel integrated DMA 64-bit
  mfd: Add support for Intel Sunrisepoint LPSS devices

Mika Westerberg (2):
  PM / QoS: Make it possible to expose device latency tolerance to
    userspace
  ACPI / PM: Attach ACPI power domain only once

Rafael J. Wysocki (1):
  Driver core: wakeup the parent device before trying probe

 drivers/acpi/device_pm.c      |   8 +
 drivers/acpi/internal.h       |   2 +
 drivers/acpi/scan.c           |  46 ++-
 drivers/base/core.c           |  43 +++
 drivers/base/dd.c             |  20 ++
 drivers/base/power/power.h    |   2 +
 drivers/base/power/qos.c      |  37 +++
 drivers/base/power/sysfs.c    |  11 +
 drivers/dma/Kconfig           |   8 +
 drivers/dma/Makefile          |   1 +
 drivers/dma/idma64.c          | 710 ++++++++++++++++++++++++++++++++++++++++++
 drivers/dma/idma64.h          | 233 ++++++++++++++
 drivers/mfd/Kconfig           |  23 ++
 drivers/mfd/Makefile          |   3 +
 drivers/mfd/intel-lpss-acpi.c |  84 +++++
 drivers/mfd/intel-lpss-pci.c  | 113 +++++++
 drivers/mfd/intel-lpss.c      | 524 +++++++++++++++++++++++++++++++
 drivers/mfd/intel-lpss.h      |  62 ++++
 drivers/mfd/mfd-core.c        |   2 +-
 include/linux/device.h        |   2 +
 include/linux/klist.h         |   1 +
 include/linux/pm_qos.h        |   5 +
 lib/klist.c                   |  41 +++
 23 files changed, 1964 insertions(+), 17 deletions(-)
 create mode 100644 drivers/dma/idma64.c
 create mode 100644 drivers/dma/idma64.h
 create mode 100644 drivers/mfd/intel-lpss-acpi.c
 create mode 100644 drivers/mfd/intel-lpss-pci.c
 create mode 100644 drivers/mfd/intel-lpss.c
 create mode 100644 drivers/mfd/intel-lpss.h

-- 
2.4.6

[PATCH v6 1/8] PM / QoS: Make it possible to expose device latency tolerance to userspace

[Andy Shevchenko]

From: Mika Westerberg <mika.westerberg@linux.intel.com>

Typically when a device is created the bus core it belongs to (for example
PCI) does not know if the device supports things like latency tolerance.
This is left to the driver that binds to the device in question. However,
at that time the device has already been created and there is no way to set
its dev->power.set_latency_tolerance anymore.

So follow what has been done for other PM QoS attributes as well and allow
drivers to expose and hide latency tolerance from userspace, if the device
supports it.

Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/base/power/power.h |  2 ++
 drivers/base/power/qos.c   | 37 +++++++++++++++++++++++++++++++++++++
 drivers/base/power/sysfs.c | 11 +++++++++++
 include/linux/pm_qos.h     |  5 +++++
 4 files changed, 55 insertions(+)

diff --git a/drivers/base/power/power.h b/drivers/base/power/power.h
index f1a5d95..998fa6b 100644
--- a/drivers/base/power/power.h
+++ b/drivers/base/power/power.h
@@ -73,6 +73,8 @@ extern int pm_qos_sysfs_add_resume_latency(struct device *dev);
 extern void pm_qos_sysfs_remove_resume_latency(struct device *dev);
 extern int pm_qos_sysfs_add_flags(struct device *dev);
 extern void pm_qos_sysfs_remove_flags(struct device *dev);
+extern int pm_qos_sysfs_add_latency_tolerance(struct device *dev);
+extern void pm_qos_sysfs_remove_latency_tolerance(struct device *dev);
 
 #else /* CONFIG_PM */
 
diff --git a/drivers/base/power/qos.c b/drivers/base/power/qos.c
index e56d538..7f3646e 100644
--- a/drivers/base/power/qos.c
+++ b/drivers/base/power/qos.c
@@ -883,3 +883,40 @@ int dev_pm_qos_update_user_latency_tolerance(struct device *dev, s32 val)
 	mutex_unlock(&dev_pm_qos_mtx);
 	return ret;
 }
+
+/**
+ * dev_pm_qos_expose_latency_tolerance - Expose latency tolerance to userspace
+ * @dev: Device whose latency tolerance to expose
+ */
+int dev_pm_qos_expose_latency_tolerance(struct device *dev)
+{
+	int ret;
+
+	if (!dev->power.set_latency_tolerance)
+		return -EINVAL;
+
+	mutex_lock(&dev_pm_qos_sysfs_mtx);
+	ret = pm_qos_sysfs_add_latency_tolerance(dev);
+	mutex_unlock(&dev_pm_qos_sysfs_mtx);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(dev_pm_qos_expose_latency_tolerance);
+
+/**
+ * dev_pm_qos_hide_latency_tolerance - Hide latency tolerance from userspace
+ * @dev: Device whose latency tolerance to hide
+ */
+void dev_pm_qos_hide_latency_tolerance(struct device *dev)
+{
+	mutex_lock(&dev_pm_qos_sysfs_mtx);
+	pm_qos_sysfs_remove_latency_tolerance(dev);
+	mutex_unlock(&dev_pm_qos_sysfs_mtx);
+
+	/* Remove the request from user space now */
+	pm_runtime_get_sync(dev);
+	dev_pm_qos_update_user_latency_tolerance(dev,
+		PM_QOS_LATENCY_TOLERANCE_NO_CONSTRAINT);
+	pm_runtime_put(dev);
+}
+EXPORT_SYMBOL_GPL(dev_pm_qos_hide_latency_tolerance);
diff --git a/drivers/base/power/sysfs.c b/drivers/base/power/sysfs.c
index d2be3f9..a7b4679 100644
--- a/drivers/base/power/sysfs.c
+++ b/drivers/base/power/sysfs.c
@@ -738,6 +738,17 @@ void pm_qos_sysfs_remove_flags(struct device *dev)
 	sysfs_unmerge_group(&dev->kobj, &pm_qos_flags_attr_group);
 }
 
+int pm_qos_sysfs_add_latency_tolerance(struct device *dev)
+{
+	return sysfs_merge_group(&dev->kobj,
+				 &pm_qos_latency_tolerance_attr_group);
+}
+
+void pm_qos_sysfs_remove_latency_tolerance(struct device *dev)
+{
+	sysfs_unmerge_group(&dev->kobj, &pm_qos_latency_tolerance_attr_group);
+}
+
 void rpm_sysfs_remove(struct device *dev)
 {
 	sysfs_unmerge_group(&dev->kobj, &pm_runtime_attr_group);
diff --git a/include/linux/pm_qos.h b/include/linux/pm_qos.h
index 7b3ae0c..0f65d36 100644
--- a/include/linux/pm_qos.h
+++ b/include/linux/pm_qos.h
@@ -161,6 +161,8 @@ void dev_pm_qos_hide_flags(struct device *dev);
 int dev_pm_qos_update_flags(struct device *dev, s32 mask, bool set);
 s32 dev_pm_qos_get_user_latency_tolerance(struct device *dev);
 int dev_pm_qos_update_user_latency_tolerance(struct device *dev, s32 val);
+int dev_pm_qos_expose_latency_tolerance(struct device *dev);
+void dev_pm_qos_hide_latency_tolerance(struct device *dev);
 
 static inline s32 dev_pm_qos_requested_resume_latency(struct device *dev)
 {
@@ -229,6 +231,9 @@ static inline s32 dev_pm_qos_get_user_latency_tolerance(struct device *dev)
 			{ return PM_QOS_LATENCY_TOLERANCE_NO_CONSTRAINT; }
 static inline int dev_pm_qos_update_user_latency_tolerance(struct device *dev, s32 val)
 			{ return 0; }
+static inline int dev_pm_qos_expose_latency_tolerance(struct device *dev)
+			{ return 0; }
+static inline void dev_pm_qos_hide_latency_tolerance(struct device *dev) {}
 
 static inline s32 dev_pm_qos_requested_resume_latency(struct device *dev) { return 0; }
 static inline s32 dev_pm_qos_requested_flags(struct device *dev) { return 0; }
-- 
2.4.6

[PATCH v6 2/8] ACPI / PM: Attach ACPI power domain only once

[Andy Shevchenko]

From: Mika Westerberg <mika.westerberg@linux.intel.com>

Some devices, like MFD subdevices, share a single ACPI companion device so
that they are able to access their resources and children. However,
currently all these subdevices are attached to the ACPI power domain and
this might cause that the power methods for the companion device get called
more than once.

In order to solve this we attach the ACPI power domain only to the first
physical device that is bound to the ACPI companion device. In case of MFD
devices, this is the parent MFD device itself.

Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/acpi/device_pm.c |  8 ++++++++
 drivers/acpi/internal.h  |  2 ++
 drivers/acpi/scan.c      | 46 ++++++++++++++++++++++++++++++----------------
 3 files changed, 40 insertions(+), 16 deletions(-)

diff --git a/drivers/acpi/device_pm.c b/drivers/acpi/device_pm.c
index 717afcd..08dc3ec 100644
--- a/drivers/acpi/device_pm.c
+++ b/drivers/acpi/device_pm.c
@@ -1123,6 +1123,14 @@ int acpi_dev_pm_attach(struct device *dev, bool power_on)
 	if (dev->pm_domain)
 		return -EEXIST;
 
+	/*
+	 * Only attach the power domain to the first device if the
+	 * companion is shared by multiple. This is to prevent doing power
+	 * management twice.
+	 */
+	if (!acpi_device_is_first_physical_node(adev, dev))
+		return -EBUSY;
+
 	acpi_add_pm_notifier(adev, dev, acpi_pm_notify_work_func);
 	dev->pm_domain = &acpi_general_pm_domain;
 	if (power_on) {
diff --git a/drivers/acpi/internal.h b/drivers/acpi/internal.h
index 4683a96..f6aefe9 100644
--- a/drivers/acpi/internal.h
+++ b/drivers/acpi/internal.h
@@ -97,6 +97,8 @@ void acpi_device_add_finalize(struct acpi_device *device);
 void acpi_free_pnp_ids(struct acpi_device_pnp *pnp);
 bool acpi_device_is_present(struct acpi_device *adev);
 bool acpi_device_is_battery(struct acpi_device *adev);
+bool acpi_device_is_first_physical_node(struct acpi_device *adev,
+					const struct device *dev);
 
 /* --------------------------------------------------------------------------
                                   Power Resource
diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c
index ec25635..89ff6d2 100644
--- a/drivers/acpi/scan.c
+++ b/drivers/acpi/scan.c
@@ -226,6 +226,35 @@ static int create_of_modalias(struct acpi_device *acpi_dev, char *modalias,
 	return len;
 }
 
+/**
+ * acpi_device_is_first_physical_node - Is given dev first physical node
+ * @adev: ACPI companion device
+ * @dev: Physical device to check
+ *
+ * Function checks if given @dev is the first physical devices attached to
+ * the ACPI companion device. This distinction is needed in some cases
+ * where the same companion device is shared between many physical devices.
+ *
+ * Note that the caller have to provide valid @adev pointer.
+ */
+bool acpi_device_is_first_physical_node(struct acpi_device *adev,
+					const struct device *dev)
+{
+	bool ret = false;
+
+	mutex_lock(&adev->physical_node_lock);
+	if (!list_empty(&adev->physical_node_list)) {
+		const struct acpi_device_physical_node *node;
+
+		node = list_first_entry(&adev->physical_node_list,
+					struct acpi_device_physical_node, node);
+		ret = node->dev == dev;
+	}
+	mutex_unlock(&adev->physical_node_lock);
+
+	return ret;
+}
+
 /*
  * acpi_companion_match() - Can we match via ACPI companion device
  * @dev: Device in question
@@ -250,7 +279,6 @@ static int create_of_modalias(struct acpi_device *acpi_dev, char *modalias,
 static struct acpi_device *acpi_companion_match(const struct device *dev)
 {
 	struct acpi_device *adev;
-	struct mutex *physical_node_lock;
 
 	adev = ACPI_COMPANION(dev);
 	if (!adev)
@@ -259,21 +287,7 @@ static struct acpi_device *acpi_companion_match(const struct device *dev)
 	if (list_empty(&adev->pnp.ids))
 		return NULL;
 
-	physical_node_lock = &adev->physical_node_lock;
-	mutex_lock(physical_node_lock);
-	if (list_empty(&adev->physical_node_list)) {
-		adev = NULL;
-	} else {
-		const struct acpi_device_physical_node *node;
-
-		node = list_first_entry(&adev->physical_node_list,
-					struct acpi_device_physical_node, node);
-		if (node->dev != dev)
-			adev = NULL;
-	}
-	mutex_unlock(physical_node_lock);
-
-	return adev;
+	return acpi_device_is_first_physical_node(adev, dev) ? adev : NULL;
 }
 
 static int __acpi_device_uevent_modalias(struct acpi_device *adev,
-- 
2.4.6

[PATCH v6 3/8] Driver core: wakeup the parent device before trying probe

[Andy Shevchenko]

From: "Rafael J. Wysocki" <rafael.j.wysocki@intel.com>

If the parent is still suspended when driver probe is
attempted, the result may be failure.

For example, if the parent is a PCI MFD device that has been
suspended when we try to probe our device, any register
reads will return 0xffffffff.

To fix the problem, making sure the parent is always awake
before attempting driver probe.

Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/base/dd.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/base/dd.c b/drivers/base/dd.c
index a638bbb..2d6df1d 100644
--- a/drivers/base/dd.c
+++ b/drivers/base/dd.c
@@ -399,6 +399,8 @@ EXPORT_SYMBOL_GPL(wait_for_device_probe);
  *
  * This function must be called with @dev lock held.  When called for a
  * USB interface, @dev->parent lock must be held as well.
+ *
+ * If the device has a parent, runtime-resume the parent before driver probing.
  */
 int driver_probe_device(struct device_driver *drv, struct device *dev)
 {
@@ -410,10 +412,16 @@ int driver_probe_device(struct device_driver *drv, struct device *dev)
 	pr_debug("bus: '%s': %s: matched device %s with driver %s\n",
 		 drv->bus->name, __func__, dev_name(dev), drv->name);
 
+	if (dev->parent)
+		pm_runtime_get_sync(dev->parent);
+
 	pm_runtime_barrier(dev);
 	ret = really_probe(dev, drv);
 	pm_request_idle(dev);
 
+	if (dev->parent)
+		pm_runtime_put(dev->parent);
+
 	return ret;
 }
 
@@ -507,11 +515,17 @@ static void __device_attach_async_helper(void *_dev, async_cookie_t cookie)
 
 	device_lock(dev);
 
+	if (dev->parent)
+		pm_runtime_get_sync(dev->parent);
+
 	bus_for_each_drv(dev->bus, NULL, &data, __device_attach_driver);
 	dev_dbg(dev, "async probe completed\n");
 
 	pm_request_idle(dev);
 
+	if (dev->parent)
+		pm_runtime_put(dev->parent);
+
 	device_unlock(dev);
 
 	put_device(dev);
@@ -541,6 +555,9 @@ static int __device_attach(struct device *dev, bool allow_async)
 			.want_async = false,
 		};
 
+		if (dev->parent)
+			pm_runtime_get_sync(dev->parent);
+
 		ret = bus_for_each_drv(dev->bus, NULL, &data,
 					__device_attach_driver);
 		if (!ret && allow_async && data.have_async) {
@@ -557,6 +574,9 @@ static int __device_attach(struct device *dev, bool allow_async)
 		} else {
 			pm_request_idle(dev);
 		}
+
+		if (dev->parent)
+			pm_runtime_put(dev->parent);
 	}
 out_unlock:
 	device_unlock(dev);
-- 
2.4.6

[PATCH v6 4/8] klist: implement klist_prev()

[Andy Shevchenko]

klist_prev() gets the previous element in the list. It is useful to traverse
through the list in reverse order, for example, to provide LIFO (last in first
out) variant of access.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 include/linux/klist.h |  1 +
 lib/klist.c           | 41 +++++++++++++++++++++++++++++++++++++++++
 2 files changed, 42 insertions(+)

diff --git a/include/linux/klist.h b/include/linux/klist.h
index 61e5b72..953f283 100644
--- a/include/linux/klist.h
+++ b/include/linux/klist.h
@@ -63,6 +63,7 @@ extern void klist_iter_init(struct klist *k, struct klist_iter *i);
 extern void klist_iter_init_node(struct klist *k, struct klist_iter *i,
 				 struct klist_node *n);
 extern void klist_iter_exit(struct klist_iter *i);
+extern struct klist_node *klist_prev(struct klist_iter *i);
 extern struct klist_node *klist_next(struct klist_iter *i);
 
 #endif
diff --git a/lib/klist.c b/lib/klist.c
index 89b485a..d74cf7a 100644
--- a/lib/klist.c
+++ b/lib/klist.c
@@ -324,6 +324,47 @@ static struct klist_node *to_klist_node(struct list_head *n)
 }
 
 /**
+ * klist_prev - Ante up prev node in list.
+ * @i: Iterator structure.
+ *
+ * First grab list lock. Decrement the reference count of the previous
+ * node, if there was one. Grab the prev node, increment its reference
+ * count, drop the lock, and return that prev node.
+ */
+struct klist_node *klist_prev(struct klist_iter *i)
+{
+	void (*put)(struct klist_node *) = i->i_klist->put;
+	struct klist_node *last = i->i_cur;
+	struct klist_node *prev;
+
+	spin_lock(&i->i_klist->k_lock);
+
+	if (last) {
+		prev = to_klist_node(last->n_node.prev);
+		if (!klist_dec_and_del(last))
+			put = NULL;
+	} else
+		prev = to_klist_node(i->i_klist->k_list.prev);
+
+	i->i_cur = NULL;
+	while (prev != to_klist_node(&i->i_klist->k_list)) {
+		if (likely(!knode_dead(prev))) {
+			kref_get(&prev->n_ref);
+			i->i_cur = prev;
+			break;
+		}
+		prev = to_klist_node(prev->n_node.prev);
+	}
+
+	spin_unlock(&i->i_klist->k_lock);
+
+	if (put && last)
+		put(last);
+	return i->i_cur;
+}
+EXPORT_SYMBOL_GPL(klist_prev);
+
+/**
  * klist_next - Ante up next node in list.
  * @i: Iterator structure.
  *
-- 
2.4.6

[PATCH v6 5/8] driver core: implement device_for_each_child_reverse()

[Andy Shevchenko]

The new function device_for_each_child_reverse() is helpful to traverse the
registered devices in a reversed order, e.g. in the case when an operation on
each device should be done first on the last added device, then on one before
last and so on.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
 drivers/base/core.c    | 43 +++++++++++++++++++++++++++++++++++++++++++
 include/linux/device.h |  2 ++
 2 files changed, 45 insertions(+)

diff --git a/drivers/base/core.c b/drivers/base/core.c
index dafae6d..7d62795 100644
--- a/drivers/base/core.c
+++ b/drivers/base/core.c
@@ -1252,6 +1252,19 @@ void device_unregister(struct device *dev)
 }
 EXPORT_SYMBOL_GPL(device_unregister);
 
+static struct device *prev_device(struct klist_iter *i)
+{
+	struct klist_node *n = klist_prev(i);
+	struct device *dev = NULL;
+	struct device_private *p;
+
+	if (n) {
+		p = to_device_private_parent(n);
+		dev = p->device;
+	}
+	return dev;
+}
+
 static struct device *next_device(struct klist_iter *i)
 {
 	struct klist_node *n = klist_next(i);
@@ -1341,6 +1354,36 @@ int device_for_each_child(struct device *parent, void *data,
 EXPORT_SYMBOL_GPL(device_for_each_child);
 
 /**
+ * device_for_each_child_reverse - device child iterator in reversed order.
+ * @parent: parent struct device.
+ * @fn: function to be called for each device.
+ * @data: data for the callback.
+ *
+ * Iterate over @parent's child devices, and call @fn for each,
+ * passing it @data.
+ *
+ * We check the return of @fn each time. If it returns anything
+ * other than 0, we break out and return that value.
+ */
+int device_for_each_child_reverse(struct device *parent, void *data,
+				  int (*fn)(struct device *dev, void *data))
+{
+	struct klist_iter i;
+	struct device *child;
+	int error = 0;
+
+	if (!parent->p)
+		return 0;
+
+	klist_iter_init(&parent->p->klist_children, &i);
+	while ((child = prev_device(&i)) && !error)
+		error = fn(child, data);
+	klist_iter_exit(&i);
+	return error;
+}
+EXPORT_SYMBOL_GPL(device_for_each_child_reverse);
+
+/**
  * device_find_child - device iterator for locating a particular device.
  * @parent: parent struct device
  * @match: Callback function to check device
diff --git a/include/linux/device.h b/include/linux/device.h
index a2b4ea7..9d212fe 100644
--- a/include/linux/device.h
+++ b/include/linux/device.h
@@ -959,6 +959,8 @@ extern int __must_check device_add(struct device *dev);
 extern void device_del(struct device *dev);
 extern int device_for_each_child(struct device *dev, void *data,
 		     int (*fn)(struct device *dev, void *data));
+extern int device_for_each_child_reverse(struct device *dev, void *data,
+		     int (*fn)(struct device *dev, void *data));
 extern struct device *device_find_child(struct device *dev, void *data,
 				int (*match)(struct device *dev, void *data));
 extern int device_rename(struct device *dev, const char *new_name);
-- 
2.4.6

[PATCH v6 6/8] mfd: make mfd_remove_devices() iterate in reverse order

[Andy Shevchenko]

The newly introduced device_for_each_child_reverse() would be used when MFD
core removes the device.

After this patch applied the devices will be removed in a reversed order. This
behaviour is useful when devices have implicit dependency on order, i.e.
consider MFD device with serial bus controller, such as SPI, and DMA IP that is
attached to serial bus controller: before remove the DMA driver we have to be
ensured that no DMA transfers is ongoing and the requested channel are unused.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/mfd/mfd-core.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mfd/mfd-core.c b/drivers/mfd/mfd-core.c
index 14fd5cb..c17635d 100644
--- a/drivers/mfd/mfd-core.c
+++ b/drivers/mfd/mfd-core.c
@@ -302,7 +302,7 @@ void mfd_remove_devices(struct device *parent)
 {
 	atomic_t *cnts = NULL;
 
-	device_for_each_child(parent, &cnts, mfd_remove_devices_fn);
+	device_for_each_child_reverse(parent, &cnts, mfd_remove_devices_fn);
 	kfree(cnts);
 }
 EXPORT_SYMBOL(mfd_remove_devices);
-- 
2.4.6

[PATCH v6 7/8] dmaengine: add a driver for Intel integrated DMA 64-bit

[Andy Shevchenko]

Intel integrated DMA (iDMA) 64-bit is a specific IP that is used as a part of
LPSS devices such as HSUART or SPI. The iDMA IP is attached for private
usage on each host controller independently.

While it has similarities with Synopsys DesignWare DMA, the following
distinctions doesn't allow to use the existing driver:
- 64-bit mode with corresponding changes in Hardware Linked List data structure
- many slight differences in the channel registers

Moreover this driver is based on the DMA virtual channels framework that helps
to make the driver cleaner and easy to understand.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/dma/Kconfig  |   8 +
 drivers/dma/Makefile |   1 +
 drivers/dma/idma64.c | 710 +++++++++++++++++++++++++++++++++++++++++++++++++++
 drivers/dma/idma64.h | 233 +++++++++++++++++
 4 files changed, 952 insertions(+)
 create mode 100644 drivers/dma/idma64.c
 create mode 100644 drivers/dma/idma64.h

diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 88d474b..bdbbe5b 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -85,6 +85,14 @@ config INTEL_IOP_ADMA
 	help
 	  Enable support for the Intel(R) IOP Series RAID engines.
 
+config IDMA64
+	tristate "Intel integrated DMA 64-bit support"
+	select DMA_ENGINE
+	select DMA_VIRTUAL_CHANNELS
+	help
+	  Enable DMA support for Intel Low Power Subsystem such as found on
+	  Intel Skylake PCH.
+
 source "drivers/dma/dw/Kconfig"
 
 config AT_HDMAC
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 6a4d6f2..56ff8c7 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_HSU_DMA) += hsu/
 obj-$(CONFIG_MPC512X_DMA) += mpc512x_dma.o
 obj-$(CONFIG_PPC_BESTCOMM) += bestcomm/
 obj-$(CONFIG_MV_XOR) += mv_xor.o
+obj-$(CONFIG_IDMA64) += idma64.o
 obj-$(CONFIG_DW_DMAC_CORE) += dw/
 obj-$(CONFIG_AT_HDMAC) += at_hdmac.o
 obj-$(CONFIG_AT_XDMAC) += at_xdmac.o
diff --git a/drivers/dma/idma64.c b/drivers/dma/idma64.c
new file mode 100644
index 0000000..18c14e1
--- /dev/null
+++ b/drivers/dma/idma64.c
@@ -0,0 +1,710 @@
+/*
+ * Core driver for the Intel integrated DMA 64-bit
+ *
+ * Copyright (C) 2015 Intel Corporation
+ * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
+#include <linux/dmapool.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include "idma64.h"
+
+/* Platform driver name */
+#define DRV_NAME		"idma64"
+
+/* For now we support only two channels */
+#define IDMA64_NR_CHAN		2
+
+/* ---------------------------------------------------------------------- */
+
+static struct device *chan2dev(struct dma_chan *chan)
+{
+	return &chan->dev->device;
+}
+
+/* ---------------------------------------------------------------------- */
+
+static void idma64_off(struct idma64 *idma64)
+{
+	unsigned short count = 100;
+
+	dma_writel(idma64, CFG, 0);
+
+	channel_clear_bit(idma64, MASK(XFER), idma64->all_chan_mask);
+	channel_clear_bit(idma64, MASK(BLOCK), idma64->all_chan_mask);
+	channel_clear_bit(idma64, MASK(SRC_TRAN), idma64->all_chan_mask);
+	channel_clear_bit(idma64, MASK(DST_TRAN), idma64->all_chan_mask);
+	channel_clear_bit(idma64, MASK(ERROR), idma64->all_chan_mask);
+
+	do {
+		cpu_relax();
+	} while (dma_readl(idma64, CFG) & IDMA64_CFG_DMA_EN && --count);
+}
+
+static void idma64_on(struct idma64 *idma64)
+{
+	dma_writel(idma64, CFG, IDMA64_CFG_DMA_EN);
+}
+
+/* ---------------------------------------------------------------------- */
+
+static void idma64_chan_init(struct idma64 *idma64, struct idma64_chan *idma64c)
+{
+	u32 cfghi = IDMA64C_CFGH_SRC_PER(1) | IDMA64C_CFGH_DST_PER(0);
+	u32 cfglo = 0;
+
+	/* Enforce FIFO drain when channel is suspended */
+	cfglo |= IDMA64C_CFGL_CH_DRAIN;
+
+	/* Set default burst alignment */
+	cfglo |= IDMA64C_CFGL_DST_BURST_ALIGN | IDMA64C_CFGL_SRC_BURST_ALIGN;
+
+	channel_writel(idma64c, CFG_LO, cfglo);
+	channel_writel(idma64c, CFG_HI, cfghi);
+
+	/* Enable interrupts */
+	channel_set_bit(idma64, MASK(XFER), idma64c->mask);
+	channel_set_bit(idma64, MASK(ERROR), idma64c->mask);
+
+	/*
+	 * Enforce the controller to be turned on.
+	 *
+	 * The iDMA is turned off in ->probe() and looses context during system
+	 * suspend / resume cycle. That's why we have to enable it each time we
+	 * use it.
+	 */
+	idma64_on(idma64);
+}
+
+static void idma64_chan_stop(struct idma64 *idma64, struct idma64_chan *idma64c)
+{
+	channel_clear_bit(idma64, CH_EN, idma64c->mask);
+}
+
+static void idma64_chan_start(struct idma64 *idma64, struct idma64_chan *idma64c)
+{
+	struct idma64_desc *desc = idma64c->desc;
+	struct idma64_hw_desc *hw = &desc->hw[0];
+
+	channel_writeq(idma64c, SAR, 0);
+	channel_writeq(idma64c, DAR, 0);
+
+	channel_writel(idma64c, CTL_HI, IDMA64C_CTLH_BLOCK_TS(~0UL));
+	channel_writel(idma64c, CTL_LO, IDMA64C_CTLL_LLP_S_EN | IDMA64C_CTLL_LLP_D_EN);
+
+	channel_writeq(idma64c, LLP, hw->llp);
+
+	channel_set_bit(idma64, CH_EN, idma64c->mask);
+}
+
+static void idma64_stop_transfer(struct idma64_chan *idma64c)
+{
+	struct idma64 *idma64 = to_idma64(idma64c->vchan.chan.device);
+
+	idma64_chan_stop(idma64, idma64c);
+}
+
+static void idma64_start_transfer(struct idma64_chan *idma64c)
+{
+	struct idma64 *idma64 = to_idma64(idma64c->vchan.chan.device);
+	struct virt_dma_desc *vdesc;
+
+	/* Get the next descriptor */
+	vdesc = vchan_next_desc(&idma64c->vchan);
+	if (!vdesc) {
+		idma64c->desc = NULL;
+		return;
+	}
+
+	list_del(&vdesc->node);
+	idma64c->desc = to_idma64_desc(vdesc);
+
+	/* Configure the channel */
+	idma64_chan_init(idma64, idma64c);
+
+	/* Start the channel with a new descriptor */
+	idma64_chan_start(idma64, idma64c);
+}
+
+/* ---------------------------------------------------------------------- */
+
+static void idma64_chan_irq(struct idma64 *idma64, unsigned short c,
+		u32 status_err, u32 status_xfer)
+{
+	struct idma64_chan *idma64c = &idma64->chan[c];
+	struct idma64_desc *desc;
+	unsigned long flags;
+
+	spin_lock_irqsave(&idma64c->vchan.lock, flags);
+	desc = idma64c->desc;
+	if (desc) {
+		if (status_err & (1 << c)) {
+			dma_writel(idma64, CLEAR(ERROR), idma64c->mask);
+			desc->status = DMA_ERROR;
+		} else if (status_xfer & (1 << c)) {
+			dma_writel(idma64, CLEAR(XFER), idma64c->mask);
+			desc->status = DMA_COMPLETE;
+			vchan_cookie_complete(&desc->vdesc);
+			idma64_start_transfer(idma64c);
+		}
+
+		/* idma64_start_transfer() updates idma64c->desc */
+		if (idma64c->desc == NULL || desc->status == DMA_ERROR)
+			idma64_stop_transfer(idma64c);
+	}
+	spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
+}
+
+static irqreturn_t idma64_irq(int irq, void *dev)
+{
+	struct idma64 *idma64 = dev;
+	u32 status = dma_readl(idma64, STATUS_INT);
+	u32 status_xfer;
+	u32 status_err;
+	unsigned short i;
+
+	dev_vdbg(idma64->dma.dev, "%s: status=%#x\n", __func__, status);
+
+	/* Check if we have any interrupt from the DMA controller */
+	if (!status)
+		return IRQ_NONE;
+
+	/* Disable interrupts */
+	channel_clear_bit(idma64, MASK(XFER), idma64->all_chan_mask);
+	channel_clear_bit(idma64, MASK(ERROR), idma64->all_chan_mask);
+
+	status_xfer = dma_readl(idma64, RAW(XFER));
+	status_err = dma_readl(idma64, RAW(ERROR));
+
+	for (i = 0; i < idma64->dma.chancnt; i++)
+		idma64_chan_irq(idma64, i, status_err, status_xfer);
+
+	/* Re-enable interrupts */
+	channel_set_bit(idma64, MASK(XFER), idma64->all_chan_mask);
+	channel_set_bit(idma64, MASK(ERROR), idma64->all_chan_mask);
+
+	return IRQ_HANDLED;
+}
+
+/* ---------------------------------------------------------------------- */
+
+static struct idma64_desc *idma64_alloc_desc(unsigned int ndesc)
+{
+	struct idma64_desc *desc;
+
+	desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
+	if (!desc)
+		return NULL;
+
+	desc->hw = kcalloc(ndesc, sizeof(*desc->hw), GFP_NOWAIT);
+	if (!desc->hw) {
+		kfree(desc);
+		return NULL;
+	}
+
+	return desc;
+}
+
+static void idma64_desc_free(struct idma64_chan *idma64c,
+		struct idma64_desc *desc)
+{
+	struct idma64_hw_desc *hw;
+
+	if (desc->ndesc) {
+		unsigned int i = desc->ndesc;
+
+		do {
+			hw = &desc->hw[--i];
+			dma_pool_free(idma64c->pool, hw->lli, hw->llp);
+		} while (i);
+	}
+
+	kfree(desc->hw);
+	kfree(desc);
+}
+
+static void idma64_vdesc_free(struct virt_dma_desc *vdesc)
+{
+	struct idma64_chan *idma64c = to_idma64_chan(vdesc->tx.chan);
+
+	idma64_desc_free(idma64c, to_idma64_desc(vdesc));
+}
+
+static u64 idma64_hw_desc_fill(struct idma64_hw_desc *hw,
+		struct dma_slave_config *config,
+		enum dma_transfer_direction direction, u64 llp)
+{
+	struct idma64_lli *lli = hw->lli;
+	u64 sar, dar;
+	u32 ctlhi = IDMA64C_CTLH_BLOCK_TS(hw->len);
+	u32 ctllo = IDMA64C_CTLL_LLP_S_EN | IDMA64C_CTLL_LLP_D_EN;
+	u32 src_width, dst_width;
+
+	if (direction == DMA_MEM_TO_DEV) {
+		sar = hw->phys;
+		dar = config->dst_addr;
+		ctllo |= IDMA64C_CTLL_DST_FIX | IDMA64C_CTLL_SRC_INC |
+			 IDMA64C_CTLL_FC_M2P;
+		src_width = min_t(u32, 2, __fls(sar | hw->len));
+		dst_width = __fls(config->dst_addr_width);
+	} else {	/* DMA_DEV_TO_MEM */
+		sar = config->src_addr;
+		dar = hw->phys;
+		ctllo |= IDMA64C_CTLL_DST_INC | IDMA64C_CTLL_SRC_FIX |
+			 IDMA64C_CTLL_FC_P2M;
+		src_width = __fls(config->src_addr_width);
+		dst_width = min_t(u32, 2, __fls(dar | hw->len));
+	}
+
+	lli->sar = sar;
+	lli->dar = dar;
+
+	lli->ctlhi = ctlhi;
+	lli->ctllo = ctllo |
+		     IDMA64C_CTLL_SRC_MSIZE(config->src_maxburst) |
+		     IDMA64C_CTLL_DST_MSIZE(config->dst_maxburst) |
+		     IDMA64C_CTLL_DST_WIDTH(dst_width) |
+		     IDMA64C_CTLL_SRC_WIDTH(src_width);
+
+	lli->llp = llp;
+	return hw->llp;
+}
+
+static void idma64_desc_fill(struct idma64_chan *idma64c,
+		struct idma64_desc *desc)
+{
+	struct dma_slave_config *config = &idma64c->config;
+	struct idma64_hw_desc *hw = &desc->hw[desc->ndesc - 1];
+	struct idma64_lli *lli = hw->lli;
+	u64 llp = 0;
+	unsigned int i = desc->ndesc;
+
+	/* Fill the hardware descriptors and link them to a list */
+	do {
+		hw = &desc->hw[--i];
+		llp = idma64_hw_desc_fill(hw, config, desc->direction, llp);
+		desc->length += hw->len;
+	} while (i);
+
+	/* Trigger interrupt after last block */
+	lli->ctllo |= IDMA64C_CTLL_INT_EN;
+}
+
+static struct dma_async_tx_descriptor *idma64_prep_slave_sg(
+		struct dma_chan *chan, struct scatterlist *sgl,
+		unsigned int sg_len, enum dma_transfer_direction direction,
+		unsigned long flags, void *context)
+{
+	struct idma64_chan *idma64c = to_idma64_chan(chan);
+	struct idma64_desc *desc;
+	struct scatterlist *sg;
+	unsigned int i;
+
+	desc = idma64_alloc_desc(sg_len);
+	if (!desc)
+		return NULL;
+
+	for_each_sg(sgl, sg, sg_len, i) {
+		struct idma64_hw_desc *hw = &desc->hw[i];
+
+		/* Allocate DMA capable memory for hardware descriptor */
+		hw->lli = dma_pool_alloc(idma64c->pool, GFP_NOWAIT, &hw->llp);
+		if (!hw->lli) {
+			desc->ndesc = i;
+			idma64_desc_free(idma64c, desc);
+			return NULL;
+		}
+
+		hw->phys = sg_dma_address(sg);
+		hw->len = sg_dma_len(sg);
+	}
+
+	desc->ndesc = sg_len;
+	desc->direction = direction;
+	desc->status = DMA_IN_PROGRESS;
+
+	idma64_desc_fill(idma64c, desc);
+	return vchan_tx_prep(&idma64c->vchan, &desc->vdesc, flags);
+}
+
+static void idma64_issue_pending(struct dma_chan *chan)
+{
+	struct idma64_chan *idma64c = to_idma64_chan(chan);
+	unsigned long flags;
+
+	spin_lock_irqsave(&idma64c->vchan.lock, flags);
+	if (vchan_issue_pending(&idma64c->vchan) && !idma64c->desc)
+		idma64_start_transfer(idma64c);
+	spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
+}
+
+static size_t idma64_active_desc_size(struct idma64_chan *idma64c)
+{
+	struct idma64_desc *desc = idma64c->desc;
+	struct idma64_hw_desc *hw;
+	size_t bytes = desc->length;
+	u64 llp;
+	u32 ctlhi;
+	unsigned int i = 0;
+
+	llp = channel_readq(idma64c, LLP);
+	do {
+		hw = &desc->hw[i];
+	} while ((hw->llp != llp) && (++i < desc->ndesc));
+
+	if (!i)
+		return bytes;
+
+	do {
+		bytes -= desc->hw[--i].len;
+	} while (i);
+
+	ctlhi = channel_readl(idma64c, CTL_HI);
+	return bytes - IDMA64C_CTLH_BLOCK_TS(ctlhi);
+}
+
+static enum dma_status idma64_tx_status(struct dma_chan *chan,
+		dma_cookie_t cookie, struct dma_tx_state *state)
+{
+	struct idma64_chan *idma64c = to_idma64_chan(chan);
+	struct virt_dma_desc *vdesc;
+	enum dma_status status;
+	size_t bytes;
+	unsigned long flags;
+
+	status = dma_cookie_status(chan, cookie, state);
+	if (status == DMA_COMPLETE)
+		return status;
+
+	spin_lock_irqsave(&idma64c->vchan.lock, flags);
+	vdesc = vchan_find_desc(&idma64c->vchan, cookie);
+	if (idma64c->desc && cookie == idma64c->desc->vdesc.tx.cookie) {
+		bytes = idma64_active_desc_size(idma64c);
+		dma_set_residue(state, bytes);
+		status = idma64c->desc->status;
+	} else if (vdesc) {
+		bytes = to_idma64_desc(vdesc)->length;
+		dma_set_residue(state, bytes);
+	}
+	spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
+
+	return status;
+}
+
+static void convert_burst(u32 *maxburst)
+{
+	if (*maxburst)
+		*maxburst = __fls(*maxburst);
+	else
+		*maxburst = 0;
+}
+
+static int idma64_slave_config(struct dma_chan *chan,
+		struct dma_slave_config *config)
+{
+	struct idma64_chan *idma64c = to_idma64_chan(chan);
+
+	/* Check if chan will be configured for slave transfers */
+	if (!is_slave_direction(config->direction))
+		return -EINVAL;
+
+	memcpy(&idma64c->config, config, sizeof(idma64c->config));
+
+	convert_burst(&idma64c->config.src_maxburst);
+	convert_burst(&idma64c->config.dst_maxburst);
+
+	return 0;
+}
+
+static void idma64_chan_deactivate(struct idma64_chan *idma64c)
+{
+	unsigned short count = 100;
+	u32 cfglo;
+
+	cfglo = channel_readl(idma64c, CFG_LO);
+	channel_writel(idma64c, CFG_LO, cfglo | IDMA64C_CFGL_CH_SUSP);
+	do {
+		udelay(1);
+		cfglo = channel_readl(idma64c, CFG_LO);
+	} while (!(cfglo & IDMA64C_CFGL_FIFO_EMPTY) && --count);
+}
+
+static void idma64_chan_activate(struct idma64_chan *idma64c)
+{
+	u32 cfglo;
+
+	cfglo = channel_readl(idma64c, CFG_LO);
+	channel_writel(idma64c, CFG_LO, cfglo & ~IDMA64C_CFGL_CH_SUSP);
+}
+
+static int idma64_pause(struct dma_chan *chan)
+{
+	struct idma64_chan *idma64c = to_idma64_chan(chan);
+	unsigned long flags;
+
+	spin_lock_irqsave(&idma64c->vchan.lock, flags);
+	if (idma64c->desc && idma64c->desc->status == DMA_IN_PROGRESS) {
+		idma64_chan_deactivate(idma64c);
+		idma64c->desc->status = DMA_PAUSED;
+	}
+	spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
+
+	return 0;
+}
+
+static int idma64_resume(struct dma_chan *chan)
+{
+	struct idma64_chan *idma64c = to_idma64_chan(chan);
+	unsigned long flags;
+
+	spin_lock_irqsave(&idma64c->vchan.lock, flags);
+	if (idma64c->desc && idma64c->desc->status == DMA_PAUSED) {
+		idma64c->desc->status = DMA_IN_PROGRESS;
+		idma64_chan_activate(idma64c);
+	}
+	spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
+
+	return 0;
+}
+
+static int idma64_terminate_all(struct dma_chan *chan)
+{
+	struct idma64_chan *idma64c = to_idma64_chan(chan);
+	unsigned long flags;
+	LIST_HEAD(head);
+
+	spin_lock_irqsave(&idma64c->vchan.lock, flags);
+	idma64_chan_deactivate(idma64c);
+	idma64_stop_transfer(idma64c);
+	if (idma64c->desc) {
+		idma64_vdesc_free(&idma64c->desc->vdesc);
+		idma64c->desc = NULL;
+	}
+	vchan_get_all_descriptors(&idma64c->vchan, &head);
+	spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
+
+	vchan_dma_desc_free_list(&idma64c->vchan, &head);
+	return 0;
+}
+
+static int idma64_alloc_chan_resources(struct dma_chan *chan)
+{
+	struct idma64_chan *idma64c = to_idma64_chan(chan);
+
+	/* Create a pool of consistent memory blocks for hardware descriptors */
+	idma64c->pool = dma_pool_create(dev_name(chan2dev(chan)),
+					chan->device->dev,
+					sizeof(struct idma64_lli), 8, 0);
+	if (!idma64c->pool) {
+		dev_err(chan2dev(chan), "No memory for descriptors\n");
+		return -ENOMEM;
+	}
+
+	return 0;
+}
+
+static void idma64_free_chan_resources(struct dma_chan *chan)
+{
+	struct idma64_chan *idma64c = to_idma64_chan(chan);
+
+	vchan_free_chan_resources(to_virt_chan(chan));
+	dma_pool_destroy(idma64c->pool);
+	idma64c->pool = NULL;
+}
+
+/* ---------------------------------------------------------------------- */
+
+#define IDMA64_BUSWIDTHS				\
+	BIT(DMA_SLAVE_BUSWIDTH_1_BYTE)		|	\
+	BIT(DMA_SLAVE_BUSWIDTH_2_BYTES)		|	\
+	BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)
+
+static int idma64_probe(struct idma64_chip *chip)
+{
+	struct idma64 *idma64;
+	unsigned short nr_chan = IDMA64_NR_CHAN;
+	unsigned short i;
+	int ret;
+
+	idma64 = devm_kzalloc(chip->dev, sizeof(*idma64), GFP_KERNEL);
+	if (!idma64)
+		return -ENOMEM;
+
+	idma64->regs = chip->regs;
+	chip->idma64 = idma64;
+
+	idma64->chan = devm_kcalloc(chip->dev, nr_chan, sizeof(*idma64->chan),
+				    GFP_KERNEL);
+	if (!idma64->chan)
+		return -ENOMEM;
+
+	idma64->all_chan_mask = (1 << nr_chan) - 1;
+
+	/* Turn off iDMA controller */
+	idma64_off(idma64);
+
+	ret = devm_request_irq(chip->dev, chip->irq, idma64_irq, IRQF_SHARED,
+			       dev_name(chip->dev), idma64);
+	if (ret)
+		return ret;
+
+	INIT_LIST_HEAD(&idma64->dma.channels);
+	for (i = 0; i < nr_chan; i++) {
+		struct idma64_chan *idma64c = &idma64->chan[i];
+
+		idma64c->vchan.desc_free = idma64_vdesc_free;
+		vchan_init(&idma64c->vchan, &idma64->dma);
+
+		idma64c->regs = idma64->regs + i * IDMA64_CH_LENGTH;
+		idma64c->mask = BIT(i);
+	}
+
+	dma_cap_set(DMA_SLAVE, idma64->dma.cap_mask);
+	dma_cap_set(DMA_PRIVATE, idma64->dma.cap_mask);
+
+	idma64->dma.device_alloc_chan_resources = idma64_alloc_chan_resources;
+	idma64->dma.device_free_chan_resources = idma64_free_chan_resources;
+
+	idma64->dma.device_prep_slave_sg = idma64_prep_slave_sg;
+
+	idma64->dma.device_issue_pending = idma64_issue_pending;
+	idma64->dma.device_tx_status = idma64_tx_status;
+
+	idma64->dma.device_config = idma64_slave_config;
+	idma64->dma.device_pause = idma64_pause;
+	idma64->dma.device_resume = idma64_resume;
+	idma64->dma.device_terminate_all = idma64_terminate_all;
+
+	idma64->dma.src_addr_widths = IDMA64_BUSWIDTHS;
+	idma64->dma.dst_addr_widths = IDMA64_BUSWIDTHS;
+	idma64->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
+	idma64->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
+
+	idma64->dma.dev = chip->dev;
+
+	ret = dma_async_device_register(&idma64->dma);
+	if (ret)
+		return ret;
+
+	dev_info(chip->dev, "Found Intel integrated DMA 64-bit\n");
+	return 0;
+}
+
+static int idma64_remove(struct idma64_chip *chip)
+{
+	struct idma64 *idma64 = chip->idma64;
+	unsigned short i;
+
+	dma_async_device_unregister(&idma64->dma);
+
+	/*
+	 * Explicitly call devm_request_irq() to avoid the side effects with
+	 * the scheduled tasklets.
+	 */
+	devm_free_irq(chip->dev, chip->irq, idma64);
+
+	for (i = 0; i < idma64->dma.chancnt; i++) {
+		struct idma64_chan *idma64c = &idma64->chan[i];
+
+		tasklet_kill(&idma64c->vchan.task);
+	}
+
+	return 0;
+}
+
+/* ---------------------------------------------------------------------- */
+
+static int idma64_platform_probe(struct platform_device *pdev)
+{
+	struct idma64_chip *chip;
+	struct device *dev = &pdev->dev;
+	struct resource *mem;
+	int ret;
+
+	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
+	if (!chip)
+		return -ENOMEM;
+
+	chip->irq = platform_get_irq(pdev, 0);
+	if (chip->irq < 0)
+		return chip->irq;
+
+	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	chip->regs = devm_ioremap_resource(dev, mem);
+	if (IS_ERR(chip->regs))
+		return PTR_ERR(chip->regs);
+
+	ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
+	if (ret)
+		return ret;
+
+	chip->dev = dev;
+
+	ret = idma64_probe(chip);
+	if (ret)
+		return ret;
+
+	platform_set_drvdata(pdev, chip);
+	return 0;
+}
+
+static int idma64_platform_remove(struct platform_device *pdev)
+{
+	struct idma64_chip *chip = platform_get_drvdata(pdev);
+
+	return idma64_remove(chip);
+}
+
+#ifdef CONFIG_PM_SLEEP
+
+static int idma64_pm_suspend(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct idma64_chip *chip = platform_get_drvdata(pdev);
+
+	idma64_off(chip->idma64);
+	return 0;
+}
+
+static int idma64_pm_resume(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct idma64_chip *chip = platform_get_drvdata(pdev);
+
+	idma64_on(chip->idma64);
+	return 0;
+}
+
+#endif /* CONFIG_PM_SLEEP */
+
+static const struct dev_pm_ops idma64_dev_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(idma64_pm_suspend, idma64_pm_resume)
+};
+
+static struct platform_driver idma64_platform_driver = {
+	.probe		= idma64_platform_probe,
+	.remove		= idma64_platform_remove,
+	.driver = {
+		.name	= DRV_NAME,
+		.pm	= &idma64_dev_pm_ops,
+	},
+};
+
+module_platform_driver(idma64_platform_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("iDMA64 core driver");
+MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
+MODULE_ALIAS("platform:" DRV_NAME);
diff --git a/drivers/dma/idma64.h b/drivers/dma/idma64.h
new file mode 100644
index 0000000..a4d9968
--- /dev/null
+++ b/drivers/dma/idma64.h
@@ -0,0 +1,233 @@
+/*
+ * Driver for the Intel integrated DMA 64-bit
+ *
+ * Copyright (C) 2015 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __DMA_IDMA64_H__
+#define __DMA_IDMA64_H__
+
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+
+#include "virt-dma.h"
+
+/* Channel registers */
+
+#define IDMA64_CH_SAR		0x00	/* Source Address Register */
+#define IDMA64_CH_DAR		0x08	/* Destination Address Register */
+#define IDMA64_CH_LLP		0x10	/* Linked List Pointer */
+#define IDMA64_CH_CTL_LO	0x18	/* Control Register Low */
+#define IDMA64_CH_CTL_HI	0x1c	/* Control Register High */
+#define IDMA64_CH_SSTAT		0x20
+#define IDMA64_CH_DSTAT		0x28
+#define IDMA64_CH_SSTATAR	0x30
+#define IDMA64_CH_DSTATAR	0x38
+#define IDMA64_CH_CFG_LO	0x40	/* Configuration Register Low */
+#define IDMA64_CH_CFG_HI	0x44	/* Configuration Register High */
+#define IDMA64_CH_SGR		0x48
+#define IDMA64_CH_DSR		0x50
+
+#define IDMA64_CH_LENGTH	0x58
+
+/* Bitfields in CTL_LO */
+#define IDMA64C_CTLL_INT_EN		(1 << 0)	/* irqs enabled? */
+#define IDMA64C_CTLL_DST_WIDTH(x)	((x) << 1)	/* bytes per element */
+#define IDMA64C_CTLL_SRC_WIDTH(x)	((x) << 4)
+#define IDMA64C_CTLL_DST_INC		(0 << 8)	/* DAR update/not */
+#define IDMA64C_CTLL_DST_FIX		(1 << 8)
+#define IDMA64C_CTLL_SRC_INC		(0 << 10)	/* SAR update/not */
+#define IDMA64C_CTLL_SRC_FIX		(1 << 10)
+#define IDMA64C_CTLL_DST_MSIZE(x)	((x) << 11)	/* burst, #elements */
+#define IDMA64C_CTLL_SRC_MSIZE(x)	((x) << 14)
+#define IDMA64C_CTLL_FC_M2P		(1 << 20)	/* mem-to-periph */
+#define IDMA64C_CTLL_FC_P2M		(2 << 20)	/* periph-to-mem */
+#define IDMA64C_CTLL_LLP_D_EN		(1 << 27)	/* dest block chain */
+#define IDMA64C_CTLL_LLP_S_EN		(1 << 28)	/* src block chain */
+
+/* Bitfields in CTL_HI */
+#define IDMA64C_CTLH_BLOCK_TS(x)	((x) & ((1 << 17) - 1))
+#define IDMA64C_CTLH_DONE		(1 << 17)
+
+/* Bitfields in CFG_LO */
+#define IDMA64C_CFGL_DST_BURST_ALIGN	(1 << 0)	/* dst burst align */
+#define IDMA64C_CFGL_SRC_BURST_ALIGN	(1 << 1)	/* src burst align */
+#define IDMA64C_CFGL_CH_SUSP		(1 << 8)
+#define IDMA64C_CFGL_FIFO_EMPTY		(1 << 9)
+#define IDMA64C_CFGL_CH_DRAIN		(1 << 10)	/* drain FIFO */
+#define IDMA64C_CFGL_DST_OPT_BL		(1 << 20)	/* optimize dst burst length */
+#define IDMA64C_CFGL_SRC_OPT_BL		(1 << 21)	/* optimize src burst length */
+
+/* Bitfields in CFG_HI */
+#define IDMA64C_CFGH_SRC_PER(x)		((x) << 0)	/* src peripheral */
+#define IDMA64C_CFGH_DST_PER(x)		((x) << 4)	/* dst peripheral */
+#define IDMA64C_CFGH_RD_ISSUE_THD(x)	((x) << 8)
+#define IDMA64C_CFGH_RW_ISSUE_THD(x)	((x) << 18)
+
+/* Interrupt registers */
+
+#define IDMA64_INT_XFER		0x00
+#define IDMA64_INT_BLOCK	0x08
+#define IDMA64_INT_SRC_TRAN	0x10
+#define IDMA64_INT_DST_TRAN	0x18
+#define IDMA64_INT_ERROR	0x20
+
+#define IDMA64_RAW(x)		(0x2c0 + IDMA64_INT_##x)	/* r */
+#define IDMA64_STATUS(x)	(0x2e8 + IDMA64_INT_##x)	/* r (raw & mask) */
+#define IDMA64_MASK(x)		(0x310 + IDMA64_INT_##x)	/* rw (set = irq enabled) */
+#define IDMA64_CLEAR(x)		(0x338 + IDMA64_INT_##x)	/* w (ack, affects "raw") */
+
+/* Common registers */
+
+#define IDMA64_STATUS_INT	0x360	/* r */
+#define IDMA64_CFG		0x398
+#define IDMA64_CH_EN		0x3a0
+
+/* Bitfields in CFG */
+#define IDMA64_CFG_DMA_EN		(1 << 0)
+
+/* Hardware descriptor for Linked LIst transfers */
+struct idma64_lli {
+	u64		sar;
+	u64		dar;
+	u64		llp;
+	u32		ctllo;
+	u32		ctlhi;
+	u32		sstat;
+	u32		dstat;
+};
+
+struct idma64_hw_desc {
+	struct idma64_lli *lli;
+	dma_addr_t llp;
+	dma_addr_t phys;
+	unsigned int len;
+};
+
+struct idma64_desc {
+	struct virt_dma_desc vdesc;
+	enum dma_transfer_direction direction;
+	struct idma64_hw_desc *hw;
+	unsigned int ndesc;
+	size_t length;
+	enum dma_status status;
+};
+
+static inline struct idma64_desc *to_idma64_desc(struct virt_dma_desc *vdesc)
+{
+	return container_of(vdesc, struct idma64_desc, vdesc);
+}
+
+struct idma64_chan {
+	struct virt_dma_chan vchan;
+
+	void __iomem *regs;
+
+	/* hardware configuration */
+	enum dma_transfer_direction direction;
+	unsigned int mask;
+	struct dma_slave_config config;
+
+	void *pool;
+	struct idma64_desc *desc;
+};
+
+static inline struct idma64_chan *to_idma64_chan(struct dma_chan *chan)
+{
+	return container_of(chan, struct idma64_chan, vchan.chan);
+}
+
+#define channel_set_bit(idma64, reg, mask)	\
+	dma_writel(idma64, reg, ((mask) << 8) | (mask))
+#define channel_clear_bit(idma64, reg, mask)	\
+	dma_writel(idma64, reg, ((mask) << 8) | 0)
+
+static inline u32 idma64c_readl(struct idma64_chan *idma64c, int offset)
+{
+	return readl(idma64c->regs + offset);
+}
+
+static inline void idma64c_writel(struct idma64_chan *idma64c, int offset,
+				  u32 value)
+{
+	writel(value, idma64c->regs + offset);
+}
+
+#define channel_readl(idma64c, reg)		\
+	idma64c_readl(idma64c, IDMA64_CH_##reg)
+#define channel_writel(idma64c, reg, value)	\
+	idma64c_writel(idma64c, IDMA64_CH_##reg, (value))
+
+static inline u64 idma64c_readq(struct idma64_chan *idma64c, int offset)
+{
+	u64 l, h;
+
+	l = idma64c_readl(idma64c, offset);
+	h = idma64c_readl(idma64c, offset + 4);
+
+	return l | (h << 32);
+}
+
+static inline void idma64c_writeq(struct idma64_chan *idma64c, int offset,
+				  u64 value)
+{
+	idma64c_writel(idma64c, offset, value);
+	idma64c_writel(idma64c, offset + 4, value >> 32);
+}
+
+#define channel_readq(idma64c, reg)		\
+	idma64c_readq(idma64c, IDMA64_CH_##reg)
+#define channel_writeq(idma64c, reg, value)	\
+	idma64c_writeq(idma64c, IDMA64_CH_##reg, (value))
+
+struct idma64 {
+	struct dma_device dma;
+
+	void __iomem *regs;
+
+	/* channels */
+	unsigned short all_chan_mask;
+	struct idma64_chan *chan;
+};
+
+static inline struct idma64 *to_idma64(struct dma_device *ddev)
+{
+	return container_of(ddev, struct idma64, dma);
+}
+
+static inline u32 idma64_readl(struct idma64 *idma64, int offset)
+{
+	return readl(idma64->regs + offset);
+}
+
+static inline void idma64_writel(struct idma64 *idma64, int offset, u32 value)
+{
+	writel(value, idma64->regs + offset);
+}
+
+#define dma_readl(idma64, reg)			\
+	idma64_readl(idma64, IDMA64_##reg)
+#define dma_writel(idma64, reg, value)		\
+	idma64_writel(idma64, IDMA64_##reg, (value))
+
+/**
+ * struct idma64_chip - representation of DesignWare DMA controller hardware
+ * @dev:		struct device of the DMA controller
+ * @irq:		irq line
+ * @regs:		memory mapped I/O space
+ * @idma64:		struct idma64 that is filed by idma64_probe()
+ */
+struct idma64_chip {
+	struct device	*dev;
+	int		irq;
+	void __iomem	*regs;
+	struct idma64	*idma64;
+};
+
+#endif /* __DMA_IDMA64_H__ */
-- 
2.4.6

[PATCH v6 8/8] mfd: Add support for Intel Sunrisepoint LPSS devices

[Andy Shevchenko]

The new coming Intel platforms such as Skylake will contain Sunrisepoint PCH.
The main difference to the previous platforms is that the LPSS devices are
compound devices where usually main (SPI, HSUART, or I2C) and DMA IPs are
present.

This patch brings the driver for such devices found on Sunrisepoint PCH.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 drivers/mfd/Kconfig           |  23 ++
 drivers/mfd/Makefile          |   3 +
 drivers/mfd/intel-lpss-acpi.c |  84 +++++++
 drivers/mfd/intel-lpss-pci.c  | 113 +++++++++
 drivers/mfd/intel-lpss.c      | 524 ++++++++++++++++++++++++++++++++++++++++++
 drivers/mfd/intel-lpss.h      |  62 +++++
 6 files changed, 809 insertions(+)
 create mode 100644 drivers/mfd/intel-lpss-acpi.c
 create mode 100644 drivers/mfd/intel-lpss-pci.c
 create mode 100644 drivers/mfd/intel-lpss.c
 create mode 100644 drivers/mfd/intel-lpss.h

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 6538159..268b6dd 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -328,6 +328,29 @@ config INTEL_SOC_PMIC
 	  thermal, charger and related power management functions
 	  on these systems.
 
+config MFD_INTEL_LPSS
+	tristate
+	select COMMON_CLK
+	select MFD_CORE
+
+config MFD_INTEL_LPSS_ACPI
+	tristate "Intel Low Power Subsystem support in ACPI mode"
+	select MFD_INTEL_LPSS
+	depends on X86 && ACPI
+	help
+	  This driver supports Intel Low Power Subsystem (LPSS) devices such as
+	  I2C, SPI and HS-UART starting from Intel Sunrisepoint (Intel Skylake
+	  PCH) in ACPI mode.
+
+config MFD_INTEL_LPSS_PCI
+	tristate "Intel Low Power Subsystem support in PCI mode"
+	select MFD_INTEL_LPSS
+	depends on X86 && PCI
+	help
+	  This driver supports Intel Low Power Subsystem (LPSS) devices such as
+	  I2C, SPI and HS-UART starting from Intel Sunrisepoint (Intel Skylake
+	  PCH) in PCI mode.
+
 config MFD_INTEL_MSIC
 	bool "Intel MSIC"
 	depends on INTEL_SCU_IPC
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index ea40e07..9d730a2 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -161,6 +161,9 @@ obj-$(CONFIG_TPS65911_COMPARATOR)	+= tps65911-comparator.o
 obj-$(CONFIG_MFD_TPS65090)	+= tps65090.o
 obj-$(CONFIG_MFD_AAT2870_CORE)	+= aat2870-core.o
 obj-$(CONFIG_MFD_ATMEL_HLCDC)	+= atmel-hlcdc.o
+obj-$(CONFIG_MFD_INTEL_LPSS)	+= intel-lpss.o
+obj-$(CONFIG_MFD_INTEL_LPSS_PCI)	+= intel-lpss-pci.o
+obj-$(CONFIG_MFD_INTEL_LPSS_ACPI)	+= intel-lpss-acpi.o
 obj-$(CONFIG_MFD_INTEL_MSIC)	+= intel_msic.o
 obj-$(CONFIG_MFD_PALMAS)	+= palmas.o
 obj-$(CONFIG_MFD_VIPERBOARD)    += viperboard.o
diff --git a/drivers/mfd/intel-lpss-acpi.c b/drivers/mfd/intel-lpss-acpi.c
new file mode 100644
index 0000000..0d92d73
--- /dev/null
+++ b/drivers/mfd/intel-lpss-acpi.c
@@ -0,0 +1,84 @@
+/*
+ * Intel LPSS ACPI support.
+ *
+ * Copyright (C) 2015, Intel Corporation
+ *
+ * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+ *          Mika Westerberg <mika.westerberg@linux.intel.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/acpi.h>
+#include <linux/ioport.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/pm.h>
+#include <linux/pm_runtime.h>
+#include <linux/platform_device.h>
+
+#include "intel-lpss.h"
+
+static const struct intel_lpss_platform_info spt_info = {
+	.clk_rate = 120000000,
+};
+
+static const struct acpi_device_id intel_lpss_acpi_ids[] = {
+	/* SPT */
+	{ "INT3446", (kernel_ulong_t)&spt_info },
+	{ "INT3447", (kernel_ulong_t)&spt_info },
+	{ }
+};
+MODULE_DEVICE_TABLE(acpi, intel_lpss_acpi_ids);
+
+static int intel_lpss_acpi_probe(struct platform_device *pdev)
+{
+	struct intel_lpss_platform_info *info;
+	const struct acpi_device_id *id;
+
+	id = acpi_match_device(intel_lpss_acpi_ids, &pdev->dev);
+	if (!id)
+		return -ENODEV;
+
+	info = devm_kmemdup(&pdev->dev, (void *)id->driver_data, sizeof(*info),
+			    GFP_KERNEL);
+	if (!info)
+		return -ENOMEM;
+
+	info->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	info->irq = platform_get_irq(pdev, 0);
+
+	pm_runtime_set_active(&pdev->dev);
+	pm_runtime_enable(&pdev->dev);
+
+	return intel_lpss_probe(&pdev->dev, info);
+}
+
+static int intel_lpss_acpi_remove(struct platform_device *pdev)
+{
+	intel_lpss_remove(&pdev->dev);
+	pm_runtime_disable(&pdev->dev);
+
+	return 0;
+}
+
+static INTEL_LPSS_PM_OPS(intel_lpss_acpi_pm_ops);
+
+static struct platform_driver intel_lpss_acpi_driver = {
+	.probe = intel_lpss_acpi_probe,
+	.remove = intel_lpss_acpi_remove,
+	.driver = {
+		.name = "intel-lpss",
+		.acpi_match_table = intel_lpss_acpi_ids,
+		.pm = &intel_lpss_acpi_pm_ops,
+	},
+};
+
+module_platform_driver(intel_lpss_acpi_driver);
+
+MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
+MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
+MODULE_DESCRIPTION("Intel LPSS ACPI driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/mfd/intel-lpss-pci.c b/drivers/mfd/intel-lpss-pci.c
new file mode 100644
index 0000000..9236dff
--- /dev/null
+++ b/drivers/mfd/intel-lpss-pci.c
@@ -0,0 +1,113 @@
+/*
+ * Intel LPSS PCI support.
+ *
+ * Copyright (C) 2015, Intel Corporation
+ *
+ * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+ *          Mika Westerberg <mika.westerberg@linux.intel.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/ioport.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/pm.h>
+#include <linux/pm_runtime.h>
+
+#include "intel-lpss.h"
+
+static int intel_lpss_pci_probe(struct pci_dev *pdev,
+				const struct pci_device_id *id)
+{
+	struct intel_lpss_platform_info *info;
+	int ret;
+
+	ret = pcim_enable_device(pdev);
+	if (ret)
+		return ret;
+
+	info = devm_kmemdup(&pdev->dev, (void *)id->driver_data, sizeof(*info),
+			    GFP_KERNEL);
+	if (!info)
+		return -ENOMEM;
+
+	info->mem = &pdev->resource[0];
+	info->irq = pdev->irq;
+
+	/* Probably it is enough to set this for iDMA capable devices only */
+	pci_set_master(pdev);
+
+	ret = intel_lpss_probe(&pdev->dev, info);
+	if (ret)
+		return ret;
+
+	pm_runtime_put(&pdev->dev);
+	pm_runtime_allow(&pdev->dev);
+
+	return 0;
+}
+
+static void intel_lpss_pci_remove(struct pci_dev *pdev)
+{
+	pm_runtime_forbid(&pdev->dev);
+	pm_runtime_get_sync(&pdev->dev);
+
+	intel_lpss_remove(&pdev->dev);
+}
+
+static INTEL_LPSS_PM_OPS(intel_lpss_pci_pm_ops);
+
+static const struct intel_lpss_platform_info spt_info = {
+	.clk_rate = 120000000,
+};
+
+static const struct intel_lpss_platform_info spt_uart_info = {
+	.clk_rate = 120000000,
+	.clk_con_id = "baudclk",
+};
+
+static const struct pci_device_id intel_lpss_pci_ids[] = {
+	/* SPT-LP */
+	{ PCI_VDEVICE(INTEL, 0x9d27), (kernel_ulong_t)&spt_uart_info },
+	{ PCI_VDEVICE(INTEL, 0x9d28), (kernel_ulong_t)&spt_uart_info },
+	{ PCI_VDEVICE(INTEL, 0x9d29), (kernel_ulong_t)&spt_info },
+	{ PCI_VDEVICE(INTEL, 0x9d2a), (kernel_ulong_t)&spt_info },
+	{ PCI_VDEVICE(INTEL, 0x9d60), (kernel_ulong_t)&spt_info },
+	{ PCI_VDEVICE(INTEL, 0x9d61), (kernel_ulong_t)&spt_info },
+	{ PCI_VDEVICE(INTEL, 0x9d62), (kernel_ulong_t)&spt_info },
+	{ PCI_VDEVICE(INTEL, 0x9d63), (kernel_ulong_t)&spt_info },
+	{ PCI_VDEVICE(INTEL, 0x9d64), (kernel_ulong_t)&spt_info },
+	{ PCI_VDEVICE(INTEL, 0x9d65), (kernel_ulong_t)&spt_info },
+	{ PCI_VDEVICE(INTEL, 0x9d66), (kernel_ulong_t)&spt_uart_info },
+	/* SPT-H */
+	{ PCI_VDEVICE(INTEL, 0xa127), (kernel_ulong_t)&spt_uart_info },
+	{ PCI_VDEVICE(INTEL, 0xa128), (kernel_ulong_t)&spt_uart_info },
+	{ PCI_VDEVICE(INTEL, 0xa129), (kernel_ulong_t)&spt_info },
+	{ PCI_VDEVICE(INTEL, 0xa12a), (kernel_ulong_t)&spt_info },
+	{ PCI_VDEVICE(INTEL, 0xa160), (kernel_ulong_t)&spt_info },
+	{ PCI_VDEVICE(INTEL, 0xa161), (kernel_ulong_t)&spt_info },
+	{ PCI_VDEVICE(INTEL, 0xa166), (kernel_ulong_t)&spt_uart_info },
+	{ }
+};
+MODULE_DEVICE_TABLE(pci, intel_lpss_pci_ids);
+
+static struct pci_driver intel_lpss_pci_driver = {
+	.name = "intel-lpss",
+	.id_table = intel_lpss_pci_ids,
+	.probe = intel_lpss_pci_probe,
+	.remove = intel_lpss_pci_remove,
+	.driver = {
+		.pm = &intel_lpss_pci_pm_ops,
+	},
+};
+
+module_pci_driver(intel_lpss_pci_driver);
+
+MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
+MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
+MODULE_DESCRIPTION("Intel LPSS PCI driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/mfd/intel-lpss.c b/drivers/mfd/intel-lpss.c
new file mode 100644
index 0000000..fdf4d5c
--- /dev/null
+++ b/drivers/mfd/intel-lpss.c
@@ -0,0 +1,524 @@
+/*
+ * Intel Sunrisepoint LPSS core support.
+ *
+ * Copyright (C) 2015, Intel Corporation
+ *
+ * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+ *          Mika Westerberg <mika.westerberg@linux.intel.com>
+ *          Heikki Krogerus <heikki.krogerus@linux.intel.com>
+ *          Jarkko Nikula <jarkko.nikula@linux.intel.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/debugfs.h>
+#include <linux/idr.h>
+#include <linux/ioport.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mfd/core.h>
+#include <linux/pm_qos.h>
+#include <linux/pm_runtime.h>
+#include <linux/seq_file.h>
+
+#include "intel-lpss.h"
+
+#define LPSS_DEV_OFFSET		0x000
+#define LPSS_DEV_SIZE		0x200
+#define LPSS_PRIV_OFFSET	0x200
+#define LPSS_PRIV_SIZE		0x100
+#define LPSS_IDMA64_OFFSET	0x800
+#define LPSS_IDMA64_SIZE	0x800
+
+/* Offsets from lpss->priv */
+#define LPSS_PRIV_RESETS		0x04
+#define LPSS_PRIV_RESETS_FUNC		BIT(2)
+#define LPSS_PRIV_RESETS_IDMA		0x3
+
+#define LPSS_PRIV_ACTIVELTR		0x10
+#define LPSS_PRIV_IDLELTR		0x14
+
+#define LPSS_PRIV_LTR_REQ		BIT(15)
+#define LPSS_PRIV_LTR_SCALE_MASK	0xc00
+#define LPSS_PRIV_LTR_SCALE_1US		0x800
+#define LPSS_PRIV_LTR_SCALE_32US	0xc00
+#define LPSS_PRIV_LTR_VALUE_MASK	0x3ff
+
+#define LPSS_PRIV_SSP_REG		0x20
+#define LPSS_PRIV_SSP_REG_DIS_DMA_FIN	BIT(0)
+
+#define LPSS_PRIV_REMAP_ADDR_LO		0x40
+#define LPSS_PRIV_REMAP_ADDR_HI		0x44
+
+#define LPSS_PRIV_CAPS			0xfc
+#define LPSS_PRIV_CAPS_NO_IDMA		BIT(8)
+#define LPSS_PRIV_CAPS_TYPE_SHIFT	4
+#define LPSS_PRIV_CAPS_TYPE_MASK	(0xf << LPSS_PRIV_CAPS_TYPE_SHIFT)
+
+/* This matches the type field in CAPS register */
+enum intel_lpss_dev_type {
+	LPSS_DEV_I2C = 0,
+	LPSS_DEV_UART,
+	LPSS_DEV_SPI,
+};
+
+struct intel_lpss {
+	const struct intel_lpss_platform_info *info;
+	enum intel_lpss_dev_type type;
+	struct clk *clk;
+	struct clk_lookup *clock;
+	const struct mfd_cell *cell;
+	struct device *dev;
+	void __iomem *priv;
+	int devid;
+	u32 caps;
+	u32 active_ltr;
+	u32 idle_ltr;
+	struct dentry *debugfs;
+};
+
+static const struct resource intel_lpss_dev_resources[] = {
+	DEFINE_RES_MEM_NAMED(LPSS_DEV_OFFSET, LPSS_DEV_SIZE, "lpss_dev"),
+	DEFINE_RES_MEM_NAMED(LPSS_PRIV_OFFSET, LPSS_PRIV_SIZE, "lpss_priv"),
+	DEFINE_RES_IRQ(0),
+};
+
+static const struct resource intel_lpss_idma64_resources[] = {
+	DEFINE_RES_MEM(LPSS_IDMA64_OFFSET, LPSS_IDMA64_SIZE),
+	DEFINE_RES_IRQ(0),
+};
+
+#define LPSS_IDMA64_DRIVER_NAME		"idma64"
+
+/*
+ * Cells needs to be ordered so that the iDMA is created first. This is
+ * because we need to be sure the DMA is available when the host controller
+ * driver is probed.
+ */
+static const struct mfd_cell intel_lpss_idma64_cell = {
+	.name = LPSS_IDMA64_DRIVER_NAME,
+	.num_resources = ARRAY_SIZE(intel_lpss_idma64_resources),
+	.resources = intel_lpss_idma64_resources,
+};
+
+static const struct mfd_cell intel_lpss_i2c_cell = {
+	.name = "i2c_designware",
+	.num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
+	.resources = intel_lpss_dev_resources,
+};
+
+static const struct mfd_cell intel_lpss_uart_cell = {
+	.name = "dw-apb-uart",
+	.num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
+	.resources = intel_lpss_dev_resources,
+};
+
+static const struct mfd_cell intel_lpss_spi_cell = {
+	.name = "pxa2xx-spi",
+	.num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
+	.resources = intel_lpss_dev_resources,
+};
+
+static DEFINE_IDA(intel_lpss_devid_ida);
+static struct dentry *intel_lpss_debugfs;
+
+static int intel_lpss_request_dma_module(const char *name)
+{
+	static bool intel_lpss_dma_requested;
+
+	if (intel_lpss_dma_requested)
+		return 0;
+
+	intel_lpss_dma_requested = true;
+	return request_module("%s", name);
+}
+
+static void intel_lpss_cache_ltr(struct intel_lpss *lpss)
+{
+	lpss->active_ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR);
+	lpss->idle_ltr = readl(lpss->priv + LPSS_PRIV_IDLELTR);
+}
+
+static int intel_lpss_debugfs_add(struct intel_lpss *lpss)
+{
+	struct dentry *dir;
+
+	dir = debugfs_create_dir(dev_name(lpss->dev), intel_lpss_debugfs);
+	if (IS_ERR(dir))
+		return PTR_ERR(dir);
+
+	/* Cache the values into lpss structure */
+	intel_lpss_cache_ltr(lpss);
+
+	debugfs_create_x32("capabilities", S_IRUGO, dir, &lpss->caps);
+	debugfs_create_x32("active_ltr", S_IRUGO, dir, &lpss->active_ltr);
+	debugfs_create_x32("idle_ltr", S_IRUGO, dir, &lpss->idle_ltr);
+
+	lpss->debugfs = dir;
+	return 0;
+}
+
+static void intel_lpss_debugfs_remove(struct intel_lpss *lpss)
+{
+	debugfs_remove_recursive(lpss->debugfs);
+}
+
+static void intel_lpss_ltr_set(struct device *dev, s32 val)
+{
+	struct intel_lpss *lpss = dev_get_drvdata(dev);
+	u32 ltr;
+
+	/*
+	 * Program latency tolerance (LTR) accordingly what has been asked
+	 * by the PM QoS layer or disable it in case we were passed
+	 * negative value or PM_QOS_LATENCY_ANY.
+	 */
+	ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR);
+
+	if (val == PM_QOS_LATENCY_ANY || val < 0) {
+		ltr &= ~LPSS_PRIV_LTR_REQ;
+	} else {
+		ltr |= LPSS_PRIV_LTR_REQ;
+		ltr &= ~LPSS_PRIV_LTR_SCALE_MASK;
+		ltr &= ~LPSS_PRIV_LTR_VALUE_MASK;
+
+		if (val > LPSS_PRIV_LTR_VALUE_MASK)
+			ltr |= LPSS_PRIV_LTR_SCALE_32US | val >> 5;
+		else
+			ltr |= LPSS_PRIV_LTR_SCALE_1US | val;
+	}
+
+	if (ltr == lpss->active_ltr)
+		return;
+
+	writel(ltr, lpss->priv + LPSS_PRIV_ACTIVELTR);
+	writel(ltr, lpss->priv + LPSS_PRIV_IDLELTR);
+
+	/* Cache the values into lpss structure */
+	intel_lpss_cache_ltr(lpss);
+}
+
+static void intel_lpss_ltr_expose(struct intel_lpss *lpss)
+{
+	lpss->dev->power.set_latency_tolerance = intel_lpss_ltr_set;
+	dev_pm_qos_expose_latency_tolerance(lpss->dev);
+}
+
+static void intel_lpss_ltr_hide(struct intel_lpss *lpss)
+{
+	dev_pm_qos_hide_latency_tolerance(lpss->dev);
+	lpss->dev->power.set_latency_tolerance = NULL;
+}
+
+static int intel_lpss_assign_devs(struct intel_lpss *lpss)
+{
+	unsigned int type;
+
+	type = lpss->caps & LPSS_PRIV_CAPS_TYPE_MASK;
+	type >>= LPSS_PRIV_CAPS_TYPE_SHIFT;
+
+	switch (type) {
+	case LPSS_DEV_I2C:
+		lpss->cell = &intel_lpss_i2c_cell;
+		break;
+	case LPSS_DEV_UART:
+		lpss->cell = &intel_lpss_uart_cell;
+		break;
+	case LPSS_DEV_SPI:
+		lpss->cell = &intel_lpss_spi_cell;
+		break;
+	default:
+		return -ENODEV;
+	}
+
+	lpss->type = type;
+
+	return 0;
+}
+
+static bool intel_lpss_has_idma(const struct intel_lpss *lpss)
+{
+	return (lpss->caps & LPSS_PRIV_CAPS_NO_IDMA) == 0;
+}
+
+static void intel_lpss_set_remap_addr(const struct intel_lpss *lpss)
+{
+	resource_size_t addr = lpss->info->mem->start;
+
+	writel(addr, lpss->priv + LPSS_PRIV_REMAP_ADDR_LO);
+#if BITS_PER_LONG > 32
+	writel(addr >> 32, lpss->priv + LPSS_PRIV_REMAP_ADDR_HI);
+#else
+	writel(0, lpss->priv + LPSS_PRIV_REMAP_ADDR_HI);
+#endif
+}
+
+static void intel_lpss_deassert_reset(const struct intel_lpss *lpss)
+{
+	u32 value = LPSS_PRIV_RESETS_FUNC | LPSS_PRIV_RESETS_IDMA;
+
+	/* Bring out the device from reset */
+	writel(value, lpss->priv + LPSS_PRIV_RESETS);
+}
+
+static void intel_lpss_init_dev(const struct intel_lpss *lpss)
+{
+	u32 value = LPSS_PRIV_SSP_REG_DIS_DMA_FIN;
+
+	intel_lpss_deassert_reset(lpss);
+
+	if (!intel_lpss_has_idma(lpss))
+		return;
+
+	intel_lpss_set_remap_addr(lpss);
+
+	/* Make sure that SPI multiblock DMA transfers are re-enabled */
+	if (lpss->type == LPSS_DEV_SPI)
+		writel(value, lpss->priv + LPSS_PRIV_SSP_REG);
+}
+
+static void intel_lpss_unregister_clock_tree(struct clk *clk)
+{
+	struct clk *parent;
+
+	while (clk) {
+		parent = clk_get_parent(clk);
+		clk_unregister(clk);
+		clk = parent;
+	}
+}
+
+static int intel_lpss_register_clock_divider(struct intel_lpss *lpss,
+					     const char *devname,
+					     struct clk **clk)
+{
+	char name[32];
+	struct clk *tmp = *clk;
+
+	snprintf(name, sizeof(name), "%s-enable", devname);
+	tmp = clk_register_gate(NULL, name, __clk_get_name(tmp), 0,
+				lpss->priv, 0, 0, NULL);
+	if (IS_ERR(tmp))
+		return PTR_ERR(tmp);
+
+	snprintf(name, sizeof(name), "%s-div", devname);
+	tmp = clk_register_fractional_divider(NULL, name, __clk_get_name(tmp),
+					      0, lpss->priv, 1, 15, 16, 15, 0,
+					      NULL);
+	if (IS_ERR(tmp))
+		return PTR_ERR(tmp);
+	*clk = tmp;
+
+	snprintf(name, sizeof(name), "%s-update", devname);
+	tmp = clk_register_gate(NULL, name, __clk_get_name(tmp),
+				CLK_SET_RATE_PARENT, lpss->priv, 31, 0, NULL);
+	if (IS_ERR(tmp))
+		return PTR_ERR(tmp);
+	*clk = tmp;
+
+	return 0;
+}
+
+static int intel_lpss_register_clock(struct intel_lpss *lpss)
+{
+	const struct mfd_cell *cell = lpss->cell;
+	struct clk *clk;
+	char devname[24];
+	int ret;
+
+	if (!lpss->info->clk_rate)
+		return 0;
+
+	/* Root clock */
+	clk = clk_register_fixed_rate(NULL, dev_name(lpss->dev), NULL,
+				      CLK_IS_ROOT, lpss->info->clk_rate);
+	if (IS_ERR(clk))
+		return PTR_ERR(clk);
+
+	snprintf(devname, sizeof(devname), "%s.%d", cell->name, lpss->devid);
+
+	/*
+	 * Support for clock divider only if it has some preset value.
+	 * Otherwise we assume that the divider is not used.
+	 */
+	if (lpss->type != LPSS_DEV_I2C) {
+		ret = intel_lpss_register_clock_divider(lpss, devname, &clk);
+		if (ret)
+			goto err_clk_register;
+	}
+
+	ret = -ENOMEM;
+
+	/* Clock for the host controller */
+	lpss->clock = clkdev_create(clk, lpss->info->clk_con_id, "%s", devname);
+	if (!lpss->clock)
+		goto err_clk_register;
+
+	lpss->clk = clk;
+
+	return 0;
+
+err_clk_register:
+	intel_lpss_unregister_clock_tree(clk);
+
+	return ret;
+}
+
+static void intel_lpss_unregister_clock(struct intel_lpss *lpss)
+{
+	if (IS_ERR_OR_NULL(lpss->clk))
+		return;
+
+	clkdev_drop(lpss->clock);
+	intel_lpss_unregister_clock_tree(lpss->clk);
+}
+
+int intel_lpss_probe(struct device *dev,
+		     const struct intel_lpss_platform_info *info)
+{
+	struct intel_lpss *lpss;
+	int ret;
+
+	if (!info || !info->mem || info->irq <= 0)
+		return -EINVAL;
+
+	lpss = devm_kzalloc(dev, sizeof(*lpss), GFP_KERNEL);
+	if (!lpss)
+		return -ENOMEM;
+
+	lpss->priv = devm_ioremap(dev, info->mem->start + LPSS_PRIV_OFFSET,
+				  LPSS_PRIV_SIZE);
+	if (!lpss->priv)
+		return -ENOMEM;
+
+	lpss->info = info;
+	lpss->dev = dev;
+	lpss->caps = readl(lpss->priv + LPSS_PRIV_CAPS);
+
+	dev_set_drvdata(dev, lpss);
+
+	ret = intel_lpss_assign_devs(lpss);
+	if (ret)
+		return ret;
+
+	intel_lpss_init_dev(lpss);
+
+	lpss->devid = ida_simple_get(&intel_lpss_devid_ida, 0, 0, GFP_KERNEL);
+	if (lpss->devid < 0)
+		return lpss->devid;
+
+	ret = intel_lpss_register_clock(lpss);
+	if (ret)
+		goto err_clk_register;
+
+	intel_lpss_ltr_expose(lpss);
+
+	ret = intel_lpss_debugfs_add(lpss);
+	if (ret)
+		dev_warn(dev, "Failed to create debugfs entries\n");
+
+	if (intel_lpss_has_idma(lpss)) {
+		/*
+		 * Ensure the DMA driver is loaded before the host
+		 * controller device appears, so that the host controller
+		 * driver can request its DMA channels as early as
+		 * possible.
+		 *
+		 * If the DMA module is not there that's OK as well.
+		 */
+		intel_lpss_request_dma_module(LPSS_IDMA64_DRIVER_NAME);
+
+		ret = mfd_add_devices(dev, lpss->devid, &intel_lpss_idma64_cell,
+				      1, info->mem, info->irq, NULL);
+		if (ret)
+			dev_warn(dev, "Failed to add %s, fallback to PIO\n",
+				 LPSS_IDMA64_DRIVER_NAME);
+	}
+
+	ret = mfd_add_devices(dev, lpss->devid, lpss->cell,
+			      1, info->mem, info->irq, NULL);
+	if (ret)
+		goto err_remove_ltr;
+
+	return 0;
+
+err_remove_ltr:
+	intel_lpss_debugfs_remove(lpss);
+	intel_lpss_ltr_hide(lpss);
+
+err_clk_register:
+	ida_simple_remove(&intel_lpss_devid_ida, lpss->devid);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(intel_lpss_probe);
+
+void intel_lpss_remove(struct device *dev)
+{
+	struct intel_lpss *lpss = dev_get_drvdata(dev);
+
+	mfd_remove_devices(dev);
+	intel_lpss_debugfs_remove(lpss);
+	intel_lpss_ltr_hide(lpss);
+	intel_lpss_unregister_clock(lpss);
+	ida_simple_remove(&intel_lpss_devid_ida, lpss->devid);
+}
+EXPORT_SYMBOL_GPL(intel_lpss_remove);
+
+static int resume_lpss_device(struct device *dev, void *data)
+{
+	pm_runtime_resume(dev);
+	return 0;
+}
+
+int intel_lpss_prepare(struct device *dev)
+{
+	/*
+	 * Resume both child devices before entering system sleep. This
+	 * ensures that they are in proper state before they get suspended.
+	 */
+	device_for_each_child_reverse(dev, NULL, resume_lpss_device);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(intel_lpss_prepare);
+
+int intel_lpss_suspend(struct device *dev)
+{
+	return 0;
+}
+EXPORT_SYMBOL_GPL(intel_lpss_suspend);
+
+int intel_lpss_resume(struct device *dev)
+{
+	struct intel_lpss *lpss = dev_get_drvdata(dev);
+
+	intel_lpss_init_dev(lpss);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(intel_lpss_resume);
+
+static int __init intel_lpss_init(void)
+{
+	intel_lpss_debugfs = debugfs_create_dir("intel_lpss", NULL);
+	return 0;
+}
+module_init(intel_lpss_init);
+
+static void __exit intel_lpss_exit(void)
+{
+	debugfs_remove(intel_lpss_debugfs);
+}
+module_exit(intel_lpss_exit);
+
+MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
+MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
+MODULE_AUTHOR("Heikki Krogerus <heikki.krogerus@linux.intel.com>");
+MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@linux.intel.com>");
+MODULE_DESCRIPTION("Intel LPSS core driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/mfd/intel-lpss.h b/drivers/mfd/intel-lpss.h
new file mode 100644
index 0000000..f28cb28a
--- /dev/null
+++ b/drivers/mfd/intel-lpss.h
@@ -0,0 +1,62 @@
+/*
+ * Intel LPSS core support.
+ *
+ * Copyright (C) 2015, Intel Corporation
+ *
+ * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+ *          Mika Westerberg <mika.westerberg@linux.intel.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __MFD_INTEL_LPSS_H
+#define __MFD_INTEL_LPSS_H
+
+struct device;
+struct resource;
+
+struct intel_lpss_platform_info {
+	struct resource *mem;
+	int irq;
+	unsigned long clk_rate;
+	const char *clk_con_id;
+};
+
+int intel_lpss_probe(struct device *dev,
+		     const struct intel_lpss_platform_info *info);
+void intel_lpss_remove(struct device *dev);
+
+#ifdef CONFIG_PM
+int intel_lpss_prepare(struct device *dev);
+int intel_lpss_suspend(struct device *dev);
+int intel_lpss_resume(struct device *dev);
+
+#ifdef CONFIG_PM_SLEEP
+#define INTEL_LPSS_SLEEP_PM_OPS			\
+	.prepare = intel_lpss_prepare,		\
+	.suspend = intel_lpss_suspend,		\
+	.resume = intel_lpss_resume,		\
+	.freeze = intel_lpss_suspend,		\
+	.thaw = intel_lpss_resume,		\
+	.poweroff = intel_lpss_suspend,		\
+	.restore = intel_lpss_resume,
+#endif
+
+#define INTEL_LPSS_RUNTIME_PM_OPS		\
+	.runtime_suspend = intel_lpss_suspend,	\
+	.runtime_resume = intel_lpss_resume,
+
+#else /* !CONFIG_PM */
+#define INTEL_LPSS_SLEEP_PM_OPS
+#define INTEL_LPSS_RUNTIME_PM_OPS
+#endif /* CONFIG_PM */
+
+#define INTEL_LPSS_PM_OPS(name)			\
+const struct dev_pm_ops name = {		\
+	INTEL_LPSS_SLEEP_PM_OPS			\
+	INTEL_LPSS_RUNTIME_PM_OPS		\
+}
+
+#endif /* __MFD_INTEL_LPSS_H */
-- 
2.4.6

Re: [PATCH v6 0/8] mfd: introduce a driver for LPSS devices on SPT

[Lee Jones]

FAO Stephen Boyd,

> Stephen, can you, please, have a look into patch 8 regarding to clock name
> matching and other stuff Lee asked?

Patch 8:

      "Can you review the clock implementation please?  It looks
      fragile to me as it relies heavily on device names constructed
      of MFD cell names and IDA numbers cat'ed together!"

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

Re: [PATCH v6 0/8] mfd: introduce a driver for LPSS devices on SPT

[Mika Westerberg]

On Mon, Jul 27, 2015 at 04:27:33PM +0100, Lee Jones wrote:
> FAO Stephen Boyd,
> 
> > Stephen, can you, please, have a look into patch 8 regarding to clock name
> > matching and other stuff Lee asked?
> 
> Patch 8:
> 
>       "Can you review the clock implementation please?  It looks
>       fragile to me as it relies heavily on device names constructed
>       of MFD cell names and IDA numbers cat'ed together!"

Lee, can you suggest an alternative then?

Why we are doing it like this is that number of different LPSS devices
changes from SoC to SoC. In addition to that the device (called "slice")
might have iDMA block or not.

Since the drivers in question (pxa2xx-spi, i2c-designware and 8250_dw)
use standard clk framework to request their clocks the Linux device must
have clock registered which matches the device in advance.

Because we add the host controller device dynamically (from the MFD
driver) based on how many devices are actually present, we need somehow
predict what would be the correct name and instance number for that
device to get the clock for it. That's the reason we use IDA here along
with the cell name (or driver name).

Re: [PATCH v6 0/8] mfd: introduce a driver for LPSS devices on SPT

[Lee Jones]

On Mon, 27 Jul 2015, Mika Westerberg wrote:

> On Mon, Jul 27, 2015 at 04:27:33PM +0100, Lee Jones wrote:
> > FAO Stephen Boyd,
> > 
> > > Stephen, can you, please, have a look into patch 8 regarding to clock name
> > > matching and other stuff Lee asked?
> > 
> > Patch 8:
> > 
> >       "Can you review the clock implementation please?  It looks
> >       fragile to me as it relies heavily on device names constructed
> >       of MFD cell names and IDA numbers cat'ed together!"
> 
> Lee, can you suggest an alternative then?
> 
> Why we are doing it like this is that number of different LPSS devices
> changes from SoC to SoC. In addition to that the device (called "slice")
> might have iDMA block or not.
> 
> Since the drivers in question (pxa2xx-spi, i2c-designware and 8250_dw)
> use standard clk framework to request their clocks the Linux device must
> have clock registered which matches the device in advance.
> 
> Because we add the host controller device dynamically (from the MFD
> driver) based on how many devices are actually present, we need somehow
> predict what would be the correct name and instance number for that
> device to get the clock for it. That's the reason we use IDA here along
> with the cell name (or driver name).

I'm sure there are perfectly viable reasons for you doing this.  And I
don't know the CCF well enough to know whether it's the best idea or
not, or else I would have made a suggestion rather than waiting all
this time.

It's for this reason that I needed Mike (now Stephen) to take a look
and give me either an Ack, to say it's the best solution, or to
provide a better alternative.

Until that happens, I'm stuck!

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
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Re: [PATCH v6 0/8] mfd: introduce a driver for LPSS devices on SPT

[Lee Jones]

On Mon, 27 Jul 2015, Rafael J. Wysocki wrote:

> On Monday, July 27, 2015 05:24:13 PM Lee Jones wrote:
> > On Mon, 27 Jul 2015, Mika Westerberg wrote:
> > 
> > > On Mon, Jul 27, 2015 at 04:27:33PM +0100, Lee Jones wrote:
> > > > FAO Stephen Boyd,
> > > > 
> > > > > Stephen, can you, please, have a look into patch 8 regarding to clock name
> > > > > matching and other stuff Lee asked?
> > > > 
> > > > Patch 8:
> > > > 
> > > >       "Can you review the clock implementation please?  It looks
> > > >       fragile to me as it relies heavily on device names constructed
> > > >       of MFD cell names and IDA numbers cat'ed together!"
> > > 
> > > Lee, can you suggest an alternative then?
> > > 
> > > Why we are doing it like this is that number of different LPSS devices
> > > changes from SoC to SoC. In addition to that the device (called "slice")
> > > might have iDMA block or not.
> > > 
> > > Since the drivers in question (pxa2xx-spi, i2c-designware and 8250_dw)
> > > use standard clk framework to request their clocks the Linux device must
> > > have clock registered which matches the device in advance.
> > > 
> > > Because we add the host controller device dynamically (from the MFD
> > > driver) based on how many devices are actually present, we need somehow
> > > predict what would be the correct name and instance number for that
> > > device to get the clock for it. That's the reason we use IDA here along
> > > with the cell name (or driver name).
> > 
> > I'm sure there are perfectly viable reasons for you doing this.  And I
> > don't know the CCF well enough to know whether it's the best idea or
> > not, or else I would have made a suggestion rather than waiting all
> > this time.
> > 
> > It's for this reason that I needed Mike (now Stephen) to take a look
> > and give me either an Ack, to say it's the best solution, or to
> > provide a better alternative.
> > 
> > Until that happens, I'm stuck!
> 
> Well, what if we had no one at hand to review that code?  Would that mean it
> would not be applicable forever?

No, but that's not the case is it?

I don't understand why Mike and Stephen aren't helping!

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

Re: [PATCH v6 0/8] mfd: introduce a driver for LPSS devices on SPT

[Lee Jones]

On Mon, 27 Jul 2015, Lee Jones wrote:

> On Mon, 27 Jul 2015, Rafael J. Wysocki wrote:
> 
> > On Monday, July 27, 2015 05:24:13 PM Lee Jones wrote:
> > > On Mon, 27 Jul 2015, Mika Westerberg wrote:
> > > 
> > > > On Mon, Jul 27, 2015 at 04:27:33PM +0100, Lee Jones wrote:
> > > > > FAO Stephen Boyd,
> > > > > 
> > > > > > Stephen, can you, please, have a look into patch 8 regarding to clock name
> > > > > > matching and other stuff Lee asked?
> > > > > 
> > > > > Patch 8:
> > > > > 
> > > > >       "Can you review the clock implementation please?  It looks
> > > > >       fragile to me as it relies heavily on device names constructed
> > > > >       of MFD cell names and IDA numbers cat'ed together!"
> > > > 
> > > > Lee, can you suggest an alternative then?
> > > > 
> > > > Why we are doing it like this is that number of different LPSS devices
> > > > changes from SoC to SoC. In addition to that the device (called "slice")
> > > > might have iDMA block or not.
> > > > 
> > > > Since the drivers in question (pxa2xx-spi, i2c-designware and 8250_dw)
> > > > use standard clk framework to request their clocks the Linux device must
> > > > have clock registered which matches the device in advance.
> > > > 
> > > > Because we add the host controller device dynamically (from the MFD
> > > > driver) based on how many devices are actually present, we need somehow
> > > > predict what would be the correct name and instance number for that
> > > > device to get the clock for it. That's the reason we use IDA here along
> > > > with the cell name (or driver name).
> > > 
> > > I'm sure there are perfectly viable reasons for you doing this.  And I
> > > don't know the CCF well enough to know whether it's the best idea or
> > > not, or else I would have made a suggestion rather than waiting all
> > > this time.
> > > 
> > > It's for this reason that I needed Mike (now Stephen) to take a look
> > > and give me either an Ack, to say it's the best solution, or to
> > > provide a better alternative.
> > > 
> > > Until that happens, I'm stuck!
> > 
> > Well, what if we had no one at hand to review that code?  Would that mean it
> > would not be applicable forever?
> 
> No, but that's not the case is it?
> 
> I don't understand why Mike and Stephen aren't helping!

I'll wait until tomorrow and if we haven't heard anything I'll make a
decision.

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
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Re: [PATCH v6 0/8] mfd: introduce a driver for LPSS devices on SPT

[Rafael J. Wysocki]

On Monday, July 27, 2015 05:24:13 PM Lee Jones wrote:
> On Mon, 27 Jul 2015, Mika Westerberg wrote:
> 
> > On Mon, Jul 27, 2015 at 04:27:33PM +0100, Lee Jones wrote:
> > > FAO Stephen Boyd,
> > > 
> > > > Stephen, can you, please, have a look into patch 8 regarding to clock name
> > > > matching and other stuff Lee asked?
> > > 
> > > Patch 8:
> > > 
> > >       "Can you review the clock implementation please?  It looks
> > >       fragile to me as it relies heavily on device names constructed
> > >       of MFD cell names and IDA numbers cat'ed together!"
> > 
> > Lee, can you suggest an alternative then?
> > 
> > Why we are doing it like this is that number of different LPSS devices
> > changes from SoC to SoC. In addition to that the device (called "slice")
> > might have iDMA block or not.
> > 
> > Since the drivers in question (pxa2xx-spi, i2c-designware and 8250_dw)
> > use standard clk framework to request their clocks the Linux device must
> > have clock registered which matches the device in advance.
> > 
> > Because we add the host controller device dynamically (from the MFD
> > driver) based on how many devices are actually present, we need somehow
> > predict what would be the correct name and instance number for that
> > device to get the clock for it. That's the reason we use IDA here along
> > with the cell name (or driver name).
> 
> I'm sure there are perfectly viable reasons for you doing this.  And I
> don't know the CCF well enough to know whether it's the best idea or
> not, or else I would have made a suggestion rather than waiting all
> this time.
> 
> It's for this reason that I needed Mike (now Stephen) to take a look
> and give me either an Ack, to say it's the best solution, or to
> provide a better alternative.
> 
> Until that happens, I'm stuck!

Well, what if we had no one at hand to review that code?  Would that mean it
would not be applicable forever?

Thanks,
Rafael

Re: [PATCH v6 0/8] mfd: introduce a driver for LPSS devices on SPT

[Rafael J. Wysocki]

On Monday, July 27, 2015 10:29:34 PM Lee Jones wrote:
> On Mon, 27 Jul 2015, Lee Jones wrote:
> 
> > On Mon, 27 Jul 2015, Rafael J. Wysocki wrote:
> > 
> > > On Monday, July 27, 2015 05:24:13 PM Lee Jones wrote:
> > > > On Mon, 27 Jul 2015, Mika Westerberg wrote:
> > > > 
> > > > > On Mon, Jul 27, 2015 at 04:27:33PM +0100, Lee Jones wrote:
> > > > > > FAO Stephen Boyd,
> > > > > > 
> > > > > > > Stephen, can you, please, have a look into patch 8 regarding to clock name
> > > > > > > matching and other stuff Lee asked?
> > > > > > 
> > > > > > Patch 8:
> > > > > > 
> > > > > >       "Can you review the clock implementation please?  It looks
> > > > > >       fragile to me as it relies heavily on device names constructed
> > > > > >       of MFD cell names and IDA numbers cat'ed together!"
> > > > > 
> > > > > Lee, can you suggest an alternative then?
> > > > > 
> > > > > Why we are doing it like this is that number of different LPSS devices
> > > > > changes from SoC to SoC. In addition to that the device (called "slice")
> > > > > might have iDMA block or not.
> > > > > 
> > > > > Since the drivers in question (pxa2xx-spi, i2c-designware and 8250_dw)
> > > > > use standard clk framework to request their clocks the Linux device must
> > > > > have clock registered which matches the device in advance.
> > > > > 
> > > > > Because we add the host controller device dynamically (from the MFD
> > > > > driver) based on how many devices are actually present, we need somehow
> > > > > predict what would be the correct name and instance number for that
> > > > > device to get the clock for it. That's the reason we use IDA here along
> > > > > with the cell name (or driver name).
> > > > 
> > > > I'm sure there are perfectly viable reasons for you doing this.  And I
> > > > don't know the CCF well enough to know whether it's the best idea or
> > > > not, or else I would have made a suggestion rather than waiting all
> > > > this time.
> > > > 
> > > > It's for this reason that I needed Mike (now Stephen) to take a look
> > > > and give me either an Ack, to say it's the best solution, or to
> > > > provide a better alternative.
> > > > 
> > > > Until that happens, I'm stuck!
> > > 
> > > Well, what if we had no one at hand to review that code?  Would that mean it
> > > would not be applicable forever?
> > 
> > No, but that's not the case is it?
> > 
> > I don't understand why Mike and Stephen aren't helping!
> 
> I'll wait until tomorrow and if we haven't heard anything I'll make a
> decision.

OK, thanks!

BTW, I don't have the time to review every single patch using ACPI
or one of the PM frameworks.  If people who use them make mistakes,
it is their burden to fix those mistakes when they show up in testing.

What's happening here is that Andy and Mika are taking the responsibility
for fixing the new code if it turns out to be buggy and so it's their
problem if it happens to be broken.

And you can still revert commits that introduce bugs as a last resort.

Re: [PATCH v6 0/8] mfd: introduce a driver for LPSS devices on SPT

[Lee Jones]

On Tue, 28 Jul 2015, Rafael J. Wysocki wrote:

> On Monday, July 27, 2015 10:29:34 PM Lee Jones wrote:
> > On Mon, 27 Jul 2015, Lee Jones wrote:
> > 
> > > On Mon, 27 Jul 2015, Rafael J. Wysocki wrote:
> > > 
> > > > On Monday, July 27, 2015 05:24:13 PM Lee Jones wrote:
> > > > > On Mon, 27 Jul 2015, Mika Westerberg wrote:
> > > > > 
> > > > > > On Mon, Jul 27, 2015 at 04:27:33PM +0100, Lee Jones wrote:
> > > > > > > FAO Stephen Boyd,
> > > > > > > 
> > > > > > > > Stephen, can you, please, have a look into patch 8 regarding to clock name
> > > > > > > > matching and other stuff Lee asked?
> > > > > > > 
> > > > > > > Patch 8:
> > > > > > > 
> > > > > > >       "Can you review the clock implementation please?  It looks
> > > > > > >       fragile to me as it relies heavily on device names constructed
> > > > > > >       of MFD cell names and IDA numbers cat'ed together!"
> > > > > > 
> > > > > > Lee, can you suggest an alternative then?
> > > > > > 
> > > > > > Why we are doing it like this is that number of different LPSS devices
> > > > > > changes from SoC to SoC. In addition to that the device (called "slice")
> > > > > > might have iDMA block or not.
> > > > > > 
> > > > > > Since the drivers in question (pxa2xx-spi, i2c-designware and 8250_dw)
> > > > > > use standard clk framework to request their clocks the Linux device must
> > > > > > have clock registered which matches the device in advance.
> > > > > > 
> > > > > > Because we add the host controller device dynamically (from the MFD
> > > > > > driver) based on how many devices are actually present, we need somehow
> > > > > > predict what would be the correct name and instance number for that
> > > > > > device to get the clock for it. That's the reason we use IDA here along
> > > > > > with the cell name (or driver name).
> > > > > 
> > > > > I'm sure there are perfectly viable reasons for you doing this.  And I
> > > > > don't know the CCF well enough to know whether it's the best idea or
> > > > > not, or else I would have made a suggestion rather than waiting all
> > > > > this time.
> > > > > 
> > > > > It's for this reason that I needed Mike (now Stephen) to take a look
> > > > > and give me either an Ack, to say it's the best solution, or to
> > > > > provide a better alternative.
> > > > > 
> > > > > Until that happens, I'm stuck!
> > > > 
> > > > Well, what if we had no one at hand to review that code?  Would that mean it
> > > > would not be applicable forever?
> > > 
> > > No, but that's not the case is it?
> > > 
> > > I don't understand why Mike and Stephen aren't helping!
> > 
> > I'll wait until tomorrow and if we haven't heard anything I'll make a
> > decision.
> 
> OK, thanks!
> 
> BTW, I don't have the time to review every single patch using ACPI
> or one of the PM frameworks.  If people who use them make mistakes,
> it is their burden to fix those mistakes when they show up in testing.
> 
> What's happening here is that Andy and Mika are taking the responsibility
> for fixing the new code if it turns out to be buggy and so it's their
> problem if it happens to be broken.
> 
> And you can still revert commits that introduce bugs as a last resort.

I'm fine with that in principle.  My issue here was that it looks
wrong to me.  I just don't know enough about the inner workings of the
CCF to be able to say that for sure, or to provide a suitable
alternative.  I think, probably the correct thing to do is to have an
accompanying clock driver, but who knows (I guess Stephen and Mike to,
but are seemingly unwilling to help).

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

Re: [PATCH v6 1/8] PM / QoS: Make it possible to expose device latency tolerance to userspace

[Lee Jones]

On Mon, 27 Jul 2015, Andy Shevchenko wrote:

> From: Mika Westerberg <mika.westerberg@linux.intel.com>
> 
> Typically when a device is created the bus core it belongs to (for example
> PCI) does not know if the device supports things like latency tolerance.
> This is left to the driver that binds to the device in question. However,
> at that time the device has already been created and there is no way to set
> its dev->power.set_latency_tolerance anymore.
> 
> So follow what has been done for other PM QoS attributes as well and allow
> drivers to expose and hide latency tolerance from userspace, if the device
> supports it.
> 
> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> ---
>  drivers/base/power/power.h |  2 ++
>  drivers/base/power/qos.c   | 37 +++++++++++++++++++++++++++++++++++++
>  drivers/base/power/sysfs.c | 11 +++++++++++
>  include/linux/pm_qos.h     |  5 +++++
>  4 files changed, 55 insertions(+)

Applied, thanks.  Pull request to follow.

> diff --git a/drivers/base/power/power.h b/drivers/base/power/power.h
> index f1a5d95..998fa6b 100644
> --- a/drivers/base/power/power.h
> +++ b/drivers/base/power/power.h
> @@ -73,6 +73,8 @@ extern int pm_qos_sysfs_add_resume_latency(struct device *dev);
>  extern void pm_qos_sysfs_remove_resume_latency(struct device *dev);
>  extern int pm_qos_sysfs_add_flags(struct device *dev);
>  extern void pm_qos_sysfs_remove_flags(struct device *dev);
> +extern int pm_qos_sysfs_add_latency_tolerance(struct device *dev);
> +extern void pm_qos_sysfs_remove_latency_tolerance(struct device *dev);
>  
>  #else /* CONFIG_PM */
>  
> diff --git a/drivers/base/power/qos.c b/drivers/base/power/qos.c
> index e56d538..7f3646e 100644
> --- a/drivers/base/power/qos.c
> +++ b/drivers/base/power/qos.c
> @@ -883,3 +883,40 @@ int dev_pm_qos_update_user_latency_tolerance(struct device *dev, s32 val)
>  	mutex_unlock(&dev_pm_qos_mtx);
>  	return ret;
>  }
> +
> +/**
> + * dev_pm_qos_expose_latency_tolerance - Expose latency tolerance to userspace
> + * @dev: Device whose latency tolerance to expose
> + */
> +int dev_pm_qos_expose_latency_tolerance(struct device *dev)
> +{
> +	int ret;
> +
> +	if (!dev->power.set_latency_tolerance)
> +		return -EINVAL;
> +
> +	mutex_lock(&dev_pm_qos_sysfs_mtx);
> +	ret = pm_qos_sysfs_add_latency_tolerance(dev);
> +	mutex_unlock(&dev_pm_qos_sysfs_mtx);
> +
> +	return ret;
> +}
> +EXPORT_SYMBOL_GPL(dev_pm_qos_expose_latency_tolerance);
> +
> +/**
> + * dev_pm_qos_hide_latency_tolerance - Hide latency tolerance from userspace
> + * @dev: Device whose latency tolerance to hide
> + */
> +void dev_pm_qos_hide_latency_tolerance(struct device *dev)
> +{
> +	mutex_lock(&dev_pm_qos_sysfs_mtx);
> +	pm_qos_sysfs_remove_latency_tolerance(dev);
> +	mutex_unlock(&dev_pm_qos_sysfs_mtx);
> +
> +	/* Remove the request from user space now */
> +	pm_runtime_get_sync(dev);
> +	dev_pm_qos_update_user_latency_tolerance(dev,
> +		PM_QOS_LATENCY_TOLERANCE_NO_CONSTRAINT);
> +	pm_runtime_put(dev);
> +}
> +EXPORT_SYMBOL_GPL(dev_pm_qos_hide_latency_tolerance);
> diff --git a/drivers/base/power/sysfs.c b/drivers/base/power/sysfs.c
> index d2be3f9..a7b4679 100644
> --- a/drivers/base/power/sysfs.c
> +++ b/drivers/base/power/sysfs.c
> @@ -738,6 +738,17 @@ void pm_qos_sysfs_remove_flags(struct device *dev)
>  	sysfs_unmerge_group(&dev->kobj, &pm_qos_flags_attr_group);
>  }
>  
> +int pm_qos_sysfs_add_latency_tolerance(struct device *dev)
> +{
> +	return sysfs_merge_group(&dev->kobj,
> +				 &pm_qos_latency_tolerance_attr_group);
> +}
> +
> +void pm_qos_sysfs_remove_latency_tolerance(struct device *dev)
> +{
> +	sysfs_unmerge_group(&dev->kobj, &pm_qos_latency_tolerance_attr_group);
> +}
> +
>  void rpm_sysfs_remove(struct device *dev)
>  {
>  	sysfs_unmerge_group(&dev->kobj, &pm_runtime_attr_group);
> diff --git a/include/linux/pm_qos.h b/include/linux/pm_qos.h
> index 7b3ae0c..0f65d36 100644
> --- a/include/linux/pm_qos.h
> +++ b/include/linux/pm_qos.h
> @@ -161,6 +161,8 @@ void dev_pm_qos_hide_flags(struct device *dev);
>  int dev_pm_qos_update_flags(struct device *dev, s32 mask, bool set);
>  s32 dev_pm_qos_get_user_latency_tolerance(struct device *dev);
>  int dev_pm_qos_update_user_latency_tolerance(struct device *dev, s32 val);
> +int dev_pm_qos_expose_latency_tolerance(struct device *dev);
> +void dev_pm_qos_hide_latency_tolerance(struct device *dev);
>  
>  static inline s32 dev_pm_qos_requested_resume_latency(struct device *dev)
>  {
> @@ -229,6 +231,9 @@ static inline s32 dev_pm_qos_get_user_latency_tolerance(struct device *dev)
>  			{ return PM_QOS_LATENCY_TOLERANCE_NO_CONSTRAINT; }
>  static inline int dev_pm_qos_update_user_latency_tolerance(struct device *dev, s32 val)
>  			{ return 0; }
> +static inline int dev_pm_qos_expose_latency_tolerance(struct device *dev)
> +			{ return 0; }
> +static inline void dev_pm_qos_hide_latency_tolerance(struct device *dev) {}
>  
>  static inline s32 dev_pm_qos_requested_resume_latency(struct device *dev) { return 0; }
>  static inline s32 dev_pm_qos_requested_flags(struct device *dev) { return 0; }

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

Re: [PATCH v6 2/8] ACPI / PM: Attach ACPI power domain only once

[Lee Jones]

On Mon, 27 Jul 2015, Andy Shevchenko wrote:

> From: Mika Westerberg <mika.westerberg@linux.intel.com>
> 
> Some devices, like MFD subdevices, share a single ACPI companion device so
> that they are able to access their resources and children. However,
> currently all these subdevices are attached to the ACPI power domain and
> this might cause that the power methods for the companion device get called
> more than once.
> 
> In order to solve this we attach the ACPI power domain only to the first
> physical device that is bound to the ACPI companion device. In case of MFD
> devices, this is the parent MFD device itself.
> 
> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> ---
>  drivers/acpi/device_pm.c |  8 ++++++++
>  drivers/acpi/internal.h  |  2 ++
>  drivers/acpi/scan.c      | 46 ++++++++++++++++++++++++++++++----------------
>  3 files changed, 40 insertions(+), 16 deletions(-)

Applied, thanks.  Pull request to follow.

> diff --git a/drivers/acpi/device_pm.c b/drivers/acpi/device_pm.c
> index 717afcd..08dc3ec 100644
> --- a/drivers/acpi/device_pm.c
> +++ b/drivers/acpi/device_pm.c
> @@ -1123,6 +1123,14 @@ int acpi_dev_pm_attach(struct device *dev, bool power_on)
>  	if (dev->pm_domain)
>  		return -EEXIST;
>  
> +	/*
> +	 * Only attach the power domain to the first device if the
> +	 * companion is shared by multiple. This is to prevent doing power
> +	 * management twice.
> +	 */
> +	if (!acpi_device_is_first_physical_node(adev, dev))
> +		return -EBUSY;
> +
>  	acpi_add_pm_notifier(adev, dev, acpi_pm_notify_work_func);
>  	dev->pm_domain = &acpi_general_pm_domain;
>  	if (power_on) {
> diff --git a/drivers/acpi/internal.h b/drivers/acpi/internal.h
> index 4683a96..f6aefe9 100644
> --- a/drivers/acpi/internal.h
> +++ b/drivers/acpi/internal.h
> @@ -97,6 +97,8 @@ void acpi_device_add_finalize(struct acpi_device *device);
>  void acpi_free_pnp_ids(struct acpi_device_pnp *pnp);
>  bool acpi_device_is_present(struct acpi_device *adev);
>  bool acpi_device_is_battery(struct acpi_device *adev);
> +bool acpi_device_is_first_physical_node(struct acpi_device *adev,
> +					const struct device *dev);
>  
>  /* --------------------------------------------------------------------------
>                                    Power Resource
> diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c
> index ec25635..89ff6d2 100644
> --- a/drivers/acpi/scan.c
> +++ b/drivers/acpi/scan.c
> @@ -226,6 +226,35 @@ static int create_of_modalias(struct acpi_device *acpi_dev, char *modalias,
>  	return len;
>  }
>  
> +/**
> + * acpi_device_is_first_physical_node - Is given dev first physical node
> + * @adev: ACPI companion device
> + * @dev: Physical device to check
> + *
> + * Function checks if given @dev is the first physical devices attached to
> + * the ACPI companion device. This distinction is needed in some cases
> + * where the same companion device is shared between many physical devices.
> + *
> + * Note that the caller have to provide valid @adev pointer.
> + */
> +bool acpi_device_is_first_physical_node(struct acpi_device *adev,
> +					const struct device *dev)
> +{
> +	bool ret = false;
> +
> +	mutex_lock(&adev->physical_node_lock);
> +	if (!list_empty(&adev->physical_node_list)) {
> +		const struct acpi_device_physical_node *node;
> +
> +		node = list_first_entry(&adev->physical_node_list,
> +					struct acpi_device_physical_node, node);
> +		ret = node->dev == dev;
> +	}
> +	mutex_unlock(&adev->physical_node_lock);
> +
> +	return ret;
> +}
> +
>  /*
>   * acpi_companion_match() - Can we match via ACPI companion device
>   * @dev: Device in question
> @@ -250,7 +279,6 @@ static int create_of_modalias(struct acpi_device *acpi_dev, char *modalias,
>  static struct acpi_device *acpi_companion_match(const struct device *dev)
>  {
>  	struct acpi_device *adev;
> -	struct mutex *physical_node_lock;
>  
>  	adev = ACPI_COMPANION(dev);
>  	if (!adev)
> @@ -259,21 +287,7 @@ static struct acpi_device *acpi_companion_match(const struct device *dev)
>  	if (list_empty(&adev->pnp.ids))
>  		return NULL;
>  
> -	physical_node_lock = &adev->physical_node_lock;
> -	mutex_lock(physical_node_lock);
> -	if (list_empty(&adev->physical_node_list)) {
> -		adev = NULL;
> -	} else {
> -		const struct acpi_device_physical_node *node;
> -
> -		node = list_first_entry(&adev->physical_node_list,
> -					struct acpi_device_physical_node, node);
> -		if (node->dev != dev)
> -			adev = NULL;
> -	}
> -	mutex_unlock(physical_node_lock);
> -
> -	return adev;
> +	return acpi_device_is_first_physical_node(adev, dev) ? adev : NULL;
>  }
>  
>  static int __acpi_device_uevent_modalias(struct acpi_device *adev,

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
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Re: [PATCH v6 3/8] Driver core: wakeup the parent device before trying probe

[Lee Jones]

On Mon, 27 Jul 2015, Andy Shevchenko wrote:

> From: "Rafael J. Wysocki" <rafael.j.wysocki@intel.com>
> 
> If the parent is still suspended when driver probe is
> attempted, the result may be failure.
> 
> For example, if the parent is a PCI MFD device that has been
> suspended when we try to probe our device, any register
> reads will return 0xffffffff.
> 
> To fix the problem, making sure the parent is always awake
> before attempting driver probe.
> 
> Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> ---
>  drivers/base/dd.c | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)

Applied, thanks.  Pull request to follow.

> diff --git a/drivers/base/dd.c b/drivers/base/dd.c
> index a638bbb..2d6df1d 100644
> --- a/drivers/base/dd.c
> +++ b/drivers/base/dd.c
> @@ -399,6 +399,8 @@ EXPORT_SYMBOL_GPL(wait_for_device_probe);
>   *
>   * This function must be called with @dev lock held.  When called for a
>   * USB interface, @dev->parent lock must be held as well.
> + *
> + * If the device has a parent, runtime-resume the parent before driver probing.
>   */
>  int driver_probe_device(struct device_driver *drv, struct device *dev)
>  {
> @@ -410,10 +412,16 @@ int driver_probe_device(struct device_driver *drv, struct device *dev)
>  	pr_debug("bus: '%s': %s: matched device %s with driver %s\n",
>  		 drv->bus->name, __func__, dev_name(dev), drv->name);
>  
> +	if (dev->parent)
> +		pm_runtime_get_sync(dev->parent);
> +
>  	pm_runtime_barrier(dev);
>  	ret = really_probe(dev, drv);
>  	pm_request_idle(dev);
>  
> +	if (dev->parent)
> +		pm_runtime_put(dev->parent);
> +
>  	return ret;
>  }
>  
> @@ -507,11 +515,17 @@ static void __device_attach_async_helper(void *_dev, async_cookie_t cookie)
>  
>  	device_lock(dev);
>  
> +	if (dev->parent)
> +		pm_runtime_get_sync(dev->parent);
> +
>  	bus_for_each_drv(dev->bus, NULL, &data, __device_attach_driver);
>  	dev_dbg(dev, "async probe completed\n");
>  
>  	pm_request_idle(dev);
>  
> +	if (dev->parent)
> +		pm_runtime_put(dev->parent);
> +
>  	device_unlock(dev);
>  
>  	put_device(dev);
> @@ -541,6 +555,9 @@ static int __device_attach(struct device *dev, bool allow_async)
>  			.want_async = false,
>  		};
>  
> +		if (dev->parent)
> +			pm_runtime_get_sync(dev->parent);
> +
>  		ret = bus_for_each_drv(dev->bus, NULL, &data,
>  					__device_attach_driver);
>  		if (!ret && allow_async && data.have_async) {
> @@ -557,6 +574,9 @@ static int __device_attach(struct device *dev, bool allow_async)
>  		} else {
>  			pm_request_idle(dev);
>  		}
> +
> +		if (dev->parent)
> +			pm_runtime_put(dev->parent);
>  	}
>  out_unlock:
>  	device_unlock(dev);

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

Re: [PATCH v6 4/8] klist: implement klist_prev()

[Lee Jones]

On Mon, 27 Jul 2015, Andy Shevchenko wrote:

> klist_prev() gets the previous element in the list. It is useful to traverse
> through the list in reverse order, for example, to provide LIFO (last in first
> out) variant of access.
> 
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> ---
>  include/linux/klist.h |  1 +
>  lib/klist.c           | 41 +++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 42 insertions(+)

Applied, thanks.  Pull request to follow.

> diff --git a/include/linux/klist.h b/include/linux/klist.h
> index 61e5b72..953f283 100644
> --- a/include/linux/klist.h
> +++ b/include/linux/klist.h
> @@ -63,6 +63,7 @@ extern void klist_iter_init(struct klist *k, struct klist_iter *i);
>  extern void klist_iter_init_node(struct klist *k, struct klist_iter *i,
>  				 struct klist_node *n);
>  extern void klist_iter_exit(struct klist_iter *i);
> +extern struct klist_node *klist_prev(struct klist_iter *i);
>  extern struct klist_node *klist_next(struct klist_iter *i);
>  
>  #endif
> diff --git a/lib/klist.c b/lib/klist.c
> index 89b485a..d74cf7a 100644
> --- a/lib/klist.c
> +++ b/lib/klist.c
> @@ -324,6 +324,47 @@ static struct klist_node *to_klist_node(struct list_head *n)
>  }
>  
>  /**
> + * klist_prev - Ante up prev node in list.
> + * @i: Iterator structure.
> + *
> + * First grab list lock. Decrement the reference count of the previous
> + * node, if there was one. Grab the prev node, increment its reference
> + * count, drop the lock, and return that prev node.
> + */
> +struct klist_node *klist_prev(struct klist_iter *i)
> +{
> +	void (*put)(struct klist_node *) = i->i_klist->put;
> +	struct klist_node *last = i->i_cur;
> +	struct klist_node *prev;
> +
> +	spin_lock(&i->i_klist->k_lock);
> +
> +	if (last) {
> +		prev = to_klist_node(last->n_node.prev);
> +		if (!klist_dec_and_del(last))
> +			put = NULL;
> +	} else
> +		prev = to_klist_node(i->i_klist->k_list.prev);
> +
> +	i->i_cur = NULL;
> +	while (prev != to_klist_node(&i->i_klist->k_list)) {
> +		if (likely(!knode_dead(prev))) {
> +			kref_get(&prev->n_ref);
> +			i->i_cur = prev;
> +			break;
> +		}
> +		prev = to_klist_node(prev->n_node.prev);
> +	}
> +
> +	spin_unlock(&i->i_klist->k_lock);
> +
> +	if (put && last)
> +		put(last);
> +	return i->i_cur;
> +}
> +EXPORT_SYMBOL_GPL(klist_prev);
> +
> +/**
>   * klist_next - Ante up next node in list.
>   * @i: Iterator structure.
>   *

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

Re: [PATCH v6 5/8] driver core: implement device_for_each_child_reverse()

[Lee Jones]

On Mon, 27 Jul 2015, Andy Shevchenko wrote:

> The new function device_for_each_child_reverse() is helpful to traverse the
> registered devices in a reversed order, e.g. in the case when an operation on
> each device should be done first on the last added device, then on one before
> last and so on.
> 
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> ---
>  drivers/base/core.c    | 43 +++++++++++++++++++++++++++++++++++++++++++
>  include/linux/device.h |  2 ++
>  2 files changed, 45 insertions(+)

Applied, thanks.  Pull request to follow.

> diff --git a/drivers/base/core.c b/drivers/base/core.c
> index dafae6d..7d62795 100644
> --- a/drivers/base/core.c
> +++ b/drivers/base/core.c
> @@ -1252,6 +1252,19 @@ void device_unregister(struct device *dev)
>  }
>  EXPORT_SYMBOL_GPL(device_unregister);
>  
> +static struct device *prev_device(struct klist_iter *i)
> +{
> +	struct klist_node *n = klist_prev(i);
> +	struct device *dev = NULL;
> +	struct device_private *p;
> +
> +	if (n) {
> +		p = to_device_private_parent(n);
> +		dev = p->device;
> +	}
> +	return dev;
> +}
> +
>  static struct device *next_device(struct klist_iter *i)
>  {
>  	struct klist_node *n = klist_next(i);
> @@ -1341,6 +1354,36 @@ int device_for_each_child(struct device *parent, void *data,
>  EXPORT_SYMBOL_GPL(device_for_each_child);
>  
>  /**
> + * device_for_each_child_reverse - device child iterator in reversed order.
> + * @parent: parent struct device.
> + * @fn: function to be called for each device.
> + * @data: data for the callback.
> + *
> + * Iterate over @parent's child devices, and call @fn for each,
> + * passing it @data.
> + *
> + * We check the return of @fn each time. If it returns anything
> + * other than 0, we break out and return that value.
> + */
> +int device_for_each_child_reverse(struct device *parent, void *data,
> +				  int (*fn)(struct device *dev, void *data))
> +{
> +	struct klist_iter i;
> +	struct device *child;
> +	int error = 0;
> +
> +	if (!parent->p)
> +		return 0;
> +
> +	klist_iter_init(&parent->p->klist_children, &i);
> +	while ((child = prev_device(&i)) && !error)
> +		error = fn(child, data);
> +	klist_iter_exit(&i);
> +	return error;
> +}
> +EXPORT_SYMBOL_GPL(device_for_each_child_reverse);
> +
> +/**
>   * device_find_child - device iterator for locating a particular device.
>   * @parent: parent struct device
>   * @match: Callback function to check device
> diff --git a/include/linux/device.h b/include/linux/device.h
> index a2b4ea7..9d212fe 100644
> --- a/include/linux/device.h
> +++ b/include/linux/device.h
> @@ -959,6 +959,8 @@ extern int __must_check device_add(struct device *dev);
>  extern void device_del(struct device *dev);
>  extern int device_for_each_child(struct device *dev, void *data,
>  		     int (*fn)(struct device *dev, void *data));
> +extern int device_for_each_child_reverse(struct device *dev, void *data,
> +		     int (*fn)(struct device *dev, void *data));
>  extern struct device *device_find_child(struct device *dev, void *data,
>  				int (*match)(struct device *dev, void *data));
>  extern int device_rename(struct device *dev, const char *new_name);

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

Re: [PATCH v6 6/8] mfd: make mfd_remove_devices() iterate in reverse order

[Lee Jones]

On Mon, 27 Jul 2015, Andy Shevchenko wrote:

> The newly introduced device_for_each_child_reverse() would be used when MFD
> core removes the device.
> 
> After this patch applied the devices will be removed in a reversed order. This
> behaviour is useful when devices have implicit dependency on order, i.e.
> consider MFD device with serial bus controller, such as SPI, and DMA IP that is
> attached to serial bus controller: before remove the DMA driver we have to be
> ensured that no DMA transfers is ongoing and the requested channel are unused.
> 
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> ---
>  drivers/mfd/mfd-core.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Applied, thanks.  Pull request to follow.

> diff --git a/drivers/mfd/mfd-core.c b/drivers/mfd/mfd-core.c
> index 14fd5cb..c17635d 100644
> --- a/drivers/mfd/mfd-core.c
> +++ b/drivers/mfd/mfd-core.c
> @@ -302,7 +302,7 @@ void mfd_remove_devices(struct device *parent)
>  {
>  	atomic_t *cnts = NULL;
>  
> -	device_for_each_child(parent, &cnts, mfd_remove_devices_fn);
> +	device_for_each_child_reverse(parent, &cnts, mfd_remove_devices_fn);
>  	kfree(cnts);
>  }
>  EXPORT_SYMBOL(mfd_remove_devices);

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
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Re: [PATCH v6 7/8] dmaengine: add a driver for Intel integrated DMA 64-bit

[Lee Jones]

On Mon, 27 Jul 2015, Andy Shevchenko wrote:

> Intel integrated DMA (iDMA) 64-bit is a specific IP that is used as a part of
> LPSS devices such as HSUART or SPI. The iDMA IP is attached for private
> usage on each host controller independently.
> 
> While it has similarities with Synopsys DesignWare DMA, the following
> distinctions doesn't allow to use the existing driver:
> - 64-bit mode with corresponding changes in Hardware Linked List data structure
> - many slight differences in the channel registers
> 
> Moreover this driver is based on the DMA virtual channels framework that helps
> to make the driver cleaner and easy to understand.
> 
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> ---
>  drivers/dma/Kconfig  |   8 +
>  drivers/dma/Makefile |   1 +
>  drivers/dma/idma64.c | 710 +++++++++++++++++++++++++++++++++++++++++++++++++++
>  drivers/dma/idma64.h | 233 +++++++++++++++++
>  4 files changed, 952 insertions(+)
>  create mode 100644 drivers/dma/idma64.c
>  create mode 100644 drivers/dma/idma64.h

Applied, thanks.  Pull request to follow.

> diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
> index 88d474b..bdbbe5b 100644
> --- a/drivers/dma/Kconfig
> +++ b/drivers/dma/Kconfig
> @@ -85,6 +85,14 @@ config INTEL_IOP_ADMA
>  	help
>  	  Enable support for the Intel(R) IOP Series RAID engines.
>  
> +config IDMA64
> +	tristate "Intel integrated DMA 64-bit support"
> +	select DMA_ENGINE
> +	select DMA_VIRTUAL_CHANNELS
> +	help
> +	  Enable DMA support for Intel Low Power Subsystem such as found on
> +	  Intel Skylake PCH.
> +
>  source "drivers/dma/dw/Kconfig"
>  
>  config AT_HDMAC
> diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
> index 6a4d6f2..56ff8c7 100644
> --- a/drivers/dma/Makefile
> +++ b/drivers/dma/Makefile
> @@ -14,6 +14,7 @@ obj-$(CONFIG_HSU_DMA) += hsu/
>  obj-$(CONFIG_MPC512X_DMA) += mpc512x_dma.o
>  obj-$(CONFIG_PPC_BESTCOMM) += bestcomm/
>  obj-$(CONFIG_MV_XOR) += mv_xor.o
> +obj-$(CONFIG_IDMA64) += idma64.o
>  obj-$(CONFIG_DW_DMAC_CORE) += dw/
>  obj-$(CONFIG_AT_HDMAC) += at_hdmac.o
>  obj-$(CONFIG_AT_XDMAC) += at_xdmac.o
> diff --git a/drivers/dma/idma64.c b/drivers/dma/idma64.c
> new file mode 100644
> index 0000000..18c14e1
> --- /dev/null
> +++ b/drivers/dma/idma64.c
> @@ -0,0 +1,710 @@
> +/*
> + * Core driver for the Intel integrated DMA 64-bit
> + *
> + * Copyright (C) 2015 Intel Corporation
> + * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/bitops.h>
> +#include <linux/delay.h>
> +#include <linux/dmaengine.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/dmapool.h>
> +#include <linux/init.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +
> +#include "idma64.h"
> +
> +/* Platform driver name */
> +#define DRV_NAME		"idma64"
> +
> +/* For now we support only two channels */
> +#define IDMA64_NR_CHAN		2
> +
> +/* ---------------------------------------------------------------------- */
> +
> +static struct device *chan2dev(struct dma_chan *chan)
> +{
> +	return &chan->dev->device;
> +}
> +
> +/* ---------------------------------------------------------------------- */
> +
> +static void idma64_off(struct idma64 *idma64)
> +{
> +	unsigned short count = 100;
> +
> +	dma_writel(idma64, CFG, 0);
> +
> +	channel_clear_bit(idma64, MASK(XFER), idma64->all_chan_mask);
> +	channel_clear_bit(idma64, MASK(BLOCK), idma64->all_chan_mask);
> +	channel_clear_bit(idma64, MASK(SRC_TRAN), idma64->all_chan_mask);
> +	channel_clear_bit(idma64, MASK(DST_TRAN), idma64->all_chan_mask);
> +	channel_clear_bit(idma64, MASK(ERROR), idma64->all_chan_mask);
> +
> +	do {
> +		cpu_relax();
> +	} while (dma_readl(idma64, CFG) & IDMA64_CFG_DMA_EN && --count);
> +}
> +
> +static void idma64_on(struct idma64 *idma64)
> +{
> +	dma_writel(idma64, CFG, IDMA64_CFG_DMA_EN);
> +}
> +
> +/* ---------------------------------------------------------------------- */
> +
> +static void idma64_chan_init(struct idma64 *idma64, struct idma64_chan *idma64c)
> +{
> +	u32 cfghi = IDMA64C_CFGH_SRC_PER(1) | IDMA64C_CFGH_DST_PER(0);
> +	u32 cfglo = 0;
> +
> +	/* Enforce FIFO drain when channel is suspended */
> +	cfglo |= IDMA64C_CFGL_CH_DRAIN;
> +
> +	/* Set default burst alignment */
> +	cfglo |= IDMA64C_CFGL_DST_BURST_ALIGN | IDMA64C_CFGL_SRC_BURST_ALIGN;
> +
> +	channel_writel(idma64c, CFG_LO, cfglo);
> +	channel_writel(idma64c, CFG_HI, cfghi);
> +
> +	/* Enable interrupts */
> +	channel_set_bit(idma64, MASK(XFER), idma64c->mask);
> +	channel_set_bit(idma64, MASK(ERROR), idma64c->mask);
> +
> +	/*
> +	 * Enforce the controller to be turned on.
> +	 *
> +	 * The iDMA is turned off in ->probe() and looses context during system
> +	 * suspend / resume cycle. That's why we have to enable it each time we
> +	 * use it.
> +	 */
> +	idma64_on(idma64);
> +}
> +
> +static void idma64_chan_stop(struct idma64 *idma64, struct idma64_chan *idma64c)
> +{
> +	channel_clear_bit(idma64, CH_EN, idma64c->mask);
> +}
> +
> +static void idma64_chan_start(struct idma64 *idma64, struct idma64_chan *idma64c)
> +{
> +	struct idma64_desc *desc = idma64c->desc;
> +	struct idma64_hw_desc *hw = &desc->hw[0];
> +
> +	channel_writeq(idma64c, SAR, 0);
> +	channel_writeq(idma64c, DAR, 0);
> +
> +	channel_writel(idma64c, CTL_HI, IDMA64C_CTLH_BLOCK_TS(~0UL));
> +	channel_writel(idma64c, CTL_LO, IDMA64C_CTLL_LLP_S_EN | IDMA64C_CTLL_LLP_D_EN);
> +
> +	channel_writeq(idma64c, LLP, hw->llp);
> +
> +	channel_set_bit(idma64, CH_EN, idma64c->mask);
> +}
> +
> +static void idma64_stop_transfer(struct idma64_chan *idma64c)
> +{
> +	struct idma64 *idma64 = to_idma64(idma64c->vchan.chan.device);
> +
> +	idma64_chan_stop(idma64, idma64c);
> +}
> +
> +static void idma64_start_transfer(struct idma64_chan *idma64c)
> +{
> +	struct idma64 *idma64 = to_idma64(idma64c->vchan.chan.device);
> +	struct virt_dma_desc *vdesc;
> +
> +	/* Get the next descriptor */
> +	vdesc = vchan_next_desc(&idma64c->vchan);
> +	if (!vdesc) {
> +		idma64c->desc = NULL;
> +		return;
> +	}
> +
> +	list_del(&vdesc->node);
> +	idma64c->desc = to_idma64_desc(vdesc);
> +
> +	/* Configure the channel */
> +	idma64_chan_init(idma64, idma64c);
> +
> +	/* Start the channel with a new descriptor */
> +	idma64_chan_start(idma64, idma64c);
> +}
> +
> +/* ---------------------------------------------------------------------- */
> +
> +static void idma64_chan_irq(struct idma64 *idma64, unsigned short c,
> +		u32 status_err, u32 status_xfer)
> +{
> +	struct idma64_chan *idma64c = &idma64->chan[c];
> +	struct idma64_desc *desc;
> +	unsigned long flags;
> +
> +	spin_lock_irqsave(&idma64c->vchan.lock, flags);
> +	desc = idma64c->desc;
> +	if (desc) {
> +		if (status_err & (1 << c)) {
> +			dma_writel(idma64, CLEAR(ERROR), idma64c->mask);
> +			desc->status = DMA_ERROR;
> +		} else if (status_xfer & (1 << c)) {
> +			dma_writel(idma64, CLEAR(XFER), idma64c->mask);
> +			desc->status = DMA_COMPLETE;
> +			vchan_cookie_complete(&desc->vdesc);
> +			idma64_start_transfer(idma64c);
> +		}
> +
> +		/* idma64_start_transfer() updates idma64c->desc */
> +		if (idma64c->desc == NULL || desc->status == DMA_ERROR)
> +			idma64_stop_transfer(idma64c);
> +	}
> +	spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
> +}
> +
> +static irqreturn_t idma64_irq(int irq, void *dev)
> +{
> +	struct idma64 *idma64 = dev;
> +	u32 status = dma_readl(idma64, STATUS_INT);
> +	u32 status_xfer;
> +	u32 status_err;
> +	unsigned short i;
> +
> +	dev_vdbg(idma64->dma.dev, "%s: status=%#x\n", __func__, status);
> +
> +	/* Check if we have any interrupt from the DMA controller */
> +	if (!status)
> +		return IRQ_NONE;
> +
> +	/* Disable interrupts */
> +	channel_clear_bit(idma64, MASK(XFER), idma64->all_chan_mask);
> +	channel_clear_bit(idma64, MASK(ERROR), idma64->all_chan_mask);
> +
> +	status_xfer = dma_readl(idma64, RAW(XFER));
> +	status_err = dma_readl(idma64, RAW(ERROR));
> +
> +	for (i = 0; i < idma64->dma.chancnt; i++)
> +		idma64_chan_irq(idma64, i, status_err, status_xfer);
> +
> +	/* Re-enable interrupts */
> +	channel_set_bit(idma64, MASK(XFER), idma64->all_chan_mask);
> +	channel_set_bit(idma64, MASK(ERROR), idma64->all_chan_mask);
> +
> +	return IRQ_HANDLED;
> +}
> +
> +/* ---------------------------------------------------------------------- */
> +
> +static struct idma64_desc *idma64_alloc_desc(unsigned int ndesc)
> +{
> +	struct idma64_desc *desc;
> +
> +	desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
> +	if (!desc)
> +		return NULL;
> +
> +	desc->hw = kcalloc(ndesc, sizeof(*desc->hw), GFP_NOWAIT);
> +	if (!desc->hw) {
> +		kfree(desc);
> +		return NULL;
> +	}
> +
> +	return desc;
> +}
> +
> +static void idma64_desc_free(struct idma64_chan *idma64c,
> +		struct idma64_desc *desc)
> +{
> +	struct idma64_hw_desc *hw;
> +
> +	if (desc->ndesc) {
> +		unsigned int i = desc->ndesc;
> +
> +		do {
> +			hw = &desc->hw[--i];
> +			dma_pool_free(idma64c->pool, hw->lli, hw->llp);
> +		} while (i);
> +	}
> +
> +	kfree(desc->hw);
> +	kfree(desc);
> +}
> +
> +static void idma64_vdesc_free(struct virt_dma_desc *vdesc)
> +{
> +	struct idma64_chan *idma64c = to_idma64_chan(vdesc->tx.chan);
> +
> +	idma64_desc_free(idma64c, to_idma64_desc(vdesc));
> +}
> +
> +static u64 idma64_hw_desc_fill(struct idma64_hw_desc *hw,
> +		struct dma_slave_config *config,
> +		enum dma_transfer_direction direction, u64 llp)
> +{
> +	struct idma64_lli *lli = hw->lli;
> +	u64 sar, dar;
> +	u32 ctlhi = IDMA64C_CTLH_BLOCK_TS(hw->len);
> +	u32 ctllo = IDMA64C_CTLL_LLP_S_EN | IDMA64C_CTLL_LLP_D_EN;
> +	u32 src_width, dst_width;
> +
> +	if (direction == DMA_MEM_TO_DEV) {
> +		sar = hw->phys;
> +		dar = config->dst_addr;
> +		ctllo |= IDMA64C_CTLL_DST_FIX | IDMA64C_CTLL_SRC_INC |
> +			 IDMA64C_CTLL_FC_M2P;
> +		src_width = min_t(u32, 2, __fls(sar | hw->len));
> +		dst_width = __fls(config->dst_addr_width);
> +	} else {	/* DMA_DEV_TO_MEM */
> +		sar = config->src_addr;
> +		dar = hw->phys;
> +		ctllo |= IDMA64C_CTLL_DST_INC | IDMA64C_CTLL_SRC_FIX |
> +			 IDMA64C_CTLL_FC_P2M;
> +		src_width = __fls(config->src_addr_width);
> +		dst_width = min_t(u32, 2, __fls(dar | hw->len));
> +	}
> +
> +	lli->sar = sar;
> +	lli->dar = dar;
> +
> +	lli->ctlhi = ctlhi;
> +	lli->ctllo = ctllo |
> +		     IDMA64C_CTLL_SRC_MSIZE(config->src_maxburst) |
> +		     IDMA64C_CTLL_DST_MSIZE(config->dst_maxburst) |
> +		     IDMA64C_CTLL_DST_WIDTH(dst_width) |
> +		     IDMA64C_CTLL_SRC_WIDTH(src_width);
> +
> +	lli->llp = llp;
> +	return hw->llp;
> +}
> +
> +static void idma64_desc_fill(struct idma64_chan *idma64c,
> +		struct idma64_desc *desc)
> +{
> +	struct dma_slave_config *config = &idma64c->config;
> +	struct idma64_hw_desc *hw = &desc->hw[desc->ndesc - 1];
> +	struct idma64_lli *lli = hw->lli;
> +	u64 llp = 0;
> +	unsigned int i = desc->ndesc;
> +
> +	/* Fill the hardware descriptors and link them to a list */
> +	do {
> +		hw = &desc->hw[--i];
> +		llp = idma64_hw_desc_fill(hw, config, desc->direction, llp);
> +		desc->length += hw->len;
> +	} while (i);
> +
> +	/* Trigger interrupt after last block */
> +	lli->ctllo |= IDMA64C_CTLL_INT_EN;
> +}
> +
> +static struct dma_async_tx_descriptor *idma64_prep_slave_sg(
> +		struct dma_chan *chan, struct scatterlist *sgl,
> +		unsigned int sg_len, enum dma_transfer_direction direction,
> +		unsigned long flags, void *context)
> +{
> +	struct idma64_chan *idma64c = to_idma64_chan(chan);
> +	struct idma64_desc *desc;
> +	struct scatterlist *sg;
> +	unsigned int i;
> +
> +	desc = idma64_alloc_desc(sg_len);
> +	if (!desc)
> +		return NULL;
> +
> +	for_each_sg(sgl, sg, sg_len, i) {
> +		struct idma64_hw_desc *hw = &desc->hw[i];
> +
> +		/* Allocate DMA capable memory for hardware descriptor */
> +		hw->lli = dma_pool_alloc(idma64c->pool, GFP_NOWAIT, &hw->llp);
> +		if (!hw->lli) {
> +			desc->ndesc = i;
> +			idma64_desc_free(idma64c, desc);
> +			return NULL;
> +		}
> +
> +		hw->phys = sg_dma_address(sg);
> +		hw->len = sg_dma_len(sg);
> +	}
> +
> +	desc->ndesc = sg_len;
> +	desc->direction = direction;
> +	desc->status = DMA_IN_PROGRESS;
> +
> +	idma64_desc_fill(idma64c, desc);
> +	return vchan_tx_prep(&idma64c->vchan, &desc->vdesc, flags);
> +}
> +
> +static void idma64_issue_pending(struct dma_chan *chan)
> +{
> +	struct idma64_chan *idma64c = to_idma64_chan(chan);
> +	unsigned long flags;
> +
> +	spin_lock_irqsave(&idma64c->vchan.lock, flags);
> +	if (vchan_issue_pending(&idma64c->vchan) && !idma64c->desc)
> +		idma64_start_transfer(idma64c);
> +	spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
> +}
> +
> +static size_t idma64_active_desc_size(struct idma64_chan *idma64c)
> +{
> +	struct idma64_desc *desc = idma64c->desc;
> +	struct idma64_hw_desc *hw;
> +	size_t bytes = desc->length;
> +	u64 llp;
> +	u32 ctlhi;
> +	unsigned int i = 0;
> +
> +	llp = channel_readq(idma64c, LLP);
> +	do {
> +		hw = &desc->hw[i];
> +	} while ((hw->llp != llp) && (++i < desc->ndesc));
> +
> +	if (!i)
> +		return bytes;
> +
> +	do {
> +		bytes -= desc->hw[--i].len;
> +	} while (i);
> +
> +	ctlhi = channel_readl(idma64c, CTL_HI);
> +	return bytes - IDMA64C_CTLH_BLOCK_TS(ctlhi);
> +}
> +
> +static enum dma_status idma64_tx_status(struct dma_chan *chan,
> +		dma_cookie_t cookie, struct dma_tx_state *state)
> +{
> +	struct idma64_chan *idma64c = to_idma64_chan(chan);
> +	struct virt_dma_desc *vdesc;
> +	enum dma_status status;
> +	size_t bytes;
> +	unsigned long flags;
> +
> +	status = dma_cookie_status(chan, cookie, state);
> +	if (status == DMA_COMPLETE)
> +		return status;
> +
> +	spin_lock_irqsave(&idma64c->vchan.lock, flags);
> +	vdesc = vchan_find_desc(&idma64c->vchan, cookie);
> +	if (idma64c->desc && cookie == idma64c->desc->vdesc.tx.cookie) {
> +		bytes = idma64_active_desc_size(idma64c);
> +		dma_set_residue(state, bytes);
> +		status = idma64c->desc->status;
> +	} else if (vdesc) {
> +		bytes = to_idma64_desc(vdesc)->length;
> +		dma_set_residue(state, bytes);
> +	}
> +	spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
> +
> +	return status;
> +}
> +
> +static void convert_burst(u32 *maxburst)
> +{
> +	if (*maxburst)
> +		*maxburst = __fls(*maxburst);
> +	else
> +		*maxburst = 0;
> +}
> +
> +static int idma64_slave_config(struct dma_chan *chan,
> +		struct dma_slave_config *config)
> +{
> +	struct idma64_chan *idma64c = to_idma64_chan(chan);
> +
> +	/* Check if chan will be configured for slave transfers */
> +	if (!is_slave_direction(config->direction))
> +		return -EINVAL;
> +
> +	memcpy(&idma64c->config, config, sizeof(idma64c->config));
> +
> +	convert_burst(&idma64c->config.src_maxburst);
> +	convert_burst(&idma64c->config.dst_maxburst);
> +
> +	return 0;
> +}
> +
> +static void idma64_chan_deactivate(struct idma64_chan *idma64c)
> +{
> +	unsigned short count = 100;
> +	u32 cfglo;
> +
> +	cfglo = channel_readl(idma64c, CFG_LO);
> +	channel_writel(idma64c, CFG_LO, cfglo | IDMA64C_CFGL_CH_SUSP);
> +	do {
> +		udelay(1);
> +		cfglo = channel_readl(idma64c, CFG_LO);
> +	} while (!(cfglo & IDMA64C_CFGL_FIFO_EMPTY) && --count);
> +}
> +
> +static void idma64_chan_activate(struct idma64_chan *idma64c)
> +{
> +	u32 cfglo;
> +
> +	cfglo = channel_readl(idma64c, CFG_LO);
> +	channel_writel(idma64c, CFG_LO, cfglo & ~IDMA64C_CFGL_CH_SUSP);
> +}
> +
> +static int idma64_pause(struct dma_chan *chan)
> +{
> +	struct idma64_chan *idma64c = to_idma64_chan(chan);
> +	unsigned long flags;
> +
> +	spin_lock_irqsave(&idma64c->vchan.lock, flags);
> +	if (idma64c->desc && idma64c->desc->status == DMA_IN_PROGRESS) {
> +		idma64_chan_deactivate(idma64c);
> +		idma64c->desc->status = DMA_PAUSED;
> +	}
> +	spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
> +
> +	return 0;
> +}
> +
> +static int idma64_resume(struct dma_chan *chan)
> +{
> +	struct idma64_chan *idma64c = to_idma64_chan(chan);
> +	unsigned long flags;
> +
> +	spin_lock_irqsave(&idma64c->vchan.lock, flags);
> +	if (idma64c->desc && idma64c->desc->status == DMA_PAUSED) {
> +		idma64c->desc->status = DMA_IN_PROGRESS;
> +		idma64_chan_activate(idma64c);
> +	}
> +	spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
> +
> +	return 0;
> +}
> +
> +static int idma64_terminate_all(struct dma_chan *chan)
> +{
> +	struct idma64_chan *idma64c = to_idma64_chan(chan);
> +	unsigned long flags;
> +	LIST_HEAD(head);
> +
> +	spin_lock_irqsave(&idma64c->vchan.lock, flags);
> +	idma64_chan_deactivate(idma64c);
> +	idma64_stop_transfer(idma64c);
> +	if (idma64c->desc) {
> +		idma64_vdesc_free(&idma64c->desc->vdesc);
> +		idma64c->desc = NULL;
> +	}
> +	vchan_get_all_descriptors(&idma64c->vchan, &head);
> +	spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
> +
> +	vchan_dma_desc_free_list(&idma64c->vchan, &head);
> +	return 0;
> +}
> +
> +static int idma64_alloc_chan_resources(struct dma_chan *chan)
> +{
> +	struct idma64_chan *idma64c = to_idma64_chan(chan);
> +
> +	/* Create a pool of consistent memory blocks for hardware descriptors */
> +	idma64c->pool = dma_pool_create(dev_name(chan2dev(chan)),
> +					chan->device->dev,
> +					sizeof(struct idma64_lli), 8, 0);
> +	if (!idma64c->pool) {
> +		dev_err(chan2dev(chan), "No memory for descriptors\n");
> +		return -ENOMEM;
> +	}
> +
> +	return 0;
> +}
> +
> +static void idma64_free_chan_resources(struct dma_chan *chan)
> +{
> +	struct idma64_chan *idma64c = to_idma64_chan(chan);
> +
> +	vchan_free_chan_resources(to_virt_chan(chan));
> +	dma_pool_destroy(idma64c->pool);
> +	idma64c->pool = NULL;
> +}
> +
> +/* ---------------------------------------------------------------------- */
> +
> +#define IDMA64_BUSWIDTHS				\
> +	BIT(DMA_SLAVE_BUSWIDTH_1_BYTE)		|	\
> +	BIT(DMA_SLAVE_BUSWIDTH_2_BYTES)		|	\
> +	BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)
> +
> +static int idma64_probe(struct idma64_chip *chip)
> +{
> +	struct idma64 *idma64;
> +	unsigned short nr_chan = IDMA64_NR_CHAN;
> +	unsigned short i;
> +	int ret;
> +
> +	idma64 = devm_kzalloc(chip->dev, sizeof(*idma64), GFP_KERNEL);
> +	if (!idma64)
> +		return -ENOMEM;
> +
> +	idma64->regs = chip->regs;
> +	chip->idma64 = idma64;
> +
> +	idma64->chan = devm_kcalloc(chip->dev, nr_chan, sizeof(*idma64->chan),
> +				    GFP_KERNEL);
> +	if (!idma64->chan)
> +		return -ENOMEM;
> +
> +	idma64->all_chan_mask = (1 << nr_chan) - 1;
> +
> +	/* Turn off iDMA controller */
> +	idma64_off(idma64);
> +
> +	ret = devm_request_irq(chip->dev, chip->irq, idma64_irq, IRQF_SHARED,
> +			       dev_name(chip->dev), idma64);
> +	if (ret)
> +		return ret;
> +
> +	INIT_LIST_HEAD(&idma64->dma.channels);
> +	for (i = 0; i < nr_chan; i++) {
> +		struct idma64_chan *idma64c = &idma64->chan[i];
> +
> +		idma64c->vchan.desc_free = idma64_vdesc_free;
> +		vchan_init(&idma64c->vchan, &idma64->dma);
> +
> +		idma64c->regs = idma64->regs + i * IDMA64_CH_LENGTH;
> +		idma64c->mask = BIT(i);
> +	}
> +
> +	dma_cap_set(DMA_SLAVE, idma64->dma.cap_mask);
> +	dma_cap_set(DMA_PRIVATE, idma64->dma.cap_mask);
> +
> +	idma64->dma.device_alloc_chan_resources = idma64_alloc_chan_resources;
> +	idma64->dma.device_free_chan_resources = idma64_free_chan_resources;
> +
> +	idma64->dma.device_prep_slave_sg = idma64_prep_slave_sg;
> +
> +	idma64->dma.device_issue_pending = idma64_issue_pending;
> +	idma64->dma.device_tx_status = idma64_tx_status;
> +
> +	idma64->dma.device_config = idma64_slave_config;
> +	idma64->dma.device_pause = idma64_pause;
> +	idma64->dma.device_resume = idma64_resume;
> +	idma64->dma.device_terminate_all = idma64_terminate_all;
> +
> +	idma64->dma.src_addr_widths = IDMA64_BUSWIDTHS;
> +	idma64->dma.dst_addr_widths = IDMA64_BUSWIDTHS;
> +	idma64->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
> +	idma64->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
> +
> +	idma64->dma.dev = chip->dev;
> +
> +	ret = dma_async_device_register(&idma64->dma);
> +	if (ret)
> +		return ret;
> +
> +	dev_info(chip->dev, "Found Intel integrated DMA 64-bit\n");
> +	return 0;
> +}
> +
> +static int idma64_remove(struct idma64_chip *chip)
> +{
> +	struct idma64 *idma64 = chip->idma64;
> +	unsigned short i;
> +
> +	dma_async_device_unregister(&idma64->dma);
> +
> +	/*
> +	 * Explicitly call devm_request_irq() to avoid the side effects with
> +	 * the scheduled tasklets.
> +	 */
> +	devm_free_irq(chip->dev, chip->irq, idma64);
> +
> +	for (i = 0; i < idma64->dma.chancnt; i++) {
> +		struct idma64_chan *idma64c = &idma64->chan[i];
> +
> +		tasklet_kill(&idma64c->vchan.task);
> +	}
> +
> +	return 0;
> +}
> +
> +/* ---------------------------------------------------------------------- */
> +
> +static int idma64_platform_probe(struct platform_device *pdev)
> +{
> +	struct idma64_chip *chip;
> +	struct device *dev = &pdev->dev;
> +	struct resource *mem;
> +	int ret;
> +
> +	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
> +	if (!chip)
> +		return -ENOMEM;
> +
> +	chip->irq = platform_get_irq(pdev, 0);
> +	if (chip->irq < 0)
> +		return chip->irq;
> +
> +	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	chip->regs = devm_ioremap_resource(dev, mem);
> +	if (IS_ERR(chip->regs))
> +		return PTR_ERR(chip->regs);
> +
> +	ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
> +	if (ret)
> +		return ret;
> +
> +	chip->dev = dev;
> +
> +	ret = idma64_probe(chip);
> +	if (ret)
> +		return ret;
> +
> +	platform_set_drvdata(pdev, chip);
> +	return 0;
> +}
> +
> +static int idma64_platform_remove(struct platform_device *pdev)
> +{
> +	struct idma64_chip *chip = platform_get_drvdata(pdev);
> +
> +	return idma64_remove(chip);
> +}
> +
> +#ifdef CONFIG_PM_SLEEP
> +
> +static int idma64_pm_suspend(struct device *dev)
> +{
> +	struct platform_device *pdev = to_platform_device(dev);
> +	struct idma64_chip *chip = platform_get_drvdata(pdev);
> +
> +	idma64_off(chip->idma64);
> +	return 0;
> +}
> +
> +static int idma64_pm_resume(struct device *dev)
> +{
> +	struct platform_device *pdev = to_platform_device(dev);
> +	struct idma64_chip *chip = platform_get_drvdata(pdev);
> +
> +	idma64_on(chip->idma64);
> +	return 0;
> +}
> +
> +#endif /* CONFIG_PM_SLEEP */
> +
> +static const struct dev_pm_ops idma64_dev_pm_ops = {
> +	SET_SYSTEM_SLEEP_PM_OPS(idma64_pm_suspend, idma64_pm_resume)
> +};
> +
> +static struct platform_driver idma64_platform_driver = {
> +	.probe		= idma64_platform_probe,
> +	.remove		= idma64_platform_remove,
> +	.driver = {
> +		.name	= DRV_NAME,
> +		.pm	= &idma64_dev_pm_ops,
> +	},
> +};
> +
> +module_platform_driver(idma64_platform_driver);
> +
> +MODULE_LICENSE("GPL v2");
> +MODULE_DESCRIPTION("iDMA64 core driver");
> +MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
> +MODULE_ALIAS("platform:" DRV_NAME);
> diff --git a/drivers/dma/idma64.h b/drivers/dma/idma64.h
> new file mode 100644
> index 0000000..a4d9968
> --- /dev/null
> +++ b/drivers/dma/idma64.h
> @@ -0,0 +1,233 @@
> +/*
> + * Driver for the Intel integrated DMA 64-bit
> + *
> + * Copyright (C) 2015 Intel Corporation
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#ifndef __DMA_IDMA64_H__
> +#define __DMA_IDMA64_H__
> +
> +#include <linux/device.h>
> +#include <linux/io.h>
> +#include <linux/spinlock.h>
> +#include <linux/types.h>
> +
> +#include "virt-dma.h"
> +
> +/* Channel registers */
> +
> +#define IDMA64_CH_SAR		0x00	/* Source Address Register */
> +#define IDMA64_CH_DAR		0x08	/* Destination Address Register */
> +#define IDMA64_CH_LLP		0x10	/* Linked List Pointer */
> +#define IDMA64_CH_CTL_LO	0x18	/* Control Register Low */
> +#define IDMA64_CH_CTL_HI	0x1c	/* Control Register High */
> +#define IDMA64_CH_SSTAT		0x20
> +#define IDMA64_CH_DSTAT		0x28
> +#define IDMA64_CH_SSTATAR	0x30
> +#define IDMA64_CH_DSTATAR	0x38
> +#define IDMA64_CH_CFG_LO	0x40	/* Configuration Register Low */
> +#define IDMA64_CH_CFG_HI	0x44	/* Configuration Register High */
> +#define IDMA64_CH_SGR		0x48
> +#define IDMA64_CH_DSR		0x50
> +
> +#define IDMA64_CH_LENGTH	0x58
> +
> +/* Bitfields in CTL_LO */
> +#define IDMA64C_CTLL_INT_EN		(1 << 0)	/* irqs enabled? */
> +#define IDMA64C_CTLL_DST_WIDTH(x)	((x) << 1)	/* bytes per element */
> +#define IDMA64C_CTLL_SRC_WIDTH(x)	((x) << 4)
> +#define IDMA64C_CTLL_DST_INC		(0 << 8)	/* DAR update/not */
> +#define IDMA64C_CTLL_DST_FIX		(1 << 8)
> +#define IDMA64C_CTLL_SRC_INC		(0 << 10)	/* SAR update/not */
> +#define IDMA64C_CTLL_SRC_FIX		(1 << 10)
> +#define IDMA64C_CTLL_DST_MSIZE(x)	((x) << 11)	/* burst, #elements */
> +#define IDMA64C_CTLL_SRC_MSIZE(x)	((x) << 14)
> +#define IDMA64C_CTLL_FC_M2P		(1 << 20)	/* mem-to-periph */
> +#define IDMA64C_CTLL_FC_P2M		(2 << 20)	/* periph-to-mem */
> +#define IDMA64C_CTLL_LLP_D_EN		(1 << 27)	/* dest block chain */
> +#define IDMA64C_CTLL_LLP_S_EN		(1 << 28)	/* src block chain */
> +
> +/* Bitfields in CTL_HI */
> +#define IDMA64C_CTLH_BLOCK_TS(x)	((x) & ((1 << 17) - 1))
> +#define IDMA64C_CTLH_DONE		(1 << 17)
> +
> +/* Bitfields in CFG_LO */
> +#define IDMA64C_CFGL_DST_BURST_ALIGN	(1 << 0)	/* dst burst align */
> +#define IDMA64C_CFGL_SRC_BURST_ALIGN	(1 << 1)	/* src burst align */
> +#define IDMA64C_CFGL_CH_SUSP		(1 << 8)
> +#define IDMA64C_CFGL_FIFO_EMPTY		(1 << 9)
> +#define IDMA64C_CFGL_CH_DRAIN		(1 << 10)	/* drain FIFO */
> +#define IDMA64C_CFGL_DST_OPT_BL		(1 << 20)	/* optimize dst burst length */
> +#define IDMA64C_CFGL_SRC_OPT_BL		(1 << 21)	/* optimize src burst length */
> +
> +/* Bitfields in CFG_HI */
> +#define IDMA64C_CFGH_SRC_PER(x)		((x) << 0)	/* src peripheral */
> +#define IDMA64C_CFGH_DST_PER(x)		((x) << 4)	/* dst peripheral */
> +#define IDMA64C_CFGH_RD_ISSUE_THD(x)	((x) << 8)
> +#define IDMA64C_CFGH_RW_ISSUE_THD(x)	((x) << 18)
> +
> +/* Interrupt registers */
> +
> +#define IDMA64_INT_XFER		0x00
> +#define IDMA64_INT_BLOCK	0x08
> +#define IDMA64_INT_SRC_TRAN	0x10
> +#define IDMA64_INT_DST_TRAN	0x18
> +#define IDMA64_INT_ERROR	0x20
> +
> +#define IDMA64_RAW(x)		(0x2c0 + IDMA64_INT_##x)	/* r */
> +#define IDMA64_STATUS(x)	(0x2e8 + IDMA64_INT_##x)	/* r (raw & mask) */
> +#define IDMA64_MASK(x)		(0x310 + IDMA64_INT_##x)	/* rw (set = irq enabled) */
> +#define IDMA64_CLEAR(x)		(0x338 + IDMA64_INT_##x)	/* w (ack, affects "raw") */
> +
> +/* Common registers */
> +
> +#define IDMA64_STATUS_INT	0x360	/* r */
> +#define IDMA64_CFG		0x398
> +#define IDMA64_CH_EN		0x3a0
> +
> +/* Bitfields in CFG */
> +#define IDMA64_CFG_DMA_EN		(1 << 0)
> +
> +/* Hardware descriptor for Linked LIst transfers */
> +struct idma64_lli {
> +	u64		sar;
> +	u64		dar;
> +	u64		llp;
> +	u32		ctllo;
> +	u32		ctlhi;
> +	u32		sstat;
> +	u32		dstat;
> +};
> +
> +struct idma64_hw_desc {
> +	struct idma64_lli *lli;
> +	dma_addr_t llp;
> +	dma_addr_t phys;
> +	unsigned int len;
> +};
> +
> +struct idma64_desc {
> +	struct virt_dma_desc vdesc;
> +	enum dma_transfer_direction direction;
> +	struct idma64_hw_desc *hw;
> +	unsigned int ndesc;
> +	size_t length;
> +	enum dma_status status;
> +};
> +
> +static inline struct idma64_desc *to_idma64_desc(struct virt_dma_desc *vdesc)
> +{
> +	return container_of(vdesc, struct idma64_desc, vdesc);
> +}
> +
> +struct idma64_chan {
> +	struct virt_dma_chan vchan;
> +
> +	void __iomem *regs;
> +
> +	/* hardware configuration */
> +	enum dma_transfer_direction direction;
> +	unsigned int mask;
> +	struct dma_slave_config config;
> +
> +	void *pool;
> +	struct idma64_desc *desc;
> +};
> +
> +static inline struct idma64_chan *to_idma64_chan(struct dma_chan *chan)
> +{
> +	return container_of(chan, struct idma64_chan, vchan.chan);
> +}
> +
> +#define channel_set_bit(idma64, reg, mask)	\
> +	dma_writel(idma64, reg, ((mask) << 8) | (mask))
> +#define channel_clear_bit(idma64, reg, mask)	\
> +	dma_writel(idma64, reg, ((mask) << 8) | 0)
> +
> +static inline u32 idma64c_readl(struct idma64_chan *idma64c, int offset)
> +{
> +	return readl(idma64c->regs + offset);
> +}
> +
> +static inline void idma64c_writel(struct idma64_chan *idma64c, int offset,
> +				  u32 value)
> +{
> +	writel(value, idma64c->regs + offset);
> +}
> +
> +#define channel_readl(idma64c, reg)		\
> +	idma64c_readl(idma64c, IDMA64_CH_##reg)
> +#define channel_writel(idma64c, reg, value)	\
> +	idma64c_writel(idma64c, IDMA64_CH_##reg, (value))
> +
> +static inline u64 idma64c_readq(struct idma64_chan *idma64c, int offset)
> +{
> +	u64 l, h;
> +
> +	l = idma64c_readl(idma64c, offset);
> +	h = idma64c_readl(idma64c, offset + 4);
> +
> +	return l | (h << 32);
> +}
> +
> +static inline void idma64c_writeq(struct idma64_chan *idma64c, int offset,
> +				  u64 value)
> +{
> +	idma64c_writel(idma64c, offset, value);
> +	idma64c_writel(idma64c, offset + 4, value >> 32);
> +}
> +
> +#define channel_readq(idma64c, reg)		\
> +	idma64c_readq(idma64c, IDMA64_CH_##reg)
> +#define channel_writeq(idma64c, reg, value)	\
> +	idma64c_writeq(idma64c, IDMA64_CH_##reg, (value))
> +
> +struct idma64 {
> +	struct dma_device dma;
> +
> +	void __iomem *regs;
> +
> +	/* channels */
> +	unsigned short all_chan_mask;
> +	struct idma64_chan *chan;
> +};
> +
> +static inline struct idma64 *to_idma64(struct dma_device *ddev)
> +{
> +	return container_of(ddev, struct idma64, dma);
> +}
> +
> +static inline u32 idma64_readl(struct idma64 *idma64, int offset)
> +{
> +	return readl(idma64->regs + offset);
> +}
> +
> +static inline void idma64_writel(struct idma64 *idma64, int offset, u32 value)
> +{
> +	writel(value, idma64->regs + offset);
> +}
> +
> +#define dma_readl(idma64, reg)			\
> +	idma64_readl(idma64, IDMA64_##reg)
> +#define dma_writel(idma64, reg, value)		\
> +	idma64_writel(idma64, IDMA64_##reg, (value))
> +
> +/**
> + * struct idma64_chip - representation of DesignWare DMA controller hardware
> + * @dev:		struct device of the DMA controller
> + * @irq:		irq line
> + * @regs:		memory mapped I/O space
> + * @idma64:		struct idma64 that is filed by idma64_probe()
> + */
> +struct idma64_chip {
> +	struct device	*dev;
> +	int		irq;
> +	void __iomem	*regs;
> +	struct idma64	*idma64;
> +};
> +
> +#endif /* __DMA_IDMA64_H__ */

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

Re: [PATCH v6 8/8] mfd: Add support for Intel Sunrisepoint LPSS devices

[Lee Jones]

On Mon, 27 Jul 2015, Andy Shevchenko wrote:

> The new coming Intel platforms such as Skylake will contain Sunrisepoint PCH.
> The main difference to the previous platforms is that the LPSS devices are
> compound devices where usually main (SPI, HSUART, or I2C) and DMA IPs are
> present.
> 
> This patch brings the driver for such devices found on Sunrisepoint PCH.
> 
> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> ---
>  drivers/mfd/Kconfig           |  23 ++
>  drivers/mfd/Makefile          |   3 +
>  drivers/mfd/intel-lpss-acpi.c |  84 +++++++
>  drivers/mfd/intel-lpss-pci.c  | 113 +++++++++
>  drivers/mfd/intel-lpss.c      | 524 ++++++++++++++++++++++++++++++++++++++++++
>  drivers/mfd/intel-lpss.h      |  62 +++++
>  6 files changed, 809 insertions(+)
>  create mode 100644 drivers/mfd/intel-lpss-acpi.c
>  create mode 100644 drivers/mfd/intel-lpss-pci.c
>  create mode 100644 drivers/mfd/intel-lpss.c
>  create mode 100644 drivers/mfd/intel-lpss.h

Applied, thanks.  Pull request to follow.

> diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
> index 6538159..268b6dd 100644
> --- a/drivers/mfd/Kconfig
> +++ b/drivers/mfd/Kconfig
> @@ -328,6 +328,29 @@ config INTEL_SOC_PMIC
>  	  thermal, charger and related power management functions
>  	  on these systems.
>  
> +config MFD_INTEL_LPSS
> +	tristate
> +	select COMMON_CLK
> +	select MFD_CORE
> +
> +config MFD_INTEL_LPSS_ACPI
> +	tristate "Intel Low Power Subsystem support in ACPI mode"
> +	select MFD_INTEL_LPSS
> +	depends on X86 && ACPI
> +	help
> +	  This driver supports Intel Low Power Subsystem (LPSS) devices such as
> +	  I2C, SPI and HS-UART starting from Intel Sunrisepoint (Intel Skylake
> +	  PCH) in ACPI mode.
> +
> +config MFD_INTEL_LPSS_PCI
> +	tristate "Intel Low Power Subsystem support in PCI mode"
> +	select MFD_INTEL_LPSS
> +	depends on X86 && PCI
> +	help
> +	  This driver supports Intel Low Power Subsystem (LPSS) devices such as
> +	  I2C, SPI and HS-UART starting from Intel Sunrisepoint (Intel Skylake
> +	  PCH) in PCI mode.
> +
>  config MFD_INTEL_MSIC
>  	bool "Intel MSIC"
>  	depends on INTEL_SCU_IPC
> diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
> index ea40e07..9d730a2 100644
> --- a/drivers/mfd/Makefile
> +++ b/drivers/mfd/Makefile
> @@ -161,6 +161,9 @@ obj-$(CONFIG_TPS65911_COMPARATOR)	+= tps65911-comparator.o
>  obj-$(CONFIG_MFD_TPS65090)	+= tps65090.o
>  obj-$(CONFIG_MFD_AAT2870_CORE)	+= aat2870-core.o
>  obj-$(CONFIG_MFD_ATMEL_HLCDC)	+= atmel-hlcdc.o
> +obj-$(CONFIG_MFD_INTEL_LPSS)	+= intel-lpss.o
> +obj-$(CONFIG_MFD_INTEL_LPSS_PCI)	+= intel-lpss-pci.o
> +obj-$(CONFIG_MFD_INTEL_LPSS_ACPI)	+= intel-lpss-acpi.o
>  obj-$(CONFIG_MFD_INTEL_MSIC)	+= intel_msic.o
>  obj-$(CONFIG_MFD_PALMAS)	+= palmas.o
>  obj-$(CONFIG_MFD_VIPERBOARD)    += viperboard.o
> diff --git a/drivers/mfd/intel-lpss-acpi.c b/drivers/mfd/intel-lpss-acpi.c
> new file mode 100644
> index 0000000..0d92d73
> --- /dev/null
> +++ b/drivers/mfd/intel-lpss-acpi.c
> @@ -0,0 +1,84 @@
> +/*
> + * Intel LPSS ACPI support.
> + *
> + * Copyright (C) 2015, Intel Corporation
> + *
> + * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> + *          Mika Westerberg <mika.westerberg@linux.intel.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/acpi.h>
> +#include <linux/ioport.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/pm.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/platform_device.h>
> +
> +#include "intel-lpss.h"
> +
> +static const struct intel_lpss_platform_info spt_info = {
> +	.clk_rate = 120000000,
> +};
> +
> +static const struct acpi_device_id intel_lpss_acpi_ids[] = {
> +	/* SPT */
> +	{ "INT3446", (kernel_ulong_t)&spt_info },
> +	{ "INT3447", (kernel_ulong_t)&spt_info },
> +	{ }
> +};
> +MODULE_DEVICE_TABLE(acpi, intel_lpss_acpi_ids);
> +
> +static int intel_lpss_acpi_probe(struct platform_device *pdev)
> +{
> +	struct intel_lpss_platform_info *info;
> +	const struct acpi_device_id *id;
> +
> +	id = acpi_match_device(intel_lpss_acpi_ids, &pdev->dev);
> +	if (!id)
> +		return -ENODEV;
> +
> +	info = devm_kmemdup(&pdev->dev, (void *)id->driver_data, sizeof(*info),
> +			    GFP_KERNEL);
> +	if (!info)
> +		return -ENOMEM;
> +
> +	info->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	info->irq = platform_get_irq(pdev, 0);
> +
> +	pm_runtime_set_active(&pdev->dev);
> +	pm_runtime_enable(&pdev->dev);
> +
> +	return intel_lpss_probe(&pdev->dev, info);
> +}
> +
> +static int intel_lpss_acpi_remove(struct platform_device *pdev)
> +{
> +	intel_lpss_remove(&pdev->dev);
> +	pm_runtime_disable(&pdev->dev);
> +
> +	return 0;
> +}
> +
> +static INTEL_LPSS_PM_OPS(intel_lpss_acpi_pm_ops);
> +
> +static struct platform_driver intel_lpss_acpi_driver = {
> +	.probe = intel_lpss_acpi_probe,
> +	.remove = intel_lpss_acpi_remove,
> +	.driver = {
> +		.name = "intel-lpss",
> +		.acpi_match_table = intel_lpss_acpi_ids,
> +		.pm = &intel_lpss_acpi_pm_ops,
> +	},
> +};
> +
> +module_platform_driver(intel_lpss_acpi_driver);
> +
> +MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
> +MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
> +MODULE_DESCRIPTION("Intel LPSS ACPI driver");
> +MODULE_LICENSE("GPL v2");
> diff --git a/drivers/mfd/intel-lpss-pci.c b/drivers/mfd/intel-lpss-pci.c
> new file mode 100644
> index 0000000..9236dff
> --- /dev/null
> +++ b/drivers/mfd/intel-lpss-pci.c
> @@ -0,0 +1,113 @@
> +/*
> + * Intel LPSS PCI support.
> + *
> + * Copyright (C) 2015, Intel Corporation
> + *
> + * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> + *          Mika Westerberg <mika.westerberg@linux.intel.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/ioport.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/pci.h>
> +#include <linux/pm.h>
> +#include <linux/pm_runtime.h>
> +
> +#include "intel-lpss.h"
> +
> +static int intel_lpss_pci_probe(struct pci_dev *pdev,
> +				const struct pci_device_id *id)
> +{
> +	struct intel_lpss_platform_info *info;
> +	int ret;
> +
> +	ret = pcim_enable_device(pdev);
> +	if (ret)
> +		return ret;
> +
> +	info = devm_kmemdup(&pdev->dev, (void *)id->driver_data, sizeof(*info),
> +			    GFP_KERNEL);
> +	if (!info)
> +		return -ENOMEM;
> +
> +	info->mem = &pdev->resource[0];
> +	info->irq = pdev->irq;
> +
> +	/* Probably it is enough to set this for iDMA capable devices only */
> +	pci_set_master(pdev);
> +
> +	ret = intel_lpss_probe(&pdev->dev, info);
> +	if (ret)
> +		return ret;
> +
> +	pm_runtime_put(&pdev->dev);
> +	pm_runtime_allow(&pdev->dev);
> +
> +	return 0;
> +}
> +
> +static void intel_lpss_pci_remove(struct pci_dev *pdev)
> +{
> +	pm_runtime_forbid(&pdev->dev);
> +	pm_runtime_get_sync(&pdev->dev);
> +
> +	intel_lpss_remove(&pdev->dev);
> +}
> +
> +static INTEL_LPSS_PM_OPS(intel_lpss_pci_pm_ops);
> +
> +static const struct intel_lpss_platform_info spt_info = {
> +	.clk_rate = 120000000,
> +};
> +
> +static const struct intel_lpss_platform_info spt_uart_info = {
> +	.clk_rate = 120000000,
> +	.clk_con_id = "baudclk",
> +};
> +
> +static const struct pci_device_id intel_lpss_pci_ids[] = {
> +	/* SPT-LP */
> +	{ PCI_VDEVICE(INTEL, 0x9d27), (kernel_ulong_t)&spt_uart_info },
> +	{ PCI_VDEVICE(INTEL, 0x9d28), (kernel_ulong_t)&spt_uart_info },
> +	{ PCI_VDEVICE(INTEL, 0x9d29), (kernel_ulong_t)&spt_info },
> +	{ PCI_VDEVICE(INTEL, 0x9d2a), (kernel_ulong_t)&spt_info },
> +	{ PCI_VDEVICE(INTEL, 0x9d60), (kernel_ulong_t)&spt_info },
> +	{ PCI_VDEVICE(INTEL, 0x9d61), (kernel_ulong_t)&spt_info },
> +	{ PCI_VDEVICE(INTEL, 0x9d62), (kernel_ulong_t)&spt_info },
> +	{ PCI_VDEVICE(INTEL, 0x9d63), (kernel_ulong_t)&spt_info },
> +	{ PCI_VDEVICE(INTEL, 0x9d64), (kernel_ulong_t)&spt_info },
> +	{ PCI_VDEVICE(INTEL, 0x9d65), (kernel_ulong_t)&spt_info },
> +	{ PCI_VDEVICE(INTEL, 0x9d66), (kernel_ulong_t)&spt_uart_info },
> +	/* SPT-H */
> +	{ PCI_VDEVICE(INTEL, 0xa127), (kernel_ulong_t)&spt_uart_info },
> +	{ PCI_VDEVICE(INTEL, 0xa128), (kernel_ulong_t)&spt_uart_info },
> +	{ PCI_VDEVICE(INTEL, 0xa129), (kernel_ulong_t)&spt_info },
> +	{ PCI_VDEVICE(INTEL, 0xa12a), (kernel_ulong_t)&spt_info },
> +	{ PCI_VDEVICE(INTEL, 0xa160), (kernel_ulong_t)&spt_info },
> +	{ PCI_VDEVICE(INTEL, 0xa161), (kernel_ulong_t)&spt_info },
> +	{ PCI_VDEVICE(INTEL, 0xa166), (kernel_ulong_t)&spt_uart_info },
> +	{ }
> +};
> +MODULE_DEVICE_TABLE(pci, intel_lpss_pci_ids);
> +
> +static struct pci_driver intel_lpss_pci_driver = {
> +	.name = "intel-lpss",
> +	.id_table = intel_lpss_pci_ids,
> +	.probe = intel_lpss_pci_probe,
> +	.remove = intel_lpss_pci_remove,
> +	.driver = {
> +		.pm = &intel_lpss_pci_pm_ops,
> +	},
> +};
> +
> +module_pci_driver(intel_lpss_pci_driver);
> +
> +MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
> +MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
> +MODULE_DESCRIPTION("Intel LPSS PCI driver");
> +MODULE_LICENSE("GPL v2");
> diff --git a/drivers/mfd/intel-lpss.c b/drivers/mfd/intel-lpss.c
> new file mode 100644
> index 0000000..fdf4d5c
> --- /dev/null
> +++ b/drivers/mfd/intel-lpss.c
> @@ -0,0 +1,524 @@
> +/*
> + * Intel Sunrisepoint LPSS core support.
> + *
> + * Copyright (C) 2015, Intel Corporation
> + *
> + * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> + *          Mika Westerberg <mika.westerberg@linux.intel.com>
> + *          Heikki Krogerus <heikki.krogerus@linux.intel.com>
> + *          Jarkko Nikula <jarkko.nikula@linux.intel.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clkdev.h>
> +#include <linux/clk-provider.h>
> +#include <linux/debugfs.h>
> +#include <linux/idr.h>
> +#include <linux/ioport.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/mfd/core.h>
> +#include <linux/pm_qos.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/seq_file.h>
> +
> +#include "intel-lpss.h"
> +
> +#define LPSS_DEV_OFFSET		0x000
> +#define LPSS_DEV_SIZE		0x200
> +#define LPSS_PRIV_OFFSET	0x200
> +#define LPSS_PRIV_SIZE		0x100
> +#define LPSS_IDMA64_OFFSET	0x800
> +#define LPSS_IDMA64_SIZE	0x800
> +
> +/* Offsets from lpss->priv */
> +#define LPSS_PRIV_RESETS		0x04
> +#define LPSS_PRIV_RESETS_FUNC		BIT(2)
> +#define LPSS_PRIV_RESETS_IDMA		0x3
> +
> +#define LPSS_PRIV_ACTIVELTR		0x10
> +#define LPSS_PRIV_IDLELTR		0x14
> +
> +#define LPSS_PRIV_LTR_REQ		BIT(15)
> +#define LPSS_PRIV_LTR_SCALE_MASK	0xc00
> +#define LPSS_PRIV_LTR_SCALE_1US		0x800
> +#define LPSS_PRIV_LTR_SCALE_32US	0xc00
> +#define LPSS_PRIV_LTR_VALUE_MASK	0x3ff
> +
> +#define LPSS_PRIV_SSP_REG		0x20
> +#define LPSS_PRIV_SSP_REG_DIS_DMA_FIN	BIT(0)
> +
> +#define LPSS_PRIV_REMAP_ADDR_LO		0x40
> +#define LPSS_PRIV_REMAP_ADDR_HI		0x44
> +
> +#define LPSS_PRIV_CAPS			0xfc
> +#define LPSS_PRIV_CAPS_NO_IDMA		BIT(8)
> +#define LPSS_PRIV_CAPS_TYPE_SHIFT	4
> +#define LPSS_PRIV_CAPS_TYPE_MASK	(0xf << LPSS_PRIV_CAPS_TYPE_SHIFT)
> +
> +/* This matches the type field in CAPS register */
> +enum intel_lpss_dev_type {
> +	LPSS_DEV_I2C = 0,
> +	LPSS_DEV_UART,
> +	LPSS_DEV_SPI,
> +};
> +
> +struct intel_lpss {
> +	const struct intel_lpss_platform_info *info;
> +	enum intel_lpss_dev_type type;
> +	struct clk *clk;
> +	struct clk_lookup *clock;
> +	const struct mfd_cell *cell;
> +	struct device *dev;
> +	void __iomem *priv;
> +	int devid;
> +	u32 caps;
> +	u32 active_ltr;
> +	u32 idle_ltr;
> +	struct dentry *debugfs;
> +};
> +
> +static const struct resource intel_lpss_dev_resources[] = {
> +	DEFINE_RES_MEM_NAMED(LPSS_DEV_OFFSET, LPSS_DEV_SIZE, "lpss_dev"),
> +	DEFINE_RES_MEM_NAMED(LPSS_PRIV_OFFSET, LPSS_PRIV_SIZE, "lpss_priv"),
> +	DEFINE_RES_IRQ(0),
> +};
> +
> +static const struct resource intel_lpss_idma64_resources[] = {
> +	DEFINE_RES_MEM(LPSS_IDMA64_OFFSET, LPSS_IDMA64_SIZE),
> +	DEFINE_RES_IRQ(0),
> +};
> +
> +#define LPSS_IDMA64_DRIVER_NAME		"idma64"
> +
> +/*
> + * Cells needs to be ordered so that the iDMA is created first. This is
> + * because we need to be sure the DMA is available when the host controller
> + * driver is probed.
> + */
> +static const struct mfd_cell intel_lpss_idma64_cell = {
> +	.name = LPSS_IDMA64_DRIVER_NAME,
> +	.num_resources = ARRAY_SIZE(intel_lpss_idma64_resources),
> +	.resources = intel_lpss_idma64_resources,
> +};
> +
> +static const struct mfd_cell intel_lpss_i2c_cell = {
> +	.name = "i2c_designware",
> +	.num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
> +	.resources = intel_lpss_dev_resources,
> +};
> +
> +static const struct mfd_cell intel_lpss_uart_cell = {
> +	.name = "dw-apb-uart",
> +	.num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
> +	.resources = intel_lpss_dev_resources,
> +};
> +
> +static const struct mfd_cell intel_lpss_spi_cell = {
> +	.name = "pxa2xx-spi",
> +	.num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
> +	.resources = intel_lpss_dev_resources,
> +};
> +
> +static DEFINE_IDA(intel_lpss_devid_ida);
> +static struct dentry *intel_lpss_debugfs;
> +
> +static int intel_lpss_request_dma_module(const char *name)
> +{
> +	static bool intel_lpss_dma_requested;
> +
> +	if (intel_lpss_dma_requested)
> +		return 0;
> +
> +	intel_lpss_dma_requested = true;
> +	return request_module("%s", name);
> +}
> +
> +static void intel_lpss_cache_ltr(struct intel_lpss *lpss)
> +{
> +	lpss->active_ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR);
> +	lpss->idle_ltr = readl(lpss->priv + LPSS_PRIV_IDLELTR);
> +}
> +
> +static int intel_lpss_debugfs_add(struct intel_lpss *lpss)
> +{
> +	struct dentry *dir;
> +
> +	dir = debugfs_create_dir(dev_name(lpss->dev), intel_lpss_debugfs);
> +	if (IS_ERR(dir))
> +		return PTR_ERR(dir);
> +
> +	/* Cache the values into lpss structure */
> +	intel_lpss_cache_ltr(lpss);
> +
> +	debugfs_create_x32("capabilities", S_IRUGO, dir, &lpss->caps);
> +	debugfs_create_x32("active_ltr", S_IRUGO, dir, &lpss->active_ltr);
> +	debugfs_create_x32("idle_ltr", S_IRUGO, dir, &lpss->idle_ltr);
> +
> +	lpss->debugfs = dir;
> +	return 0;
> +}
> +
> +static void intel_lpss_debugfs_remove(struct intel_lpss *lpss)
> +{
> +	debugfs_remove_recursive(lpss->debugfs);
> +}
> +
> +static void intel_lpss_ltr_set(struct device *dev, s32 val)
> +{
> +	struct intel_lpss *lpss = dev_get_drvdata(dev);
> +	u32 ltr;
> +
> +	/*
> +	 * Program latency tolerance (LTR) accordingly what has been asked
> +	 * by the PM QoS layer or disable it in case we were passed
> +	 * negative value or PM_QOS_LATENCY_ANY.
> +	 */
> +	ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR);
> +
> +	if (val == PM_QOS_LATENCY_ANY || val < 0) {
> +		ltr &= ~LPSS_PRIV_LTR_REQ;
> +	} else {
> +		ltr |= LPSS_PRIV_LTR_REQ;
> +		ltr &= ~LPSS_PRIV_LTR_SCALE_MASK;
> +		ltr &= ~LPSS_PRIV_LTR_VALUE_MASK;
> +
> +		if (val > LPSS_PRIV_LTR_VALUE_MASK)
> +			ltr |= LPSS_PRIV_LTR_SCALE_32US | val >> 5;
> +		else
> +			ltr |= LPSS_PRIV_LTR_SCALE_1US | val;
> +	}
> +
> +	if (ltr == lpss->active_ltr)
> +		return;
> +
> +	writel(ltr, lpss->priv + LPSS_PRIV_ACTIVELTR);
> +	writel(ltr, lpss->priv + LPSS_PRIV_IDLELTR);
> +
> +	/* Cache the values into lpss structure */
> +	intel_lpss_cache_ltr(lpss);
> +}
> +
> +static void intel_lpss_ltr_expose(struct intel_lpss *lpss)
> +{
> +	lpss->dev->power.set_latency_tolerance = intel_lpss_ltr_set;
> +	dev_pm_qos_expose_latency_tolerance(lpss->dev);
> +}
> +
> +static void intel_lpss_ltr_hide(struct intel_lpss *lpss)
> +{
> +	dev_pm_qos_hide_latency_tolerance(lpss->dev);
> +	lpss->dev->power.set_latency_tolerance = NULL;
> +}
> +
> +static int intel_lpss_assign_devs(struct intel_lpss *lpss)
> +{
> +	unsigned int type;
> +
> +	type = lpss->caps & LPSS_PRIV_CAPS_TYPE_MASK;
> +	type >>= LPSS_PRIV_CAPS_TYPE_SHIFT;
> +
> +	switch (type) {
> +	case LPSS_DEV_I2C:
> +		lpss->cell = &intel_lpss_i2c_cell;
> +		break;
> +	case LPSS_DEV_UART:
> +		lpss->cell = &intel_lpss_uart_cell;
> +		break;
> +	case LPSS_DEV_SPI:
> +		lpss->cell = &intel_lpss_spi_cell;
> +		break;
> +	default:
> +		return -ENODEV;
> +	}
> +
> +	lpss->type = type;
> +
> +	return 0;
> +}
> +
> +static bool intel_lpss_has_idma(const struct intel_lpss *lpss)
> +{
> +	return (lpss->caps & LPSS_PRIV_CAPS_NO_IDMA) == 0;
> +}
> +
> +static void intel_lpss_set_remap_addr(const struct intel_lpss *lpss)
> +{
> +	resource_size_t addr = lpss->info->mem->start;
> +
> +	writel(addr, lpss->priv + LPSS_PRIV_REMAP_ADDR_LO);
> +#if BITS_PER_LONG > 32
> +	writel(addr >> 32, lpss->priv + LPSS_PRIV_REMAP_ADDR_HI);
> +#else
> +	writel(0, lpss->priv + LPSS_PRIV_REMAP_ADDR_HI);
> +#endif
> +}
> +
> +static void intel_lpss_deassert_reset(const struct intel_lpss *lpss)
> +{
> +	u32 value = LPSS_PRIV_RESETS_FUNC | LPSS_PRIV_RESETS_IDMA;
> +
> +	/* Bring out the device from reset */
> +	writel(value, lpss->priv + LPSS_PRIV_RESETS);
> +}
> +
> +static void intel_lpss_init_dev(const struct intel_lpss *lpss)
> +{
> +	u32 value = LPSS_PRIV_SSP_REG_DIS_DMA_FIN;
> +
> +	intel_lpss_deassert_reset(lpss);
> +
> +	if (!intel_lpss_has_idma(lpss))
> +		return;
> +
> +	intel_lpss_set_remap_addr(lpss);
> +
> +	/* Make sure that SPI multiblock DMA transfers are re-enabled */
> +	if (lpss->type == LPSS_DEV_SPI)
> +		writel(value, lpss->priv + LPSS_PRIV_SSP_REG);
> +}
> +
> +static void intel_lpss_unregister_clock_tree(struct clk *clk)
> +{
> +	struct clk *parent;
> +
> +	while (clk) {
> +		parent = clk_get_parent(clk);
> +		clk_unregister(clk);
> +		clk = parent;
> +	}
> +}
> +
> +static int intel_lpss_register_clock_divider(struct intel_lpss *lpss,
> +					     const char *devname,
> +					     struct clk **clk)
> +{
> +	char name[32];
> +	struct clk *tmp = *clk;
> +
> +	snprintf(name, sizeof(name), "%s-enable", devname);
> +	tmp = clk_register_gate(NULL, name, __clk_get_name(tmp), 0,
> +				lpss->priv, 0, 0, NULL);
> +	if (IS_ERR(tmp))
> +		return PTR_ERR(tmp);
> +
> +	snprintf(name, sizeof(name), "%s-div", devname);
> +	tmp = clk_register_fractional_divider(NULL, name, __clk_get_name(tmp),
> +					      0, lpss->priv, 1, 15, 16, 15, 0,
> +					      NULL);
> +	if (IS_ERR(tmp))
> +		return PTR_ERR(tmp);
> +	*clk = tmp;
> +
> +	snprintf(name, sizeof(name), "%s-update", devname);
> +	tmp = clk_register_gate(NULL, name, __clk_get_name(tmp),
> +				CLK_SET_RATE_PARENT, lpss->priv, 31, 0, NULL);
> +	if (IS_ERR(tmp))
> +		return PTR_ERR(tmp);
> +	*clk = tmp;
> +
> +	return 0;
> +}
> +
> +static int intel_lpss_register_clock(struct intel_lpss *lpss)
> +{
> +	const struct mfd_cell *cell = lpss->cell;
> +	struct clk *clk;
> +	char devname[24];
> +	int ret;
> +
> +	if (!lpss->info->clk_rate)
> +		return 0;
> +
> +	/* Root clock */
> +	clk = clk_register_fixed_rate(NULL, dev_name(lpss->dev), NULL,
> +				      CLK_IS_ROOT, lpss->info->clk_rate);
> +	if (IS_ERR(clk))
> +		return PTR_ERR(clk);
> +
> +	snprintf(devname, sizeof(devname), "%s.%d", cell->name, lpss->devid);
> +
> +	/*
> +	 * Support for clock divider only if it has some preset value.
> +	 * Otherwise we assume that the divider is not used.
> +	 */
> +	if (lpss->type != LPSS_DEV_I2C) {
> +		ret = intel_lpss_register_clock_divider(lpss, devname, &clk);
> +		if (ret)
> +			goto err_clk_register;
> +	}
> +
> +	ret = -ENOMEM;
> +
> +	/* Clock for the host controller */
> +	lpss->clock = clkdev_create(clk, lpss->info->clk_con_id, "%s", devname);
> +	if (!lpss->clock)
> +		goto err_clk_register;
> +
> +	lpss->clk = clk;
> +
> +	return 0;
> +
> +err_clk_register:
> +	intel_lpss_unregister_clock_tree(clk);
> +
> +	return ret;
> +}
> +
> +static void intel_lpss_unregister_clock(struct intel_lpss *lpss)
> +{
> +	if (IS_ERR_OR_NULL(lpss->clk))
> +		return;
> +
> +	clkdev_drop(lpss->clock);
> +	intel_lpss_unregister_clock_tree(lpss->clk);
> +}
> +
> +int intel_lpss_probe(struct device *dev,
> +		     const struct intel_lpss_platform_info *info)
> +{
> +	struct intel_lpss *lpss;
> +	int ret;
> +
> +	if (!info || !info->mem || info->irq <= 0)
> +		return -EINVAL;
> +
> +	lpss = devm_kzalloc(dev, sizeof(*lpss), GFP_KERNEL);
> +	if (!lpss)
> +		return -ENOMEM;
> +
> +	lpss->priv = devm_ioremap(dev, info->mem->start + LPSS_PRIV_OFFSET,
> +				  LPSS_PRIV_SIZE);
> +	if (!lpss->priv)
> +		return -ENOMEM;
> +
> +	lpss->info = info;
> +	lpss->dev = dev;
> +	lpss->caps = readl(lpss->priv + LPSS_PRIV_CAPS);
> +
> +	dev_set_drvdata(dev, lpss);
> +
> +	ret = intel_lpss_assign_devs(lpss);
> +	if (ret)
> +		return ret;
> +
> +	intel_lpss_init_dev(lpss);
> +
> +	lpss->devid = ida_simple_get(&intel_lpss_devid_ida, 0, 0, GFP_KERNEL);
> +	if (lpss->devid < 0)
> +		return lpss->devid;
> +
> +	ret = intel_lpss_register_clock(lpss);
> +	if (ret)
> +		goto err_clk_register;
> +
> +	intel_lpss_ltr_expose(lpss);
> +
> +	ret = intel_lpss_debugfs_add(lpss);
> +	if (ret)
> +		dev_warn(dev, "Failed to create debugfs entries\n");
> +
> +	if (intel_lpss_has_idma(lpss)) {
> +		/*
> +		 * Ensure the DMA driver is loaded before the host
> +		 * controller device appears, so that the host controller
> +		 * driver can request its DMA channels as early as
> +		 * possible.
> +		 *
> +		 * If the DMA module is not there that's OK as well.
> +		 */
> +		intel_lpss_request_dma_module(LPSS_IDMA64_DRIVER_NAME);
> +
> +		ret = mfd_add_devices(dev, lpss->devid, &intel_lpss_idma64_cell,
> +				      1, info->mem, info->irq, NULL);
> +		if (ret)
> +			dev_warn(dev, "Failed to add %s, fallback to PIO\n",
> +				 LPSS_IDMA64_DRIVER_NAME);
> +	}
> +
> +	ret = mfd_add_devices(dev, lpss->devid, lpss->cell,
> +			      1, info->mem, info->irq, NULL);
> +	if (ret)
> +		goto err_remove_ltr;
> +
> +	return 0;
> +
> +err_remove_ltr:
> +	intel_lpss_debugfs_remove(lpss);
> +	intel_lpss_ltr_hide(lpss);
> +
> +err_clk_register:
> +	ida_simple_remove(&intel_lpss_devid_ida, lpss->devid);
> +
> +	return ret;
> +}
> +EXPORT_SYMBOL_GPL(intel_lpss_probe);
> +
> +void intel_lpss_remove(struct device *dev)
> +{
> +	struct intel_lpss *lpss = dev_get_drvdata(dev);
> +
> +	mfd_remove_devices(dev);
> +	intel_lpss_debugfs_remove(lpss);
> +	intel_lpss_ltr_hide(lpss);
> +	intel_lpss_unregister_clock(lpss);
> +	ida_simple_remove(&intel_lpss_devid_ida, lpss->devid);
> +}
> +EXPORT_SYMBOL_GPL(intel_lpss_remove);
> +
> +static int resume_lpss_device(struct device *dev, void *data)
> +{
> +	pm_runtime_resume(dev);
> +	return 0;
> +}
> +
> +int intel_lpss_prepare(struct device *dev)
> +{
> +	/*
> +	 * Resume both child devices before entering system sleep. This
> +	 * ensures that they are in proper state before they get suspended.
> +	 */
> +	device_for_each_child_reverse(dev, NULL, resume_lpss_device);
> +	return 0;
> +}
> +EXPORT_SYMBOL_GPL(intel_lpss_prepare);
> +
> +int intel_lpss_suspend(struct device *dev)
> +{
> +	return 0;
> +}
> +EXPORT_SYMBOL_GPL(intel_lpss_suspend);
> +
> +int intel_lpss_resume(struct device *dev)
> +{
> +	struct intel_lpss *lpss = dev_get_drvdata(dev);
> +
> +	intel_lpss_init_dev(lpss);
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL_GPL(intel_lpss_resume);
> +
> +static int __init intel_lpss_init(void)
> +{
> +	intel_lpss_debugfs = debugfs_create_dir("intel_lpss", NULL);
> +	return 0;
> +}
> +module_init(intel_lpss_init);
> +
> +static void __exit intel_lpss_exit(void)
> +{
> +	debugfs_remove(intel_lpss_debugfs);
> +}
> +module_exit(intel_lpss_exit);
> +
> +MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
> +MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
> +MODULE_AUTHOR("Heikki Krogerus <heikki.krogerus@linux.intel.com>");
> +MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@linux.intel.com>");
> +MODULE_DESCRIPTION("Intel LPSS core driver");
> +MODULE_LICENSE("GPL v2");
> diff --git a/drivers/mfd/intel-lpss.h b/drivers/mfd/intel-lpss.h
> new file mode 100644
> index 0000000..f28cb28a
> --- /dev/null
> +++ b/drivers/mfd/intel-lpss.h
> @@ -0,0 +1,62 @@
> +/*
> + * Intel LPSS core support.
> + *
> + * Copyright (C) 2015, Intel Corporation
> + *
> + * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> + *          Mika Westerberg <mika.westerberg@linux.intel.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#ifndef __MFD_INTEL_LPSS_H
> +#define __MFD_INTEL_LPSS_H
> +
> +struct device;
> +struct resource;
> +
> +struct intel_lpss_platform_info {
> +	struct resource *mem;
> +	int irq;
> +	unsigned long clk_rate;
> +	const char *clk_con_id;
> +};
> +
> +int intel_lpss_probe(struct device *dev,
> +		     const struct intel_lpss_platform_info *info);
> +void intel_lpss_remove(struct device *dev);
> +
> +#ifdef CONFIG_PM
> +int intel_lpss_prepare(struct device *dev);
> +int intel_lpss_suspend(struct device *dev);
> +int intel_lpss_resume(struct device *dev);
> +
> +#ifdef CONFIG_PM_SLEEP
> +#define INTEL_LPSS_SLEEP_PM_OPS			\
> +	.prepare = intel_lpss_prepare,		\
> +	.suspend = intel_lpss_suspend,		\
> +	.resume = intel_lpss_resume,		\
> +	.freeze = intel_lpss_suspend,		\
> +	.thaw = intel_lpss_resume,		\
> +	.poweroff = intel_lpss_suspend,		\
> +	.restore = intel_lpss_resume,
> +#endif
> +
> +#define INTEL_LPSS_RUNTIME_PM_OPS		\
> +	.runtime_suspend = intel_lpss_suspend,	\
> +	.runtime_resume = intel_lpss_resume,
> +
> +#else /* !CONFIG_PM */
> +#define INTEL_LPSS_SLEEP_PM_OPS
> +#define INTEL_LPSS_RUNTIME_PM_OPS
> +#endif /* CONFIG_PM */
> +
> +#define INTEL_LPSS_PM_OPS(name)			\
> +const struct dev_pm_ops name = {		\
> +	INTEL_LPSS_SLEEP_PM_OPS			\
> +	INTEL_LPSS_RUNTIME_PM_OPS		\
> +}
> +
> +#endif /* __MFD_INTEL_LPSS_H */

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

Re: [PATCH v6 7/8] dmaengine: add a driver for Intel integrated DMA 64-bit

[Lee Jones]

FAO Vinod,

On Tue, 28 Jul 2015, Lee Jones wrote:
> On Mon, 27 Jul 2015, Andy Shevchenko wrote:
> 
> > Intel integrated DMA (iDMA) 64-bit is a specific IP that is used as a part of
> > LPSS devices such as HSUART or SPI. The iDMA IP is attached for private
> > usage on each host controller independently.
> > 
> > While it has similarities with Synopsys DesignWare DMA, the following
> > distinctions doesn't allow to use the existing driver:
> > - 64-bit mode with corresponding changes in Hardware Linked List data structure
> > - many slight differences in the channel registers
> > 
> > Moreover this driver is based on the DMA virtual channels framework that helps
> > to make the driver cleaner and easy to understand.
> > 
> > Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> > ---
> >  drivers/dma/Kconfig  |   8 +
> >  drivers/dma/Makefile |   1 +
> >  drivers/dma/idma64.c | 710 +++++++++++++++++++++++++++++++++++++++++++++++++++
> >  drivers/dma/idma64.h | 233 +++++++++++++++++
> >  4 files changed, 952 insertions(+)
> >  create mode 100644 drivers/dma/idma64.c
> >  create mode 100644 drivers/dma/idma64.h
> 
> Applied, thanks.  Pull request to follow.

Will send out a pull request when I have Vinod's Ack.

[...]

Patches will still be applied to -next for soak testing though.

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

Re: [PATCH v6 7/8] dmaengine: add a driver for Intel integrated DMA 64-bit

[Andy Shevchenko]

On Tue, 2015-07-28 at 08:53 +0100, Lee Jones wrote:
> FAO Vinod,
> 
> On Tue, 28 Jul 2015, Lee Jones wrote:
> > On Mon, 27 Jul 2015, Andy Shevchenko wrote:
> > 
> > > Intel integrated DMA (iDMA) 64-bit is a specific IP that is used 
> > > as a part of
> > > LPSS devices such as HSUART or SPI. The iDMA IP is attached for 
> > > private
> > > usage on each host controller independently.
> > > 
> > > While it has similarities with Synopsys DesignWare DMA, the 
> > > following
> > > distinctions doesn't allow to use the existing driver:
> > > - 64-bit mode with corresponding changes in Hardware Linked List 
> > > data structure
> > > - many slight differences in the channel registers
> > > 
> > > Moreover this driver is based on the DMA virtual channels 
> > > framework that helps
> > > to make the driver cleaner and easy to understand.
> > > 
> > > Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com
> > > >
> > > ---
> > >  drivers/dma/Kconfig  |   8 +
> > >  drivers/dma/Makefile |   1 +
> > >  drivers/dma/idma64.c | 710 
> > > +++++++++++++++++++++++++++++++++++++++++++++++++++
> > >  drivers/dma/idma64.h | 233 +++++++++++++++++
> > >  4 files changed, 952 insertions(+)
> > >  create mode 100644 drivers/dma/idma64.c
> > >  create mode 100644 drivers/dma/idma64.h
> > 
> > Applied, thanks.  Pull request to follow.
> 
> Will send out a pull request when I have Vinod's Ack.

Vinod, could you have a look at this once again?

> 
> [...]
> 
> Patches will still be applied to -next for soak testing though.

Thanks!


-- 
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy

Re: [PATCH v6 7/8] dmaengine: add a driver for Intel integrated DMA 64-bit

[Vinod Koul]

On Mon, Jul 27, 2015 at 06:04:02PM +0300, Andy Shevchenko wrote:
> Intel integrated DMA (iDMA) 64-bit is a specific IP that is used as a part of
> LPSS devices such as HSUART or SPI. The iDMA IP is attached for private
> usage on each host controller independently.
> 
> While it has similarities with Synopsys DesignWare DMA, the following
> distinctions doesn't allow to use the existing driver:
> - 64-bit mode with corresponding changes in Hardware Linked List data structure
> - many slight differences in the channel registers
> 
> Moreover this driver is based on the DMA virtual channels framework that helps
> to make the driver cleaner and easy to understand.
Acked-by: Vinod Koul <vinod.koul@intel.com>

-- 
~Vinod

Re: [PATCH v6 0/8] mfd: introduce a driver for LPSS devices on SPT

[Lee Jones]

Enjoy,

The following changes since commit bc0195aad0daa2ad5b0d76cce22b167bc3435590:

  Linux 4.2-rc2 (2015-07-12 15:10:30 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git tags/ib-mfd-base-acpi-dma-v4.3

for you to fetch changes up to 4b45efe8526359a11ca60a299bef3aebf413fd77:

  mfd: Add support for Intel Sunrisepoint LPSS devices (2015-07-28 09:56:47 +0100)

----------------------------------------------------------------
Immutable branch between MFD, Base, ACPI and DMA due for v4.3

----------------------------------------------------------------
Andy Shevchenko (5):
      klist: implement klist_prev()
      driver core: implement device_for_each_child_reverse()
      mfd: make mfd_remove_devices() iterate in reverse order
      dmaengine: add a driver for Intel integrated DMA 64-bit
      mfd: Add support for Intel Sunrisepoint LPSS devices

Mika Westerberg (2):
      PM / QoS: Make it possible to expose device latency tolerance to userspace
      ACPI / PM: Attach ACPI power domain only once

Rafael J. Wysocki (1):
      Driver core: wakeup the parent device before trying probe

 drivers/acpi/device_pm.c      |   8 +
 drivers/acpi/internal.h       |   2 +
 drivers/acpi/scan.c           |  46 ++-
 drivers/base/core.c           |  43 +++
 drivers/base/dd.c             |  20 ++
 drivers/base/power/power.h    |   2 +
 drivers/base/power/qos.c      |  37 +++
 drivers/base/power/sysfs.c    |  11 +
 drivers/dma/Kconfig           |   8 +
 drivers/dma/Makefile          |   1 +
 drivers/dma/idma64.c          | 710 ++++++++++++++++++++++++++++++++++++++++++
 drivers/dma/idma64.h          | 233 ++++++++++++++
 drivers/mfd/Kconfig           |  23 ++
 drivers/mfd/Makefile          |   3 +
 drivers/mfd/intel-lpss-acpi.c |  84 +++++
 drivers/mfd/intel-lpss-pci.c  | 113 +++++++
 drivers/mfd/intel-lpss.c      | 524 +++++++++++++++++++++++++++++++
 drivers/mfd/intel-lpss.h      |  62 ++++
 drivers/mfd/mfd-core.c        |   2 +-
 include/linux/device.h        |   2 +
 include/linux/klist.h         |   1 +
 include/linux/pm_qos.h        |   5 +
 lib/klist.c                   |  41 +++
 23 files changed, 1964 insertions(+), 17 deletions(-)
 create mode 100644 drivers/dma/idma64.c
 create mode 100644 drivers/dma/idma64.h
 create mode 100644 drivers/mfd/intel-lpss-acpi.c
 create mode 100644 drivers/mfd/intel-lpss-pci.c
 create mode 100644 drivers/mfd/intel-lpss.c
 create mode 100644 drivers/mfd/intel-lpss.h

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
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[GIT PULL] mfd: Immutable branch between MFD, Base, ACPI and DMA

[Lee Jones]

With more explicit $SUBJECT line this time.

Sorry for the noise.

> Enjoy,
> 
> The following changes since commit bc0195aad0daa2ad5b0d76cce22b167bc3435590:
> 
>   Linux 4.2-rc2 (2015-07-12 15:10:30 -0700)
> 
> are available in the git repository at:
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git tags/ib-mfd-base-acpi-dma-v4.3
> 
> for you to fetch changes up to 4b45efe8526359a11ca60a299bef3aebf413fd77:
> 
>   mfd: Add support for Intel Sunrisepoint LPSS devices (2015-07-28 09:56:47 +0100)
> 
> ----------------------------------------------------------------
> Immutable branch between MFD, Base, ACPI and DMA due for v4.3
> 
> ----------------------------------------------------------------
> Andy Shevchenko (5):
>       klist: implement klist_prev()
>       driver core: implement device_for_each_child_reverse()
>       mfd: make mfd_remove_devices() iterate in reverse order
>       dmaengine: add a driver for Intel integrated DMA 64-bit
>       mfd: Add support for Intel Sunrisepoint LPSS devices
> 
> Mika Westerberg (2):
>       PM / QoS: Make it possible to expose device latency tolerance to userspace
>       ACPI / PM: Attach ACPI power domain only once
> 
> Rafael J. Wysocki (1):
>       Driver core: wakeup the parent device before trying probe
> 
>  drivers/acpi/device_pm.c      |   8 +
>  drivers/acpi/internal.h       |   2 +
>  drivers/acpi/scan.c           |  46 ++-
>  drivers/base/core.c           |  43 +++
>  drivers/base/dd.c             |  20 ++
>  drivers/base/power/power.h    |   2 +
>  drivers/base/power/qos.c      |  37 +++
>  drivers/base/power/sysfs.c    |  11 +
>  drivers/dma/Kconfig           |   8 +
>  drivers/dma/Makefile          |   1 +
>  drivers/dma/idma64.c          | 710 ++++++++++++++++++++++++++++++++++++++++++
>  drivers/dma/idma64.h          | 233 ++++++++++++++
>  drivers/mfd/Kconfig           |  23 ++
>  drivers/mfd/Makefile          |   3 +
>  drivers/mfd/intel-lpss-acpi.c |  84 +++++
>  drivers/mfd/intel-lpss-pci.c  | 113 +++++++
>  drivers/mfd/intel-lpss.c      | 524 +++++++++++++++++++++++++++++++
>  drivers/mfd/intel-lpss.h      |  62 ++++
>  drivers/mfd/mfd-core.c        |   2 +-
>  include/linux/device.h        |   2 +
>  include/linux/klist.h         |   1 +
>  include/linux/pm_qos.h        |   5 +
>  lib/klist.c                   |  41 +++
>  23 files changed, 1964 insertions(+), 17 deletions(-)
>  create mode 100644 drivers/dma/idma64.c
>  create mode 100644 drivers/dma/idma64.h
>  create mode 100644 drivers/mfd/intel-lpss-acpi.c
>  create mode 100644 drivers/mfd/intel-lpss-pci.c
>  create mode 100644 drivers/mfd/intel-lpss.c
>  create mode 100644 drivers/mfd/intel-lpss.h
> 

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

Re: [PATCH v6 0/8] mfd: introduce a driver for LPSS devices on SPT

[Mika Westerberg]

On Tue, Jul 28, 2015 at 09:59:30AM +0100, Lee Jones wrote:
> Enjoy,
> 
> The following changes since commit bc0195aad0daa2ad5b0d76cce22b167bc3435590:
> 
>   Linux 4.2-rc2 (2015-07-12 15:10:30 -0700)
> 
> are available in the git repository at:
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git tags/ib-mfd-base-acpi-dma-v4.3
> 
> for you to fetch changes up to 4b45efe8526359a11ca60a299bef3aebf413fd77:
> 
>   mfd: Add support for Intel Sunrisepoint LPSS devices (2015-07-28 09:56:47 +0100)
> 
> ----------------------------------------------------------------
> Immutable branch between MFD, Base, ACPI and DMA due for v4.3
> 
> ----------------------------------------------------------------
> Andy Shevchenko (5):
>       klist: implement klist_prev()
>       driver core: implement device_for_each_child_reverse()
>       mfd: make mfd_remove_devices() iterate in reverse order
>       dmaengine: add a driver for Intel integrated DMA 64-bit
>       mfd: Add support for Intel Sunrisepoint LPSS devices
> 
> Mika Westerberg (2):
>       PM / QoS: Make it possible to expose device latency tolerance to userspace
>       ACPI / PM: Attach ACPI power domain only once
> 
> Rafael J. Wysocki (1):
>       Driver core: wakeup the parent device before trying probe

Thank you :-)

Re: [PATCH v6 0/8] mfd: introduce a driver for LPSS devices on SPT

[Rafael J. Wysocki]

On Tuesday, July 28, 2015 09:59:30 AM Lee Jones wrote:
> Enjoy,
> 
> The following changes since commit bc0195aad0daa2ad5b0d76cce22b167bc3435590:
> 
>   Linux 4.2-rc2 (2015-07-12 15:10:30 -0700)
> 
> are available in the git repository at:
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git tags/ib-mfd-base-acpi-dma-v4.3
> 
> for you to fetch changes up to 4b45efe8526359a11ca60a299bef3aebf413fd77:
> 
>   mfd: Add support for Intel Sunrisepoint LPSS devices (2015-07-28 09:56:47 +0100)
> 
> ----------------------------------------------------------------
> Immutable branch between MFD, Base, ACPI and DMA due for v4.3

Thanks, much appreciated!

Rafael

Re: [PATCH v6 8/8] mfd: Add support for Intel Sunrisepoint LPSS devices

[Michael Turquette]

Hi Andy,

Is there a data sheet or reference manual publicly available for the
LPSS?

Quoting Andy Shevchenko (2015-07-27 08:04:03)
> diff --git a/drivers/mfd/intel-lpss.c b/drivers/mfd/intel-lpss.c
> new file mode 100644
> index 0000000..fdf4d5c
> --- /dev/null
> +++ b/drivers/mfd/intel-lpss.c
> @@ -0,0 +1,524 @@
> +/*
> + * Intel Sunrisepoint LPSS core support.
> + *
> + * Copyright (C) 2015, Intel Corporation
> + *
> + * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> + *          Mika Westerberg <mika.westerberg@linux.intel.com>
> + *          Heikki Krogerus <heikki.krogerus@linux.intel.com>
> + *          Jarkko Nikula <jarkko.nikula@linux.intel.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clkdev.h>

I hope that we can get rid of the above two headers. See more below.

> +struct intel_lpss {
> +       const struct intel_lpss_platform_info *info;
> +       enum intel_lpss_dev_type type;
> +       struct clk *clk;
> +       struct clk_lookup *clock;

Same here. I don't see a use for the clk_lookup?

> +static void intel_lpss_unregister_clock_tree(struct clk *clk)
> +{
> +       struct clk *parent;
> +
> +       while (clk) {
> +               parent = clk_get_parent(clk);
> +               clk_unregister(clk);
> +               clk = parent;
> +       }

clk_unregister is for clock provider drivers that might be unloaded at
run-time, so it is nice of you to support it. However this
implementation isn't fully safe.

For instance, what happens if one day you plug in another clock provider
on top of this one? Your root clock here no longer be a root clock; it
would have a parent, and possibly a whole tree of clocks up above. If
the above happens then you'll unregister all of the parents up until you
hit a root clock!

A better alternative is for your clock provider driver (i.e. _this_
driver) to keep track of which clocks its registers and then unregister
them later.

In fact we have a nice function to help with that: devm_clk_register!
There are plenty of examples of how that is used. It doesn't work with
the "basic" clock types you are using here, but I'm not convinced that
you should be using those anyways...

> +}
> +
> +static int intel_lpss_register_clock_divider(struct intel_lpss *lpss,
> +                                            const char *devname,
> +                                            struct clk **clk)
> +{
> +       char name[32];
> +       struct clk *tmp = *clk;
> +
> +       snprintf(name, sizeof(name), "%s-enable", devname);
> +       tmp = clk_register_gate(NULL, name, __clk_get_name(tmp), 0,
> +                               lpss->priv, 0, 0, NULL);
> +       if (IS_ERR(tmp))
> +               return PTR_ERR(tmp);
> +
> +       snprintf(name, sizeof(name), "%s-div", devname);
> +       tmp = clk_register_fractional_divider(NULL, name, __clk_get_name(tmp),
> +                                             0, lpss->priv, 1, 15, 16, 15, 0,
> +                                             NULL);
> +       if (IS_ERR(tmp))
> +               return PTR_ERR(tmp);
> +       *clk = tmp;
> +
> +       snprintf(name, sizeof(name), "%s-update", devname);
> +       tmp = clk_register_gate(NULL, name, __clk_get_name(tmp),
> +                               CLK_SET_RATE_PARENT, lpss->priv, 31, 0, NULL);

A gate, then a fixed divider, and then another gate? Seems weird. Do you
have other clock signals that are not enumerated here?

Where did those clock names come from? Are they like that in the data
sheet or just made up for the sake of writing this driver?

Why are the names generated dynamically? Some static data might be
better here. Do you anticipate having more than one LPSS in a running
system? I really hate __clk_get_name and would like to remove it some
day. If we can avoid using it here then I would be grateful.

Also, why do you register these clocks with clkdev? Do other drivers
clk_get them? When are the gates ever enabled/disabled?

> +       if (IS_ERR(tmp))
> +               return PTR_ERR(tmp);
> +       *clk = tmp;
> +
> +       return 0;
> +}
> +
> +static int intel_lpss_register_clock(struct intel_lpss *lpss)
> +{
> +       const struct mfd_cell *cell = lpss->cell;
> +       struct clk *clk;
> +       char devname[24];
> +       int ret;
> +
> +       if (!lpss->info->clk_rate)
> +               return 0;
> +
> +       /* Root clock */
> +       clk = clk_register_fixed_rate(NULL, dev_name(lpss->dev), NULL,
> +                                     CLK_IS_ROOT, lpss->info->clk_rate);
> +       if (IS_ERR(clk))
> +               return PTR_ERR(clk);
> +
> +       snprintf(devname, sizeof(devname), "%s.%d", cell->name, lpss->devid);
> +
> +       /*
> +        * Support for clock divider only if it has some preset value.
> +        * Otherwise we assume that the divider is not used.
> +        */
> +       if (lpss->type != LPSS_DEV_I2C) {
> +               ret = intel_lpss_register_clock_divider(lpss, devname, &clk);
> +               if (ret)
> +                       goto err_clk_register;
> +       }

Do ACPI tables encode any meaningful data about clock signals? I gave
some advice on this topic a couple of years ago to folks hacking on ACPI
stuff in Linux, but I haven't kept up with the topic.

By comparison, most ARM-based platforms use Devicetree to link up a
clock provider to a clock consumer. I do not think similar
infrastructure exists yet for ACPI-based designs, but I wonder if the
clock data exists in newer ACPI tables to at least make it possible?

Regards,
Mike

Re: [PATCH v6 8/8] mfd: Add support for Intel Sunrisepoint LPSS devices

[Rafael J. Wysocki]

On Wednesday, July 29, 2015 03:44:34 PM Michael Turquette wrote:
> Hi Andy,

[cut]

> Do ACPI tables encode any meaningful data about clock signals? I gave
> some advice on this topic a couple of years ago to folks hacking on ACPI
> stuff in Linux, but I haven't kept up with the topic.
> 
> By comparison, most ARM-based platforms use Devicetree to link up a
> clock provider to a clock consumer. I do not think similar
> infrastructure exists yet for ACPI-based designs, but I wonder if the
> clock data exists in newer ACPI tables to at least make it possible?

No, it doesn't.

Thanks,
Rafael

Re: [PATCH v6 8/8] mfd: Add support for Intel Sunrisepoint LPSS devices

[Andy Shevchenko]

On Wed, 2015-07-29 at 15:44 -0700, Michael Turquette wrote:
> Hi Andy,
> 
> Is there a data sheet or reference manual publicly available for the
> LPSS?

Yes, I mentioned it in cover letter. For your convenience I just
copy'n'paste it here:

https://download.01.org/future-platform-configuration
-hub/skylake/register-definitions/332219-002.pdf


> 
> Quoting Andy Shevchenko (2015-07-27 08:04:03)
> > diff --git a/drivers/mfd/intel-lpss.c b/drivers/mfd/intel-lpss.c
> > new file mode 100644
> > index 0000000..fdf4d5c
> > --- /dev/null
> > +++ b/drivers/mfd/intel-lpss.c
> > @@ -0,0 +1,524 @@
> > +/*
> > + * Intel Sunrisepoint LPSS core support.
> > + *
> > + * Copyright (C) 2015, Intel Corporation
> > + *
> > + * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> > + *          Mika Westerberg <mika.westerberg@linux.intel.com>
> > + *          Heikki Krogerus <heikki.krogerus@linux.intel.com>
> > + *          Jarkko Nikula <jarkko.nikula@linux.intel.com>
> > + *
> > + * This program is free software; you can redistribute it and/or 
> > modify
> > + * it under the terms of the GNU General Public License version 2 
> > as
> > + * published by the Free Software Foundation.
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/clkdev.h>
> 
> I hope that we can get rid of the above two headers. See more below.
> 
> > +struct intel_lpss {
> > +       const struct intel_lpss_platform_info *info;
> > +       enum intel_lpss_dev_type type;
> > +       struct clk *clk;
> > +       struct clk_lookup *clock;
> 
> Same here. I don't see a use for the clk_lookup?

clkdev_create() returns it.

> 
> > +static void intel_lpss_unregister_clock_tree(struct clk *clk)
> > +{
> > +       struct clk *parent;
> > +
> > +       while (clk) {
> > +               parent = clk_get_parent(clk);
> > +               clk_unregister(clk);
> > +               clk = parent;
> > +       }
> 
> clk_unregister is for clock provider drivers that might be unloaded 
> at
> run-time, so it is nice of you to support it. However this
> implementation isn't fully safe.
> 
> For instance, what happens if one day you plug in another clock 
> provider
> on top of this one? Your root clock here no longer be a root clock; 
> it
> would have a parent, and possibly a whole tree of clocks up above. If
> the above happens then you'll unregister all of the parents up until 
> you
> hit a root clock!
> 
> A better alternative is for your clock provider driver (i.e. _this_
> driver) to keep track of which clocks its registers and then 
> unregister
> them later.
> 
> In fact we have a nice function to help with that: devm_clk_register!
> 

I will look at this.

> There are plenty of examples of how that is used. It doesn't work 
> with
> the "basic" clock types you are using here, but I'm not convinced 
> that
> you should be using those anyways...
> 
> > +}
> > +
> > +static int intel_lpss_register_clock_divider(struct intel_lpss 
> > *lpss,
> > +                                            const char *devname,
> > +                                            struct clk **clk)
> > +{
> > +       char name[32];
> > +       struct clk *tmp = *clk;
> > +
> > +       snprintf(name, sizeof(name), "%s-enable", devname);
> > +       tmp = clk_register_gate(NULL, name, __clk_get_name(tmp), 0,
> > +                               lpss->priv, 0, 0, NULL);
> > +       if (IS_ERR(tmp))
> > +               return PTR_ERR(tmp);
> > +
> > +       snprintf(name, sizeof(name), "%s-div", devname);
> > +       tmp = clk_register_fractional_divider(NULL, name, 
> > __clk_get_name(tmp),
> > +                                             0, lpss->priv, 1, 15, 
> > 16, 15, 0,
> > +                                             NULL);
> > +       if (IS_ERR(tmp))
> > +               return PTR_ERR(tmp);
> > +       *clk = tmp;
> > +
> > +       snprintf(name, sizeof(name), "%s-update", devname);
> > +       tmp = clk_register_gate(NULL, name, __clk_get_name(tmp),
> > +                               CLK_SET_RATE_PARENT, lpss->priv, 
> > 31, 0, NULL);
> 
> A gate, then a fixed divider, and then another gate? Seems weird. Do 
> you
> have other clock signals that are not enumerated here?
> 
> Where did those clock names come from? Are they like that in the data
> sheet or just made up for the sake of writing this driver?

For example, chapter 1.0, section 1.1 describes clock gating and
fractional divider for UART. Also the high bit updates the actual
divider after we supply m and n values.

Since we have the clock implementation which enables one bit per device
we have to do this in a way of clock tree.

If you have any better suggestion we would improve our driver.

> 
> Why are the names generated dynamically? Some static data might be
> better here. Do you anticipate having more than one LPSS in a running
> system? 

What do you mean under LPSS? We mean the entire IP block consists of
several devices (we only can say which and in what configuration
dynamically). devname here corresponds to the each device in the LPSS
IP block.

As an example
   clock                         enable_cnt  prepare_cnt        rate  
 accuracy   phase
-----------------------------------------------------------------------
-----------------
 0000:00:1e.3                             0            0   120000000   
       0 0  
    pxa2xx-spi.6-enable                   0            0   120000000   
       0 0  
       pxa2xx-spi.6-div                   0            0   120000000   
       0 0  
          pxa2xx-spi.6-update             0            0   120000000   
       0 0  
 0000:00:1e.0                             0            0   120000000   
       0 0  
    dw-apb-uart.5-enable                  0            0   120000000   
       0 0  
       dw-apb-uart.5-div                  0            0     1843200   
       0 0  
          dw-apb-uart.5-update            0            0     1843200   
       0 0  
 0000:00:19.0                             0            0   120000000   
       0 0  
    dw-apb-uart.4-enable                  0            0   120000000   
       0 0  
       dw-apb-uart.4-div                  0            0     1843200   
       0 0  
          dw-apb-uart.4-update            0            0     1843200   
       0 0  

> I really hate __clk_get_name and would like to remove it some
> day. If we can avoid using it here then I would be grateful.
> 
> Also, why do you register these clocks with clkdev? Do other drivers
> clk_get them?

Yes. The actual consumers do that: spi-pxa2xx, 8250_dw, i2c-designware.

>  When are the gates ever enabled/disabled?

In the mentioned drivers. For example, for UART is a clock called
'baudclk' which is changed whenever user changes a baud rate.


-- 
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy