* [PATCH] intel_idle: Add support for Goldmont core in the Broxton Socs
@ 2015-11-05 16:43 Srinidhi Kasagar
2015-11-07 1:08 ` Rafael J. Wysocki
0 siblings, 1 reply; 3+ messages in thread
From: Srinidhi Kasagar @ 2015-11-05 16:43 UTC (permalink / raw)
To: lenb, len.brown; +Cc: rjw, linux-pm, srinidhi.kasagar
Broxton SoC uses similar Haswell like C states. Add a dedicated
table for this Soc.
Signed-off-by: Srinidhi Kasagar <srinidhi.kasagar@intel.com>
---
drivers/idle/intel_idle.c | 76 +++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 76 insertions(+)
diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c
index 3a3738fe016b..beb950838cda 100644
--- a/drivers/idle/intel_idle.c
+++ b/drivers/idle/intel_idle.c
@@ -522,6 +522,76 @@ static struct cpuidle_state hsw_cstates[] = {
{
.enter = NULL }
};
+
+static struct cpuidle_state bxt_cstates[] = {
+ {
+ .name = "C1-BXT",
+ .desc = "MWAIT 0x00",
+ .flags = MWAIT2flg(0x00),
+ .exit_latency = 2,
+ .target_residency = 2,
+ .enter = &intel_idle,
+ .enter_freeze = intel_idle_freeze, },
+ {
+ .name = "C1E-BXT",
+ .desc = "MWAIT 0x01",
+ .flags = MWAIT2flg(0x01),
+ .exit_latency = 10,
+ .target_residency = 20,
+ .enter = &intel_idle,
+ .enter_freeze = intel_idle_freeze, },
+ {
+ .name = "C3-BXT",
+ .desc = "MWAIT 0x10",
+ .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
+ .exit_latency = 33,
+ .target_residency = 100,
+ .enter = &intel_idle,
+ .enter_freeze = intel_idle_freeze, },
+ {
+ .name = "C6-BXT",
+ .desc = "MWAIT 0x20",
+ .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
+ .exit_latency = 133,
+ .target_residency = 400,
+ .enter = &intel_idle,
+ .enter_freeze = intel_idle_freeze, },
+ {
+ .name = "C7s-BXT",
+ .desc = "MWAIT 0x32",
+ .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
+ .exit_latency = 166,
+ .target_residency = 500,
+ .enter = &intel_idle,
+ .enter_freeze = intel_idle_freeze, },
+ {
+ .name = "C8-BXT",
+ .desc = "MWAIT 0x40",
+ .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
+ .exit_latency = 300,
+ .target_residency = 900,
+ .enter = &intel_idle,
+ .enter_freeze = intel_idle_freeze, },
+ {
+ .name = "C9-BXT",
+ .desc = "MWAIT 0x50",
+ .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
+ .exit_latency = 600,
+ .target_residency = 1800,
+ .enter = &intel_idle,
+ .enter_freeze = intel_idle_freeze, },
+ {
+ .name = "C10-BXT",
+ .desc = "MWAIT 0x60",
+ .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
+ .exit_latency = 2600,
+ .target_residency = 7700,
+ .enter = &intel_idle,
+ .enter_freeze = intel_idle_freeze, },
+ {
+ .enter = NULL }
+};
+
static struct cpuidle_state bdw_cstates[] = {
{
.name = "C1-BDW",
@@ -882,6 +952,11 @@ static const struct idle_cpu idle_cpu_avn = {
.disable_promotion_to_c1e = true,
};
+static const struct idle_cpu idle_cpu_bxt = {
+ .state_table = bxt_cstates,
+ .disable_promotion_to_c1e = true,
+};
+
#define ICPU(model, cpu) \
{ X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (unsigned long)&cpu }
@@ -911,6 +986,7 @@ static const struct x86_cpu_id intel_idle_ids[] __initconst = {
ICPU(0x47, idle_cpu_bdw),
ICPU(0x4f, idle_cpu_bdw),
ICPU(0x56, idle_cpu_bdw),
+ ICPU(0x5c, idle_cpu_bxt),
ICPU(0x4e, idle_cpu_skl),
ICPU(0x5e, idle_cpu_skl),
{}
--
1.7.9.5
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH] intel_idle: Add support for Goldmont core in the Broxton Socs
2015-11-05 16:43 [PATCH] intel_idle: Add support for Goldmont core in the Broxton Socs Srinidhi Kasagar
@ 2015-11-07 1:08 ` Rafael J. Wysocki
2015-11-17 12:28 ` Kasagar, Srinidhi
0 siblings, 1 reply; 3+ messages in thread
From: Rafael J. Wysocki @ 2015-11-07 1:08 UTC (permalink / raw)
To: Srinidhi Kasagar; +Cc: lenb, len.brown, linux-pm
On Thursday, November 05, 2015 10:13:37 PM Srinidhi Kasagar wrote:
> Broxton SoC uses similar Haswell like C states. Add a dedicated
> table for this Soc.
>
> Signed-off-by: Srinidhi Kasagar <srinidhi.kasagar@intel.com>
I need an ACK from Len to apply this one.
Thanks,
Rafael
> ---
> drivers/idle/intel_idle.c | 76 +++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 76 insertions(+)
>
> diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c
> index 3a3738fe016b..beb950838cda 100644
> --- a/drivers/idle/intel_idle.c
> +++ b/drivers/idle/intel_idle.c
> @@ -522,6 +522,76 @@ static struct cpuidle_state hsw_cstates[] = {
> {
> .enter = NULL }
> };
> +
> +static struct cpuidle_state bxt_cstates[] = {
> + {
> + .name = "C1-BXT",
> + .desc = "MWAIT 0x00",
> + .flags = MWAIT2flg(0x00),
> + .exit_latency = 2,
> + .target_residency = 2,
> + .enter = &intel_idle,
> + .enter_freeze = intel_idle_freeze, },
> + {
> + .name = "C1E-BXT",
> + .desc = "MWAIT 0x01",
> + .flags = MWAIT2flg(0x01),
> + .exit_latency = 10,
> + .target_residency = 20,
> + .enter = &intel_idle,
> + .enter_freeze = intel_idle_freeze, },
> + {
> + .name = "C3-BXT",
> + .desc = "MWAIT 0x10",
> + .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
> + .exit_latency = 33,
> + .target_residency = 100,
> + .enter = &intel_idle,
> + .enter_freeze = intel_idle_freeze, },
> + {
> + .name = "C6-BXT",
> + .desc = "MWAIT 0x20",
> + .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
> + .exit_latency = 133,
> + .target_residency = 400,
> + .enter = &intel_idle,
> + .enter_freeze = intel_idle_freeze, },
> + {
> + .name = "C7s-BXT",
> + .desc = "MWAIT 0x32",
> + .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
> + .exit_latency = 166,
> + .target_residency = 500,
> + .enter = &intel_idle,
> + .enter_freeze = intel_idle_freeze, },
> + {
> + .name = "C8-BXT",
> + .desc = "MWAIT 0x40",
> + .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
> + .exit_latency = 300,
> + .target_residency = 900,
> + .enter = &intel_idle,
> + .enter_freeze = intel_idle_freeze, },
> + {
> + .name = "C9-BXT",
> + .desc = "MWAIT 0x50",
> + .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
> + .exit_latency = 600,
> + .target_residency = 1800,
> + .enter = &intel_idle,
> + .enter_freeze = intel_idle_freeze, },
> + {
> + .name = "C10-BXT",
> + .desc = "MWAIT 0x60",
> + .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
> + .exit_latency = 2600,
> + .target_residency = 7700,
> + .enter = &intel_idle,
> + .enter_freeze = intel_idle_freeze, },
> + {
> + .enter = NULL }
> +};
> +
> static struct cpuidle_state bdw_cstates[] = {
> {
> .name = "C1-BDW",
> @@ -882,6 +952,11 @@ static const struct idle_cpu idle_cpu_avn = {
> .disable_promotion_to_c1e = true,
> };
>
> +static const struct idle_cpu idle_cpu_bxt = {
> + .state_table = bxt_cstates,
> + .disable_promotion_to_c1e = true,
> +};
> +
> #define ICPU(model, cpu) \
> { X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (unsigned long)&cpu }
>
> @@ -911,6 +986,7 @@ static const struct x86_cpu_id intel_idle_ids[] __initconst = {
> ICPU(0x47, idle_cpu_bdw),
> ICPU(0x4f, idle_cpu_bdw),
> ICPU(0x56, idle_cpu_bdw),
> + ICPU(0x5c, idle_cpu_bxt),
> ICPU(0x4e, idle_cpu_skl),
> ICPU(0x5e, idle_cpu_skl),
> {}
>
--
I speak only for myself.
Rafael J. Wysocki, Intel Open Source Technology Center.
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH] intel_idle: Add support for Goldmont core in the Broxton Socs
2015-11-07 1:08 ` Rafael J. Wysocki
@ 2015-11-17 12:28 ` Kasagar, Srinidhi
0 siblings, 0 replies; 3+ messages in thread
From: Kasagar, Srinidhi @ 2015-11-17 12:28 UTC (permalink / raw)
To: Rafael J. Wysocki; +Cc: lenb, len.brown, linux-pm
On Sat, Nov 07, 2015 at 02:08:19AM +0100, Rafael J. Wysocki wrote:
> On Thursday, November 05, 2015 10:13:37 PM Srinidhi Kasagar wrote:
> > Broxton SoC uses similar Haswell like C states. Add a dedicated
> > table for this Soc.
> >
> > Signed-off-by: Srinidhi Kasagar <srinidhi.kasagar@intel.com>
>
> I need an ACK from Len to apply this one.
Len, did you get a time to look at this?
Srinidhi
>
> Thanks,
> Rafael
>
>
> > ---
> > drivers/idle/intel_idle.c | 76 +++++++++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 76 insertions(+)
> >
> > diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c
> > index 3a3738fe016b..beb950838cda 100644
> > --- a/drivers/idle/intel_idle.c
> > +++ b/drivers/idle/intel_idle.c
> > @@ -522,6 +522,76 @@ static struct cpuidle_state hsw_cstates[] = {
> > {
> > .enter = NULL }
> > };
> > +
> > +static struct cpuidle_state bxt_cstates[] = {
> > + {
> > + .name = "C1-BXT",
> > + .desc = "MWAIT 0x00",
> > + .flags = MWAIT2flg(0x00),
> > + .exit_latency = 2,
> > + .target_residency = 2,
> > + .enter = &intel_idle,
> > + .enter_freeze = intel_idle_freeze, },
> > + {
> > + .name = "C1E-BXT",
> > + .desc = "MWAIT 0x01",
> > + .flags = MWAIT2flg(0x01),
> > + .exit_latency = 10,
> > + .target_residency = 20,
> > + .enter = &intel_idle,
> > + .enter_freeze = intel_idle_freeze, },
> > + {
> > + .name = "C3-BXT",
> > + .desc = "MWAIT 0x10",
> > + .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
> > + .exit_latency = 33,
> > + .target_residency = 100,
> > + .enter = &intel_idle,
> > + .enter_freeze = intel_idle_freeze, },
> > + {
> > + .name = "C6-BXT",
> > + .desc = "MWAIT 0x20",
> > + .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
> > + .exit_latency = 133,
> > + .target_residency = 400,
> > + .enter = &intel_idle,
> > + .enter_freeze = intel_idle_freeze, },
> > + {
> > + .name = "C7s-BXT",
> > + .desc = "MWAIT 0x32",
> > + .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
> > + .exit_latency = 166,
> > + .target_residency = 500,
> > + .enter = &intel_idle,
> > + .enter_freeze = intel_idle_freeze, },
> > + {
> > + .name = "C8-BXT",
> > + .desc = "MWAIT 0x40",
> > + .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
> > + .exit_latency = 300,
> > + .target_residency = 900,
> > + .enter = &intel_idle,
> > + .enter_freeze = intel_idle_freeze, },
> > + {
> > + .name = "C9-BXT",
> > + .desc = "MWAIT 0x50",
> > + .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
> > + .exit_latency = 600,
> > + .target_residency = 1800,
> > + .enter = &intel_idle,
> > + .enter_freeze = intel_idle_freeze, },
> > + {
> > + .name = "C10-BXT",
> > + .desc = "MWAIT 0x60",
> > + .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
> > + .exit_latency = 2600,
> > + .target_residency = 7700,
> > + .enter = &intel_idle,
> > + .enter_freeze = intel_idle_freeze, },
> > + {
> > + .enter = NULL }
> > +};
> > +
> > static struct cpuidle_state bdw_cstates[] = {
> > {
> > .name = "C1-BDW",
> > @@ -882,6 +952,11 @@ static const struct idle_cpu idle_cpu_avn = {
> > .disable_promotion_to_c1e = true,
> > };
> >
> > +static const struct idle_cpu idle_cpu_bxt = {
> > + .state_table = bxt_cstates,
> > + .disable_promotion_to_c1e = true,
> > +};
> > +
> > #define ICPU(model, cpu) \
> > { X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (unsigned long)&cpu }
> >
> > @@ -911,6 +986,7 @@ static const struct x86_cpu_id intel_idle_ids[] __initconst = {
> > ICPU(0x47, idle_cpu_bdw),
> > ICPU(0x4f, idle_cpu_bdw),
> > ICPU(0x56, idle_cpu_bdw),
> > + ICPU(0x5c, idle_cpu_bxt),
> > ICPU(0x4e, idle_cpu_skl),
> > ICPU(0x5e, idle_cpu_skl),
> > {}
> >
>
> --
> I speak only for myself.
> Rafael J. Wysocki, Intel Open Source Technology Center.
--
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2015-11-17 4:35 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2015-11-05 16:43 [PATCH] intel_idle: Add support for Goldmont core in the Broxton Socs Srinidhi Kasagar
2015-11-07 1:08 ` Rafael J. Wysocki
2015-11-17 12:28 ` Kasagar, Srinidhi
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).