From mboxrd@z Thu Jan  1 00:00:00 1970
From: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Subject: Re: [PATCH v2 10/11] PM / Hibernate: clean cached pages on
 architectures that require it
Date: Tue, 17 Nov 2015 12:38:07 +0000
Message-ID: <20151117123807.GA22216@red-moon>
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To: "Rafael J. Wysocki" <rjw@rjwysocki.net>
Cc: James Morse <james.morse@arm.com>, Pavel Machek <pavel@ucw.cz>, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, Will Deacon <will.deacon@arm.com>, Sudeep Holla <sudeep.holla@arm.com>, Kevin Kang <kkang@intrinsyc.com>, Geoff Levand <geoff@infradead.org>, Catalin Marinas <catalin.marinas@arm.com>, Mark Rutland <mark.rutland@arm.com>, AKASHI Takahiro <takahiro.akashi@linaro.org>, wangfei <w.f@huawei.com>, Marc Zyngier <marc.zyngier@arm.com>, Russell King <linux@arm.linux.org.uk>, "David S. Miller" <davem@davemloft.net>, Benjamin Herrenschmidt <benh@kernel.crashing.org>, Guan Xuetao <gxt@mprc.pku.edu.cn>, Ralf Baechle <ralf@linux-mips.org>, Heiko Carstens <heiko.carstens@de.ibm.com>

[Cc'ed maintainers of affected arches]

On Sat, Nov 14, 2015 at 12:38:50AM +0100, Rafael J. Wysocki wrote:
> On Thursday, November 12, 2015 11:47:05 AM Lorenzo Pieralisi wrote:
> > On Thu, Nov 12, 2015 at 01:48:32AM +0100, Rafael J. Wysocki wrote:
> > > On Wednesday, November 11, 2015 11:40:39 AM Lorenzo Pieralisi wrote:
> > > > Hi Pavel, Rafael,
> > > > 
> > > > Do you have any feedback on this patch ?
> > > > 
> > > > It is fundamental to this series and affects Hibernate core code so if you
> > > > have any feedback that would be much appreciated.
> > > 
> > > I'm really not familiar with the flush_icache_range() interface.
> > > 
> > > What exactly does it do?
> > 
> > It is used to sync a memory range that is written into (eg loading
> > modules, copying from snapshot is basically the same thing, reads from
> > storage and restore pages that might well be executable code), in particular
> > to sync the I-cache and the D-cache, eg on arm64 the page that the snapshot
> > code is copying might be executable code that has to be cleaned from the
> > D-cache so that it is made visible to the I-cache.
> > 
> > On x86 it is a NOP AFAIK.
> 
> If that's the case, I have no problems with this change as long as the code
> works on architectures with non-trivial flush_icache_range().

I Cc'ed the respective arches maintainers, it should work (it may
make resuming a bit slower, owing to the cache syncing), problem is
that we have no way of testing it on platforms other than arm/arm64.

How do you want us to go on about this ? Should we add a config option
to prevent calling flush_icache_range() on all platforms (where it
is not a nop) ?

Thanks a lot !
Lorenzo