From: Pavel Machek <pavel@ucw.cz>
To: dbasehore@chromium.org
Cc: linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org,
rjw@rjwysocki.net, len.brown@intel.com, tglx@linutronix.de
Subject: Re: [PATCH 0/5] Add suspend-to-idle validation for Intel SoCs
Date: Tue, 7 Jun 2016 09:46:33 +0200 [thread overview]
Message-ID: <20160607074632.GA13858@amd> (raw)
In-Reply-To: <1464842009-21789-1-git-send-email-dbasehore@chromium.org>
On Wed 2016-06-01 21:33:24, dbasehore@chromium.org wrote:
> From: Derek Basehore <dbasehore@chromium.org>
>
> This patch set adds support for catching errors when entering freeze
> on Intel Skylake SoCs. Support for this can be added to newer SoCs in
> later patches.
>
> Verification is done by waking up the CPU once every X (default 10)
> seconds to check the residency of S0ix. This can't be verified before
> attempting to enter S0ix through mwait, so we have to repeatedly
> verify entry into that state. Successfully entering S0ix is no
> guarantee that it will be entered on the next attempt, so we have to
> schedule another check. This has a minimal power impact of <1% of the
> total system power on our systems.
Dunno. Should this be protected with something like CONFIG_TEST_SLEEP?
People probably don't want this for production...
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
next prev parent reply other threads:[~2016-06-07 7:46 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-02 4:33 [PATCH 0/5] Add suspend-to-idle validation for Intel SoCs dbasehore
2016-06-02 4:33 ` [PATCH 1/5] x86: stub out pmc function dbasehore
2016-06-02 4:33 ` [PATCH 2/5] clockevents: Add timed freeze dbasehore
2016-06-02 4:33 ` [PATCH 3/5] x86, apic: Add timed freeze support dbasehore
2016-06-02 4:33 ` [PATCH 4/5] freeze: Add error reporting dbasehore
2016-06-02 4:33 ` [PATCH 5/5] intel_idle: Add S0ix validation dbasehore
2016-06-02 9:25 ` Peter Zijlstra
2016-06-02 13:23 ` One Thousand Gnomes
2016-06-02 18:31 ` dbasehore .
2016-06-02 18:55 ` dbasehore .
2016-06-02 19:53 ` One Thousand Gnomes
2016-06-02 20:35 ` dbasehore .
2016-06-04 12:22 ` Alan
2016-06-06 21:39 ` dbasehore .
2016-06-07 7:46 ` Pavel Machek [this message]
2016-06-08 0:07 ` [PATCH 0/5] Add suspend-to-idle validation for Intel SoCs dbasehore .
2016-06-11 20:31 ` Pavel Machek
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20160607074632.GA13858@amd \
--to=pavel@ucw.cz \
--cc=dbasehore@chromium.org \
--cc=len.brown@intel.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pm@vger.kernel.org \
--cc=rjw@rjwysocki.net \
--cc=tglx@linutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).