Re: [PATCH v3 1/3] powernv:idle: Add IDLE_STATE_ENTER_SEQ_NORET macro

[Gautham R Shenoy <ego@linux.vnet.ibm.com>]

Hi Balbir,

On Tue, Nov 29, 2016 at 09:42:20PM +1100, Balbir Singh wrote:
> 
> 
> On 10/11/16 18:54, Gautham R. Shenoy wrote:
> > From: "Gautham R. Shenoy" <ego@linux.vnet.ibm.com>
> > 
> > Currently all the low-power idle states are expected to wake up
> > at reset vector 0x100. Which is why the macro IDLE_STATE_ENTER_SEQ
> > that puts the CPU to an idle state and never returns.
> > 
> > On ISA_300, when the ESL and EC bits in the PSSCR are zero, the
> > CPU is expected to wake up at the next instruction of the idle
> > instruction.
> > 
> > This patch adds a new macro named IDLE_STATE_ENTER_SEQ_NORET for the
> 
> I think something like IDLE_STATE_ENTER_SEQ_LOSE_CTX would be better?

As you pointed out below, the macro encapsulates the magic sequence
that needs to be executed to go to a particular idle-state.

The behaviour changes based on ESL=EC=1 (or nap,fastsleep,winkle on
POWER8) in which case wake up is at 0x100. When ESL=EC=0, the wakeup
happens at the subsequent instruction.

So, more than whether the context is lost or not, the intent is to
indicate whether the wakeup happens at the next instruction or at
0x100.

> 
> > no-return variant and reuses the name IDLE_STATE_ENTER_SEQ
> > for a variant that allows resuming operation at the instruction next
> > to the idle-instruction.
> > 
> <snip>
> > +
> > +#define	IDLE_STATE_ENTER_SEQ_NORET(IDLE_INST)			\
> > +	IDLE_STATE_ENTER_SEQ(IDLE_INST)                         \
> 
> So we start off with both as the same?
> 
> >  	b	.
> >  #endif /* CONFIG_PPC_P7_NAP */
> <snip>
> Balbir
> 
--
Thanks and Regards
gautham.