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From: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
To: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
Cc: linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	Quentin Schulz
	<quentin.schulz-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>,
	Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>,
	linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Subject: Re: [PATCH 4/5] ARM: sun8i: h3: add operating-points-v2 table for CPU
Date: Mon, 17 Apr 2017 09:46:19 +0200	[thread overview]
Message-ID: <20170417074619.ilxkrdavmcoeno2v@lukather> (raw)
In-Reply-To: <40F4D1F2-EA59-4BD1-9A00-4C0AA7FED9D3-h8G6r0blFSE@public.gmane.org>

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On Mon, Apr 17, 2017 at 05:00:00AM +0800, Icenowy Zheng wrote:
> 
> 
> 于 2017年4月17日 GMT+08:00 上午4:57:40, Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> 写到:
> >On Tue, Apr 11, 2017 at 09:28:55PM +0800, icenowy-h8G6r0blFSE@public.gmane.org wrote:
> >> 在 2017-04-11 17:13,Maxime Ripard 写道:
> >> > On Sun, Apr 09, 2017 at 02:50:24AM +0800, Icenowy Zheng wrote:
> >> > > The CPU on Allwinner H3 can do dynamic frequency scaling.
> >> > > 
> >> > > Add a DVFS table based on the one tweaked by Armbian developers,
> >which
> >> > > are proven to work stably on BSP kernels.
> >> > > 
> >> > > Frequencies higher than 1008MHz are temporarily dropped in the
> >> > > table, as
> >> > > they may lead to over voltage on boards without proper regulator
> >> > > settings or over temperature on boards with proper regulator
> >settings.
> >> > > They will be added back once regulator settings are ready and
> >thermal
> >> > > sensor driver is merged.
> >> > > 
> >> > > In order to satisfy all different regulators (SY8106A which is
> >50mV
> >> > > per
> >> > > level, SY8113B which have two states: 1.1V and 1.3V, and some
> >board
> >> > > with
> >> > > non-tweakable regulators), all the OPPs are defined with a range
> >> > > which has
> >> > > the target value as the minimum allowed value, and 1.3V (the
> >highest
> >> > > VDD-CPUX voltage suggested by the datasheet) as the maximum
> >allowed
> >> > > value.
> >> > > It's proven to work well with a board with SY8113B.
> >> > > 
> >> > > Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
> >> > > ---
> >> > >  arch/arm/boot/dts/sun8i-h3.dtsi | 38
> >> > > +++++++++++++++++++++++++++++++++++++-
> >> > >  1 file changed, 37 insertions(+), 1 deletion(-)
> >> > > 
> >> > > diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi
> >> > > b/arch/arm/boot/dts/sun8i-h3.dtsi
> >> > > index b36f9f423c39..a0cee17fe44b 100644
> >> > > --- a/arch/arm/boot/dts/sun8i-h3.dtsi
> >> > > +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
> >> > > @@ -43,32 +43,68 @@
> >> > >  #include "sunxi-h3-h5.dtsi"
> >> > > 
> >> > >  / {
> >> > > +	cpu0_opp_table: opp_table0 {
> >> > > +		compatible = "operating-points-v2";
> >> > > +		opp-shared;
> >> > > +
> >> > > +		opp@480000000 {
> >> > > +			opp-hz = /bits/ 64 <480000000>;
> >> > > +			opp-microvolt = <980000 980000 1300000>;
> >> > > +			clock-latency-ns = <244144>; /* 8 32k periods */
> >> > > +		};
> >> > > +
> >> > > +		opp@648000000 {
> >> > > +			opp-hz = /bits/ 64 <816000000>;
> >> > > +			opp-microvolt = <1020000 1020000 1300000>;
> >> > > +			clock-latency-ns = <244144>; /* 8 32k periods */
> >> > > +		};
> >> > > +
> >> > > +		opp@912000000 {
> >> > > +			opp-hz = /bits/ 64 <960000000>;
> >> > > +			opp-microvolt = <1080000 1080000 1300000>;
> >> > > +			clock-latency-ns = <244144>; /* 8 32k periods */
> >> > > +		};
> >> > > +
> >> > > +		opp@1008000000 {
> >> > > +			opp-hz = /bits/ 64 <1008000000>;
> >> > > +			opp-microvolt = <1140000 1140000 1300000>;
> >> > > +			clock-latency-ns = <244144>; /* 8 32k periods */
> >> > > +		};
> >> > > +	};
> >> > > +
> >> > 
> >> > From your serie, I guess you never actually tested those OPPs on
> >any
> >> > board without SY8113B, right?
> >> 
> >> Yes. But I will test them on an Orange Pi PC (newly got) soon.
> >
> >The orange pi pc also uses the SY8113B.
> 
> I remember in H3 Orange Pi's only One, Lite and Zero uses SY8113B,
> and PC is SY8106A.

Ah, my bad, I confused the two.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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  parent reply	other threads:[~2017-04-17  7:46 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-04-08 18:50 [PATCH 0/5] Some Allwinner CCU tweaks and basical DVFS support for H3/H2+ Icenowy Zheng
2017-04-08 18:50 ` [PATCH 1/5] clk: sunxi-ng: prevent NKMP clocks from temporarily get higher freq Icenowy Zheng
     [not found]   ` <20170408185025.53841-2-icenowy-h8G6r0blFSE@public.gmane.org>
2017-04-08 21:59     ` 'Ondřej Jirman' via linux-sunxi
2017-04-08 18:50 ` [PATCH 2/5] clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3 Icenowy Zheng
     [not found]   ` <20170408185025.53841-3-icenowy-h8G6r0blFSE@public.gmane.org>
2017-04-09  1:05     ` Chen-Yu Tsai
2017-04-08 18:50 ` [PATCH 3/5] cpufreq: dt: Add support for some new Allwinner SoCs Icenowy Zheng
2017-04-11  7:03   ` Viresh Kumar
     [not found] ` <20170408185025.53841-1-icenowy-h8G6r0blFSE@public.gmane.org>
2017-04-08 18:50   ` [PATCH 4/5] ARM: sun8i: h3: add operating-points-v2 table for CPU Icenowy Zheng
     [not found]     ` <20170408185025.53841-5-icenowy-h8G6r0blFSE@public.gmane.org>
2017-04-11  9:13       ` Maxime Ripard
2017-04-11 13:28         ` icenowy
     [not found]           ` <b37490ed1282f45542168701dea332bb-h8G6r0blFSE@public.gmane.org>
2017-04-16 20:57             ` Maxime Ripard
2017-04-16 21:00               ` Icenowy Zheng
     [not found]                 ` <40F4D1F2-EA59-4BD1-9A00-4C0AA7FED9D3-h8G6r0blFSE@public.gmane.org>
2017-04-17  7:46                   ` Maxime Ripard [this message]
2017-04-16 21:06               ` icenowy-h8G6r0blFSE
2017-04-08 18:50   ` [PATCH 5/5] ARM: sun8i: h2+: add SY8113B regulator used by Orange Pi Zero board Icenowy Zheng

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