From: Johannes Stezenbach <js@sig21.net>
To: Hans de Goede <hdegoede@redhat.com>
Cc: Michael Turquette <mturquette@baylibre.com>,
"Rafael J. Wysocki" <rjw@rjwysocki.net>,
Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
Mika Westerberg <mika.westerberg@linux.intel.com>,
Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>,
linux-clk <linux-clk@vger.kernel.org>,
Linux PM list <linux-pm@vger.kernel.org>,
Carlo Caione <carlo@endlessm.com>,
Darren Hart <dvhart@infradead.org>,
Enric Balletbo i Serra <enric.balletbo@collabora.com>,
Takashi Iwai <tiwai@suse.de>,
ACPI Devel Maling List <linux-acpi@vger.kernel.org>
Subject: Re: [RFC PATCH 1/2] platform/x86: add Atom PMC quirk to disable SATA
Date: Wed, 13 Dec 2017 17:22:06 +0100 [thread overview]
Message-ID: <20171213162206.GA7337@sig21.net> (raw)
In-Reply-To: <e4760a03-b6af-00fc-6c26-9fff8ed6c378@redhat.com>
Hi,
On Wed, Dec 13, 2017 at 05:04:34PM +0100, Hans de Goede wrote:
> On 13-12-17 16:25, Michael Turquette wrote:
> > On Wed, Dec 13, 2017 at 12:53 AM, Hans de Goede <hdegoede@redhat.com> wrote:
> > > Although, maybe we need to have a specialized (derived)
> > > ahci driver for these Atom SoCs and in there if no
> > > disk is detected do this through the clock framework?
> >
> > Yes please. x86 is already modeling some clocks properly through the
> > clock framework. During late init we clean up any clocks that were
> > enabled out of reset or by the firmware/bootloader but not claimed and
> > enabled by any Linux driver. That should ideally disable this
> > particular clock for the case when no SATA drive is present, and
> > require no quirk logic in the driver.
>
> Ah so you're thinking a special ahci driver which knows about
> the clock, yes I think that could work.
>
> Or maybe do a match on the CPU model and if it is know to
> not have SATA (or not routed to the outside), disable
> the clock? That seems better because if I understood Johannes
> correctly there is no SATA/AHCI PCI device (so nothing for
> a driver to bind to) but the clock is still enabled, although
> in that case the clock framework should do the right thing
> if we revert commit d31fd43c0f9a "clk: x86: Do not gate clocks enabled by the firmware"
Please don't get confused with the other thread about clocks.
This issue sets the "disable IP" bit, found by doing stupid
experiments to enable S0ix on E200HA.
1. no idea if Cherry Trail even has SATA IP, maybe this is a
meaningless bit but PMC firmware carried over from
Bay Trail looks at it
2. BIOS should have set the bit, so it is a BIOS quirk
3. or maybe there is a much better solution that I don't know about
https://bugzilla.kernel.org/show_bug.cgi?id=193891
also has lspci output
Thanks,
Johannes
next prev parent reply other threads:[~2017-12-13 16:22 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-06 20:42 S0ix failure due to "clk: x86: Do not gate clocks enabled by the firmware" Johannes Stezenbach
2017-09-06 21:02 ` Pierre-Louis Bossart
2017-09-08 13:49 ` Johannes Stezenbach
2017-09-21 9:40 ` Johannes Stezenbach
2017-09-21 14:21 ` Rafael J. Wysocki
2017-09-21 16:23 ` Johannes Stezenbach
2017-09-21 22:20 ` Rafael J. Wysocki
2017-09-21 22:24 ` Rafael J. Wysocki
2017-09-21 22:35 ` Rafael J. Wysocki
2017-09-22 8:04 ` Johannes Stezenbach
2017-09-22 12:27 ` Takashi Iwai
2017-09-22 21:04 ` Johannes Stezenbach
2017-09-22 22:12 ` Rafael J. Wysocki
2017-09-22 22:09 ` Rafael J. Wysocki
2017-09-25 19:17 ` Johannes Stezenbach
2017-09-25 19:21 ` [RFC PATCH 1/2] platform/x86: add Atom PMC quirk to disable SATA Johannes Stezenbach
2017-12-13 0:00 ` Rafael J. Wysocki
2017-12-13 8:53 ` Hans de Goede
2017-12-13 11:13 ` Johannes Stezenbach
2017-12-13 15:25 ` Michael Turquette
2017-12-13 16:04 ` Hans de Goede
2017-12-13 16:22 ` Johannes Stezenbach [this message]
2017-12-13 16:37 ` Hans de Goede
2017-12-13 19:33 ` Andy Shevchenko
2017-12-14 10:53 ` Hans de Goede
2017-09-25 19:23 ` [RFC PATCH 2/2] clk: x86: Disable unused clocks to fix S0ix Johannes Stezenbach
2017-12-13 0:01 ` Rafael J. Wysocki
2017-12-13 8:56 ` Hans de Goede
2017-12-13 10:20 ` Carlo Caione
2017-12-13 11:22 ` Johannes Stezenbach
2017-12-13 14:25 ` Pierre-Louis Bossart
2017-12-13 14:29 ` Andy Shevchenko
2017-09-06 21:14 ` S0ix failure due to "clk: x86: Do not gate clocks enabled by the firmware" Carlo Caione
2017-09-18 8:00 ` Andy Shevchenko
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