From: Miquel RAYNAL <miquel.raynal-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
To: Baruch Siach <baruch-NswTu9S1W3P6gbPvEgmw2w@public.gmane.org>
Cc: Zhang Rui <rui.zhang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>,
Eduardo Valentin
<edubezval-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>,
Jason Cooper <jason-NLaQJdtUoK4Be96aLqz0jA@public.gmane.org>,
Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org>,
Gregory Clement
<gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>,
Sebastian Hesselbarth
<sebastian.hesselbarth-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
Catalin Marinas <catalin.marinas-5wv7dgnIgG8@public.gmane.org>,
Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>,
linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
Thomas Petazzoni
<thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>,
Antoine Tenart
<antoine.tenart-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>,
Nadav Haklai <nadavh-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>,
David Sniatkiwicz
<davidsn-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>
Subject: Re: [PATCH v4 04/12] thermal: armada: Clarify control registers accesses
Date: Tue, 19 Dec 2017 01:32:33 +0100 [thread overview]
Message-ID: <20171219013233.319365c4@xps13> (raw)
In-Reply-To: <20171218203542.msnswjqeyuudyusz@tarshish>
Hello Baruch,
On Mon, 18 Dec 2017 22:35:42 +0200
Baruch Siach <baruch-NswTu9S1W3P6gbPvEgmw2w@public.gmane.org> wrote:
> Hi Miquèl,
>
> On Mon, Dec 18, 2017 at 03:36:35PM +0100, Miquel Raynal wrote:
> > Bindings were incomplete for a long time by only exposing one of
> > the two available control registers. To ease the migration to the
> > full bindings (already in use for the Armada 375 SoC), rename the
> > pointers for clarification. This way, it will only be needed to add
> > another pointer to access the other control register when the time
> > comes.
> >
> > This avoids dangerous situations where the offset 0 of the control
> > area can be either one register or the other depending on the
> > bindings used. After this change, device trees of other SoCs could
> > be migrated to the "full" bindings if they may benefit from
> > features from the unaccessible register, without any change in the
> > driver.
> >
> > Signed-off-by: Miquel Raynal <miquel.raynal-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> > Reviewed-by: Gregory CLEMENT <gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> > ---
>
> [...]
>
> > + /*
> > + * Legacy DT bindings only described "control1" register
> > (also referred
> > + * as "control MSB" on old documentation). New bindings
> > cover
> > + * "control0/control LSB" and "control1/control MSB"
> > registers within
> > + * the same resource, which is then of size 8 instead of 4.
> > + */
> > + if (resource_size(res) == LEGACY_CONTROL_MEM_LEN) {
> > + /* ->control0 unavailable in this configuration */
> > + priv->control1 = control + LEGACY_CONTROL1_OFFSET;
> > + } else {
> > + priv->control0 = control + CONTROL0_OFFSET;
> > + priv->control1 = control + CONTROL1_OFFSET;
> > + }
>
> The needs_control0 field that you mentioned in the cover page is
> missing here.
Yes, at this point nobody actually *needs* control0 so the limitation
is added with the patch that introduce ap806 support as it is the first
compatible that needs both control0 and control1 to work correctly.
Does this bother you?
Thanks,
Miquèl
>
> baruch
>
--
Miquel Raynal, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
next prev parent reply other threads:[~2017-12-19 0:32 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-12-18 14:36 [PATCH v4 00/12] Armada thermal: improvements and A7K/A8K SoCs support Miquel Raynal
2017-12-18 14:36 ` [PATCH v4 01/12] dt-bindings: thermal: Describe Armada AP806 and CP110 Miquel Raynal
[not found] ` <20171218143643.7714-2-miquel.raynal-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2017-12-18 20:33 ` Baruch Siach
2017-12-19 0:43 ` Miquel RAYNAL
2017-12-19 6:09 ` Baruch Siach
[not found] ` <20171219060918.nr4ojwpmqf6ju6od-MwjkAAnuF3khR1HGirfZ1z4kX+cae0hd@public.gmane.org>
2017-12-19 7:44 ` Miquel RAYNAL
2017-12-18 14:36 ` [PATCH v4 02/12] thermal: armada: Use msleep for long delays Miquel Raynal
2017-12-18 14:36 ` [PATCH v4 04/12] thermal: armada: Clarify control registers accesses Miquel Raynal
[not found] ` <20171218143643.7714-5-miquel.raynal-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2017-12-18 20:35 ` Baruch Siach
2017-12-19 0:32 ` Miquel RAYNAL [this message]
2017-12-19 5:51 ` Baruch Siach
[not found] ` <20171219055154.f23leaob3zndmmqo-MwjkAAnuF3khR1HGirfZ1z4kX+cae0hd@public.gmane.org>
2017-12-19 8:08 ` Miquel RAYNAL
2017-12-19 8:19 ` Baruch Siach
2017-12-19 8:23 ` Miquel RAYNAL
[not found] ` <20171218143643.7714-1-miquel.raynal-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2017-12-18 14:36 ` [PATCH v4 03/12] thermal: armada: Simplify the check of the validity bit Miquel Raynal
2017-12-18 14:36 ` [PATCH v4 05/12] thermal: armada: Use real status register name Miquel Raynal
[not found] ` <20171218143643.7714-6-miquel.raynal-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2017-12-18 15:58 ` Gregory CLEMENT
2017-12-18 14:36 ` [PATCH v4 06/12] thermal: armada: Add support for Armada AP806 Miquel Raynal
[not found] ` <20171218143643.7714-7-miquel.raynal-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2017-12-18 16:05 ` Gregory CLEMENT
[not found] ` <87y3m0hvik.fsf-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2017-12-19 0:27 ` Miquel RAYNAL
2017-12-18 14:36 ` [PATCH v4 07/12] thermal: armada: Add support for Armada CP110 Miquel Raynal
[not found] ` <20171218143643.7714-8-miquel.raynal-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2017-12-18 16:07 ` Gregory CLEMENT
2017-12-18 14:36 ` [PATCH v4 08/12] thermal: armada: Update Kconfig and module description Miquel Raynal
[not found] ` <20171218143643.7714-9-miquel.raynal-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2017-12-18 16:07 ` Gregory CLEMENT
2017-12-18 14:36 ` [PATCH v4 10/12] thermal: armada: Wait sensors validity before exiting the init callback Miquel Raynal
2017-12-18 16:12 ` Gregory CLEMENT
2017-12-18 14:36 ` [PATCH v4 11/12] thermal: armada: Give meaningful names to the thermal zones Miquel Raynal
2017-12-18 16:12 ` Gregory CLEMENT
2017-12-18 14:36 ` [PATCH v4 12/12] ARM64: dts: marvell: Add thermal support for A7K/A8K Miquel Raynal
2017-12-18 16:13 ` Gregory CLEMENT
2017-12-18 14:36 ` [PATCH v4 09/12] thermal: armada: Change sensors trim default value Miquel Raynal
[not found] ` <20171218143643.7714-10-miquel.raynal-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
2017-12-18 16:08 ` Gregory CLEMENT
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20171219013233.319365c4@xps13 \
--to=miquel.raynal-wi1+55scjutkeb57/3fjtnbpr1lh4cv8@public.gmane.org \
--cc=andrew-g2DYL2Zd6BY@public.gmane.org \
--cc=antoine.tenart-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org \
--cc=baruch-NswTu9S1W3P6gbPvEgmw2w@public.gmane.org \
--cc=catalin.marinas-5wv7dgnIgG8@public.gmane.org \
--cc=davidsn-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org \
--cc=devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org \
--cc=edubezval-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org \
--cc=gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org \
--cc=jason-NLaQJdtUoK4Be96aLqz0jA@public.gmane.org \
--cc=linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org \
--cc=linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org \
--cc=mark.rutland-5wv7dgnIgG8@public.gmane.org \
--cc=nadavh-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org \
--cc=robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org \
--cc=rui.zhang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org \
--cc=sebastian.hesselbarth-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org \
--cc=thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org \
--cc=will.deacon-5wv7dgnIgG8@public.gmane.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).