From: Alan Cox <gnomes@lxorguk.ukuu.org.uk>
To: TimGuo <timguo@zhaoxin.com>
Cc: tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com,
mingo@kernel.org, x86@kernel.org, linux-pm@vger.kernel.org,
linux-kernel@vger.kernel.org, brucechang@via-alliance.com,
cooperyan@zhaoxin.com, qiyuanwang@zhaoxin.com,
benjaminpan@viatech.com
Subject: Re: [PATCH] x86/centaur: Mark TSC invariant
Date: Wed, 24 Jan 2018 18:26:42 +0000 [thread overview]
Message-ID: <20180124182642.0669c9bd@alans-desktop> (raw)
In-Reply-To: <1515980145-3693-1-git-send-email-timguo@zhaoxin.com>
On Mon, 15 Jan 2018 09:35:45 +0800
TimGuo <timguo@zhaoxin.com> wrote:
> Centaur CPU has a constant frequency TSC and that TSC does not stop in C-States.
> But because the flags are not set for that CPU, the TSC is treated as non constant
> frequency and assumed to stop in C-States, which makes it an unreliable and unusable
> clock source. Setting those flags tells the kernel that the TSC is usable, so it
> will select it over HPET. The effect of this is that reading time stamps (from kernel
> or userspace) will be faster and more efficient.
And this is true for all processors back to IDT WinChip ?
Alan
next prev parent reply other threads:[~2018-01-24 18:26 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-15 1:35 [PATCH] x86/centaur: Mark TSC invariant TimGuo
2018-01-15 9:49 ` Thomas Gleixner
2018-01-24 18:26 ` Alan Cox [this message]
-- strict thread matches above, loose matches on Subject: below --
2018-01-22 10:14 davidwang
2018-01-10 10:27 (unknown), TimGuo
2018-01-14 12:06 ` [PATCH] x86/centaur: Mark TSC invariant Thomas Gleixner
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