[PATCH V4 11/20] cpufreq: tegra124: do not handle the CPU rail

[PATCH V4 11/20] cpufreq: tegra124: do not handle the CPU rail

[Joseph Lo]

The Tegra124 cpufreq driver has no information to handle the Vdd-CPU
rail. So this driver shouldn't handle for the CPU clock switching from
DFLL to other PLL clocks. It was designed to work on DFLL clock only,
which handle the frequency/voltage scaling in the background.

This patch removes the driver dependency of the CPU rail, as well as not
allow it to be built as a module and remove the removal function. So it
can keep working on DFLL clock.

Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: linux-pm@vger.kernel.org
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
---
*V4:
 - no change
*V3:
 - add ack tags
*V2:
 - update the commit message since we change the driver not able to be
 built as a module and remove the removal function in V2
---
 drivers/cpufreq/Kconfig.arm        |  4 +--
 drivers/cpufreq/tegra124-cpufreq.c | 41 ++----------------------------
 2 files changed, 4 insertions(+), 41 deletions(-)

diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index 688f10227793..1a6778e81f90 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -272,8 +272,8 @@ config ARM_TEGRA20_CPUFREQ
 	  This adds the CPUFreq driver support for Tegra20 SOCs.
 
 config ARM_TEGRA124_CPUFREQ
-	tristate "Tegra124 CPUFreq support"
-	depends on ARCH_TEGRA && CPUFREQ_DT && REGULATOR
+	bool "Tegra124 CPUFreq support"
+	depends on ARCH_TEGRA && CPUFREQ_DT
 	default y
 	help
 	  This adds the CPUFreq driver support for Tegra124 SOCs.
diff --git a/drivers/cpufreq/tegra124-cpufreq.c b/drivers/cpufreq/tegra124-cpufreq.c
index 43530254201a..a1bfde0a7950 100644
--- a/drivers/cpufreq/tegra124-cpufreq.c
+++ b/drivers/cpufreq/tegra124-cpufreq.c
@@ -22,11 +22,9 @@
 #include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/pm_opp.h>
-#include <linux/regulator/consumer.h>
 #include <linux/types.h>
 
 struct tegra124_cpufreq_priv {
-	struct regulator *vdd_cpu_reg;
 	struct clk *cpu_clk;
 	struct clk *pllp_clk;
 	struct clk *pllx_clk;
@@ -60,14 +58,6 @@ static int tegra124_cpu_switch_to_dfll(struct tegra124_cpufreq_priv *priv)
 	return ret;
 }
 
-static void tegra124_cpu_switch_to_pllx(struct tegra124_cpufreq_priv *priv)
-{
-	clk_set_parent(priv->cpu_clk, priv->pllp_clk);
-	clk_disable_unprepare(priv->dfll_clk);
-	regulator_sync_voltage(priv->vdd_cpu_reg);
-	clk_set_parent(priv->cpu_clk, priv->pllx_clk);
-}
-
 static int tegra124_cpufreq_probe(struct platform_device *pdev)
 {
 	struct tegra124_cpufreq_priv *priv;
@@ -88,16 +78,10 @@ static int tegra124_cpufreq_probe(struct platform_device *pdev)
 	if (!np)
 		return -ENODEV;
 
-	priv->vdd_cpu_reg = regulator_get(cpu_dev, "vdd-cpu");
-	if (IS_ERR(priv->vdd_cpu_reg)) {
-		ret = PTR_ERR(priv->vdd_cpu_reg);
-		goto out_put_np;
-	}
-
 	priv->cpu_clk = of_clk_get_by_name(np, "cpu_g");
 	if (IS_ERR(priv->cpu_clk)) {
 		ret = PTR_ERR(priv->cpu_clk);
-		goto out_put_vdd_cpu_reg;
+		goto out_put_np;
 	}
 
 	priv->dfll_clk = of_clk_get_by_name(np, "dfll");
@@ -129,15 +113,13 @@ static int tegra124_cpufreq_probe(struct platform_device *pdev)
 		platform_device_register_full(&cpufreq_dt_devinfo);
 	if (IS_ERR(priv->cpufreq_dt_pdev)) {
 		ret = PTR_ERR(priv->cpufreq_dt_pdev);
-		goto out_switch_to_pllx;
+		goto out_put_pllp_clk;
 	}
 
 	platform_set_drvdata(pdev, priv);
 
 	return 0;
 
-out_switch_to_pllx:
-	tegra124_cpu_switch_to_pllx(priv);
 out_put_pllp_clk:
 	clk_put(priv->pllp_clk);
 out_put_pllx_clk:
@@ -146,34 +128,15 @@ static int tegra124_cpufreq_probe(struct platform_device *pdev)
 	clk_put(priv->dfll_clk);
 out_put_cpu_clk:
 	clk_put(priv->cpu_clk);
-out_put_vdd_cpu_reg:
-	regulator_put(priv->vdd_cpu_reg);
 out_put_np:
 	of_node_put(np);
 
 	return ret;
 }
 
-static int tegra124_cpufreq_remove(struct platform_device *pdev)
-{
-	struct tegra124_cpufreq_priv *priv = platform_get_drvdata(pdev);
-
-	platform_device_unregister(priv->cpufreq_dt_pdev);
-	tegra124_cpu_switch_to_pllx(priv);
-
-	clk_put(priv->pllp_clk);
-	clk_put(priv->pllx_clk);
-	clk_put(priv->dfll_clk);
-	clk_put(priv->cpu_clk);
-	regulator_put(priv->vdd_cpu_reg);
-
-	return 0;
-}
-
 static struct platform_driver tegra124_cpufreq_platdrv = {
 	.driver.name	= "cpufreq-tegra124",
 	.probe		= tegra124_cpufreq_probe,
-	.remove		= tegra124_cpufreq_remove,
 };
 
 static int __init tegra_cpufreq_init(void)
-- 
2.20.1

[PATCH V4 12/20] cpufreq: tegra124: extend to support Tegra210

[Joseph Lo]

Tegra210 uses the same methodology as Tegra124 for CPUFreq controlling
that based on DFLL clock. So extending this driver to support Tegra210.

Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: linux-pm@vger.kernel.org
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
---
*V4:
 - no change
*V3:
 - no change
*V2:
 - add two ack tags
---
 drivers/cpufreq/tegra124-cpufreq.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/cpufreq/tegra124-cpufreq.c b/drivers/cpufreq/tegra124-cpufreq.c
index a1bfde0a7950..ba3795e13ac6 100644
--- a/drivers/cpufreq/tegra124-cpufreq.c
+++ b/drivers/cpufreq/tegra124-cpufreq.c
@@ -144,7 +144,8 @@ static int __init tegra_cpufreq_init(void)
 	int ret;
 	struct platform_device *pdev;
 
-	if (!of_machine_is_compatible("nvidia,tegra124"))
+	if (!(of_machine_is_compatible("nvidia,tegra124") ||
+		of_machine_is_compatible("nvidia,tegra210")))
 		return -ENODEV;
 
 	/*
-- 
2.20.1

[PATCH V4 13/20] cpufreq: dt-platdev: add Tegra210 to blacklist

[Joseph Lo]

Tegra210 uses "tegra124-cpufreq" platform driver to register device data
for "cpufreq-dt" driver. So add it in the blacklist for
"cpufreq-dt-platdev" driver to drop that.

Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: linux-pm@vger.kernel.org
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
---
*V4:
 - no change
*V3:
 - add ack tags
*V2:
 - new added in V2
---
 drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index b1c5468dca16..47729a22c159 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -119,6 +119,7 @@ static const struct of_device_id blacklist[] __initconst = {
 	{ .compatible = "mediatek,mt8176", },
 
 	{ .compatible = "nvidia,tegra124", },
+	{ .compatible = "nvidia,tegra210", },
 
 	{ .compatible = "qcom,apq8096", },
 	{ .compatible = "qcom,msm8996", },
-- 
2.20.1

Re: [PATCH V4 00/20] Tegra210 DFLL support

[Thierry Reding]

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On Mon, Jan 28, 2019 at 09:43:00AM +0800, Joseph Lo wrote:
> On 1/25/19 9:46 PM, Thierry Reding wrote:
> > On Fri, Jan 04, 2019 at 11:06:42AM +0800, Joseph Lo wrote:
> > > This series introduces support for the DFLL as a CPU clock source
> > > on Tegra210. As Jetson TX1 uses a PWM controlled regulator IC which
> > > is driven directly by the DFLLs PWM output, we also introduce support
> > > for PWM regulators next to I2C controlled regulators. The DFLL output
> > > frequency is directly controlled by the regulator voltage. The registers
> > > for controlling the PWM are part of the DFLL IP block, so there's no
> > > separate linux regulator object involved because the regulator IC only
> > > supplies the rail powering the CPUs. It doesn't have any other controls.
> > > 
> > > The patch 1~4 are the patches of DT bindings update for DFLL clock and
> > > Tegra124 cpufreq, which add PWM and Tegra210 support for DFLL clock and
> > > remove deprecate properties for Tegra124 cpufreq bindings.
> > > 
> > > The patch 5~10 are the patches for DFLL clock driver update for PWM-mode
> > > DFLL support.
> > > 
> > > The patch 11~13 are the Tegra124 cpufreq driver update to make it
> > > work with Tegra210.
> > > 
> > > The patch 14~19 are the devicetree files update for Tegra210 SoC and
> > > platforms. Two platforms are updated here for different DFLL mode usage.
> > > The Tegra210-p2371-2180 (a.k.a. Jetson Tx1) uses DFLL-PWM and the
> > > Tegra210-smaug (a.k.a. Pixel C) uses DFLL-I2C. So two different modes
> > > are verified with this series.
> > > 
> > > The patch 20 is the patch for enabling the CPU regulator for Smaug
> > > board.
> > > 
> > > * Update in V4:
> > >   - s/nvidia,pwm-period/nvidia,pwm-period-nanoseconds/ in patch 1 for
> > >   DFLL DT bindings update.
> > >   - remove parenthesis in Kconfig of DFLL driver
> > >   - add more ack and RB tags
> > > 
> > > * Update in V3:
> > >   - Squash patch 9 in previous series into patch 7 (ref. [0])
> > >   - minor fixes in patch 6 for geting alignment data
> > >   - more variable type fixes in patch 7
> > >   - fix the error handling in patch 8
> > >   - collect more ack tags
> > > 
> > > * Update in V2:
> > >   - Add two patches that suggested from comments in V1. See patch 9 and
> > >   14.
> > >   - Update DT binding for DFLL-PWM mode in patch 1.
> > >   - Update the code for how to get regulator data from DT or regulator
> > >   API in patch 6.
> > >   - Update to use lut_uv table for LUT lookup in patch 7. That makes the
> > >   generic lut table to work with both I2C and PWM mode.
> > >   - not allow Tegra124 cpufreq driver to be built as a module and remove
> > >   the removal function in patch 12.
> > > 
> > > [0]: http://patchwork.ozlabs.org/project/linux-tegra/list/?series=81595
> > > 
> > > Joseph Lo (17):
> > >    dt-bindings: clock: tegra124-dfll: add Tegra210 support
> > >    dt-bindings: cpufreq: tegra124: remove vdd-cpu-supply from required
> > >      properties
> > >    dt-bindings: cpufreq: tegra124: remove cpu_lp clock from required
> > >      properties
> > >    clk: tegra: dfll: CVB calculation alignment with the regulator
> > >    clk: tegra: dfll: support PWM regulator control
> > >    clk: tegra: dfll: round down voltages based on alignment
> > >    clk: tegra: dfll: add CVB tables for Tegra210
> > >    cpufreq: tegra124: do not handle the CPU rail
> > >    cpufreq: tegra124: extend to support Tegra210
> > >    cpufreq: dt-platdev: add Tegra210 to blacklist
> > >    arm64: dts: tegra210: add DFLL clock
> > >    arm64: dts: tegra210: add CPU clocks
> > >    arm64: dts: tegra210-p2597: add pinmux for PWM-based DFLL support
> > >    arm64: dts: tegra210-p2371-2180: enable DFLL clock
> > >    arm64: dts: tegra210-smaug: add CPU power rail regulator
> > >    arm64: dts: tegra210-smaug: enable DFLL clock
> > >    arm64: defconfig: Enable MAX8973 regulator
> > > 
> > > Peter De Schrijver (3):
> > >    dt-bindings: clock: tegra124-dfll: Update DFLL binding for PWM
> > >      regulator
> > >    clk: tegra: dfll: registration for multiple SoCs
> > >    clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210
> > 
> > Joseph,
> > 
> > can you detail the dependencies between the various patches. From a
> > brief look the CPU frequency driver changes are completely separate
> > bits and it should be possible to apply them to the cpufreq tree.
> > 
> > The clock changes also seem independent of the rest.
> > 
> > Are there any dependencies at all that we need to be mindful about?
> > Or can individual maintainers just pick up the subseries directly?
> > 
> 
> Yes, no dependence with each other. We can apply them separately.
> Please let me know if I need to inform cpufreq or clk maintainer to pick
> them up.

Rafael,

the three CPU frequency patches in this series were acked by Viresh
already, but unfortunately you don't seem to be Cc'ed on these. Are
you okay with me picking these up into the Tegra tree and send you
a pull request in a couple of days? That way we can get the whole
set tested a bit in linux-next. If you'd prefer to pick these up in
the PM tree, here are the corresponding patchwork links:

	https://patchwork.kernel.org/patch/10747943/
	https://patchwork.kernel.org/patch/10747947/
	https://patchwork.kernel.org/patch/10747953/

I'll go and give my Acked-by on these patches if the latter is the
way you prefer.


Stephen, Mike,

the same applies for clk patches. Stephen's acked all of them and I
think all of the series is good to go. How about if I pick up these
up in the Tegra tree and let this all cook in linux-next for a week
or so and then send you a pull request with these? Stephen already
picked up a couple of fixes for clk/tegra, but I don't think any of
those would conflict with this series.

All of that said, Joseph confirmed that there are no dependencies
between these subsystem subseries, so if you'd prefer to pick up the
patches into your respective trees, I have no objections to that.

Thierry

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Re: [PATCH V4 00/20] Tegra210 DFLL support

[Joseph Lo]

On 1/28/19 3:54 PM, Thierry Reding wrote:
> On Mon, Jan 28, 2019 at 09:43:00AM +0800, Joseph Lo wrote:
>> On 1/25/19 9:46 PM, Thierry Reding wrote:
>>> On Fri, Jan 04, 2019 at 11:06:42AM +0800, Joseph Lo wrote:
>>>> This series introduces support for the DFLL as a CPU clock source
>>>> on Tegra210. As Jetson TX1 uses a PWM controlled regulator IC which
>>>> is driven directly by the DFLLs PWM output, we also introduce support
>>>> for PWM regulators next to I2C controlled regulators. The DFLL output
>>>> frequency is directly controlled by the regulator voltage. The registers
>>>> for controlling the PWM are part of the DFLL IP block, so there's no
>>>> separate linux regulator object involved because the regulator IC only
>>>> supplies the rail powering the CPUs. It doesn't have any other controls.
[snip]
>>> Joseph,
>>>
>>> can you detail the dependencies between the various patches. From a
>>> brief look the CPU frequency driver changes are completely separate
>>> bits and it should be possible to apply them to the cpufreq tree.
>>>
>>> The clock changes also seem independent of the rest.
>>>
>>> Are there any dependencies at all that we need to be mindful about?
>>> Or can individual maintainers just pick up the subseries directly?
>>>
>>
>> Yes, no dependence with each other. We can apply them separately.
>> Please let me know if I need to inform cpufreq or clk maintainer to pick
>> them up.
> 
> Rafael,
> 
> the three CPU frequency patches in this series were acked by Viresh
> already, but unfortunately you don't seem to be Cc'ed on these. Are
> you okay with me picking these up into the Tegra tree and send you
> a pull request in a couple of days? That way we can get the whole
> set tested a bit in linux-next. If you'd prefer to pick these up in
> the PM tree, here are the corresponding patchwork links:
> 
> 	https://patchwork.kernel.org/patch/10747943/
> 	https://patchwork.kernel.org/patch/10747947/
> 	https://patchwork.kernel.org/patch/10747953/
> 
> I'll go and give my Acked-by on these patches if the latter is the
> way you prefer.
> 
> 
> Stephen, Mike,
> 
> the same applies for clk patches. Stephen's acked all of them and I
> think all of the series is good to go. How about if I pick up these
> up in the Tegra tree and let this all cook in linux-next for a week
> or so and then send you a pull request with these? Stephen already
> picked up a couple of fixes for clk/tegra, but I don't think any of
> those would conflict with this series.
> 
> All of that said, Joseph confirmed that there are no dependencies
> between these subsystem subseries, so if you'd prefer to pick up the
> patches into your respective trees, I have no objections to that.
> 
> Thierry
> 

Hi Rafael, Stephen,

Gental ping. Please let Thierry know if the cpufreq and DFLL clock 
related changes can go through Tegra tree.

I know Rafael did say [1] it's okay to go through Tegra tree in earlier 
comment.

Thanks,
Joseph

[1]: http://patchwork.ozlabs.org/patch/1015181/

Re: [PATCH V4 00/20] Tegra210 DFLL support

[Stephen Boyd]

Quoting Joseph Lo (2019-01-31 18:49:38)
> On 1/28/19 3:54 PM, Thierry Reding wrote:
> > 
> > the same applies for clk patches. Stephen's acked all of them and I
> > think all of the series is good to go. How about if I pick up these
> > up in the Tegra tree and let this all cook in linux-next for a week
> > or so and then send you a pull request with these? Stephen already
> > picked up a couple of fixes for clk/tegra, but I don't think any of
> > those would conflict with this series.
> > 
> > All of that said, Joseph confirmed that there are no dependencies
> > between these subsystem subseries, so if you'd prefer to pick up the
> > patches into your respective trees, I have no objections to that.
> > 
> > Thierry
> > 
> 
> Hi Rafael, Stephen,
> 
> Gental ping. Please let Thierry know if the cpufreq and DFLL clock 
> related changes can go through Tegra tree.
> 
> I know Rafael did say [1] it's okay to go through Tegra tree in earlier 
> comment.
> 

I am happy with the plan. Thanks!