Re: [PATCH v4] x86/power: Fix 'nosmt' vs. hibernation triple fault during resume

[Sean Christopherson <sean.j.christopherson@intel.com>]

On Mon, Jun 03, 2019 at 05:24:26PM +0200, Jiri Kosina wrote:
> On Mon, 3 Jun 2019, Sean Christopherson wrote:
> 
> > For P6 and later, i.e. all modern CPUs, Intel processors go straight to
> > halted state and don't fetch/decode the HLT instruction.
> 
> That'd be a rather relieving fact actually. Do you happen to know if this 
> is stated in some Intel documentation and we've just overlooked it, or 
> whether it's rather an information that's being carried over from 
> generation to generation by whispering through grapevine?

I highly doubt it's officially stated anywhere.  Intel's approach to this
type of micro-architecture specific behavior is (usually) to word the SDM
in such a way that both approaches are legal.  E.g. a 1993 version of the
SDM says "Returns to interrupted HLT instruction", whereas in 1995, which
just so happens to coincide with the introduction of the P6 architecture,
the SDM started saying "Returns to HALT state" and added the blurb about
"will generate a memory access to fetch the HLT instruction (if it is not
in the internal cache)" so that the old behavior is still legal.

All that being said, the "straight to HALT" behavior is now the de facto
standard since lots of people will yell loudly if it changes.