From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75740CA9EBD for ; Thu, 24 Oct 2019 15:26:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3431B2166E for ; Thu, 24 Oct 2019 15:26:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2503188AbfJXP0m (ORCPT ); Thu, 24 Oct 2019 11:26:42 -0400 Received: from foss.arm.com ([217.140.110.172]:54312 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2503092AbfJXP0j (ORCPT ); Thu, 24 Oct 2019 11:26:39 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6950031F; Thu, 24 Oct 2019 08:26:24 -0700 (PDT) Received: from bogus (e107155-lin.cambridge.arm.com [10.1.196.42]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 66B193F71F; Thu, 24 Oct 2019 08:26:22 -0700 (PDT) Date: Thu, 24 Oct 2019 16:26:16 +0100 From: Sudeep Holla To: Ulf Hansson Cc: "Rafael J . Wysocki" , Daniel Lezcano , Lorenzo Pieralisi , Mark Rutland , Lina Iyer , linux-pm@vger.kernel.org, Rob Herring , Vincent Guittot , Stephen Boyd , Bjorn Andersson , Kevin Hilman , Sudeep Holla , linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, Lina Iyer Subject: Re: [PATCH 02/13] dt: psci: Update DT bindings to support hierarchical PSCI states Message-ID: <20191024152504.GA11467@bogus> References: <20191010113937.15962-1-ulf.hansson@linaro.org> <20191010113937.15962-3-ulf.hansson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20191010113937.15962-3-ulf.hansson@linaro.org> User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org On Thu, Oct 10, 2019 at 01:39:26PM +0200, Ulf Hansson wrote: > Update PSCI DT bindings to allow to represent idle states for CPUs and the > CPU topology, by using a hierarchical layout. Primarily this is done by > re-using the existing power domain description [1] and the domain idle > state description [2]. > > Let's also take the opportunity to update the examples to clarify the > difference between the currently supported flattened layout vs the new > hierarchical layout. > This looks fine to me. FWIW: Reviewed-by: Sudeep Holla But before this gets merged, I would like to add another but "the golden" example Qcom *always* referred during ACPI LPI discussions. Ofcourse, it can be addition patch and if I get time, I can write this but no promise ATM. Hierarchical Representation: System 1. SYSTEM_RET 2. SYSTEM_PG Cluster#0 1. CLUSTER_RET 2. CLUSTER_PG Core#0 1. CORE_CG 2. CORE_RET 3. CORE_PG Core#1 1. CORE_CG 2. CORE_RET 3. CORE_PG Cluster#1 (ditto) Flattened Representation: Core#0 1 CORE_CG 2 CORE_RET 3 CORE_RET + CLUSTER_RET 4 CORE_RET + CLUSTER_RET + SYSTEM_RET 5 CORE_PG 6 CORE_PG + CLUSTER_RET 7 CORE_PG + CLUSTER_RET + SYSTEM_RET 8 CORE_PG + CLUSTER_PG 9 CORE_PG + CLUSTER_PG + SYSTEM_RET 10 CORE_PG + CLUSTER_PG + SYSTEM_PG Though we may not implement everything needed to support this, but we must ensure we don't have to end up in a situation breaking backward compatibility trying to support the same. -- Regards, Sudeep