From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.3 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5FB62C10DCE for ; Fri, 6 Mar 2020 12:06:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3EF862072D for ; Fri, 6 Mar 2020 12:06:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726182AbgCFMGu (ORCPT ); Fri, 6 Mar 2020 07:06:50 -0500 Received: from foss.arm.com ([217.140.110.172]:60366 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726162AbgCFMGu (ORCPT ); Fri, 6 Mar 2020 07:06:50 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DF38D31B; Fri, 6 Mar 2020 04:06:49 -0800 (PST) Received: from bogus (e103737-lin.cambridge.arm.com [10.1.197.49]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5A8CC3F6C4; Fri, 6 Mar 2020 04:06:48 -0800 (PST) Date: Fri, 6 Mar 2020 12:06:46 +0000 From: Sudeep Holla To: Benjamin Gaignard Cc: Ulf Hansson , Lorenzo Pieralisi , Benjamin Gaignard , Linux PM , Stephen Boyd , Daniel Lezcano , "Rafael J . Wysocki" , Lina Iyer , Bjorn Andersson , Sudeep Holla , Linux ARM Subject: Re: [PATCH v2 4/4] cpuidle: psci: Allow WFI to be the only state for the hierarchical topology Message-ID: <20200306120646.GB44221@bogus> References: <20200303203559.23995-1-ulf.hansson@linaro.org> <20200303203559.23995-5-ulf.hansson@linaro.org> <20200304122312.GE25004@bogus> <20200305162321.GB53631@bogus> <20200306100431.GA16541@bogus> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org On Fri, Mar 06, 2020 at 11:47:40AM +0100, Benjamin Gaignard wrote: > Le ven. 6 mars 2020 à 11:04, Sudeep Holla a écrit : > > > > On Fri, Mar 06, 2020 at 10:28:10AM +0100, Ulf Hansson wrote: > > > On Thu, 5 Mar 2020 at 17:23, Sudeep Holla wrote: > > > > > > > > [...] > > > > > > OK. The only state that cluster can enter when CPUs are in WFI are > > > > cluster WFI and most hardware can handle it automatically. I don't see > > > > the need to do any extra work for that. > > > > > > This isn't about cluster WFI, but about deeper cluster states, such as > > > a cluster-clock-gated-state and a cluster-power-off-state. It's an ST > > > platform, which Benjamin is working on. > > > > > > > Then definitely something is completely wrong. You can't enter deeper > > cluster states(clock-gated and power-off to be specific) with CPU in > > just WFI state. So, if the attempt here is to enter those states, I > > disagree with the change. > > > > Benjamin, please share the complete hierarchical topology for your platform. > > The platform is stm32mp157 SoC which embedded two Cortex A7 in one cluster. Hang on a minute, is this the same platform where you wanted high resolution timer and were hacking moving dirty tricks around[1]. Now I think you have landed here. > I would like to be able to put the system in a state where clocks of CPUs and > hardware blocks are gated. In this state local timer are off. Sure, please create a deeper CPU state than WFI and enter so that the CPU state is saved and restored correctly. What is the problem doing that ? > The platform should be allowed to go in this state when the devices > within the power domain are pm_runtime_suspend and the CPUs in WFI. Nope, we don't save and restore state when we enter/exit WFI. And hence we can't allow deeper idle states in the hierarchy. No more discussion on that. > In DT I have one system power domain where the hardware blocks (i2, > uart; spi, etc..) are attached + a power per CPU. You really need a CPU idle state here. -- Regards, Sudeep [1] https://lore.kernel.org/linux-arm-kernel/a42dd20677cddd8d09ea91a369a4e10b@www.loen.fr/