From: Krzysztof Kozlowski <krzk@kernel.org>
To: Marek Szyprowski <m.szyprowski@samsung.com>
Cc: linux-clk@vger.kernel.org, linux-pm@vger.kernel.org,
linux-samsung-soc@vger.kernel.org,
Sylwester Nawrocki <snawrocki@kernel.org>,
Chanwoo Choi <cw00.choi@samsung.com>,
Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>,
Lukasz Luba <lukasz.luba@arm.com>,
Stephen Boyd <sboyd@kernel.org>
Subject: Re: [PATCH] clk: samsung: Mark top BPLL mux on Exynos542x as critical
Date: Wed, 5 Aug 2020 12:57:00 +0200 [thread overview]
Message-ID: <20200805105700.GA6100@pi3> (raw)
In-Reply-To: <20200805091601.11983-1-m.szyprowski@samsung.com>
On Wed, Aug 05, 2020 at 11:16:01AM +0200, Marek Szyprowski wrote:
> BPLL clock must not be disabled because it is needed for proper DRAM
> operation. This is normally handled by respective memory devfreq driver,
> but when that driver is not yet probed or its probe has been deferred the
> clock might got disabled what causes board hang. Fix this by marking it
> as critical.
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
> drivers/clk/samsung/clk-exynos5420.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Best regards,
Krzysztof
next prev parent reply other threads:[~2020-08-05 19:48 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20200805091612eucas1p28c955b21e57898de60d3ed50c95b9d18@eucas1p2.samsung.com>
2020-08-05 9:16 ` [PATCH] clk: samsung: Mark top BPLL mux on Exynos542x as critical Marek Szyprowski
2020-08-05 10:39 ` Lukasz Luba
2020-08-05 10:57 ` Krzysztof Kozlowski [this message]
2020-08-06 2:49 ` Chanwoo Choi
2020-08-07 13:24 ` Sylwester Nawrocki
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