From: Bjorn Helgaas <helgaas@kernel.org>
To: "Rafael J. Wysocki" <rafael@kernel.org>
Cc: "Keith Busch" <kbusch@kernel.org>,
"Kai-Heng Feng" <kai.heng.feng@canonical.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Linux PM" <linux-pm@vger.kernel.org>,
"Nirmal Patel" <nirmal.patel@linux.intel.com>,
"Jonathan Derrick" <jonathan.derrick@linux.dev>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Linux PCI" <linux-pci@vger.kernel.org>,
"Linux Kernel Mailing List" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v3] PCI: vmd: Honor ACPI _OSC on PCIe features
Date: Wed, 9 Feb 2022 15:36:38 -0600 [thread overview]
Message-ID: <20220209213638.GA587920@bhelgaas> (raw)
In-Reply-To: <CAJZ5v0gUFY8fFKFhqmRHLKvaRA7mqDwkx7q=7soSGmu51dSD_Q@mail.gmail.com>
On Tue, Dec 07, 2021 at 02:15:04PM +0100, Rafael J. Wysocki wrote:
> On Tue, Dec 7, 2021 at 12:12 AM Keith Busch <kbusch@kernel.org> wrote:
> > On Fri, Dec 03, 2021 at 11:15:41AM +0800, Kai-Heng Feng wrote:
> > > When Samsung PCIe Gen4 NVMe is connected to Intel ADL VMD, the
> > > combination causes AER message flood and drags the system performance
> > > down.
> > >
> > > The issue doesn't happen when VMD mode is disabled in BIOS, since AER
> > > isn't enabled by acpi_pci_root_create() . When VMD mode is enabled, AER
> > > is enabled regardless of _OSC:
> > > [ 0.410076] acpi PNP0A08:00: _OSC: platform does not support [AER]
> > > ...
> > > [ 1.486704] pcieport 10000:e0:06.0: AER: enabled with IRQ 146
> > >
> > > Since VMD is an aperture to regular PCIe root ports, honor ACPI _OSC to
> > > disable PCIe features accordingly to resolve the issue.
> >
> > At least for some versions of this hardare, I recall ACPI is unaware of
> > any devices in the VMD domain; the platform can not see past the VMD
> > endpoint, so I throught the driver was supposed to always let the VMD
> > domain use OS native support regardless of the parent's ACPI _OSC.
>
> This is orthogonal to whether or not ACPI is aware of the VMD domain
> or the devices in it.
>
> If the platform firmware does not allow the OS to control specific
> PCIe features at the physical host bridge level, that extends to the
> VMD "bus", because it is just a way to expose a hidden part of the
> PCIe hierarchy.
I don't understand what's going on here. Do we understand the AER
message flood? Are we just papering over it by disabling AER?
If an error occurs below a VMD, who notices and reports it? If we
disable native AER below VMD because of _OSC, as this patch does, I
guess we're assuming the platform will handle AER events below VMD.
Is that really true? Does the platform know how to find AER log
registers of devices below VMD?
> The platform firmware does that through ACPI _OSC under the host
> bridge device (not under the VMD device) which it is very well aware
> of.
next prev parent reply other threads:[~2022-02-09 21:36 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-03 3:15 [PATCH v3] PCI: vmd: Honor ACPI _OSC on PCIe features Kai-Heng Feng
2021-12-03 14:00 ` Rafael J. Wysocki
2021-12-06 23:12 ` Keith Busch
2021-12-07 13:15 ` Rafael J. Wysocki
2022-02-09 21:36 ` Bjorn Helgaas [this message]
2022-02-10 17:52 ` Jonathan Derrick
2022-02-14 0:27 ` Kai-Heng Feng
2022-02-14 0:23 ` Kai-Heng Feng
2022-02-15 15:09 ` Bjorn Helgaas
2022-02-15 17:09 ` Rafael J. Wysocki
2022-02-16 1:53 ` Bjorn Helgaas
2022-02-16 8:14 ` Christoph Hellwig
2022-02-16 12:37 ` Rafael J. Wysocki
2022-01-04 15:26 ` Lorenzo Pieralisi
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