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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT024.mail.protection.outlook.com (10.13.177.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5417.15 via Frontend Transport; Sat, 9 Jul 2022 14:10:19 +0000 Received: from pyuan-desktop.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Sat, 9 Jul 2022 09:10:15 -0500 From: Perry Yuan To: , , CC: , , , , , , , , , , Perry Yuan Subject: [PATCH v2 00/14] AMD Pstate Enhancement And Issue Fixs Date: Sat, 9 Jul 2022 10:08:35 -0400 Message-ID: <20220709140835.830084-1-Perry.Yuan@amd.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 72952b6b-225e-44d1-b02b-08da61b4c1c6 X-MS-TrafficTypeDiagnostic: MW5PR12MB5681:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jul 2022 14:10:19.8596 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 72952b6b-225e-44d1-b02b-08da61b4c1c6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT024.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW5PR12MB5681 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Hello, This patchsets adds support for precision boost hardware control for AMD processors. Meanwhile the patchset fixs lowest perf query and desired perf scope issues. Update transition delay and latency default value to meet SMU firmware requirement. and do some code cleanups, It also exports cpufreq cpu release and acquire for coming amd-pstate epp mode driver The patch series are tested on the AMD mobile and EYPC server systems v1->v2: - add two new patches to remove the acpi_disabled check - fix some typos in the commit info - move the clamp_t() into amd_pstate_update() function - rebased to 5.19-rc5 [1]:https://patchwork.kernel.org/project/linux-pm/list/?series=657510 Perry Yuan (14): x86/msr: Add the MSR definition for AMD CPPC hardware control. cpufreq: amd-pstate: enable AMD Precision Boost mode switch cpufreq: amd-pstate: cleanup the unused and duplicated headers declaration cpufreq: amd-pstate: prefetch cppc_req_cached value in amd_pstate_cpu_init() cpufreq: amd-pstate: simplify cpudata pointer assignment cpufreq: amd_pstate: fix wrong lowest perf fetch cpufreq: amd_pstate: map desired perf into pstate scope for powersave governor cpufreq: amd-pstate: fix white-space cpufreq: amd-pstate: update pstate frequency transition delay time cpufreq: cpufreq: export cpufreq cpu release and acquire cpufreq: amd-pstate: add ACPI disabled check in acpi_cpc_valid() cpufreq: amd_pstate: update transition delay time to 1ms arch_topology: remove the acpi_disabled check cpufreq: CPPC: remove the acpi_disabled check arch/x86/include/asm/msr-index.h | 3 ++ drivers/acpi/cppc_acpi.c | 3 ++ drivers/base/arch_topology.c | 2 +- drivers/cpufreq/amd-pstate.c | 57 +++++++++++++++++++------------- drivers/cpufreq/cppc_cpufreq.c | 2 +- drivers/cpufreq/cpufreq.c | 2 ++ 6 files changed, 44 insertions(+), 25 deletions(-) -- 2.25.1