From: Ninad Malwade <nmalwade@nvidia.com>
To: <nmalwade@nvidia.com>, <treding@nvidia.com>,
<jonathanh@nvidia.com>, <linux@roeck-us.net>, <jdelvare@suse.com>,
<nicolinc@nvidia.com>, <rkasirajan@nvidia.com>
Cc: <linux-hwmon@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-pm@vger.kernel.org>
Subject: [PATCH] ina3221: Fix shunt sum critical calculation
Date: Tue, 8 Nov 2022 12:45:08 +0800 [thread overview]
Message-ID: <20221108044508.23463-1-nmalwade@nvidia.com> (raw)
The shunt sum critical limit register value should be left shifted
by one bit as its LSB-0 is a reserved bit.
Signed-off-by: Ninad Malwade <nmalwade@nvidia.com>
---
drivers/hwmon/ina3221.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/hwmon/ina3221.c b/drivers/hwmon/ina3221.c
index 2a57f4b60c29..e06186986444 100644
--- a/drivers/hwmon/ina3221.c
+++ b/drivers/hwmon/ina3221.c
@@ -228,7 +228,7 @@ static int ina3221_read_value(struct ina3221_data *ina, unsigned int reg,
* Shunt Voltage Sum register has 14-bit value with 1-bit shift
* Other Shunt Voltage registers have 12 bits with 3-bit shift
*/
- if (reg == INA3221_SHUNT_SUM)
+ if (reg == INA3221_SHUNT_SUM || reg == INA3221_CRIT_SUM)
*val = sign_extend32(regval >> 1, 14);
else
*val = sign_extend32(regval >> 3, 12);
@@ -465,7 +465,7 @@ static int ina3221_write_curr(struct device *dev, u32 attr,
* SHUNT_SUM: (1 / 40uV) << 1 = 1 / 20uV
* SHUNT[1-3]: (1 / 40uV) << 3 = 1 / 5uV
*/
- if (reg == INA3221_SHUNT_SUM)
+ if (reg == INA3221_SHUNT_SUM || reg == INA3221_CRIT_SUM)
regval = DIV_ROUND_CLOSEST(voltage_uv, 20) & 0xfffe;
else
regval = DIV_ROUND_CLOSEST(voltage_uv, 5) & 0xfff8;
--
2.17.1
next reply other threads:[~2022-11-08 4:45 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-08 4:45 Ninad Malwade [this message]
2022-11-08 13:25 ` [PATCH] ina3221: Fix shunt sum critical calculation Thierry Reding
2022-11-11 16:27 ` Guenter Roeck
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