From: bchihi@baylibre.com
To: daniel.lezcano@linaro.org,
angelogioacchino.delregno@collabora.com, rafael@kernel.org,
amitk@kernel.org, rui.zhang@intel.com, matthias.bgg@gmail.com,
robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
rdunlap@infradead.org, ye.xingchen@zte.com.cn,
p.zabel@pengutronix.de
Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org,
khilman@baylibre.com, james.lo@mediatek.com,
rex-bc.chen@mediatek.com
Subject: [PATCH v11 6/6] arm64/dts/mt8195: Add temperature mitigation threshold
Date: Tue, 24 Jan 2023 14:17:17 +0100 [thread overview]
Message-ID: <20230124131717.128660-7-bchihi@baylibre.com> (raw)
In-Reply-To: <20230124131717.128660-1-bchihi@baylibre.com>
From: Balsam CHIHI <bchihi@baylibre.com>
The mt8195 SoC has several hotspots around the CPUs. Specify the
targeted temperature threshold when to apply the mitigation and define
the associated cooling devices.
Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 169 ++++++++++++++++++++---
1 file changed, 153 insertions(+), 16 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 636676f4ba25..9544ae91379a 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -14,6 +14,7 @@
#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
#include <dt-bindings/power/mt8195-power.h>
#include <dt-bindings/reset/mt8195-resets.h>
+#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/thermal/mediatek-lvts.h>
/ {
@@ -2413,107 +2414,243 @@ dp_tx: dp-tx@1c600000 {
thermal_zones: thermal-zones {
cpu0-thermal {
- polling-delay = <0>;
- polling-delay-passive = <0>;
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU0>;
+
trips {
+ cpu0_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
cpu0_crit: trip-crit {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu0_alert>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
cpu1-thermal {
- polling-delay = <0>;
- polling-delay-passive = <0>;
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU1>;
+
trips {
+ cpu1_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
cpu1_crit: trip-crit {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu1_alert>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
cpu2-thermal {
- polling-delay = <0>;
- polling-delay-passive = <0>;
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU2>;
+
trips {
+ cpu2_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
cpu2_crit: trip-crit {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu2_alert>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
cpu3-thermal {
- polling-delay = <0>;
- polling-delay-passive = <0>;
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU3>;
+
trips {
+ cpu3_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
cpu3_crit: trip-crit {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu3_alert>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
cpu4-thermal {
- polling-delay = <0>;
- polling-delay-passive = <0>;
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU0>;
+
trips {
+ cpu4_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
cpu4_crit: trip-crit {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu4_alert>;
+ cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
cpu5-thermal {
- polling-delay = <0>;
- polling-delay-passive = <0>;
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU1>;
+
trips {
+ cpu5_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
cpu5_crit: trip-crit {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu5_alert>;
+ cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
cpu6-thermal {
- polling-delay = <0>;
- polling-delay-passive = <0>;
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU2>;
+
trips {
+ cpu6_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
cpu6_crit: trip-crit {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu6_alert>;
+ cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
cpu7-thermal {
- polling-delay = <0>;
- polling-delay-passive = <0>;
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU3>;
+
trips {
+ cpu7_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
cpu7_crit: trip-crit {
temperature = <100000>;
hysteresis = <2000>;
type = "critical";
};
};
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu7_alert>;
+ cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
};
};
};
--
2.34.1
next prev parent reply other threads:[~2023-01-24 13:17 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-24 13:17 [PATCH v11 0/6] Add LVTS thermal architecture bchihi
2023-01-24 13:17 ` [PATCH v11 1/6] thermal/drivers/mediatek: Relocate driver to mediatek folder bchihi
2023-01-24 15:37 ` AngeloGioacchino Del Regno
2023-01-25 15:02 ` Balsam CHIHI
2023-01-24 13:17 ` [PATCH v11 2/6] dt-bindings/thermal/mediatek: Add LVTS thermal controllers dt-binding definition bchihi
2023-01-25 11:14 ` Daniel Lezcano
2023-01-25 20:35 ` Rob Herring
2023-01-25 21:13 ` Daniel Lezcano
2023-01-25 20:34 ` Rob Herring
2023-01-26 10:33 ` Balsam CHIHI
2023-01-26 16:10 ` [PATCH v12 2/6] dt-bindings: thermal: mediatek: " bchihi
2023-01-27 22:10 ` Daniel Lezcano
2023-01-28 10:50 ` Krzysztof Kozlowski
2023-01-30 10:49 ` Balsam CHIHI
2023-01-28 10:48 ` Krzysztof Kozlowski
2023-01-30 10:40 ` Balsam CHIHI
2023-01-30 11:18 ` Matthias Brugger
2023-01-30 12:19 ` Balsam CHIHI
2023-01-30 16:07 ` Matthias Brugger
2023-01-31 16:53 ` Krzysztof Kozlowski
2023-01-31 17:01 ` Daniel Lezcano
2023-01-31 14:04 ` [PATCH v3] dt-bindings: thermal: mediatek: Add LVTS thermal controllers bchihi
2023-02-01 7:46 ` Krzysztof Kozlowski
2023-02-01 13:34 ` Balsam CHIHI
2023-02-01 13:37 ` Krzysztof Kozlowski
2023-02-01 13:56 ` Balsam CHIHI
2023-03-07 13:42 ` [PATCH] thermal/drivers/mediatek/lvts_thermal: fix memcpy's number of bytes in lvts_calibration_init() bchihi
2023-03-08 9:10 ` AngeloGioacchino Del Regno
2023-03-09 12:37 ` Dan Carpenter
2023-01-24 13:17 ` [PATCH v11 3/6] arm64/dts/mt8195: Add efuse node to mt8195 bchihi
2023-01-25 14:25 ` Matthias Brugger
2023-01-25 15:04 ` Balsam CHIHI
2023-01-24 13:17 ` [PATCH v11 4/6] thermal/drivers/mediatek: Add the Low Voltage Thermal Sensor driver bchihi
2023-01-24 15:31 ` AngeloGioacchino Del Regno
2023-01-25 15:06 ` Balsam CHIHI
2023-01-31 15:38 ` [PATCH v12] thermal: drivers: mediatek: " bchihi
2023-02-01 3:09 ` kernel test robot
2023-02-01 7:47 ` Krzysztof Kozlowski
2023-02-01 15:14 ` Balsam CHIHI
2023-02-01 7:55 ` Krzysztof Kozlowski
2023-02-01 16:46 ` Balsam CHIHI
2023-02-01 16:59 ` Matthias Brugger
2023-02-03 10:35 ` Balsam CHIHI
2023-02-01 17:12 ` Krzysztof Kozlowski
2023-02-03 11:06 ` Balsam CHIHI
2023-02-06 14:07 ` Daniel Lezcano
2023-02-06 14:30 ` Krzysztof Kozlowski
2023-02-06 14:38 ` Daniel Lezcano
2023-02-06 14:32 ` Balsam CHIHI
2023-01-24 13:17 ` [PATCH v11 5/6] arm64/dts/mt8195: Add thermal zones and thermal nodes bchihi
2023-01-24 15:36 ` AngeloGioacchino Del Regno
2023-01-25 15:10 ` Balsam CHIHI
2023-01-25 19:09 ` Matthias Brugger
2023-01-26 9:43 ` Balsam CHIHI
2023-01-31 15:37 ` [PATCH v12] arm64: dts: mediatek: mt8195: " bchihi
2023-01-24 13:17 ` bchihi [this message]
2023-01-24 15:36 ` [PATCH v11 6/6] arm64/dts/mt8195: Add temperature mitigation threshold AngeloGioacchino Del Regno
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