From: Zhao Liu <zhao1.liu@linux.intel.com>
To: Paolo Bonzini <pbonzini@redhat.com>,
Sean Christopherson <seanjc@google.com>,
"Rafael J . Wysocki" <rafael@kernel.org>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>,
"H . Peter Anvin" <hpa@zytor.com>,
kvm@vger.kernel.org, linux-pm@vger.kernel.org,
linux-kernel@vger.kernel.org, x86@kernel.org
Cc: Ricardo Neri <ricardo.neri-calderon@linux.intel.com>,
Len Brown <len.brown@intel.com>, Zhang Rui <rui.zhang@intel.com>,
Zhenyu Wang <zhenyu.z.wang@intel.com>,
Zhuocheng Ding <zhuocheng.ding@intel.com>,
Dapeng Mi <dapeng1.mi@intel.com>,
Yanting Jiang <yanting.jiang@intel.com>,
Yongwei Ma <yongwei.ma@intel.com>,
Vineeth Pillai <vineeth@bitbyteword.org>,
Suleiman Souhlal <suleiman@google.com>,
Masami Hiramatsu <mhiramat@google.com>,
David Dai <davidai@google.com>,
Saravana Kannan <saravanak@google.com>,
Zhao Liu <zhao1.liu@intel.com>
Subject: [RFC 01/26] thermal: Add bit definition for x86 thermal related MSRs
Date: Sat, 3 Feb 2024 17:11:49 +0800 [thread overview]
Message-ID: <20240203091214.411862-2-zhao1.liu@linux.intel.com> (raw)
In-Reply-To: <20240203091214.411862-1-zhao1.liu@linux.intel.com>
From: Zhao Liu <zhao1.liu@intel.com>
Add the definition of more bits of these MSRs:
* MSR_IA32_THERM_CONTROL
* MSR_IA32_THERM_INTERRUPT
* MSR_IA32_THERM_STATUS
* MSR_IA32_PACKAGE_THERM_STATUS
* MSR_IA32_PACKAGE_THERM_INTERRUPT
The virtualization of thermal events need these extra definitions.
While here, regroup the definitions and use the BIT_ULL() and
GENMASK_ULL() macro to improve readability.
Tested-by: Yanting Jiang <yanting.jiang@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
arch/x86/include/asm/msr-index.h | 54 +++++++++++++++++++----------
drivers/thermal/intel/therm_throt.c | 1 -
2 files changed, 35 insertions(+), 20 deletions(-)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 65b1bfb9c304..4f7ebfafa46a 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -829,17 +829,26 @@
#define MSR_IA32_MPERF 0x000000e7
#define MSR_IA32_APERF 0x000000e8
-#define MSR_IA32_THERM_CONTROL 0x0000019a
-#define MSR_IA32_THERM_INTERRUPT 0x0000019b
-
-#define THERM_INT_HIGH_ENABLE (1 << 0)
-#define THERM_INT_LOW_ENABLE (1 << 1)
-#define THERM_INT_PLN_ENABLE (1 << 24)
-
-#define MSR_IA32_THERM_STATUS 0x0000019c
+#define MSR_IA32_THERM_CONTROL 0x0000019a
+#define THERM_ON_DEM_CLO_MOD_DUTY_CYC_MASK GENMASK_ULL(3, 1)
+#define THERM_ON_DEM_CLO_MOD_ENABLE BIT_ULL(4)
-#define THERM_STATUS_PROCHOT (1 << 0)
-#define THERM_STATUS_POWER_LIMIT (1 << 10)
+#define MSR_IA32_THERM_INTERRUPT 0x0000019b
+#define THERM_INT_HIGH_ENABLE BIT_ULL(0)
+#define THERM_INT_LOW_ENABLE BIT_ULL(1)
+#define THERM_INT_PROCHOT_ENABLE BIT_ULL(2)
+#define THERM_INT_FORCEPR_ENABLE BIT_ULL(3)
+#define THERM_INT_CRITICAL_TEM_ENABLE BIT_ULL(4)
+#define THERM_INT_PLN_ENABLE BIT_ULL(24)
+
+#define MSR_IA32_THERM_STATUS 0x0000019c
+#define THERM_STATUS_PROCHOT BIT_ULL(0)
+#define THERM_STATUS_PROCHOT_LOG BIT_ULL(1)
+#define THERM_STATUS_PROCHOT_FORCEPR_EVENT BIT_ULL(2)
+#define THERM_STATUS_PROCHOT_FORCEPR_LOG BIT_ULL(3)
+#define THERM_STATUS_CRITICAL_TEMP BIT_ULL(4)
+#define THERM_STATUS_CRITICAL_TEMP_LOG BIT_ULL(5)
+#define THERM_STATUS_POWER_LIMIT BIT_ULL(10)
#define MSR_THERM2_CTL 0x0000019d
@@ -861,17 +870,24 @@
#define ENERGY_PERF_BIAS_POWERSAVE 15
#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1
-
-#define PACKAGE_THERM_STATUS_PROCHOT (1 << 0)
-#define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10)
-#define PACKAGE_THERM_STATUS_HFI_UPDATED (1 << 26)
+#define PACKAGE_THERM_STATUS_PROCHOT BIT_ULL(0)
+#define PACKAGE_THERM_STATUS_PROCHOT_LOG BIT_ULL(1)
+#define PACKAGE_THERM_STATUS_PROCHOT_EVENT BIT_ULL(2)
+#define PACKAGE_THERM_STATUS_PROCHOT_EVENT_LOG BIT_ULL(3)
+#define PACKAGE_THERM_STATUS_CRITICAL_TEMP BIT_ULL(4)
+#define PACKAGE_THERM_STATUS_CRITICAL_TEMP_LOG BIT_ULL(5)
+#define PACKAGE_THERM_STATUS_POWER_LIMIT BIT_ULL(10)
+#define PACKAGE_THERM_STATUS_POWER_LIMIT_LOG BIT_ULL(11)
+#define PACKAGE_THERM_STATUS_DIG_READOUT_MASK GENMASK_ULL(22, 16)
+#define PACKAGE_THERM_STATUS_HFI_UPDATED BIT_ULL(26)
#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2
-
-#define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0)
-#define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1)
-#define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24)
-#define PACKAGE_THERM_INT_HFI_ENABLE (1 << 25)
+#define PACKAGE_THERM_INT_HIGH_ENABLE BIT_ULL(0)
+#define PACKAGE_THERM_INT_LOW_ENABLE BIT_ULL(1)
+#define PACKAGE_THERM_INT_PROCHOT_ENABLE BIT_ULL(2)
+#define PACKAGE_THERM_INT_OVERHEAT_ENABLE BIT_ULL(4)
+#define PACKAGE_THERM_INT_PLN_ENABLE BIT_ULL(24)
+#define PACKAGE_THERM_INT_HFI_ENABLE BIT_ULL(25)
/* Thermal Thresholds Support */
#define THERM_INT_THRESHOLD0_ENABLE (1 << 15)
diff --git a/drivers/thermal/intel/therm_throt.c b/drivers/thermal/intel/therm_throt.c
index e69868e868eb..4c72fee32bf2 100644
--- a/drivers/thermal/intel/therm_throt.c
+++ b/drivers/thermal/intel/therm_throt.c
@@ -191,7 +191,6 @@ static const struct attribute_group thermal_attr_group = {
#endif /* CONFIG_SYSFS */
#define THERM_THROT_POLL_INTERVAL HZ
-#define THERM_STATUS_PROCHOT_LOG BIT(1)
static u64 therm_intr_core_clear_mask;
static u64 therm_intr_pkg_clear_mask;
--
2.34.1
next prev parent reply other threads:[~2024-02-03 8:59 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-03 9:11 [RFC 00/26] Intel Thread Director Virtualization Zhao Liu
2024-02-03 9:11 ` Zhao Liu [this message]
2024-02-03 9:11 ` [RFC 02/26] thermal: intel: hfi: Add helpers to build HFI/ITD structures Zhao Liu
2024-02-03 9:11 ` [RFC 03/26] thermal: intel: hfi: Add HFI notifier helpers to notify HFI update Zhao Liu
2024-02-03 9:11 ` [RFC 04/26] KVM: Add kvm_arch_sched_out() hook Zhao Liu
2024-02-03 9:11 ` [RFC 05/26] KVM: x86: Reset hardware history at vCPU's sched_in/out Zhao Liu
2024-02-03 9:11 ` [RFC 06/26] KVM: VMX: Add helpers to handle the writes to MSR's R/O and R/WC0 bits Zhao Liu
2024-02-03 9:11 ` [RFC 07/26] KVM: VMX: Emulate ACPI (CPUID.0x01.edx[bit 22]) feature Zhao Liu
2024-02-03 9:11 ` [RFC 08/26] KVM: x86: Expose TM/ACC (CPUID.0x01.edx[bit 29]) feature bit to VM Zhao Liu
2024-02-03 9:11 ` [RFC 09/26] KVM: x86: cpuid: Define CPUID 0x06.eax by kvm_cpu_cap_mask() Zhao Liu
2024-02-03 9:11 ` [RFC 10/26] KVM: VMX: Emulate PTM/PTS (CPUID.0x06.eax[bit 6]) feature Zhao Liu
2024-02-03 9:11 ` [RFC 11/26] KVM: VMX: Introduce HFI description structure Zhao Liu
2024-02-03 9:12 ` [RFC 12/26] KVM: VMX: Introduce HFI table index for vCPU Zhao Liu
2024-02-03 9:12 ` [RFC 13/26] KVM: VMX: Support virtual HFI table for VM Zhao Liu
2024-02-03 9:12 ` [RFC 14/26] KVM: x86: Introduce the HFI dynamic update request and kvm_x86_ops Zhao Liu
2024-02-03 9:12 ` [RFC 15/26] KVM: VMX: Sync update of Host HFI table to Guest Zhao Liu
2024-02-03 9:12 ` [RFC 16/26] KVM: VMX: Update HFI table when vCPU migrates Zhao Liu
2024-02-03 9:12 ` [RFC 17/26] KVM: VMX: Allow to inject thermal interrupt without HFI update Zhao Liu
2024-02-03 9:12 ` [RFC 18/26] KVM: VMX: Emulate HFI related bits in package thermal MSRs Zhao Liu
2024-02-03 9:12 ` [RFC 19/26] KVM: VMX: Emulate the MSRs of HFI feature Zhao Liu
2024-02-03 9:12 ` [RFC 20/26] KVM: x86: Expose HFI feature bit and HFI info in CPUID Zhao Liu
2024-02-03 9:12 ` [RFC 21/26] KVM: VMX: Extend HFI table and MSR emulation to support ITD Zhao Liu
2024-02-03 9:12 ` [RFC 22/26] KVM: VMX: Pass through ITD classification related MSRs to Guest Zhao Liu
2024-02-03 9:12 ` [RFC 23/26] KVM: x86: Expose ITD feature bit and related info in CPUID Zhao Liu
2024-02-03 9:12 ` [RFC 24/26] KVM: VMX: Emulate the MSR of HRESET feature Zhao Liu
2024-02-03 9:12 ` [RFC 25/26] KVM: x86: Expose HRESET feature's CPUID to Guest Zhao Liu
2024-02-03 9:12 ` [RFC 26/26] Documentation: KVM: Add description of pkg_therm_lock Zhao Liu
2024-02-22 7:42 ` [RFC 00/26] Intel Thread Director Virtualization Zhao Liu
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